SN74AUC32244 [TI]
32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS; 32位缓冲器/驱动器，具有三态输出
| 型号： | SN74AUC32244 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS |
| 文件： | 总10页 (文件大小：272K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74AUC32244
32-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES425 – FEBRUARY 2003
Member of the Texas Instruments
Widebus+ Family
Low Power Consumption, 40-µA Max I
CC
±8-mA Output Drive at 1.8 V
Optimized for 1.8-V Operation and is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
I
Supports Partial-Power-Down Mode
off
Operation
Sub 1-V Operable
– 1000-V Charged-Device Model (C101)
Max t of 1.8 ns at 1.8 V
pd
description/ordering information
This 32-bit buffer/driver is operational at 0.8-V to 2.7-V V , but is designed specifically for 1.65-V to 1.95-V
CC
V
operation.
CC
The SN74AUC32244 is designed specifically to improve the performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented receivers and transmitters.
Thedevicecanbeusedaseight4-bitbuffers, four8-bitbuffers, two16-bitbuffers, orone32-bitbuffer. Itprovides
true outputs and symmetrical active-low output-enable (OE) inputs.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
–40°C to 85°C LFBGA – GKE Tape and reel
SN74AUC32244GKER
MM244
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AUC32244
32-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES425 – FEBRUARY 2003
GKE PACKAGE
(TOP VIEW)
terminal assignments
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
1Y2
1Y4
2Y2
2Y4
3Y2
3Y4
4Y2
4Y3
5Y2
5Y4
6Y2
6Y4
7Y2
7Y4
8Y2
8Y3
1Y1
1Y3
2Y1
2Y3
3Y1
3Y3
4Y1
4Y4
5Y1
5Y3
6Y1
6Y3
7Y1
7Y3
8Y1
8Y4
1OE
GND
2OE
GND
1A1
1A3
2A1
2A3
3A1
3A3
4A1
4A4
5A1
5A3
6A1
6A3
7A1
7A3
8A1
8A4
1A2
1A4
2A2
2A4
3A2
3A4
4A2
4A3
5A2
5A4
6A2
6A4
7A2
7A4
8A2
8A3
A
B
C
D
V
CC
V
CC
GND
GND
GND
GND
E
F
G
H
J
V
CC
V
CC
G
H
J
GND
4OE
5OE
GND
GND
3OE
6OE
GND
K
L
K
L
V
CC
V
CC
M
N
P
R
T
GND
GND
GND
GND
M
N
P
R
T
V
CC
V
CC
GND
8OE
GND
7OE
FUNCTION TABLE
(each 4-bit buffer)
INPUTS
OUTPUT
Y
OE
A
H
L
L
L
H
L
H
X
Z
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AUC32244
32-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES425 – FEBRUARY 2003
logic diagram (positive logic)
A3
H4
E5
1OE
3OE
3A1
A5
A2
A1
B2
B1
E2
1A1
1Y1
1Y2
1Y3
1Y4
3Y1
A6
E6
F5
F6
E1
1A2
3A2
3A3
3A4
3Y2
B5
F2
1A3
3Y3
B6
F1
1A4
3Y4
A4
H3
G5
2OE
4OE
4A1
C5
C2
C1
D2
D1
G2
2A1
2Y1
2Y2
2Y3
2Y4
4Y1
C6
G6
H6
H5
G1
2A2
4A2
4A3
4A4
4Y2
D5
H1
2A3
4Y3
D6
H2
2A4
4Y4
J3
T4
N5
5OE
7OE
7A1
J5
J2
J1
N2
5A1
5Y1
5Y2
5Y3
5Y4
7Y1
J6
N6
P5
P6
N1
5A2
7A2
7A3
7A4
7Y2
K5
K2
K1
P2
5A3
7Y3
K6
P1
5A4
7Y4
J4
T3
R5
6OE
8OE
8A1
L5
L2
L1
R2
6A1
6Y1
6Y2
6Y3
6Y4
8Y1
L6
R6
T6
T5
R1
6A2
8A2
8A3
8A4
8Y2
M5
M2
M1
T1
6A3
8Y3
M6
T2
6A4
8Y4
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AUC32244
32-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES425 – FEBRUARY 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
I
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V + 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through V
Package thermal impedance, θ (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W
Storage temperature range, T
O
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CC
JA
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN
MAX
UNIT
V
Supply voltage
0.8
2.7
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 0.8 V
V
CC
V
High-level input voltage
= 1.1 V to 1.95 V
= 2.3 V to 2.7 V
= 0.8 V
0.65 × V
V
V
CC
1.7
0
0.35 × V
0.7
V
IL
Low-level input voltage
= 1.1 V to 1.95 V
= 2.3 V to 2.7 V
CC
V
V
Input voltage
0
0
0
3.6
V
V
I
Active state
3-state
V
CC
3.6
Output voltage
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 0.8 V
–0.7
–3
–5
–8
–9
0.7
3
= 1.1 V
I
High-level output current
Low-level output current
= 1.4 V
mA
mA
OH
OL
= 1.65 V
= 2.3 V
= 0.8 V
= 1.1 V
I
= 1.4 V
5
= 1.65 V
= 2.3 V
8
9
= 0.8 V
20
15
10
85
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
= 1.3 V
ns/V
= 1.6 V, 1.95 V, and 2.7 V
T
–40
°C
A
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AUC32244
32-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES425 – FEBRUARY 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
V –0.1
CC
MAX
UNIT
V
CC
I
I
I
I
I
I
I
I
I
I
I
I
= –100 µA
= –0.7 mA
= –3 mA
= –5 mA
= –8 mA
= –9 mA
= 100 µA
= 0.7 mA
= 3 mA
0.8 V to 2.7 V
0.8 V
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
0.55
1.1 V
0.8
V
OH
V
1.4 V
1
1.65 V
2.3 V
1.2
1.8
0.8 V to 2.7 V
0.8 V
0.2
0.25
1.1 V
0.3
0.4
0.45
0.6
±5
V
OL
V
= 5 mA
1.4 V
= 8 mA
1.65 V
2.3 V
= 9 mA
I
I
I
I
A or OE inputs V = V or GND
CC
0 to 2.7 V
0
µA
µA
µA
µA
pF
I
I
V or V = 2.7 V
±10
±10
40
off
I
O
V
= V or GND
CC
2.7 V
OZ
CC
O
V = V
or GND,
or GND
I
= 0
0.8 V to 2.7 V
2.5 V
I
CC
CC
O
C
C
V = V
3.5
6
4.5
i
I
V
= V or GND
CC
2.5 V
7.5
pF
o
O
†
All typical values are at T = 25°C.
A
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
V
= 1.2 V
V
= 1.5 V
V
= 1.8 V
V
= 2.5 V
CC
± 0.1 V
CC
± 0.1 V
CC
± 0.15 V
CC
± 0.2 V
V
CC
= 0.8 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
TYP
MIN MAX
MIN MAX
MIN TYP MAX
MIN MAX
t
A
5.4
8
0.8
1
2.8
4.4
4.9
0.6
0.7
1
1.9
2.6
4.6
0.7
0.8
1.5
1.3
1.4
2.6
1.8
2.5
4
0.5
0.6
0.5
1.8
1.9
2
ns
ns
ns
Y
Y
Y
pd
t
en
OE
OE
t
12
1.9
dis
operating characteristics, T = 25°C
A
V
CC
= 0.8 V
V
CC
= 1.2 V
V
CC
= 1.5 V
V
CC
= 1.8 V
V
CC
= 2.5 V
TEST
PARAMETER
UNIT
CONDITIONS
TYP
TYP
TYP
TYP
TYP
Outputs
enabled
21
1
22
1
23
1
25
1
30
1
Power
dissipation
capacitance
C
f = 10 MHz
pF
pd
Outputs
disabled
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AUC32244
32-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES425 – FEBRUARY 2003
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
Open
GND
S1
TEST
/t
S1
R
L
From Output
Under Test
t
Open
PLH PHL
t
/t
2 × V
CC
GND
PLZ PZL
C
L
t
/t
R
PHZ PZH
L
(see Note A)
V
C
R
V
∆
L
L
CC
0.8 V
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
0.1 V
0.1 V
15 pF
15 pF
15 pF
30 pF
30 pF
LOAD CIRCUIT
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
0.1 V
0.15 V
0.15 V
V
CC
Timing Input
V
CC
/2
0 V
t
w
t
t
h
su
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
V
CC
/2
V
CC
/2
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
Input
0 V
0 V
t
t
t
t
t
PHL
/2
PZL
PLZ
PLH
PHL
Output
Waveform 1
V
V
V
V
OH
CC
V
/2
/2
V
V
/2
/2
V
CC
Output
CC
CC
V
V
+ V
∆
S1 at 2 × V
(see Note B)
OL
CC
OL
OL
t
t
t
PLH
/2
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– V
OH
∆
V
CC
V
CC
CC
Output
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, slew rate ≥ 1 V/ns.
O
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SN74AUC32244GKER
SN74AUC32244ZKER
ACTIVE
ACTIVE
LFBGA
LFBGA
GKE
96
96
1000
None
SNPB
Level-3-220C-168 HR
Level-3-250C-168 HR
ZKE
1000 Green (RoHS &
no Sb/Br)
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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