SN74ACT7808PM [TI]
2048 】 9 STROBED FIRST-IN, FIRST-OUT MEMORY; 2048 】 9选通的先入先出存贮器
| 型号： | SN74ACT7808PM |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2048 】 9 STROBED FIRST-IN, FIRST-OUT MEMORY |
| 文件： | 总14页 (文件大小：185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74ACT7808
2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205D – FEBRUARY 1991 – REVISED APRIL 1998
Load Clocks and Unload Clocks Can Be
Asynchronous or Coincident
Expansion Logic for Depth Cascading
Empty, Full, and Half-Full Flags
Fall-Through Time of 20 ns Typical
Data Rates up to 50 MHz
2048 Words by 9 Bits
Low-Power Advanced CMOS Technology
Fast Access Times of 15 ns With a 50-pF
Load
3-State Outputs
Package Options Include 44-Pin Plastic
Leaded Chip Carrier (FN), 64-Pin Thin Quad
Flat (PM), and Reduced-Height 64-Pin Quad
Flat (PAG) Packages
Programmable Almost-Full/Almost-Empty
Flag
description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ACT7808 is a 2048-word by 9-bit FIFO designed for high speed and fast access times.
It processes data at rates up to 50 MHz and access times of 15 ns in a bit-parallel format.
Data is written into memory on a low-to-high transition at the load-clock (LDCK) input and is read out on a
low-to-high transition at the unload-clock (UNCK) input. The memory is full when the number of words clocked
in exceeds the number of words clocked out by 2048. When the memory is full, LDCK signals have no effect
on the data residing in memory. When the memory is empty, UNCK signals have no effect.
Status of the FIFO memory is monitored by the full (FULL), empty (EMPTY), half-full (HF), and
almost-full/almost-empty (AF/AE) flags. The FULL output is low when the memory is full and high when the
memory is not full. The EMPTY output is low when the memory is empty and high when it is not empty. The HF
output is high when the FIFO contains 1024 or more words and is low when it contains 1023 or fewer words.
The AF/AE status flag is a programmable flag. The first one or two low-to-high transitions of LDCK after reset
can be used to program the almost-empty offset value (X) and the almost-full offset value (Y) if program enable
(PEN) is low. The AF/AE flag is high when the FIFO contains X or fewer words or (2048 – Y) or more words.
The AF/AE flag is low when the FIFO contains between (X + 1) and (2047 – Y) words.
A low level on the reset (RESET) input resets the internal stack pointers and sets FULL high, AF/AE high, HF
low, and EMPTY low. The Q outputs are not reset to any specific logic level.
The first word loaded into empty memory causes EMPTY to go high and the data to appear on the Q outputs.
Itisimportanttonotethatthefirstworddoesnothavetobeunloaded. Dataoutputsarenoninvertingwithrespect
to the data inputs and are in the high-impedance state when the output-enable (OE) input is low. OE does not
affect the output flags.
Cascading is easily accomplished in the word-width and word-depth directions. When not using the FIFO in
depth expansion, cascade enable (CASEN) must be tied high.
The FIFO must be reset upon power up.
The SN74ACT7808 is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7808
2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205D – FEBRUARY 1991 – REVISED APRIL 1998
FN PACKAGE
(TOP VIEW)
6
5
4
3
2
1 44 43 42 41 40
39
D0
D1
D2
Q1
V
Q2
Q3
7
8
9
38
37
36
CC
GND
10
D3 11
D4
D5 13
14
35 GND
Q4
12
34
33
V
CC
V
32 Q5
31 Q6
30 GND
29 Q7
CC
D6 15
D7 16
D8 17
18 19 20 21 22 23 24 25 26 27 28
PAG OR PM PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
NC
Q0
GND
GND
OE
NC
Q8
V
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
2
3
CC
V
4
CC
UNCK
CASEN
NC
5
XO
6
V
7
CC
V
FL
8
CC
RESET
EMPTY
FULL
XI
9
PEN
10
11
12
13
14
15
16
GND
GND
AF/AE
HF
DP9
LDCK
GND
GND
NC
V
CC
V
CC
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NC – No internal connection
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7808
2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205D – FEBRUARY 1991 – REVISED APRIL 1998
†
logic symbol
Φ
FIFO 2048 × 9
SN74ACT7808
22
1
RESET
LDCK
UNCK
EN1
RESET
LDCK
UNCK
OE
FULL
FULL
HF
19
26
42
5
4
HALF FULL
ALMOST FULL/EMPTY
EMPTY
AF/AE
23
EMPTY
2
PEN
FL
PROGRAM ENABLE
24
25
43
FIRST LOAD
EXPANSION OUT
XO
CASEN
CASCADE ENABLE
21
20
XI
EXPANSION IN
DATA PIN 9
DP9
7
40
39
37
36
34
32
31
29
28
D0
D1
D2
D3
D4
D5
D6
D7
D8
0
0
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
8
9
11
12
13
15
16
17
Data
Data
1
8
8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the FN package.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7808
2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205D – FEBRUARY 1991 – REVISED APRIL 1998
functional block diagram
OE
D0–D8
Location 1
Location 2
Read
UNCK
Pointer
2048 × 9 RAM
Write
Pointer
LDCK
Location 2047
Location 2048
DP9
Q0–Q8
Reset
Logic
RESET
EMPTY
FULL
HF
Expansion
and
Status-Flag
PEN
Logic
FL
AF/AE
XO
CASEN
XI
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7808
2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205D – FEBRUARY 1991 – REVISED APRIL 1998
Terminal Functions
TERMINAL
NAME
I/O
O
I
DESCRIPTION
Almost-full/almost-empty flag. Depth-offset values can be programmed for AF/AE or the default value of 256 can be
used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AE is high when memory contains X or fewer
words or (2048 – Y) or more words. AF/AE is high after reset.
AF/AE
Cascadeenable. WhenmultipleSN74ACT7808devicesaredepthcascaded, everydevicemusthaveCASENtiedlow.
CASEN must be tied high when a device is not used in depth expansion.
†
CASEN
D0–D8
DP9
I
I
Nine-bit data input port
DP9 is used as the most significant bit when programming the AF/AE offset values.
Empty flag. EMPTY is low when the FIFO memory is empty. A FIFO reset also causes EMPTY to go low.
EMPTY
O
First load. When multiple SN74ACT7808 devices are depth cascaded, the first device in the chain must have its FL
input tied low and all other devices must have their FL inputs tied high.
†
FL
I
FULL
HF
O
O
I
Full flag. FULL is low when the FIFO is full. A FIFO reset causes FULL to go high.
Half-full flag. HF is high when the FIFO memory contains 1024 or more words. HF is low after reset.
Load clock. Data is written to the FIFO on the rising edge of LDCK when FULL is high.
Output enable. When OE is low, D0–D8 are in the high-impedance state.
LDCK
OE
I
Program enable. After reset and before the first word is written to the FIFO, the binary value on D0–D8 and DP9 is
latched as an AF/AE offset value when PEN is low and LDCK is high.
PEN
I
Q0–Q8
RESET
UNCK
O
I
Nine-bit data output port
Reset. A low level on RESET resets the FIFO and drives FULL and AF/AE high and HF and EMPTY low.
Unload clock. Data is read from the FIFO on the rising edge of UNCK when EMPTY is high.
I
Expansion input (XI) and expansion output (XO). When multiple SN74ACT7808 devices are depth cascaded, the XO
of one device must be connected to the XI of the next device in the chain. The XO of the last device in the chain is
connected to the XI of the first device in the chain.
†
I
XI
†
O
XO
†
See Figures 6 and 7 for application information on FIFO word-width and word-depth expansions, respectively.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7808
2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205D – FEBRUARY 1991 – REVISED APRIL 1998
offset values for AF/AE
The AF/AE flag has two programmable limits: the almost-empty offset value (X) and the almost-full offset
value (Y). They can be programmed after the FIFO is reset and before the first word is written to memory. If the
offsets are not programmed, the default values of X = Y = 256 are used. The AF/AE flag is high when the FIFO
contains X or fewer words or (2048 – Y) or more words.
To program the offset values, program enable (PEN) can be brought low after reset only when LDCK is low. On
the following low-to-high transition of LDCK, the binary value on D0–D8 and DP9 is stored as the almost-empty
offset value (X) and the almost-full offset value (Y). Holding PEN low for another low-to-high transition of LDCK
reprograms Y to the binary value on D0–D8 and DP9 at the time of the second LDCK low-to-high transition.
Writes to the FIFO memory are disabled while the offsets are programmed. A maximum value of 1023 can be
programmed for either X or Y (see Figure 1). To use the default values of X = Y = 256, PEN must be held high.
RESET
LDCK
PEN
Don’t Care
D0–D8
X and Y
Y
Don’t Care
Don’t Care
X and Y MSB
Y MSB
DP9
EMPTY
Figure 1. Programming X and Y Separately
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
RESET
PEN
1
0
1
0
CASEN
LDCK
D0–D8
UNCK
W
(X+1)
W
W1
W2
W1024
W2048
Don’t Care
(2048–Y)
OE
W
(Y+1)
W
(Y+2)
W
W
Q0–Q8
W2
W1025
W1026
W2047
W2048
W1
(2048–X) (2049–x)
EMPTY
AF/AE
HF
FULL
Define the AF/AE Flag Using
the Default Value or X and Y
Figure 2. Read
SN74ACT7808
2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205D – FEBRUARY 1991 – REVISED APRIL 1998
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Package thermal impedance, θ (see Note 1): FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
JA
PAG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
PM package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
’ACT7808-20 ’ACT7808-25 ’ACT7808-30 ’ACT7808-40
UNIT
V
MIN
4.5
3.85
2
MAX
MIN
4.5
3.85
2
MAX
MIN
4.5
3.85
2
MAX
MIN
4.5
3.85
2
MAX
V
V
V
Supply voltage
5.5
5.5
5.5
5.5
CC
XI
High-level input voltage
V
IH
Other inputs
Low-level input voltage
High-level output current
0.8
–8
16
8
0.8
–8
16
8
0.8
–8
16
8
0.8
–8
16
8
V
IL
I
mA
OH
Q outputs
Flags
I
Low-level output current
mA
OL
T
A
Operating free-air temperature
0
70
0
70
0
70
0
70
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
‡
PARAMETER
TEST CONDITIONS
= –8 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
I
I
I
2.4
V
OH
CC
CC
CC
CC
CC
CC
CC
OH
OL
OL
Flags
= 8 mA
0.5
0.5
±5
V
OL
Q outputs
= 16 mA
I
I
I
V =V
or 0
µA
µA
µA
mA
pF
pF
I
I
CC
=V
V
or 0
±5
OZ
CC
O
CC
V = V
– 0.2 V or 0
CC
400
1
I
§
∆I
CC
One input at 3.4 V,
f = 1 MHz
Other inputs at V or GND
CC
C
C
V = 0,
I
4
8
i
V
O
= 0,
f = 1 MHz
o
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
This is the increase in supply current for each input, excluding XI, that is at one of the specified TTL voltage levels rather 0 V or V
.
CC
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7808
2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205D – FEBRUARY 1991 – REVISED APRIL 1998
timing requirements over recommended operating conditions (unless otherwise noted) (see
Figures 1 through 3)
’ACT7808-20 ’ACT7808-25 ’ACT7808-30 ’ACT7808-40
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
f
t
Clock frequency
Pulse duration
50
40
33.3
25
MHz
clock
LDCK high or low
UNCK high or low
PEN low
8
8
9
9
11
11
11
16
5
13
13
13
19
5
ns
w
9
9
RESET low
10
5
13
5
D0–D8, DP9 before LDCK↑
LDCK inactive
before RESET high
5
5
5
5
t
Setup time
Hold time
ns
ns
su
h
PEN before LDCK↑
5
0
5
0
5
0
5
0
D0–D8, DP9 after LDCK↑
LDCK inactive
after RESET high
5
5
5
5
t
PEN low after LDCK↑
4
0
4
0
4
0
4
0
PEN high after LDCK low
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 3)
L
’ACT7808-20
’ACT7808-25 ’ACT7808-30 ’ACT7808-40
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MHz
ns
†
MIN TYP
MAX
MIN
40
5
MAX
MIN
33.3
5
MAX
MIN
25
5
MAX
f
t
LDCK or UNCK
LDCK↑
50
5
max
20
15
22
18
25
20
28
22
Any Q
pd
4.5
11
10
4.5
4.5
4.5
UNCK↑
UNCK↑
LDCK↑
‡
t
t
Any Q
ns
ns
pd
4
2
2
4
4
2
2
2
0
2
2
2
2
2
1
1
3
15
15
16
15
14
18
16
16
10
19
16
12
11
11
10
9
4
2
2
4
4
2
2
2
0
2
2
2
2
2
1
1
3
17
17
18
17
16
20
18
18
12
21
18
14
13
13
12
11
15
4
4
2
2
4
4
2
2
2
0
2
2
2
2
2
1
1
3
19
19
20
19
18
22
20
20
14
23
20
16
15
15
14
13
17
4
4
2
2
4
4
2
2
2
0
2
2
2
2
2
1
1
3
21
21
22
21
20
24
22
22
16
25
22
18
17
17
16
15
19
4
EMPTY
PLH
UNCK↑
RESET low
LDCK↑
EMPTY
FULL
t
ns
PHL
UNCK↑
RESET low
LDCK↑
t
t
t
t
ns
ns
ns
ns
FULL
PLH
AF/AE
pd
UNCK↑
RESET low
LDCK↑
AF/AE
HF
PLH
PHL
UNCK↑
RESET low
UNCK↑
LDCK↑
HF
t
t
t
t
t
t
XO
ns
ns
ns
ns
ns
ns
PLH
PHL
en
XO
OE
Any Q
Any Q
Any Q
Any Q
OE
dis
XI high
13
4
en
XO high
dis
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
This parameter is measured with C = 30 pF (see Figure 4).
L
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7808
2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205D – FEBRUARY 1991 – REVISED APRIL 1998
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 5 MHz
L
TYP
UNIT
C
Power dissipation capacitance per FIFO channel
Outputs enabled
C
91
pF
pd
PARAMETER MEASUREMENT INFORMATION
7 V
PARAMETER
S1
t
Open
Closed
Open
S1
PZH
t
t
t
en
dis
pd
t
PZL
500 Ω
t
PHZ
From Output
Under Test
= 50 pF
Test
Point
t
Closed
Open
PLZ
PLH
PHL
t
t
C
L
Open
500 Ω
(see Note A)
t
w
LOAD CIRCUIT
3 V
0 V
Input
1.5 V
1.5 V
3 V
0 V
Timing
Input
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
3 V
0 V
3 V
0 V
Data
Input
1.5 V
1.5 V
Output
Control
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
PZL
t
PLZ
≈ 3.5 V
Output
Waveform 1
S1 at 7 V
3 V
0 V
1.5 V
Input
1.5 V
1.5 V
V
+ 0.3 V
OL
V
OL
OH
t
PHZ
t
PLH
t
PZH
t
PHL
V
Output
Waveform 2
S1 at Open
V
OH
V
– 0.3 V
OH
1.5 V
Output
1.5 V
1.5 V
≈ 0 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTE A: C includes probe and jig capacitance.
L
Figure 3. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7808
2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205D – FEBRUARY 1991 – REVISED APRIL 1998
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME
vs
SUPPLY CURRENT
vs
LOAD CAPACITANCE
CLOCK FREQUENCY
typ + 8
typ + 6
typ + 4
160
140
120
100
T
C
= 75°C
= 0 pF
A
L
V
R
T
A
= 5 V
= 500 Ω
= 25°C
CC
L
V
CC
= 5.5 V
V
CC
= 5 V
80
60
V
CC
= 4.5 V
typ + 2
typ
40
20
typ – 2
0
0
50
C
100
150
200
250
300
0
10
20
30
40
50
60
70
80
– Load Capacitance – pF
f
– Clock Frequency – MHz
L
clock
Figure 4
Figure 5
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7808
2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205D – FEBRUARY 1991 – REVISED APRIL 1998
APPLICATION INFORMATION
SN74ACT7808
LDCK
LDCK
FULL
UNCK
UNCK
EMPTY
FULL
EMPTY
OE
OE
D0–D8
D9–D17
Q0–Q8
Q9–Q17
CASEN
H
SN74ACT7808
LDCK
UNCK
EMPTY
FULL
OE
D0–D8
Q0–Q8
D0–D8
Q0–Q8
CASEN
H
Figure 6. Word-Width Expansion: 2048 × 18 Bits
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7808
2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS205D – FEBRUARY 1991 – REVISED APRIL 1998
APPLICATION INFORMATION
depth cascading (see Figure 7)
The SN74ACT7808 provides expansion logic necessary for cascading an unlimited number of the FIFOs in
depth. CASEN must be low on all FIFOs used in depth expansion. FL must be tied low on the first FIFO in the
chain; all others must have FL tied high. The expansion-out (XO) output of a FIFO must be tied to the
expansion-in (XI) input of the next FIFO in the chain. The XO output of the last FIFO is tied to the XI input of
the first FIFO to complete the loop. Data buses are common to each FIFO in the chain. A composite EMPTY
and FULL signal must be generated to indicate boundary conditions.
RESET
OE
L
L
H
L
H
L
FL CASEN
SN74ACT7808
FL CASEN
SN74ACT7808
FL CASEN
SN74ACT7808
XI
XO
OE
XI
XO
OE
XI
XO
OE
RESET
RESET
RESET
D0–D8 Q0–Q8
D0–D8 Q0–Q8
D0–D8 Q0–Q8
9
9
LDCK
UNCK
LDCK
UNCK
LDCK
UNCK
9
9
9
FULL EMPTY
FULL EMPTY
FULL EMPTY
D0–D8
9
Q0–Q8
UNCK
9
9
LDCK
FULL
EMPTY
Figure 7. Depth Cascading to Form a 6K × 9 FIFO
13
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