SN74ACT7811-15PN [ROCHESTER]
1KX18 OTHER FIFO, 15ns, PQCC80, TQFP-80;
| 型号： | SN74ACT7811-15PN |
| 厂家： | 
Rochester Electronics |
| 描述： | 1KX18 OTHER FIFO, 15ns, PQCC80, TQFP-80 先进先出芯片 |
| 文件： | 总21页 (文件大小：987K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74ACT7811
1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996
Member of the Texas Instruments
Widebus Family
Input-Ready, Output-Ready, and Half-Full
Flags
Independent Asynchronous Inputs and
Outputs
Cascadable in Word Width and/or Word
Depth
1024 Words × 18 Bits
Fast Access Times of 15 ns With a 50-pF
Load
Read and Write Operations Can Be
Synchronized to Independent System
Clocks
High-Output Drive for Direct Bus Interface
Available in 68-Pin PLCC (FN) and
Space-Saving 80-Pin Thin Quad Flat (PN)
Packages
Programmable Almost-Full/Almost-Empty
Flag
Pin-to-Pin Compatible With SN74ACT7881,
SN74ACT7882, and SN74ACT7884
FN PACKAGE
(TOP VIEW)
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
D14
D13
D12
D11
D10
D9
10
V
CC
11
12
13
14
15
16
17
18
19
20
21
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
Q14
Q13
GND
Q12
Q11
V
V
CC
CC
D8
GND
D7
Q10
Q9
GND
Q8
D6
D5
Q7
D4 22
D3 23
V
CC
Q6
24
25
26
D2
D1
D0
Q5
GND
Q4
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7811
1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996
PN PACKAGE
(TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
V
1
2
3
4
60
59
58
57
56
NC
GND
GND
Q16
CC
V
CC
NC
Q3
Q2
5
6
Q17
55
54
53
GND
V
CC
7
8
9
OR
GND
Q1
Q0
V
CC
52
51
50
V
CC
HF
10
11
RESET
OE
IR
49
48
47
46
RDEN2
RDEN1
RDCLK
GND
GND
GND
AF/AE
12
13
14
15
16
17
18
19
V
CC
D17
45
44
WRTEN2
WRTEN1
D16
43
42
41
D15
NC
NC
WRTCLK
GND
20
NC
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
NC – No internal connection
description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ACT7811 is a 1024 × 18-bit FIFO for high speed and fast access times. It processes data
at rates up to 40 MHz and access times of 15 ns in a bit-parallel format. Data outputs are noninverting with
respect to the data inputs. Expansion is easily accomplished in both word width and word depth.
The SN74ACT7811 has normal input-bus-to-output-bus asynchronous operation. The special enable circuitry
adds the ability to synchronize independent read and write (interrupts or requests) to their respective system
clock.
The SN74ACT7811 is characterized for operation from 0°C to 70°C.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7811
1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996
†
logic symbol
Φ
FIFO 1024 × 18
SN74ACT7811
1
RESET
WRTCLK
RESET
WRTCLK
WRTEN1
WRTEN2
RDCLK
29
30
31
5
35
IN RDY
IR
&
36
33
66
WRTEN
HALF FULL
ALMOST FULL/EMPTY
OUT RDY
HF
AF/AE
OR
RDCLK
4
RDEN1
&
2
OE
RDEN2
DAF
EN1
RDEN
3
27
DEF ALMOST FULL
26
25
24
23
22
21
20
19
17
15
14
13
12
11
10
9
38
39
41
42
44
46
47
49
50
52
53
55
56
58
59
61
63
64
D0
D1
0
0
Q0
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
Data
Data
1
D8
Q8
D9
Q9
D10
D11
D12
D13
D14
D15
D16
D17
Q10
Q11
Q12
Q13
Q14
Q15
Q16
Q17
8
7
17
17
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the FN package.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7811
1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996
functional block diagram
OE
D0 – D17
Location 1
Location 2
Synchronous
RDCLK
Read
Read
Pointer
RDEN1
RDEN2
Control
1024 × 18 RAM
WRTCLK
WRTEN1
WRTEN2
Synchronous
Write
Write
Pointer
Location 1023
Location 1024
Control
Q0 – Q17
Register
Reset
Logic
RESET
DAF
Status-
Flag
Logic
OR
IR
HF
AF/AE
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7811
1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996
Terminal Functions
†
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Almost-full/almost-emptyflag. The AF/AE boundary isdefinedbythealmost-full/almost-emptyoffset
value (X). This value can beprogrammedduringresetorthedefaultvalueof256canbeused. AF/AE
is high when the FIFO contains (X + 1) or less words or (1025 – X) or more words. AF/AE is low when
the FIFO contains between (X +2) and (1024 - X) words.
Programming procedure for AF/AE – The almost-full/almost-empty flag is programmed during each
reset cycle. The almost-full/almost-empty offset value (X) is either a user-defined value or the default
of X = 256. Instructions to program AF/AE using both methods are as follows:
User-defined X
AF/AE
33
O
Step 1: Take DAF from high to low.
Step 2: If RESET is not already low, take RESET low.
Step 3: With DAF held low, take RESET high. This defines the AF/AE using X.
Step 4: To retain the current offset for the next reset, keep DAF low.
Default X
To redefine AF/AE using the default value of X = 256, hold DAF high during the reset cycle.
Define almost full. The high-to-low transition of DAF stores the binary value of data inputs as the
almost-full/almost-empty offset value (X). With DAF held low, a low pulse on RESET defines the
AF/AE flag using X.
DAF
27
I
Data inputs for 18-bit-wide data to be stored in the memory. Data lines D0–D8 also carry the
almost-full/almost-empty offset value (X) on a high-to-low transition of the DAF.
D0–D17
HF
26–19, 17, 15–7
36
I
Half-full flag. HF is high when the FIFO contains 513 or more words and is low when it contains 512
or less words.
O
Input-ready flag. IR is high when the FIFO is not full and low when the device is full. During reset, IR
isdrivenlowontherisingedgeofthesecondWRTCLKpulse. IRisthendrivenhighontherisingedge
of the second WRTCLK pulse after RESET goes high. After the FIFO is filled and IR is driven low,
IR is driven high on the second WRTCLK pulse after the first valid read.
IR
35
2
O
I
Output enable. The data-out (Q0–Q17) outputs are in the high-impedance state when OE is low. OE
must be high before the rising edge of RDCLK to read a word from memory.
OE
OR
Output-ready flag. OR is high when the FIFO is not empty and low when it is empty. During reset,
OR is set low on the rising edge of the third RDCLK pulse. OR is set high on the rising edge of the
third RDCLK pulse to occur after the first word is written into the FIFO. OR is set low on the rising
edge of the first RDCLK pulse after the last word is read.
66
O
38–39, 41–42, 44,
46–47, 49–50,
52–53, 55–56,
Data outputs. The first data word to be loaded into the FIFO is moved to Q0–Q17 on the rising edge
of the third RDCLK pulse to occur after the first valid write. The RDEN1 and RDEN2 inputs do not
affect this operation. Following data is unloaded on the rising edge of RDCLK when RDEN1, RDEN2,
OE, and the OR are high.
Q0–Q17
RDCLK
O
58–59, 61, 63–64
Read clock. Data is read out of memory on a low-to-high transition RDCLK if OR, OE, and RDEN1
and RDEN2 control inputs are high. RDCLK is a free-running clock and functions as the
synchronizing clock for all data transfers out of the FIFO. OR is also driven synchronously with
respect to RDCLK.
5
I
I
RDEN1,
RDEN2
4
3
Read enable. RDEN1 and RDEN2 must be high before a rising edge on RDCLK to read a word out
of memory. RDEN1 and RDEN2 are not used to read the first word stored in memory.
A reset is accomplished by taking RESET low and generating a minimum of four RDCLK and
WRTCLK cycles. This ensures that the internal read and write pointers are reset and OR, HF, and
IR are low and AF/AE is high. The FIFO must be reset upon power up. With DAF at a low level, a low
pulse on RESET defines the AF/AE status flag using the almost-full/almost-empty offset value (X),
where X is the value previously stored. With DAF at a high level, a low-level pulse on RESET defines
the AF/AE flag using the default value of X = 256.
RESET
1
I
†
Terminals listed are for the FN package.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7811
1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996
Terminal Functions (Continued)
†
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Write clock. Data is written into memory on a low-to-high transition of WRTCLK if IR, WRTEN1, and
WRTEN2 are high. WRTCLK is a free-running clock and functions as the synchronizing clock for all
data transfers into the FIFO. IR is also driven synchronously with respect to WRTCLK.
WRTCLK
29
I
Write enables. WRTEN1 and WRTEN2 must be high before a rising edge on WRTCLK for a word
to be written into memory. WRTEN1 and WRTEN2 do not affect the storage of the
almost-full/almost-empty offset value (X).
WRTEN1,
WRTEN2
30
31
I
†
Terminals listed are for the FN package.
RESET
DAF
Don’t Care
WRTCLK
WRTEN1
WRTEN2
D0 – D17
RDCLK
RDEN1
RDEN2
OE
1
2
3
4
1
2
Don’t Care
Don’t Care
Don’t Care
†
X
1
2
3
4
Don’t Care
Don’t Care
1
0
Q0 – Q17
Invalid
Don’t Care
OR
AF/AE
HF
Don’t Care
Don’t Care
Don’t Care
IR
Define the AF/AE Flag Using the
Value of X
Store the Value of D0–D8 as X
X is the binary value of D0–D8 only.
†
Figure 1. Reset Cycle: Define AF/AE Using the Value of X
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7811
1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996
RESET
DAF
Don’t Care
1
WRTCLK
WRTEN1
WRTEN2
D0 – D17
RDCLK
RDEN1
RDEN2
OE
2
3
4
1
2
Don’t Care
Don’t Care
Don’t Care
3 4
1
2
Don’t Care
Don’t Care
1
0
Q0 – Q17
OR
Invalid
Don’t Care
Don’t Care
Don’t Care
AF/AE
HF
Don’t Care
IR
Define the AF/AE Flag
Using the Value of X = 256
Figure 2. Reset Cycle: Define AF/AE Using the Default Value
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7811
1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996
1
0
RESET
DAF
Don’t Care
WRTCLK
WRTEN1
WRTEN2
1
0
W1
W2
W3
W4
W(X+2)
W513
W(1025–X)
W1025
D0–D17
RDCLK
1
2
3
1
0
RDEN1
RDEN2
OE
1
0
Invalid
W1
Q0–Q17
OR
AF/AE
HF
IR
Figure 3. Write Cycle
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7811
1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996
1
0
RESET
Don’t Care
DAF
WRTCLK
2
1
WRTEN1
WRTEN2
W1025
D0–D17
RDCLK
RDEN1
RDEN2
OE
W1
W1
W2
W3
W(X+1)
W(X+2)
W513
W514 W(1024–X) W(1025–X) W1024
W1025
Q0–Q17
OR
AF/AE
HF
IR
Figure 4. Read Cycle
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7811
1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN
4.5
2
MAX
UNIT
V
V
V
V
Supply voltage
5.5
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
V
IH
0.8
–8
16
70
V
IL
I
I
mA
mA
°C
OH
OL
T
A
0
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
‡
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
I
I
= – 8 mA
= 16 mA
2.4
OH
CC
CC
CC
CC
OH
0.5
±5
V
OL
OL
I
I
V =V
or 0 V
µA
µA
µA
mA
pF
pF
I
I
CC
=V
V
or 0 V
±5
OZ
O
CC
V =V
– 0.2 V or 0 V
400
1
I
CC
One input at 3.4 V,
V = 0 V, f = 1 MHz
§
I
CC
Other inputs at V
CC
or GND
C
C
4
8
i
I
V
O
= 0 V, f = 1 MHz
o
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
tested with outputs open
I
CC
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7811
1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996
timing requirements (see Figures 1 through 8)
′ACT7811-15
MIN MAX
′ACT7811-18
′ACT7811-20
′ACT7811-25
UNIT
MIN
35
MAX
MIN
28.5
14
MAX
MIN
16.7
20
MAX
f
Clock frequency
40
10
7
MHz
clock
D0–D17 high or low
WRTCLK high
WRTCLK low
RDCLK high
RDCLK low
12
8.5
11
10
17
10
7
14
23
8.5
11
10
17
10
10
14
23
t
w
Pulse duration
ns
DAF high
10
10
10
WRTEN1, WRTEN2
high or low
10
10
10
10
OE, RDEN1, RDEN2
high or low
10
5
10
5
10
5
10
5
D0–D17 before WRTCLK↑
WRTEN1, WRTEN2 high
before WRTCLK↑
5
5
5
5
OE, RDEN1, RDEN2 high
before RDCLK↑
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
Reset: RESET low before first
WRTCLK and RDCLK↑
t
su
Setup time
ns
Define AF/AE: D0–D8 before
DAF↓
Define AF/AE: DAF↓ before
RESET↑
Define AF/AE (default):
DAF high before RESET↑
5
1
1
5
1
1
5
1
1
5
1
1
D0–D17 after WRTCLK↑
WRTEN1, WRTEN2 high after
WRTCLK↑
OE, RDEN1, RDEN2 high after
RDCLK↑
1
0
1
0
1
1
0
1
0
1
1
0
1
0
1
1
0
1
0
1
Reset: RESET low after fourth
WRTCLK and RDCLK↑
t
h
Hold time
ns
Define AF/AE: D0–D8 after
DAF↓
Define AF/AE: DAF low after
RESET↑
Define AF/AE (default):
DAF high after RESET↑
†
To permit the clock pulse to be utilized for reset purposes
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7811
1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996
switching characteristics over recommended operating free-air temperature range (see Figures 9
and 10)
V
C
R
= 4.5 V to 5.5 V,
= 50 pF,
= 500 Ω,
CC
L
L
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
T
A
= 0°C to 70°C
′ACT7811-15
′ACT7811-18
′ACT7811-20
′ACT7811-25
MIN
TYP
MAX
MIN
35
4
MAX
MIN
28.5
4
MAX
MIN
16.7
4
MAX
WRTCLK or
RDCLK
f
40
4
MHz
ns
max
t
t
t
t
12
15
18
20
25
pd
Any Q
RDCLK↑
†
10.5
pd
WRTCLK↑
RDCLK↑
IR
2
2
6
6
6
6
3
4
2
2
10
10
20
20
19
19
19
21
11
14
2
2
6
6
6
6
3
4
2
2
12
12
22
22
21
21
21
23
11
14
2
2
6
6
6
6
3
4
2
2
14
14
24
24
23
23
23
25
11
14
2
2
6
6
6
6
3
4
2
2
16
16
26
26
25
25
25
27
11
14
ns
ns
pd
pd
OR
WRTCLK↑
RDCLK↑
t
pd
AF/AE
HF
ns
ns
ns
ns
t
t
t
t
t
t
WRTCLK↑
RDCLK↑
PLH
PHL
PLH
PHL
en
AF/AE
HF
RESET↓
OE
Any Q
dis
†
This parameter is measured with C = 30 pF (see Figure 5).
L
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 5 MHz
TYP
UNIT
C
Power dissipation capacitance per 1K bits
C
65
pF
pd
L
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7811
1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996
TYPICAL CHARACTERISTICS
Figure 2Figure 3Figure 4
TYPICAL PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE
18
17
16
15
V
= 5 V
= 25°C
CC
T
A
R
= 500 Ω
L
14
13
12
11
10
0
50
100
150
200
250
300
C
– Load Capacitance – pF
L
Figure 5
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7811
1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996
TYPICAL CHARACTERISTICS
TYPICAL POWER DISSIPATION CAPACITANCE
vs
SUPPLY VOLTAGE
68
f = 5 MHz
i
T
= 25°C
= 50 pF
A
C
67
66
65
64
63
62
L
4.5 4.6 4.7 4.8 4.9
5
5.1 5.2 5.3 5.4 5.5
V
CC
– Supply Voltage – V
Figure 6
calculating power dissipation
The maximum power dissipation (P ) of the SN74ACT7811 can be calculated by:
T
2
2
P = V
× [I
+ (N × ∆I
× dc)] + Σ (C × V
× f ) + Σ (C × V
× f )
CC o
T
CC
CC
CC
pd
CC
i
L
where:
I
N
∆ I
dc
C
C
=
=
=
=
=
=
=
=
power-down I
number of inputs driven by a TTL device
increase in supply current
duty cycle of inputs at a TTL high level of 3.4 V
power dissipation capacitance
output capacitive load
maximum
CC
CC
CC
pd
L
i
o
f
f
data input frequency
data output frequency
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7811
1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996
APPLICATION INFORMATION
expanding the SN74ACT7811
The SN74ACT7811 is expandable in width and depth. Expanding in word depth offers special timing
considerations:
After the first data word is loaded into the FIFO, the word is unloaded and the output-ready flag (OR) output
goes high after (N × 3) read-clock (RDCLK) cycles, where N is the number of devices used in depth
expansion.
After the FIFO is filled, the input-ready flag (IR) output goes low, the first word is unloaded, and the IR flag
output is driven high after (N × 2) write-clock cycles, where N is the number of devices used in depth
expansion.
CLOCK
SN74ACT7811
WRTCLK
SN74ACT7811
WRTCLK
WRTCLK
WRTEN1
WRTEN2
IR
RDCLK
OR
RDCLK
RDEN1
RDEN2
OR
RDCLK
RDEN1
RDEN2
OR
WRTEN1
WRTEN2
IR
WRTEN1
WRTEN2
IR
RDEN1
RDEN2
OE
5 V
OE
OE
Q0 – Q17
D0 – D17
D0 – D17
D0 – D17
Q0 – Q17
Q0 – Q17
Figure 7. Word-Depth Expansion: 2048 Words × 18 Bits, N = 2
SN74ACT7811
WRTCLK
WRTCLK
WRTEN1
WRTEN2
IR
RDCLK
RDEN1
RDEN2
OR
RDCLK
RDEN
WRTEN
OE
OE
D0 – D17
Q0 – Q17
D18 – D35
IR
Q18 – Q35
OR
SN74ACT7811
WRTCLK
WRTEN1
WRTEN2
IR
RDCLK
RDEN1
RDEN2
OR
OE
D0 – D17
D0 – D17
Q0 – Q17
Q0 – Q17
Figure 8. Word-Width Expansion: 1024 Words × 36 Bits
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7811
1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996
PARAMETER MEASUREMENT INFORMATION
3 V
0 V
Input
1.5 V
From Output
Under Test
t
pd
t
pd
R
= 500 Ω
C = 50 pF
L
L
3 V
0 V
1.5 V
Output
LOAD CIRCUIT
TOTEM-POLE OUTPUTS
Figure 9. Standard CMOS Outputs
3 V
7 V
1.5 V
1.5 V
Input
0 V
R
= R1 = R2
L
t
PZL
S1
t
PLZ
R1
≈ 3.5 V
From Output
Under Test
Test
Point
1.5 V
Output
Output
V
OL
0.3 V
C
R2
t
L
PHZ
t
PZH
V
OH
1.5 V
0.3 V
≈ 0 V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
S1
†
C
L
PARAMETER R1, R2
t
Open
Closed
Open
PZH
t
500 Ω
50 pF
en
t
PZL
PHZ
t
t
500 Ω
500 Ω
50 pF
50 pF
dis
t
Closed
Open
PLZ
t
pd
†
Includes probe and test fixture capacitanceFigure 9
Figure 10. 3-State Outputs (Any Q)
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
2-Mar-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
PLCC
LQFP
PLCC
PLCC
LQFP
LQFP
PLCC
LQFP
Drawing
SN74ACT7811-15FN
SN74ACT7811-15PN
SN74ACT7811-18FN
SN74ACT7811-18FNR
SN74ACT7811-18PN
SN74ACT7811-20PN
SN74ACT7811-25FN
SN74ACT7811-25PN
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
FN
68
80
68
68
80
80
68
80
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
PN
FN
FN
PN
PN
FN
PN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74ACT7811 :
Military: SN54ACT7811
•
NOTE: Qualified Version Definitions:
Military - QML certified for Military and Defense Applications
•
Addendum-Page 1
MECHANICAL DATA
MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996
PN (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
60
M
0,08
41
61
40
0,13 NOM
80
21
1
20
Gage Plane
9,50 TYP
0,25
12,20
SQ
11,80
0,05 MIN
0°–7°
14,20
SQ
13,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040135 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPLC004A – OCTOBER 1994
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
D
0.090 (2,29)
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
18
D2/E2
D2/E2
E
E1
8
14
0.021 (0,53)
0.013 (0,33)
0.050 (1,27)
9
13
0.007 (0,18)
M
0.008 (0,20) NOM
D/E
D1/E1
D2/E2
NO. OF
PINS
**
MIN
0.385 (9,78)
MAX
MIN
MAX
MIN
MAX
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.191 (4,85)
0.291 (7,39)
0.341 (8,66)
0.169 (4,29)
0.219 (5,56)
0.319 (8,10)
0.369 (9,37)
20
28
44
52
68
84
0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)
0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)
0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)
0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)
1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)
4040005/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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