SN74ABT821ADWRE4 [TI]
ABT SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, PLASTIC, SO-24;
| 型号： | SN74ABT821ADWRE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ABT SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, PLASTIC, SO-24 驱动 信息通信管理 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总19页 (文件大小：733K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ABT821, SN74ABT821A
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS193E – FEBRUARY 1991 – REVISED MAY 1997
SN54ABT821 . . . JT OR W PACKAGE
SN74ABT821A . . . DB, DW, OR NT PACKAGE
(TOP VIEW)
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015
OE
1D
2D
3D
4D
5D
6D
7D
8D
1
2
3
4
5
6
7
8
9
24
V
CC
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
23 1Q
22 2Q
21 3Q
20 4Q
19 5Q
18 6Q
17 7Q
16 8Q
15 9Q
14 10Q
13 CLK
Typical V
(Output Ground Bounce) < 1 V
OLP
at V
= 5 V, T = 25°C
CC
A
High-Impedance State During Power Up
and Power Down
High-Drive Outputs (–32-mA I , 64-mA I
OH
)
OL
Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages, Ceramic Chip
Carriers (FK), Ceramic Flat (W) Package,
and Plastic (NT) and Ceramic (JT) DIPs
9D 10
10D 11
GND 12
SN54ABT821 . . . FK PACKAGE
(TOP VIEW)
description
These 10-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing wider buffer
registers, I/O ports, bidirectional bus drivers with
parity, and working registers.
4
3
2
1
28 27 26
25
3D
4D
5D
NC
6D
7D
8D
3Q
4Q
5Q
NC
6Q
7Q
8Q
5
24
23
22
21
20
19
6
7
8
The ten flip-flops are edge-triggered D-type
flip-flops. On the positive transition of the clock
(CLK) input, the devices provide true data at the
Q outputs.
9
10
11
12 13 14 15 16 17 18
A buffered output-enable (OE) input can be used
to place the ten outputs in either a normal logic
state (high or low logic levels) or a high-impe-
dance state. In the high-impedance state, the
outputs neither load nor drive the bus lines
significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines without need for interface or pullup
components.
NC – No internal connection
OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can
be entered while the outputs are in the high-impedance state.
When V
is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V
the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup resistor;
CC
The SN54ABT821 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT821A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT821, SN74ABT821A
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS193E – FEBRUARY 1991 – REVISED MAY 1997
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
OE
L
CLK
D
H
L
↑
↑
H
L
L
L
H or L
X
X
X
Q
0
H
Z
†
logic symbol
1
EN
C2
OE
13
CLK
2
23
22
21
20
19
18
17
16
15
1D
2D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
3
2D
4
3D
5
4D
6
5D
7
6D
8
7D
9
8D
10
9D
11
14
10D
10Q
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DB, DW, JT, NT, and W packages.
logic diagram (positive logic)
1
OE
13
CLK
C1
23
1Q
2
1D
1D
To Nine Other Channels
Pin numbers shown are for the DB, DW, JT, NT, and W packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT821, SN74ABT821A
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS193E – FEBRUARY 1991 – REVISED MAY 1997
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high or power-off state, V
. . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I : SN54ABT821 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74ABT821A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.
recommended operating conditions (see Note 3)
SN54ABT821 SN74ABT821A
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
0.8
V
IL
0
V
CC
0
V
CC
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
–24
48
–32
64
mA
mA
ns/V
µs/V
°C
OH
OL
∆t/∆v
∆t/∆V
10
10
200
–55
200
–40
CC
T
Operating free-air temperature
125
85
A
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT821, SN74ABT821A
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS193E – FEBRUARY 1991 – REVISED MAY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54ABT821 SN74ABT821A
A
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
MIN
MAX
MIN
MAX
V
V
V
V
= 4.5 V,
= 4.5 V,
= 5 V,
I = –18 mA
–1.2
–1.2
–1.2
V
IK
CC
CC
CC
I
I
I
I
I
I
I
= –3 mA
= –3 mA
= –24 mA
= –32 mA
= 48 mA
= 64 mA
2.5
3
2.5
3
2.5
3
OH
OH
OH
OH
OL
OL
V
OH
V
2
2
V
= 4.5 V
= 4.5 V
CC
CC
2*
2
0.55
0.55
V
V
V
V
OL
0.55*
0.55
100
mV
µA
µA
µA
µA
µA
µA
µA
mA
µA
mA
µA
hys
I
I
I
I
I
I
I
I
V
CC
V
CC
V
CC
= 0 to 5.5 V,
V = V or GND
I CC
±1
±50*
±50*
10
±1
±1
±50
±50
10
I
‡
‡
= 0 to 2.1 V, V = 0.5 to 2.7 V, OE = X
OZPU
OZPD
OZH
OZL
off
O
= 2.1 V to 0, V = 0.5 to 2.7 V, OE = X
O
V
CC
= 2.1 V to 5.5 V, V = 2.7 V, OE ≥ 2 V
10
O
V
CC
= 2.1 V to 5.5 V, V = 0.5 V, OE ≥ 2 V
–10
±100
50
–10
–10
±100
50
O
V
= 0,
V or V ≤ 4.5 V
I O
CC
CC
CC
V
V
= 5.5 V, V = 5.5 V
O
Outputs high
= 2.5 V
50
–180
250
38
CEX
§
= 5.5 V,
V
O
–50
–100
1
–180
250
38
–50
–50
–180
250
38
O
Outputs high
Outputs low
V
= 5.5 V, I = 0,
O
or GND
CC
CC
I
24
CC
V = V
I
Outputs disabled
0.5
250
250
250
V
= 5.5 V, One input at 3.4 V,
CC
Other inputs at V
¶
1.5
1.5
1.5
mA
∆I
CC
or GND
CC
V = 2.5 V or 0.5 V
C
C
3.5
7.5
pF
pF
i
I
V
O
= 2.5 V or 0.5 V
o
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
‡
§
¶
All typical values are at V
= 5 V.
CC
This parameter is characterized, but not production tested.
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V or GND.
CC
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
V
T
= 5 V,
= 25°C
CC
A
SN54ABT821 SN74ABT821A
UNIT
MIN
0
MAX
MIN
0
MAX
MIN
0
MAX
f
t
Clock frequency
125
125
125
MHz
ns
clock
High
Low
2.9
3.8
2.1
1.3
2.9
3.8
2.1
1.3
2.9
3.8
2.1
1.3
Pulse duration, CLK high or low
w
t
t
Setup time, data before CLK↑
Hold time, data after CLK↑
ns
ns
su
h
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT821, SN74ABT821A
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS193E – FEBRUARY 1991 – REVISED MAY 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
SN54ABT821
= 5 V,
FROM
(INPUT)
TO
(OUTPUT)
V
CC
A
PARAMETER
UNIT
T
= 25°C
MIN
MAX
MIN
TYP
MAX
f
t
t
t
t
t
t
125
125
MHz
ns
max
PLH
PHL
PZH
PZL
PHZ
PLZ
†
†
1.6
2.1
4.1
4.6
3
5.6
6.2
4.5
5.6
6.2
6.1
1.6
2.1
6.9
6.9
6
CLK
OE
Q
Q
Q
†
†
1
1
ns
ns
2.2
2.7
4.1
4.7
4.6
2.2
2.7
6.5
7
OE
†
1.7
†
1.7
7
†
This data sheet limit may vary among suppliers.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
SN74ABT821A
= 5 V,
FROM
(INPUT)
TO
(OUTPUT)
V
CC
A
PARAMETER
UNIT
T
= 25°C
MIN
MAX
MIN
TYP
MAX
f
t
t
t
t
t
t
125
125
MHz
ns
max
PLH
PHL
PZH
PZL
PHZ
PLZ
†
†
1.6
2.3
4.1
4.6
3
5.6
6.2
4.5
5.6
6.2
6.1
1.6
2.3
6.2
6.7
5.8
6.3
6.7
6.5
CLK
Q
Q
Q
†
†
1
1
ns
ns
OE
OE
2.2
2.7
4.1
4.7
4.6
2.2
2.7
†
1.7
†
1.7
†
This data sheet limit may vary among suppliers.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT821, SN74ABT821A
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS193E – FEBRUARY 1991 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
7 V
Open
TEST
/t
S1
S1
500 Ω
From Output
Under Test
t
Open
7 V
PLH PHL
GND
t
/t
PLZ PZL
C
= 50 pF
t
/t
Open
L
PHZ PZH
500 Ω
(see Note A)
3 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
PZL
t
t
t
PHL
PLH
PHL
t
Output
Waveform 1
S1 at 7 V
PLZ
3.5 V
V
V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
PHZ
t
PLH
t
PZH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
– 0.3 V
OH
1.5 V
1.5 V
Output
≈ 0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
5962-9469101Q3A
ACTIVE
LCCC
FK
28
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
5962-
9469101Q3A
SNJ54
ABT821FK
5962-9469101QKA
5962-9469101QLA
ACTIVE
ACTIVE
CFP
W
24
24
1
1
TBD
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
5962-9469101QK
A
SNJ54ABT821W
CDIP
JT
5962-9469101QL
A
SNJ54ABT821JT
SN74ABT821ADBLE
SN74ABT821ADBR
OBSOLETE
ACTIVE
SSOP
SSOP
DB
DB
24
24
Call TI
Call TI
-40 to 85
-40 to 85
2000
2000
2000
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
AB821A
SN74ABT821ADBRE4
SN74ABT821ADBRG4
SN74ABT821ADW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
LCCC
DB
DB
24
24
24
24
24
24
24
24
24
24
28
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
POST-PLATE
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-55 to 125
AB821A
Green (RoHS
& no Sb/Br)
AB821A
DW
DW
DW
DW
DW
DW
NT
Green (RoHS
& no Sb/Br)
ABT821A
SN74ABT821ADWE4
SN74ABT821ADWG4
SN74ABT821ADWR
SN74ABT821ADWRE4
SN74ABT821ADWRG4
SN74ABT821ANT
25
Green (RoHS
& no Sb/Br)
ABT821A
25
Green (RoHS
& no Sb/Br)
ABT821A
2000
2000
2000
15
Green (RoHS
& no Sb/Br)
ABT821A
Green (RoHS
& no Sb/Br)
ABT821A
Green (RoHS
& no Sb/Br)
ABT821A
Pb-Free
(RoHS)
SN74ABT821ANT
SN74ABT821ANT
SN74ABT821ANTE4
SNJ54ABT821FK
NT
15
Pb-Free
(RoHS)
N / A for Pkg Type
FK
1
TBD
N / A for Pkg Type
5962-
9469101Q3A
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
SNJ54
ABT821FK
SNJ54ABT821JT
SNJ54ABT821W
ACTIVE
ACTIVE
CDIP
CFP
JT
W
24
24
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
5962-9469101QL
A
SNJ54ABT821JT
1
5962-9469101QK
A
SNJ54ABT821W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
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Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
OTHER QUALIFIED VERSIONS OF SN54ABT821 :
Catalog: SN74ABT821
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74ABT821ADBR
SN74ABT821ADWR
SSOP
SOIC
DB
24
24
2000
2000
330.0
330.0
16.4
24.4
8.2
8.8
2.5
2.7
12.0
12.0
16.0
24.0
Q1
Q1
DW
10.75 15.7
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74ABT821ADBR
SN74ABT821ADWR
SSOP
SOIC
DB
24
24
2000
2000
367.0
367.0
367.0
367.0
38.0
45.0
DW
Pack Materials-Page 2
MECHANICAL DATA
MCER004A – JANUARY 1995 – REVISED JANUARY 1997
JT (R-GDIP-T**)
CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
PINS **
A
24
28
DIM
13
24
1.280
(32,51) (37,08)
1.460
A MAX
1.240
(31,50) (36,58)
1.440
B
A MIN
B MAX
B MIN
0.300
(7,62)
0.291
(7,39)
1
12
0.070 (1,78)
0.030 (0,76)
0.245
(6,22)
0.285
(7,24)
0.320 (8,13)
0.290 (7,37)
0.015 (0,38) MIN
0.100 (2,54) MAX
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.014 (0,36)
0.008 (0,20)
0.100 (2,54)
4040110/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MCFP007 – OCTOBER 1994
W (R-GDFP-F24)
CERAMIC DUAL FLATPACK
0.375 (9,53)
0.340 (8,64)
Base and Seating Plane
0.006 (0,15)
0.004 (0,10)
0.045 (1,14)
0.026 (0,66)
0.090 (2,29)
0.045 (1,14)
0.395 (10,03)
0.360 (9,14)
0.360 (9,14)
0.240 (6,10)
0.360 (9,14)
0.240 (6,10)
0.019 (0,48)
0.015 (0,38)
1
24
0.050 (1,27)
0.640 (16,26)
0.490 (12,45)
0.030 (0,76)
0.015 (0,38)
12
13
30° TYP
1.115 (28,32)
0.840 (21,34)
4040180-5/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD
E. Index point is provided on cap for terminal identification only.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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