SN74ABT821ANSR [TI]
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| 型号： | SN74ABT821ANSR |
| 厂家： | 
TEXAS INSTRUMENTS |
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SN54ABT821, SN74ABT821A
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS193E – FEBRUARY 1991 – REVISED MAY 1997
SN54ABT821 . . . JT OR W PACKAGE
SN74ABT821A . . . DB, DW, OR NT PACKAGE
(TOP VIEW)
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015
OE
1D
2D
3D
4D
5D
6D
7D
8D
1
2
3
4
5
6
7
8
9
24
V
CC
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
23 1Q
22 2Q
21 3Q
20 4Q
19 5Q
18 6Q
17 7Q
16 8Q
15 9Q
14 10Q
13 CLK
Typical V
(Output Ground Bounce) < 1 V
OLP
at V
= 5 V, T = 25°C
CC
A
High-Impedance State During Power Up
and Power Down
High-Drive Outputs (–32-mA I , 64-mA I
OH
)
OL
Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages, Ceramic Chip
Carriers (FK), Ceramic Flat (W) Package,
and Plastic (NT) and Ceramic (JT) DIPs
9D 10
10D 11
GND 12
SN54ABT821 . . . FK PACKAGE
(TOP VIEW)
description
These 10-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing wider buffer
registers, I/O ports, bidirectional bus drivers with
parity, and working registers.
4
3
2
1
28 27 26
25
3D
4D
5D
NC
6D
7D
8D
3Q
4Q
5Q
NC
6Q
7Q
8Q
5
24
23
22
21
20
19
6
7
8
The ten flip-flops are edge-triggered D-type
flip-flops. On the positive transition of the clock
(CLK) input, the devices provide true data at the
Q outputs.
9
10
11
12 13 14 15 16 17 18
A buffered output-enable (OE) input can be used
to place the ten outputs in either a normal logic
state (high or low logic levels) or a high-impe-
dance state. In the high-impedance state, the
outputs neither load nor drive the bus lines
significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines without need for interface or pullup
components.
NC – No internal connection
OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can
be entered while the outputs are in the high-impedance state.
When V
is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V
the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup resistor;
CC
The SN54ABT821 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT821A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT821, SN74ABT821A
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS193E – FEBRUARY 1991 – REVISED MAY 1997
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
OE
L
CLK
D
H
L
↑
↑
H
L
L
L
H or L
X
X
X
Q
0
H
Z
†
logic symbol
1
EN
C2
OE
13
CLK
2
23
22
21
20
19
18
17
16
15
1D
2D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
3
2D
4
3D
5
4D
6
5D
7
6D
8
7D
9
8D
10
9D
11
14
10D
10Q
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DB, DW, JT, NT, and W packages.
logic diagram (positive logic)
1
OE
13
CLK
C1
23
1Q
2
1D
1D
To Nine Other Channels
Pin numbers shown are for the DB, DW, JT, NT, and W packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT821, SN74ABT821A
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS193E – FEBRUARY 1991 – REVISED MAY 1997
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high or power-off state, V
. . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I : SN54ABT821 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74ABT821A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.
recommended operating conditions (see Note 3)
SN54ABT821 SN74ABT821A
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
0.8
V
IL
0
V
CC
0
V
CC
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
–24
48
–32
64
mA
mA
ns/V
µs/V
°C
OH
OL
∆t/∆v
∆t/∆V
10
10
200
–55
200
–40
CC
T
Operating free-air temperature
125
85
A
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT821, SN74ABT821A
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS193E – FEBRUARY 1991 – REVISED MAY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54ABT821 SN74ABT821A
A
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
MIN
MAX
MIN
MAX
V
V
V
V
= 4.5 V,
= 4.5 V,
= 5 V,
I = –18 mA
–1.2
–1.2
–1.2
V
IK
CC
CC
CC
I
I
I
I
I
I
I
= –3 mA
= –3 mA
= –24 mA
= –32 mA
= 48 mA
= 64 mA
2.5
3
2.5
3
2.5
3
OH
OH
OH
OH
OL
OL
V
OH
V
2
2
V
= 4.5 V
= 4.5 V
CC
CC
2*
2
0.55
0.55
V
V
V
V
OL
0.55*
0.55
100
mV
µA
µA
µA
µA
µA
µA
µA
mA
µA
mA
µA
hys
I
I
I
I
I
I
I
I
V
CC
V
CC
V
CC
= 0 to 5.5 V,
V = V or GND
I CC
±1
±50*
±50*
10
±1
±1
±50
±50
10
I
‡
‡
= 0 to 2.1 V, V = 0.5 to 2.7 V, OE = X
OZPU
OZPD
OZH
OZL
off
O
= 2.1 V to 0, V = 0.5 to 2.7 V, OE = X
O
V
CC
= 2.1 V to 5.5 V, V = 2.7 V, OE ≥ 2 V
10
O
V
CC
= 2.1 V to 5.5 V, V = 0.5 V, OE ≥ 2 V
–10
±100
50
–10
–10
±100
50
O
V
= 0,
V or V ≤ 4.5 V
I O
CC
CC
CC
V
V
= 5.5 V, V = 5.5 V
O
Outputs high
= 2.5 V
50
–180
250
38
CEX
§
= 5.5 V,
V
O
–50
–100
1
–180
250
38
–50
–50
–180
250
38
O
Outputs high
Outputs low
V
= 5.5 V, I = 0,
O
or GND
CC
CC
I
24
CC
V = V
I
Outputs disabled
0.5
250
250
250
V
= 5.5 V, One input at 3.4 V,
CC
Other inputs at V
¶
1.5
1.5
1.5
mA
∆I
CC
or GND
CC
V = 2.5 V or 0.5 V
C
C
3.5
7.5
pF
pF
i
I
V
O
= 2.5 V or 0.5 V
o
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
‡
§
¶
All typical values are at V
= 5 V.
CC
This parameter is characterized, but not production tested.
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V or GND.
CC
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
V
T
= 5 V,
= 25°C
CC
A
SN54ABT821 SN74ABT821A
UNIT
MIN
0
MAX
MIN
0
MAX
MIN
0
MAX
f
t
Clock frequency
125
125
125
MHz
ns
clock
High
Low
2.9
3.8
2.1
1.3
2.9
3.8
2.1
1.3
2.9
3.8
2.1
1.3
Pulse duration, CLK high or low
w
t
t
Setup time, data before CLK↑
Hold time, data after CLK↑
ns
ns
su
h
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT821, SN74ABT821A
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS193E – FEBRUARY 1991 – REVISED MAY 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
SN54ABT821
= 5 V,
FROM
(INPUT)
TO
(OUTPUT)
V
CC
A
PARAMETER
UNIT
T
= 25°C
MIN
MAX
MIN
TYP
MAX
f
t
t
t
t
t
t
125
125
MHz
ns
max
PLH
PHL
PZH
PZL
PHZ
PLZ
†
†
1.6
2.1
4.1
4.6
3
5.6
6.2
4.5
5.6
6.2
6.1
1.6
2.1
6.9
6.9
6
CLK
OE
Q
Q
Q
†
†
1
1
ns
ns
2.2
2.7
4.1
4.7
4.6
2.2
2.7
6.5
7
OE
†
1.7
†
1.7
7
†
This data sheet limit may vary among suppliers.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
SN74ABT821A
= 5 V,
FROM
(INPUT)
TO
(OUTPUT)
V
CC
A
PARAMETER
UNIT
T
= 25°C
MIN
MAX
MIN
TYP
MAX
f
t
t
t
t
t
t
125
125
MHz
ns
max
PLH
PHL
PZH
PZL
PHZ
PLZ
†
†
1.6
2.3
4.1
4.6
3
5.6
6.2
4.5
5.6
6.2
6.1
1.6
2.3
6.2
6.7
5.8
6.3
6.7
6.5
CLK
Q
Q
Q
†
†
1
1
ns
ns
OE
OE
2.2
2.7
4.1
4.7
4.6
2.2
2.7
†
1.7
†
1.7
†
This data sheet limit may vary among suppliers.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT821, SN74ABT821A
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS193E – FEBRUARY 1991 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
7 V
Open
TEST
/t
S1
S1
500 Ω
From Output
Under Test
t
Open
7 V
PLH PHL
GND
t
/t
PLZ PZL
C
= 50 pF
t
/t
Open
L
PHZ PZH
500 Ω
(see Note A)
3 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
PZL
t
t
t
PHL
PLH
PHL
t
Output
Waveform 1
S1 at 7 V
PLZ
3.5 V
V
V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
PHZ
t
PLH
t
PZH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
– 0.3 V
OH
1.5 V
1.5 V
Output
≈ 0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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safeguards must be provided by the customer to minimize inherent or procedural hazards.
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Copyright 1998, Texas Instruments Incorporated
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