SN74ABT16470DLRG4 [TI]
ABT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 0.300 INCH, PLASTIC, SSOP-56;
| 型号： | SN74ABT16470DLRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ABT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 0.300 INCH, PLASTIC, SSOP-56 信息通信管理 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总9页 (文件大小：146K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ABT16470, SN74ABT16470
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS085E – FEBRUARY 1991 – REVISED MAY 1997
SN54ABT16470 . . . WD PACKAGE
SN74ABT16470 . . . DGG OR DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
1OEAB
1CLKAB
1CLKENAB
GND
1OEBA
1CLKBA
1CLKENBA
GND
1B1
1B2
1
2
3
4
5
6
7
8
9
56
55
54
53
52
51
50
49
48
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
Typical V
(Output Ground Bounce) < 1 V
OLP
1A1
1A2
at V
= 5 V, T = 25°C
CC
A
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
CC
V
V
CC
CC
1A3
1A4
1B3
1B4
Flow-Through Architecture Optimizes PCB
Layout
1A5 10
GND
1A6
47 1B5
High-Drive Outputs (–32-mA I , 64-mA I
OH
)
OL
GND
1B6
11
12
46
45
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
1A7 13
1A8 14
2A1 15
2A2 16
2A3 17
GND 18
2A4 19
2A5 20
2A6 21
44 1B7
43 1B8
42 2B1
41 2B2
40 2B3
39 GND
38 2B4
37 2B5
36 2B6
description
The ’ABT16470 are 16-bit registered transceivers
that contain two sets of D-type flip-flops for
temporary storage of data flowing in either
direction. The’ABT16470canbeusedastwo8-bit
transceivers or one 16-bit transceiver. Separate
clock (CLKAB or CLKBA) and output-enable
(OEAB or OEBA) inputs are provided for each
register to permit independent control in either
direction of data flow.
V
22
35
V
CC
CC
2A7 23
34 2B7
2A8 24
33 2B8
GND 25
32 GND
2CLKENAB 26
2CLKAB 27
2OEAB 28
31 2CLKENBA
30 2CLKBA
29 2OEBA
To avoid false clocking of the flip-flops, clock
enable(CLKEN) should not be switched from high
to low while CLK is high.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16470 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16470 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16470, SN74ABT16470
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS085E – FEBRUARY 1991 – REVISED MAY 1997
†
FUNCTION TABLE
INPUTS
OUTPUT
B
CLKAB
A
CLKENAB
OEAB
H
X
L
L
L
X
X
L
↑
X
H
L
X
X
X
L
Z
Z
‡
B
0
L
L
↑
L
H
H
†
A-to-B data flow is shown: B-to-A flow is similar but uses
CLKENBA, CLKBA, and OEBA.
Output level before the indicated steady-state input
conditions were established
‡
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16470, SN74ABT16470
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS085E – FEBRUARY 1991 – REVISED MAY 1997
†
logic symbol
56
54
55
1EN3
G1
1OEBA
1CLKENBA
1CLKBA
1C5
2EN4
G2
1
1OEAB
1CLKENAB
1CLKAB
3
2
2C6
7EN9
G7
29
31
2OEBA
2CLKENBA
2CLKBA
30
28
26
27
7C11
8EN10
G8
2OEAB
2CLKENAB
2CLKAB
8C12
5
52
1
1
1A1
5D
4
1B1
6D
6
51
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
1B2
49
8
1B3
48
9
1B4
47
10
12
13
14
15
1B5
45
1B6
44
1B7
43
1B8
42
1
1
11D
10
2B1
12D
16
17
19
20
21
23
24
41
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2B2
40
2B3
38
2B4
37
2B5
36
2B6
34
2B7
33
2B8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16470, SN74ABT16470
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS085E – FEBRUARY 1991 – REVISED MAY 1997
logic diagram (positive logic)
56
1OEBA
54
1CLKENBA
55
1CLKBA
1
1OEAB
3
1CLKENAB
2
1CLKAB
C1
1D
5
52
1A1
1B1
C1
1D
To Seven Other Channels
29
2OEBA
31
2CLKENBA
30
2CLKBA
28
2OEAB
26
2CLKENAB
27
2CLKAB
C1
1D
15
42
2A1
2B1
C1
1D
To Seven Other Channels
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16470, SN74ABT16470
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS085E – FEBRUARY 1991 – REVISED MAY 1997
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high or power-off state, V
. . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I : SN54ABT16470 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74ABT16470 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
JA
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
recommended operating conditions (see Note 3)
SN54ABT16470 SN74ABT16470
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
0.8
V
IL
0
V
0
V
CC
V
I
CC
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
–24
48
–32
64
mA
mA
ns/V
°C
OH
OL
∆t/∆v
Outputs enabled
10
10
T
–55
125
–40
85
A
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16470, SN74ABT16470
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS085E – FEBRUARY 1991 – REVISED MAY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54ABT16470 SN74ABT16470
A
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
MIN
MAX
MIN
MAX
V
V
V
V
V
= 4.5 V,
I = –18 mA
–1.2
–1.2
–1.2
V
IK
CC
CC
CC
I
= 4.5 V,
= 5 V,
I
I
I
I
I
I
= –3 mA
= –3 mA
= –24 mA
= –32 mA
= 48 mA
= 64 mA
2.5
3
2.5
3
2.5
3
OH
OH
OH
OH
OL
OL
V
OH
2
2
V
= 4.5 V
= 4.5 V
CC
CC
2*
2
0.55
0.55
V
V
V
V
OL
0.55*
0.55
100
mV
µA
hys
Control inputs
A or B ports
±1
±100
50
±1
±100
50
±1
±100
50
I
I
V
CC
= 5.5 V,
V = V
I
or GND
CC
‡
I
I
I
V
V
V
= 5.5 V,
= 5.5 V,
= 0,
V
V
= 2.7 V
= 0.5 V
µA
µA
µA
OZH
CC
CC
CC
CC
O
‡
–50
–50
–50
OZL
off
O
V or V ≤ 4.5 V
±100
±100
I
O
V
V
= 5.5 V,
= 5.5 V
I
Outputs high
= 2.5 V
50
50
50
µA
CEX
O
§
I
O
V
CC
= 5.5 V,
V
O
–50
–100
–200
2
–50
–200
2
–50
–200
2
mA
Outputs high
Outputs low
V
I
= 5.5 V,
= 0,
CC
O
I
A or B ports
35
2
35
2
35
2
mA
CC
V = V
I
or GND
CC
Outputs disabled
V
= 5.5 V, One input at 3.4 V,
CC
Other inputs at V
¶
0.5
0.5
0.5
mA
∆I
CC
or GND
CC
Control inputs V = 2.5 V or 0.5 V
C
C
3
pF
pF
i
I
A or B ports
V
O
= 2.5 V or 0.5 V
8.5
io
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
‡
§
¶
All typical values are at V
= 5 V.
CC
and I
The parameters I
include the input leakage current.
OZL
OZH
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V or GND.
CC
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
V
T
= 5 V,
= 25°C
CC
A
SN54ABT16470 SN74ABT16470
UNIT
MIN
0
MAX
MIN
0
MAX
MIN
0
MAX
f
Clock frequency
150
150
150
MHz
ns
clock
#
Pulse duration, CLKAB or CLKBA high or low
Setup time, data before CLKAB↑ or CLKBA↑
Hold time, data after CLKAB↑ or CLKBA↑
3.3
4
3.3
4
3.3
4
t
t
t
w
ns
su
h
1
1
1
ns
#
This parameter is characterized, but not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16470, SN74ABT16470
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS085E – FEBRUARY 1991 – REVISED MAY 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
V
T
= 5 V,
= 25°C
CC
A
SN54ABT16470 SN74ABT16470
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
150
1.4
1.3
1
TYP
MAX
MIN
150
1.4
1.3
1
MAX
MIN
150
1.4
1.3
1
MAX
f
t
t
t
t
t
t
t
t
t
t
MHz
ns
max
PLH
PHL
PZH
PZL
PHZ
PLZ
PZH
PZL
PHZ
PLZ
3.1
3.2
3.1
3.6
3.7
3.3
3.4
3.9
3.9
3.6
4.8
4.6
4.3
5.8
4.9
4.8
4.6
6
5.1
5.1
5
4.9
4.9
4.9
6.8
5.5
5.3
5.7
7.2
5.8
5.4
CLK
A or B
A or B
A or B
A or B
A or B
ns
ns
ns
ns
OE
OE
1.2
1.9
1.6
1
1.2
1.9
1.6
1
6.9
6
1.2
1.9
1.6
1
5.4
5.8
7.3
6.2
5.5
CLKEN
CLKEN
1.2
1.7
1.5
1.2
1.7
1.5
1.2
1.7
1.5
5.2
5.3
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16470, SN74ABT16470
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS085E – FEBRUARY 1991 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
7 V
Open
TEST
/t
S1
S1
500 Ω
From Output
Under Test
t
Open
7 V
PLH PHL
GND
t
/t
PLZ PZL
C
= 50 pF
t
/t
Open
L
PHZ PZH
500 Ω
(see Note A)
3 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
PZL
t
t
t
PHL
PLH
PHL
t
PLZ
Output
Waveform 1
S1 at 7 V
3.5 V
V
V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
PHZ
t
PLH
t
PZH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
– 0.3 V
OH
1.5 V
1.5 V
Output
≈ 0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright 1998, Texas Instruments Incorporated
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