SN74ABT16500BDGGR [TI]
具有三态输出的 18 位通用总线收发器 | DGG | 56 | -40 to 85;
| 型号： | SN74ABT16500BDGGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有三态输出的 18 位通用总线收发器 | DGG | 56 | -40 to 85 驱动 信息通信管理 光电二极管 输出元件 逻辑集成电路 触发器 总线驱动器 总线收发器 |
| 文件： | 总9页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ABT16500B, SN74ABT16500B
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS057G – DECEMBER 1990 – REVISED MAY 1997
SN54ABT16500B . . . WD PACKAGE
SN74ABT16500B . . . DGG OR DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
OEAB
LEAB
A1
GND
A2
GND
CLKAB
B1
GND
B2
1
2
3
4
5
6
7
8
9
56
55
54
53
52
51
50
49
48
UBT (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
A3
B3
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015
V
V
CC
CC
A4
A5
B4
B5
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
A6 10
47 B6
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
GND
A7
GND
B7
11
12
46
45
= 5 V, T = 25°C
CC
A
High-Impedance State During Power Up
and Power Down
A8 13
A9 14
44 B8
43 B9
Flow-Through Architecture Optimizes PCB
Layout
A10 15
A11 16
A12 17
GND 18
A13 19
A14 20
A15 21
42 B10
41 B11
40 B12
39 GND
38 B13
37 B14
36 B15
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
V
22
35
V
CC
CC
description
A16 23
A17 24
34 B16
33 B17
These 18-bit universal bus transceivers combine
D-type latches and D-type flip-flops to allow data
flow in transparent, latched, and clocked modes.
GND 25
A18 26
32 GND
31 B18
OEBA 27
LEBA 28
30 CLKBA
29 GND
Data flow in each direction is controlled by
output-enable (OEAB and OEBA), latch-enable
(LEAB and LEBA), and clock (CLKAB and
CLKBA) inputs. For A-to-B data flow, the device
operates in the transparent mode when LEAB is
high. When LEAB is low, the A data is latched if
CLKAB is held at a high or low logic level. If LEAB
is low, the A data is stored in the latch/flip-flop on
the high-to-low transition of CLKAB. OEAB is
active-high. When OEAB is high, the outputs are
active. When OEAB is low, the outputs are in the
high-impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are
complementary (OEAB is active high and OEBA is active low).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC-ΙΙB, and UBT are trademarks of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16500B, SN74ABT16500B
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS057G – DECEMBER 1990 – REVISED MAY 1997
description (continued)
When V
is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V
through a pullup resistor
CC
and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by
the current-sinking/current-sourcing capability of the driver.
The SN54ABT16500B is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16500B is characterized for operation from –40°C to 85°C.
†
FUNCTION TABLE
INPUTS
OUTPUT
B
OEAB
LEAB
CLKAB
A
X
L
L
X
H
H
L
X
X
X
↓
Z
L
H
H
H
H
H
H
H
L
H
L
L
↓
H
X
X
H
‡
B
0
§
B
0
L
H
L
L
†
‡
§
A-to-B data flow is shown: B-to-A flow is similar but
uses OEBA, LEBA, and CLKBA.
Output level before the indicated steady-state input
conditions were established
Output level before the indicated steady-state input
conditions were established, provided that CLKAB
was low before LEAB went low
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16500B, SN74ABT16500B
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS057G – DECEMBER 1990 – REVISED MAY 1997
†
logic symbol
1
OEAB
CLKAB
LEAB
EN1
2C3
55
2
C3
G2
27
30
28
EN4
OEBA
CLKBA
LEBA
5C6
C6
G5
3
54
A1
3D
4
1
1
1
B1
6D
5
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
A2
A3
B2
6
B3
8
A4
B4
9
A5
B5
10
12
13
14
15
16
17
19
20
21
23
24
26
A6
B6
A7
B7
A8
B8
A9
B9
A10
A11
A12
A13
A14
A15
A16
A17
A18
B10
B11
B12
B13
B14
B15
B16
B17
B18
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16500B, SN74ABT16500B
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS057G – DECEMBER 1990 – REVISED MAY 1997
logic diagram (positive logic)
1
OEAB
55
CLKAB
2
LEAB
28
LEBA
30
CLKBA
27
OEBA
3
A1
1D
C1
54
B1
CLK
1D
C1
CLK
To 17 Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high or power-off state, V
. . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I : SN54ABT16500B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74ABT16500B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
JA
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16500B, SN74ABT16500B
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS057G – DECEMBER 1990 – REVISED MAY 1997
recommended operating conditions (see Note 3)
SN54ABT16500B SN74ABT16500B
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
0.8
V
IL
0
V
CC
0
V
CC
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
–24
48
–32
64
mA
mA
ns/V
µs/V
°C
OH
OL
∆t/∆v
∆t/∆V
Outputs enabled
10
10
200
–55
200
–40
CC
T
Operating free-air temperature
125
85
A
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16500B, SN74ABT16500B
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS057G – DECEMBER 1990 – REVISED MAY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54ABT16500B SN74ABT16500B
A
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
MIN
MAX
MIN
MAX
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 5 V,
I = –18 mA
–1.2
–1.2
–1.2
V
IK
CC
CC
CC
I
I
I
I
I
I
I
= –3 mA
= –3 mA
= –24 mA
= –32 mA
= 48 mA
= 64 mA
2.5
3
2.5
3
2.5
3
OH
OH
OH
OH
OL
OL
V
V
OH
2
2
V
= 4.5 V
= 4.5 V
CC
CC
2*
2
0.55
0.55
V
V
V
OL
0.55*
0.55
100
mV
hys
I
off
V
CC
= 0,
V or V ≤ 4.5 V
±100
±100
µA
I
O
V
V
= 5.5 V,
= 5.5 V
CC
O
I
Outputs high
50
50
50
µA
µA
CEX
I
Control
inputs
V
= 0 to 5.5 V, V = V
I
or GND
CC
±1
±1
±1
CC
CC
I
V
= 2.1 V to 5.5 V,
or GND
CC
A or B ports
±20
–180
±50
±20
–180
±50
±20
–180
±50
V = V
I
‡
I
I
V
CC
= 5.5 V,
V = 2.5 V
O
–50
–100
–50
–50
mA
O
V
V
= 0 to 2.1 V,
= 0.5 V to 2.7 V, OE or OE = X
CC
O
§
µA
OZPU
OZPD
V
V
= 2.1 V to 0,
= 0.5 V to 2.7 V, OE or OE = X
CC
O
§
±50
10
±50
10
±50
10
µA
µA
µA
I
I
I
V
CC
= 2.1 V to 5.5 V, V = 2.7 V,
O
¶
OZH
#
OE ≥ 2 V, OE ≤ 0.8 V
V
= 2.1 V to 5.5 V, V = 0.5 V,
O
CC
OE ≥ 2 V, OE ≤ 0.8 V
¶
–10
–10
–10
OZL
#
Outputs high
Outputs low
3
36
3
3
36
3
3
36
3
V
I
= 5.5 V,
CC
= 0,
I
A or B ports
mA
CC
O
V = V
I
or GND
CC
Outputs disabled
V
= 5.5 V, One input at 3.4 V,
CC
Other inputs at V
||
50
50
50
µA
∆I
CC
or GND
CC
Control
inputs
C
C
V = 2.5 V or 0.5 V
3
9
pF
pF
i
I
A or B ports
V
O
= 2.5 V or 0.5 V
io
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
‡
§
¶
#
||
All typical values are at V
= 5 V.
CC
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This parameter is characterized, but not production tested.
The parameters I
and I
include the input leakage current.
OZL
OZH
between 2.1 V and 4 V, OE should be less than or equal to 0.5 V to ensure a low state.
For V
CC
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16500B, SN74ABT16500B
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS057G – DECEMBER 1990 – REVISED MAY 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN54ABT16500B SN74ABT16500B
UNIT
MIN
MAX
MIN
MAX
f
t
Clock frequency
Pulse duration
0
150
0
150
MHz
ns
clock
LEAB or LEBA high
CLKAB or CLKBA high or low
A before CLKAB↓
2.5
3
2.5
3
†
w
3
3
3
3
B before CLKBA↓
t
Setup time
Hold time
ns
ns
su
h
1
1
CLK high
CLK low
A before LEAB↓ or B before LEBA↓
2.5
0
2.5
0
A after CLKAB↓ or B after CLKBA↓
A after LEAB↓ or B after LEBA↓
t
2
2
†
This parameter is characterized, but not production tested.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
V
T
= 5 V,
= 25°C
CC
A
SN54ABT16500B SN74ABT16500B
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
150
1
TYP
200
2.5
3.2
3.2
3.4
3.5
3.5
3.4
3.8
4.5
3.4
MAX
MIN
150
1
MAX
MIN
150
1
MAX
f
t
t
t
t
t
t
t
t
t
t
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
3.6
4.5
4.5
4.5
4.7
4.7
4.6
4.7
5.7
4.7
4.2
5.1
5.6
5.4
5.4
5.4
5.3
5.6
6.9
5.8
4
4.9
5
A or B
B or A
B or A
B or A
B or A
B or A
1
1
1
1
1
1
ns
ns
ns
ns
LEAB or LEBA
1
1
1
5
1
1
1
5.3
5.3
5.1
5.4
6.5
5.4
CLKAB or CLKBA
OEAB or OEBA
OEAB or OEBA
1
1
1
1
1
1
1.5
1.5
1.4
1.5
1.5
1.4
1.5
1.5
1.4
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16500B, SN74ABT16500B
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS057G – DECEMBER 1990 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
7 V
Open
TEST
/t
S1
S1
500 Ω
From Output
Under Test
t
Open
7 V
PLH PHL
GND
t
/t
PLZ PZL
C
= 50 pF
t
/t
Open
L
PHZ PZH
500 Ω
(see Note A)
3 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
PZL
t
t
t
PHL
PLH
PHL
t
PLZ
Output
Waveform 1
S1 at 7 V
3.5 V
V
V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
PHZ
t
PLH
t
PZH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
– 0.3 V
OH
1.5 V
1.5 V
Output
≈ 0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright 1998, Texas Instruments Incorporated
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