SN54LVT2952_14 [TI]

3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS;
SN54LVT2952_14
型号: SN54LVT2952_14
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

输出元件
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SN54LVT2952, SN74LVT2952  
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS  
WITH 3-STATE OUTPUTS  
SCBS152E – MAY 1992 – REVISED JULY 1995  
SN54LVT2952 . . . JT PACKAGE  
SN74LVT2952 . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low-Static Power  
Dissipation  
B8  
B7  
V
CC  
A8  
1
24  
23  
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V V  
2
)
CC  
B6  
B5  
B4  
3
22 A7  
21 A6  
20 A5  
Support Unregulated Battery Operation  
Down to 2.7 V  
4
5
6
19  
18  
17  
16  
15  
14  
13  
B3  
B2  
B1  
A4  
A3  
A2  
A1  
OEBA  
CLKBA  
CLKENBA  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
7
= 3.3 V, T = 25°C  
CC  
A
8
ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model  
(C = 200 pF, R = 0)  
9
OEAB  
CLKAB  
CLKENAB  
GND  
10  
11  
12  
Latch-Up Performance Exceeds 500 mA  
Per JEDEC Standard JESD-17  
SN54LVT2952 . . . FK PACKAGE  
(TOP VIEW)  
Bus-Hold Data Inputs Eliminate the Need  
for External Pullup Resistors  
Support Live Insertion  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK), and  
Ceramic (JT) DIPs  
4
3
2
1
28 27 26  
25  
5
B5  
B4  
B3  
NC  
B2  
A6  
6
24 A5  
23 A4  
22  
21  
20  
19  
7
8
NC  
A3  
A2  
A1  
9
description  
10  
11  
B1  
OEAB  
These octal bus transceivers and registers are  
designed specifically for low-voltage (3.3-V) V  
12 13 14 15 16 17 18  
CC  
operation, but with the capability to provide a TTL  
interface to a 5-V system environment.  
The ’LVT2952 consist of two 8-bit back-to-back  
registers that store data flowing in both directions  
between two bidirectional buses. Data on the A or  
B bus is stored in the registers on the low-to-high  
NC – No internal connection  
transition of the clock (CLKAB or CLKBA) input provided that the clock-enable (CLKENAB or CLKENBA) input  
is low. Taking the output-enable (OEAB or OEBA) input low accesses the data on either port.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
The SN74LVT2952 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count  
and functionality of standard small-outline packages in less than half the printed-circuit-board area.  
The SN54LVT2952 is characterized for operation over the full military temperature range of 55°C to 125°C.  
The SN74LVT2952 is characterized for operation from 40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1995, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54LVT2952, SN74LVT2952  
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS  
WITH 3-STATE OUTPUTS  
SCBS152E – MAY 1992 – REVISED JULY 1995  
FUNCTION TABLE  
INPUTS  
OUTPUT  
B
CLKENAB CLKAB OEAB  
A
H
X
L
X
L
L
L
L
H
X
X
L
B
B
0
0
H or L  
L
H
Z
L
H
X
X
X
A-to-B data flow is shown; B-to-A data flow is similar  
but uses CLKENBA, CLKBA, and OEBA.  
Level of B before the indicated steady-state input  
conditions were established  
§
logic symbol  
15  
EN3  
13  
OEBA  
CLKENBA  
CLKBA  
G1  
14  
1 C5  
9
EN4  
11  
OEAB  
CLKENAB  
CLKAB  
G2  
10  
2 C6  
8
16  
3
1
1
5D  
B1  
A1  
6D  
4
17  
18  
19  
20  
21  
22  
23  
7
6
5
4
3
2
1
A2  
A3  
A4  
A5  
A6  
A7  
A8  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
§
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
Pin numbers shown are for the DB, DW, JT, and PW packages.  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54LVT2952, SN74LVT2952  
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS  
WITH 3-STATE OUTPUTS  
SCBS152E – MAY 1992 – REVISED JULY 1995  
logic diagram (positive logic)  
11  
CLKENAB  
10  
CLKAB  
9
OEAB  
13  
CLKENBA  
14  
CLKBA  
15  
OEBA  
C1  
1D  
16  
8
B1  
A1  
C1  
1D  
To Seven Other Channels  
Pin numbers shown are for the DB, DW, JT, and PW packages.  
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54LVT2952, SN74LVT2952  
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS  
WITH 3-STATE OUTPUTS  
SCBS152E – MAY 1992 – REVISED JULY 1995  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage range, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V  
CC  
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V  
I
Voltage range applied to any output in the high state or power-off state, V (see Note 1) . . . . 0.5 V to 7 V  
O
Current into any output in the low state, I : SN54LVT2952 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA  
O
SN74LVT2952 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA  
Current into any output in the high state, I (see Note 2): SN54LVT2952 . . . . . . . . . . . . . . . . . . . . . . . . 48 mA  
O
SN74LVT2952 . . . . . . . . . . . . . . . . . . . . . . . . 64 mA  
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA  
IK  
OK  
I
Output clamp current, I  
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA  
O
Maximum power dissipation at T = 55°C (in still air) (see Note 3): DB package . . . . . . . . . . . . . . . . . . . 0.65 W  
A
DW package . . . . . . . . . . . . . . . . . . . 1.7 W  
PW package . . . . . . . . . . . . . . . . . . . 0.7 W  
Storage temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C  
stg  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.  
2. This current flows only when the output is in the high state and V > V  
.
CC  
O
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.  
Formoreinformation,refertothePackageThermalConsiderationsapplicationnoteinthe1994ABTAdvancedBiCMOSTechnology  
Data Book, literature number SCBD002B.  
recommended operating conditions (see Note 4)  
SN54LVT2952  
SN74LVT2952  
UNIT  
MIN  
2.7  
2
MAX  
MIN  
2.7  
2
MAX  
V
V
V
V
Supply voltage  
3.6  
3.6  
V
V
CC  
High-level input voltage  
Low-level input voltage  
Input voltage  
IH  
0.8  
5.5  
24  
48  
0.8  
5.5  
32  
64  
V
IL  
V
I
I
I
High-level output current  
Low-level output current  
Input transition rise or fall rate  
Operating free-air temperature  
mA  
mA  
ns/V  
°C  
OH  
OL  
t/v  
Outputs enabled  
10  
10  
T
A
55  
125  
40  
85  
NOTE 4: Unused control inputs must be held high or low to prevent them from floating.  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54LVT2952, SN74LVT2952  
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS  
WITH 3-STATE OUTPUTS  
SCBS152E – MAY 1992 – REVISED JULY 1995  
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
SN54LVT2952  
SN74LVT2952  
PARAMETER  
TEST CONDITIONS  
UNIT  
MIN TYP  
MAX  
MIN TYP  
MAX  
V
V
V
V
= 2.7 V,  
I = –18 mA  
–1.2  
–1.2  
V
IK  
CC  
CC  
CC  
I
= MIN to MAX ,  
= 2.7 V,  
I
I
I
I
I
I
I
I
I
I
= –100 µA  
= – 8 mA  
= – 24 mA  
= 32 mA  
= 100 µA  
= 24 mA  
= 16 mA  
= 32 mA  
= 48 mA  
= 64 mA  
V
0.2  
V
0.2  
OH  
OH  
OH  
OH  
OL  
OL  
OL  
OL  
OL  
OL  
CC  
2.4  
CC  
2.4  
V
OH  
V
V
2
V
= 3 V  
CC  
CC  
2
0.2  
0.5  
0.2  
0.5  
0.4  
0.5  
V
= 2.7 V  
0.4  
V
OL  
0.5  
V
CC  
= 3 V  
0.55  
0.55  
±1  
V
V
= 3.6 V,  
V = V  
I
or GND  
±1  
10  
CC  
CC  
Control inputs  
= 0 or MAX ,  
V = 5.5 V  
I
10  
CC  
I
I
V = 5.5 V  
I
20  
20  
µA  
§
V
CC  
= 3.6 V  
V = V  
I CC  
A or B ports  
5
5
V = 0  
10  
10  
±100  
I
I
I
V
V
= 0,  
V or V = 0 to 4.5 V  
I
µA  
µA  
off  
CC  
O
V = 0.8 V  
75  
75  
I
= 3 V  
A or B ports  
I(hold)  
CC  
V = 2 V  
I
–75  
–75  
I
I
V
V
= 3.6 V,  
= 3.6 V,  
V
= 3 V  
1
–1  
1
–1  
µA  
µA  
OZH  
CC  
O
O
V
= 0.5 V  
OZL  
CC  
Outputs high  
Outputs low  
Outputs disabled  
– 0.6 V,  
0.13  
8.8  
0.19  
12  
0.13  
8.8  
0.19  
12  
V
= 3.6 V,  
or GND  
CC  
I
= 0,  
CC  
O
I
mA  
CC  
V = V  
I
0.13  
0.19  
0.13  
0.19  
V
= 3 V to 3.6 V,  
One input at V  
CC  
or GND  
CC  
Other inputs at V  
I  
0.2  
0.2  
mA  
CC  
CC  
C
C
V = 3 V or 0  
4.5  
4.5  
pF  
pF  
i
I
V
O
= 3 V or 0  
11.5  
11.5  
io  
§
All typical values are at V  
= 3.3 V, T = 25°C.  
A
CC  
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.  
Unused terminals at V or GND  
CC  
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V  
or GND.  
CC  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54LVT2952, SN74LVT2952  
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS  
WITH 3-STATE OUTPUTS  
SCBS152E – MAY 1992 – REVISED JULY 1995  
timing requirement over recommended operating free-air temperature range (unless otherwise  
noted) (see Figure 1)  
SN54LVT2952  
= 3.3 V  
SN74LVT2952  
= 3.3 V  
V
V
CC  
± 0.3 V  
CC  
± 0.3 V  
V
= 2.7 V  
MAX  
V
= 2.7 V  
UNIT  
CC  
CC  
MIN  
MAX  
MIN  
MIN  
MAX  
MIN  
MAX  
f
t
Clock frequency  
Pulse duration  
150  
150  
MHz  
ns  
clock  
CLK high  
CLK low  
Data high  
Data low  
Data high  
Data low  
3.3  
3.3  
2.5  
2.5  
0.9  
2.4  
1.5  
2.5  
3.3  
3.3  
2.8  
3
w
2.6  
2.6  
0.9  
2.5  
1.5  
2.6  
2.9  
3.1  
0.8  
2.7  
0.7  
2.6  
Setup time, A or B before CLK↑  
Setup time, CE before CLK↑  
t
t
ns  
ns  
su  
0.8  
2.7  
0.7  
2.6  
Hold time, A or B after CLK↑  
Hold time, CE after CLK↑  
h
switching characteristics over recommended operating free-air temperature range, C = 50 pF  
L
(unless otherwise noted) (see Figure 1)  
SN54LVT2952  
= 3.3 V  
SN74LVT2952  
= 3.3 V  
FROM  
(INPUT)  
TO  
(OUTPUT)  
V
V
CC  
± 0.3 V  
CC  
± 0.3 V  
V
CC  
= 2.7 V  
MAX  
V
= 2.7 V  
MAX  
PARAMETER  
UNIT  
CC  
MIN  
MAX  
MIN  
MIN TYP  
MAX  
MIN  
150  
2.7  
2.7  
2.6  
2.9  
2.7  
1.8  
f
t
t
t
t
t
t
150  
MHz  
ns  
max  
PLH  
PHL  
PZH  
PZL  
PHZ  
PLZ  
1.3  
1.8  
1
6.4  
6.1  
6.3  
6.6  
7
2.7  
2.7  
2.6  
2.9  
2.7  
1.7  
7.4  
7
1.3  
1.8  
1
3.6  
3.7  
3.2  
3.2  
4.1  
3.3  
6.1  
6
7.1  
6.9  
6.7  
8
CLKBA or  
CLKAB  
A or B  
A or B  
A or B  
7.3  
8.2  
7.6  
6
5.6  
6.5  
6.3  
5.1  
OEBA or  
OEAB  
ns  
ns  
1.1  
1
1.2  
1
6.9  
5.3  
OEBA or  
OEAB  
1.6  
5.8  
1.6  
All typical values are at V  
= 3.3 V, T = 25°C.  
A
CC  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54LVT2952, SN74LVT2952  
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS  
WITH 3-STATE OUTPUTS  
SCBS152E – MAY 1992 – REVISED JULY 1995  
PARAMETER MEASUREMENT INFORMATION  
6 V  
TEST  
S1  
S1  
t
/t  
Open  
6 V  
500 Ω  
Open  
GND  
PLH PHL  
From Output  
Under Test  
t
/t  
PLZ PZL  
t
/t  
PHZ PZH  
GND  
C
= 50 pF  
L
500 Ω  
(see Note A)  
2.7 V  
0 V  
LOAD CIRCUIT FOR OUTPUTS  
1.5 V  
Timing Input  
Data Input  
t
w
t
t
h
su  
2.7 V  
0 V  
2.7 V  
0 V  
Input  
1.5 V  
1.5 V  
1.5 V  
1.5 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
2.7 V  
0 V  
2.7 V  
0 V  
Output  
Control  
1.5 V  
1.5 V  
t
Input  
1.5 V  
1.5 V  
t
PZL  
t
t
PHL  
PLH  
PLZ  
1.5 V  
Output  
Waveform 1  
S1 at 6 V  
V
V
3 V  
OH  
1.5 V  
1.5 V  
1.5 V  
Output  
V
V
+ 0.3 V  
– 0.3 V  
OL  
V
OL  
OL  
(see Note B)  
t
PHZ  
t
PLH  
t
t
PZH  
PHL  
Output  
Waveform 2  
S1 at GND  
V
OH  
V
V
OH  
OH  
1.5 V  
1.5 V  
Output  
(see Note B)  
0 V  
OL  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
INVERTING AND NONINVERTING OUTPUTS  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
LOW- AND HIGH-LEVEL ENABLING  
NOTES: A.  
C includes probe and jig capacitance.  
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 , t 2.5 ns, t 2.5 ns.  
O
r
f
D. The outputs are measured one at a time with one transition per measurement.  
Figure 1. Load Circuit and Voltage Waveforms  
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
8
IMPORTANT NOTICE  
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue  
any product or service without notice, and advise customers to obtain the latest version of relevant information  
to verify, before placing orders, that information being relied on is current and complete. All products are sold  
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those  
pertaining to warranty, patent infringement, and limitation of liability.  
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent  
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily  
performed, except those mandated by government requirements.  
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF  
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL  
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR  
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER  
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO  
BE FULLY AT THE CUSTOMER’S RISK.  
In order to minimize risks associated with the customer’s applications, adequate design and operating  
safeguards must be provided by the customer to minimize inherent or procedural hazards.  
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent  
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other  
intellectual property right of TI covering or relating to any combination, machine, or process in which such  
semiconductor products or services might be or are used. TI’s publication of information regarding any third  
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.  
Copyright 1998, Texas Instruments Incorporated  

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SN54LVT573W

3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
TI

SN54LVT574

3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
TI

SN54LVT574FK

3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
TI

SN54LVT574J

3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
TI

SN54LVT574W

3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
TI