SN54LVT543_07 [TI]

3.3-V ABT OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS; 3.3 -V ABT八路户籍收发器,三态输出
SN54LVT543_07
型号: SN54LVT543_07
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

3.3-V ABT OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
3.3 -V ABT八路户籍收发器,三态输出

输出元件
文件: 总15页 (文件大小:386K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
SN54LVT543, SN74LVT543  
3.3-V ABT OCTAL REGISTERED TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCBS137D – MAY 1992 – REVISED JULY 1995  
SN54LVT543 . . . JT PACKAGE  
SN74LVT543 . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low Static Power  
Dissipation  
LEBA  
OEBA  
A1  
1
2
3
4
5
6
7
8
9
10  
24  
V
CC  
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V V  
23 CEBA  
22 B1  
21 B2  
20 B3  
19 B4  
18 B5  
17 B6  
16 B7  
)
CC  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
Support Unregulated Battery Operation  
Down to 2.7 V  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
CC  
A
ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model  
(C = 200 pF, R = 0)  
15  
B8  
CEAB 11  
GND 12  
14 LEAB  
13 OEAB  
Latch-Up Performance Exceeds 500 mA  
Per JEDEC Standard JESD-17  
SN54LVT543 . . . FK PACKAGE  
(TOP VIEW)  
Bus-Hold Data Inputs Eliminate the Need  
for External Pullup Resistors  
Support Live Insertion  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK), and  
Ceramic (JT) DIPs  
4
3
2
1
28 27 26  
25  
A2  
A3  
A4  
NC  
A5  
A6  
A7  
B2  
B3  
B4  
5
24  
23  
6
7
22 NC  
21 B5  
20 B6  
19 B7  
8
description  
9
10  
11  
Theseoctaltransceiversaredesignedspecifically  
for low-voltage (3.3-V) V operation, but with the  
CC  
12 13 14 15 16 17 18  
capability to provide a TTL interface to a 5-V  
system environment.  
The ’LVT543 contain two sets of D-type latches for  
temporary storage of data flowing in either  
direction. Separate latch-enable (LEAB or LEBA)  
and output-enable (OEAB or OEBA) inputs are  
provided for each register to permit independent  
control in either direction of data flow.  
NC – No internal connection  
The A-to-B enable (CEAB) input must be low in order to enter data from A or to output data from B. If CEAB  
is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts  
the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect  
the data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA,  
LEBA, and OEBA inputs.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1995, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54LVT543, SN74LVT543  
3.3-V ABT OCTAL REGISTERED TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCBS137D – MAY 1992 – REVISED JULY 1995  
description (continued)  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
The SN74LVT543 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count  
and functionality of standard small-outline packages in less than half the printed-circuit-board area.  
The SN54LVT543 is characterized for operation over the full military temperature range of 55°C to 125°C. The  
SN74LVT543 is characterized for operation from 40°C to 85°C.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
B
CEAB  
LEAB  
OEAB  
A
H
X
L
L
L
X
X
H
L
X
H
L
X
X
X
L
Z
Z
B
0
L
L
L
L
H
H
A-to-B data flow is shown; B-to-A flow control is the  
same except that it uses CEBA, LEBA, and OEBA.  
Output level before the indicated steady-state input  
conditions were established  
§
logic symbol  
2
1EN3  
OEBA  
CEBA  
LEBA  
OEAB  
CEAB  
LEAB  
23  
G1  
1
1C5  
13  
2EN4  
11  
G2  
14  
2C6  
3
22  
A1  
5D  
4
B1  
3
1
1
6D  
21  
20  
19  
4
B2  
B3  
B4  
A2  
5
6
7
A3  
A4  
A5  
18  
17  
16  
B5  
B6  
B7  
8
A6  
9
A7  
A8  
15  
10  
B8  
§
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
Pin numbers shown are for the DB, DW, JT, and PW packages.  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54LVT543, SN74LVT543  
3.3-V ABT OCTAL REGISTERED TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCBS137D – MAY 1992 – REVISED JULY 1995  
logic diagram (positive logic)  
2
OEBA  
23  
CEBA  
1
LEBA  
13  
OEAB  
11  
CEAB  
14  
LEAB  
C1  
1D  
3
A1  
22  
B1  
C1  
1D  
To Seven Other Channels  
Pin numbers shown are for the DB, DW, JT, and PW packages.  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage range, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V  
CC  
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V  
I
Voltage range applied to any output in the high state or power-off state, V (see Note 1) . . . . 0.5 V to 7 V  
O
Current into any output in the low state, I : SN54LVT543 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA  
O
SN74LVT543 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA  
Current into any output in the high state, I (see Note 2): SN54LVT543 . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA  
O
SN74LVT543 . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA  
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA  
IK  
OK  
I
Output clamp current, I  
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA  
O
Maximum power dissipation at T = 55°C (in still air) (see Note 3): DB package . . . . . . . . . . . . . . . . . . . 0.65 W  
A
DW package . . . . . . . . . . . . . . . . . . . 1.7 W  
PW package . . . . . . . . . . . . . . . . . . . 0.7 W  
Storage temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C  
stg  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.  
2. This current flows only when the output is in the high state and V > V  
.
CC  
O
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.  
Formoreinformation,refertothePackageThermalConsiderationsapplicationnoteinthe1994ABTAdvancedBiCMOSTechnology  
Data Book, literature number SCBD002B.  
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54LVT543, SN74LVT543  
3.3-V ABT OCTAL REGISTERED TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCBS137D – MAY 1992 – REVISED JULY 1995  
recommended operating conditions (see Note 4)  
SN54LVT543 SN74LVT543  
UNIT  
MIN  
2.7  
2
MAX  
MIN  
2.7  
2
MAX  
V
V
V
V
Supply voltage  
3.6  
3.6  
V
V
CC  
High-level input voltage  
Low-level input voltage  
Input voltage  
IH  
0.8  
5.5  
24  
48  
0.8  
5.5  
32  
64  
V
IL  
V
I
I
I
High-level output current  
Low-level output current  
Input transition rise or fall rate  
Operating free-air temperature  
mA  
mA  
ns/V  
°C  
OH  
OL  
t/v  
Outputs enabled  
10  
10  
T
A
55  
125  
40  
85  
NOTE 4: Unused control inputs must be held high or low to prevent them from floating.  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54LVT543, SN74LVT543  
3.3-V ABT OCTAL REGISTERED TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCBS137D – MAY 1992 – REVISED JULY 1995  
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
SN54LVT543  
SN74LVT543  
PARAMETER  
TEST CONDITIONS  
UNIT  
MIN TYP  
MAX  
MIN TYP  
MAX  
V
V
V
V
= 2.7 V,  
I = –18 mA  
–1.2  
–1.2  
V
IK  
CC  
CC  
CC  
I
= MIN to MAX ,  
= 2.7 V,  
I
I
I
I
I
I
I
I
I
I
= –100 µA  
= – 8 mA  
= – 24 mA  
= 32 mA  
= 100 µA  
= 24 mA  
= 16 mA  
= 32 mA  
= 48 mA  
= 64 mA  
V
0.2  
V
0.2  
OH  
OH  
OH  
OH  
OL  
OL  
OL  
OL  
OL  
OL  
CC  
2.4  
CC  
2.4  
V
OH  
V
V
2
V
= 3 V  
CC  
CC  
2
0.2  
0.5  
0.2  
0.5  
0.4  
0.5  
V
= 2.7 V  
0.4  
V
OL  
0.5  
V
CC  
= 3 V  
0.55  
0.55  
±1  
V
V
= 3.6 V,  
V = V  
I
or GND  
±1  
10  
20  
5
CC  
CC  
Control  
inputs  
= 0 or MAX ,  
V = 5.5 V  
I
10  
CC  
I
I
V = 5.5 V  
I
20  
µA  
§
V
CC  
= 3.6 V  
V = V  
I CC  
A or B ports  
5
V = 0  
–10  
–10  
±100  
I
I
I
V
V
= 0,  
V or V = 0 to 4.5 V  
I
µA  
µA  
off  
CC  
O
V = 0.8 V  
75  
75  
I
= 3 V  
A or B ports  
I(hold)  
CC  
V = 2 V  
I
–75  
–75  
I
I
V
V
= 3.6 V,  
= 3.6 V,  
V
= 3 V  
1
–1  
1
–1  
µA  
µA  
OZH  
CC  
O
O
V
= 0.5 V  
OZL  
CC  
Outputs high  
Outputs low  
0.13  
8.8  
0.19  
12  
0.13  
8.8  
0.19  
12  
V
= 3.6 V,  
or GND  
CC  
I
= 0,  
CC  
O
I
mA  
CC  
V = V  
I
Outputs  
disabled  
0.13  
0.19  
0.2  
0.13  
0.19  
0.2  
V
= 3 V to 3.6 V,  
One input at V  
or GND  
– 0.6 V,  
CC  
CC  
Other inputs at V  
mA  
I  
CC  
CC  
C
C
V = 3 V or 0  
4.5  
11  
4.5  
11  
pF  
pF  
i
I
V
O
= 3 V or 0  
io  
§
All typical values are at V  
= 3.3 V, T = 25°C.  
A
CC  
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.  
Unused terminals at V or GND  
CC  
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V  
or GND.  
CC  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54LVT543, SN74LVT543  
3.3-V ABT OCTAL REGISTERED TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCBS137D – MAY 1992 – REVISED JULY 1995  
timing requirements over recommended operating free-air temperature range (unless otherwise  
noted) (see Figure 1)  
SN54LVT543  
= 3.3 V  
SN74LVT543  
= 3.3 V  
V
V
CC  
± 0.3 V  
CC  
± 0.3 V  
V
CC  
= 2.7 V  
MAX  
V
CC  
= 2.7 V  
MAX  
UNIT  
MIN  
3.3  
0
MAX  
MIN  
3.3  
0
MIN  
3.3  
0
MAX  
MIN  
3.3  
0
t
t
Pulse duration, LEAB or LEBA low  
A or B before LEAB or  
LEBA↑  
Setup time  
ns  
w
Data high  
Data low  
Data high  
Data low  
0.8  
0
1.1  
0
0.8  
0
1.1  
0
ns  
ns  
su  
A or B before CEAB or  
CEBA↑  
0.9  
1.7  
1.8  
1.2  
1.7  
1.8  
0.9  
1.7  
1.8  
1.2  
1.7  
1.8  
A or B after LEAB or LEBA↑  
A or B after CEAB or CEBA↑  
t
h
Hold time  
switching characteristics over recommended operating free-air temperature range, C = 50 pF  
L
(unless otherwise noted) (see Figure 1)  
SN54LVT543  
= 3.3 V  
SN74LVT543  
= 3.3 V  
FROM  
(INPUT)  
TO  
(OUTPUT)  
V
V
CC  
± 0.3 V  
CC  
± 0.3 V  
V
CC  
= 2.7 V  
V
CC  
= 2.7 V  
PARAMETER  
UNIT  
MIN  
1
MAX  
4.9  
4.8  
6.1  
5.9  
6
MIN  
MAX  
5.7  
6
MIN TYP  
MAX  
4.7  
4.6  
5.9  
5.7  
5.8  
6.4  
6.5  
5.8  
6
MIN  
MAX  
5.5  
5.8  
7.3  
7.3  
7.6  
8.2  
7.1  
5.9  
7.6  
8.3  
7.1  
5.6  
t
t
t
t
t
t
t
t
t
t
t
t
1
1
2.9  
3.3  
4
PLH  
PHL  
PLH  
PHL  
PZH  
PZL  
PHZ  
PLZ  
PZH  
PZL  
PHZ  
PLZ  
A or B  
B or A  
A or B  
A or B  
A or B  
A or B  
A or B  
ns  
ns  
ns  
ns  
ns  
ns  
1
1
7.5  
7.5  
7.8  
8.4  
7.3  
6.1  
7.8  
8.5  
7.3  
5.8  
1
LE  
OE  
OE  
CE  
CE  
1
1
4.1  
4.1  
4.5  
4.8  
4
1
1
1.1  
2.4  
2
6.6  
6.7  
6
1.1  
2.4  
2
1
6.2  
6.9  
6.6  
5.6  
1
4.2  
4.7  
4.7  
3.8  
1.4  
2.3  
2
1.4  
2.3  
2
6.7  
6.4  
5.4  
All typical values are at V  
= 3.3 V, T = 25°C.  
A
CC  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54LVT543, SN74LVT543  
3.3-V ABT OCTAL REGISTERED TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCBS137D – MAY 1992 – REVISED JULY 1995  
PARAMETER MEASUREMENT INFORMATION  
6 V  
Open  
TEST  
S1  
S1  
500 Ω  
t
/t  
Open  
6 V  
PLH PHL  
/t  
From Output  
Under Test  
t
PLZ PZL  
/t  
GND  
t
GND  
PHZ PZH  
C
= 50 pF  
L
500 Ω  
(see Note A)  
2.7 V  
0 V  
LOAD CIRCUIT FOR OUTPUTS  
1.5 V  
Timing Input  
Data Input  
t
w
t
t
h
su  
2.7 V  
0 V  
2.7 V  
0 V  
Input  
1.5 V  
1.5 V  
1.5 V  
1.5 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
2.7 V  
0 V  
2.7 V  
0 V  
Output  
Control  
1.5 V  
1.5 V  
t
Input  
1.5 V  
1.5 V  
t
PZL  
t
t
PHL  
PLH  
PLZ  
1.5 V  
Output  
Waveform 1  
S1 at 6 V  
V
V
3 V  
OH  
1.5 V  
1.5 V  
1.5 V  
Output  
V
V
+ 0.3 V  
– 0.3 V  
OL  
V
OL  
OL  
(see Note B)  
t
PHZ  
t
PLH  
t
t
PZH  
PHL  
Output  
Waveform 2  
S1 at GND  
V
OH  
V
V
OH  
OH  
1.5 V  
1.5 V  
Output  
(see Note B)  
0 V  
OL  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
INVERTING AND NONINVERTING OUTPUTS  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
LOW- AND HIGH-LEVEL ENABLING  
NOTES: A.  
C includes probe and jig capacitance.  
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 , t 2.5 ns, t 2.5 ns.  
O
r
f
D. The outputs are measured one at a time with one transition per measurement.  
Figure 1. Load Circuit and Voltage Waveforms  
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
PACKAGE OPTION ADDENDUM  
www.ti.com  
21-Aug-2007  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
SSOP  
SOIC  
Drawing  
SN74LVT543DBLE  
SN74LVT543DW  
OBSOLETE  
NRND  
DB  
24  
24  
TBD  
Call TI  
Call TI  
DW  
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74LVT543DWR  
NRND  
SOIC  
SO  
DW  
24  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74LVT543NSR  
SN74LVT543PWLE  
SN74LVT543PWR  
OBSOLETE  
NS  
PW  
PW  
24  
24  
24  
TBD  
TBD  
Call TI  
Call TI  
Call TI  
Call TI  
OBSOLETE TSSOP  
NRND TSSOP  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
16-Jul-2007  
TAPE AND REEL INFORMATION  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
16-Jul-2007  
Device  
Package Pins  
Site  
Reel  
Reel  
A0 (mm)  
B0 (mm)  
K0 (mm)  
P1  
W
Pin1  
Diameter Width  
(mm) (mm) Quadrant  
(mm)  
330  
(mm)  
24  
SN74LVT543DWR  
SN74LVT543PWR  
DW  
PW  
24  
24  
TAI  
10.75  
6.95  
15.7  
8.3  
2.7  
1.6  
12  
8
24  
16  
Q1  
Q1  
MLA  
330  
16  
TAPE AND REEL BOX INFORMATION  
Device  
Package  
Pins  
Site  
Length (mm) Width (mm) Height (mm)  
SN74LVT543DWR  
SN74LVT543PWR  
DW  
PW  
24  
24  
TAI  
346.0  
346.0  
346.0  
346.0  
41.0  
33.0  
MLA  
Pack Materials-Page 2  
MECHANICAL DATA  
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001  
DB (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE  
28 PINS SHOWN  
0,38  
0,22  
0,65  
28  
M
0,15  
15  
0,25  
0,09  
5,60  
5,00  
8,20  
7,40  
Gage Plane  
1
14  
0,25  
A
0°ā8°  
0,95  
0,55  
Seating Plane  
0,10  
2,00 MAX  
0,05 MIN  
PINS **  
14  
16  
20  
24  
28  
30  
38  
DIM  
6,50  
5,90  
6,50  
5,90  
7,50  
8,50  
7,90  
10,50  
9,90  
10,50 12,90  
A MAX  
A MIN  
6,90  
9,90  
12,30  
4040065 /E 12/01  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-150  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999  
PW (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
14 PINS SHOWN  
0,30  
0,19  
M
0,10  
0,65  
14  
8
0,15 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
1
7
0°8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
8
14  
16  
20  
24  
28  
DIM  
3,10  
2,90  
5,10  
4,90  
5,10  
4,90  
6,60  
6,40  
7,90  
9,80  
9,60  
A MAX  
A MIN  
7,70  
4040064/F 01/97  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-153  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,  
improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.  
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s  
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and  
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Amplifiers  
Data Converters  
DSP  
Applications  
Audio  
amplifier.ti.com  
dataconverter.ti.com  
dsp.ti.com  
www.ti.com/audio  
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Military  
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www.ti.com/broadband  
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www.ti.com/military  
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logic.ti.com  
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Microcontrollers  
RFID  
power.ti.com  
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Security  
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