SN54LS222AJ [TI]
16 Ã 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH 3-STATE OUTPUTS; 16 ？ 4同步FIRST -IN ，具有三态输出的先出存储器
| 型号： | SN54LS222AJ |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16 Ã 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH 3-STATE OUTPUTS |
| 文件： | 总12页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LS222A
16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
WITH 3-STATE OUTPUTS
SDLS959A – DECEMBER 2001 – REVISED APRIL 2003
J PACKAGE
(TOP VIEW)
Independent Synchronous Inputs and
Outputs
16 Words by 4 Bits Each
OE
IRE
IR
LDCK
D0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
3-State Outputs Drive Bus Lines Directly
Data Rates up to 10 MHz
UNCK
ORE
OR
Q0
NC
Q1
Q2
Q3
CLR
Fall-Through Time 50 ns Typical
Data Terminals Arranged for Printed Circuit
Board Layout
NC
D1
D2
D3
Expandable, Using External Gating
Packaged in Standard Ceramic (J) 300-mil
DIPs
GND
NC – No internal connection
description
The SN54LS222A 64-bit, low-power Schottky memory is organized as 16 words by 4 bits each. It can be
expanded in multiples of 15m + 1 words or 4n bits, or both (where n is the number of packages in the vertical
array, and m is the number of packages in the horizontal array); however, some external gating is required. For
longer words, the input-ready (IR) signals of the first-rank packages and output-ready (OR) signals of the
last-rank packages must be ANDed for proper synchronization.
A first-in, first-out (FIFO) memory is a storage device that allows data to be written to and read from its array
at independent data rates. These FIFOs are designed to process data at rates up to 10 MHz in a bit-parallel
format, word by word.
The load clock (LDCK) normally is held low, and data is written into memory on the high-to-low transition of
LDCK. The unload clock (UNCK) normally is held high, and data is read out on the low-to-high transition of
UNCK. The memory is full when the number of words clocked in exceeds by 16 the number of words clocked
out. When the memory is full, LDCK signals have no effect on the data residing in memory. When the memory
is empty, UNCK signals have no effect.
Status of the FIFO memory is monitored by the IR and OR flags that indicate not-full and not-empty conditions.
IR is high only when the memory is not full and LDCK is low. OR is high only when the memory is not empty
and UNCK is high.
A low level on the clear (CLR) input resets the internal stack-control pointers and also sets IR high and OR low
to indicate that old data remaining at the data outputs is invalid. Data outputs are noninverting with respect to
the data inputs and are at high impedance when the output-enable (OE) input is low. OE does not affect the IR
and OR outputs.
The SN54LS222A is characterized over the full military temperature range of –55°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
unless otherwise noted. On all other products, production
testing of all parameters.
processing does not necessarily include testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS222A
16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
WITH 3-STATE OUTPUTS
SDLS959A – DECEMBER 2001 – REVISED APRIL 2003
†
logic symbol
FIFO 16 × 4
CTR
1
OE
EN7
11
3
CT = 0
CT < 16
2, 3
4, 5
IR
CLR
&
+ /C1
Z2
4
2
LDCK
IRE
17
G3
OR
&
CT > 0
–
19
18
Z4
UNCK
ORE
&
G5
1D
CT = 0
2
V6
5
7
8
9
16
14
13
12
D0
D1
D2
D3
6, 7
Q0
Q1
Q2
Q3
†
This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12. This symbol is functionally accurate, but does
not show the details of implementation; for these details, see the logic diagram. The symbol represents the memory as if it were controlled by
a single counter whose content is the number of words stored at the time. Output data is invalid when the counter content (CT) is 0.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS222A
16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
WITH 3-STATE OUTPUTS
SDLS959A – DECEMBER 2001 – REVISED APRIL 2003
logic diagram (positive logic)
1
OE
11
CLR
4
LDCK
Ring
Counter
S
CTR
DIV 16
1
1D
COMP
Q=P+1
2
3
4
5
6
7
8
9
10
11
12
C1
16
+
P
Write
Address
2
P=Q+1
P=Q
IRE
Q
S
EMPTY
CT = 1
13
14
15
16
2D
C2
3
IR
17
OR
19
UNCK
Ring
16
Counter
CTR
DIV 16
R
1
3D
16
2
3
4
5
6
7
8
C3
+
Read
RAM
16 × 4
1
Address
9
18
10
11
12
ORE
1A
16
13
14
15
16
R
CT = 1
16
1
4D
2A
16
C4
EN
C5
5
16
14
13
12
1A,5D 2A
≥1
Q0
D0
7
Q1
Q2
Q3
D1
8
D2
D3
9
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS222A
16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
WITH 3-STATE OUTPUTS
SDLS959A – DECEMBER 2001 – REVISED APRIL 2003
schematics of inputs and outputs
EQUIVALENT OF
OTHER INPUTS
EQUIVALENT OF CLR
AND ORE INPUTS
V
CC
V
CC
13 kΩ NOM
19 kΩ NOM
Input
Input
TYPICAL OF IR
AND OR OUTPUTS
TYPICAL OF
Q OUTPUTS
V
CC
V
CC
120 Ω NOM
100 Ω NOM
Output
Output
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS222A
16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
WITH 3-STATE OUTPUTS
SDLS959A – DECEMBER 2001 – REVISED APRIL 2003
timing diagram
CLR
LDCK
UNCK
D0–D3
W1
W2
W1
W2
W15
W16
IR
OR
Invalid
Word 1
Word 2
Invalid
Word 1
Q0–Q3
Word 2
Load
Two Words
Unload
Two Words
Load Until Full
Initialize
Unload
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Off-state output voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
O
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
recommended operating conditions (see Note 2)
MIN NOM
MAX
UNIT
V
V
V
Supply voltage
4.5
2
5
5.5
V
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
0.7
–1
Q outputs
IR, OR
I
High-level output current
mA
OH
OL
–0.4
12
Q outputs
IR, OR
I
Low-level output current
mA
4
T
A
Operating free-air temperature
–55
125
°C
NOTE 2: To ensure proper operation of this high-speed FIFO device, it is necessary to provide a clean signal to the LDCK and UNCK clock inputs.
Any excessive noise or glitching on the clock inputs that violates the V , V , or minimum pulse-duration limits can cause a false clock
IL IH
or improper operation of the internal read and write pointers.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS222A
16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
WITH 3-STATE OUTPUTS
SDLS959A – DECEMBER 2001 – REVISED APRIL 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
‡
†
PARAMETER
MIN TYP
MAX
UNIT
TEST CONDITIONS
I = –18 mA
V
V
V
V
V
V
V
V
V
V
V
V
= MIN,
= MIN,
= MIN,
= MIN,
= MIN,
= MAX,
= MAX,
= MAX,
= MAX,
= MAX,
–1.5
V
IK
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
I
Q outputs
IR, OR
I
I
I
I
= –1 mA
= –0.4 mA
= 12 mA
= 4 mA
2.4
2.5
3.3
3.4
OH
OH
OL
OL
V
V
OH
Q outputs
IR, OR
0.25
0.25
0.4
0.4
V
OL
I
I
I
I
I
Q outputs
Q outputs
V
= 2.7 V
20
µA
µA
OZH
OZL
I
O
O
V
= 0.4 V
–20
0.1
V = 7 V
I
mA
µA
V = 2.7 V
20
IH
I
V = 0.4 V
I
–0.4
–130
–100
135
155
155
mA
IL
Q outputs
IR, OR
–30
–20
§
V
CC
= MAX
mA
I
OS
Outputs high
Outputs low
84
87
89
I
V
CC
= MAX
mA
CC
Outputs disabled
†
‡
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at V = 5 V, T = 25°C.
Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
CC
A
timing requirements over recommended operating conditions (see Note 2 and Figure 2)
MIN
60
15
30
30
20
50
50
50
10
MAX
UNIT
LDCK high
LDCK low
t
Pulse duration
UNCK low
ns
w
UNCK high
CLR low
Data to LDCK↓
LDCK↓ before UNCK↓
UNCK↑ before LDCK↑
Data from LDCK↓
t
t
Setup time
Hold time
ns
ns
su
h
NOTE 2: To ensure proper operation of this high-speed FIFO device, it is necessary to provide a clean signal to the LDCK and UNCK clock inputs.
Any excessive noise or glitching on the clock inputs that violates the V , V , or minimum pulse-duration limits can cause a false clock
IL IH
or improper operation of the internal read and write pointers.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS222A
16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
WITH 3-STATE OUTPUTS
SDLS959A – DECEMBER 2001 – REVISED APRIL 2003
switching characteristics, V
= 5 V, T = 25°C (see Figure 2)
A
CC
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX
UNIT
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
IRE↑
IRE↓
23
9
35
15
35
15
40
50
70
45
45
70
55
40
50
80
70
35
35
30
30
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PLH
PHL
PLH
PLH
PHL
PHL
PLH
PHL
PZL
PZH
PLZ
PHZ
IR
R
R
= 2 kΩ,
= 2 kΩ,
C
C
= 15 pF
= 15 pF
ns
L
L
L
L
ORE↑
22
9
OR
ns
ORE↓
LDCK↓
LDCK↑
LDCK↓
UNCK↑
UNCK↓
UNCK↑
25
36
48
29
28
49
36
25
34
54
45
22
21
16
18
IR
R
R
R
R
R
R
R
= 2 kΩ,
= 2 kΩ,
= 2 kΩ,
= 2 kΩ,
= 2 kΩ,
= 667 Ω,
= 667 Ω,
C
C
C
C
C
C
C
= 15 pF
= 15 pF
= 15 pF
= 15 pF
= 15 pF
= 45 pF
= 45 pF
ns
ns
ns
ns
ns
ns
ns
L
L
L
L
L
L
L
L
L
L
L
L
L
L
OR
OR
IR
IR
CLR↓
OR
Q
LDCK↓
Q
Q
Q
UNCK↑
OE↑
R
R
= 667 Ω,
= 667 Ω,
C
C
= 45 pF
= 5 pF
ns
ns
L
L
L
L
OE↓
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS222A
16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
WITH 3-STATE OUTPUTS
SDLS959A – DECEMBER 2001 – REVISED APRIL 2003
APPLICATION INFORMATION
CLR
OE
CLR
LDCK
CLR
LDCK
CLR
LDCK
OE
OR
OE
OR
5 V
UNCK
OR
OE
OR
5 V
LDCK
IR
10 ns
10 ns
UNCK
UNCK
UNCK
IR
IR
IR
ORE
ORE
ORE
IRE
IRE
5 V
5 V
IRE
Q0
Q1
Q2
Q0
Q1
Q2
Q0
Q1
Q2
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
Q3
Q3
Q3
CLR
CLR
CLR
OE
OR
OE
OR
OE
OR
5 V
5 V
LDCK
LDCK
Open
LDCK
Open
UNCK
UNCK
UNCK
IR
IR
IR
ORE
ORE
ORE
IRE
IRE
5 V
5 V
IRE
Q0
Q1
Q2
Q0
Q1
Q2
Q0
Q1
Q2
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
Q3
Q3
Q3
CLR
CLR
CLR
OE
OR
OE
OR
OE
OR
5 V
5 V
LDCK
LDCK
LDCK
Open
Open
UNCK
UNCK
UNCK
IR
IR
IR
ORE
ORE
ORE
IRE
IRE
5 V
5 V
IRE
Q0
Q1
Q2
Q0
Q1
Q2
Q0
Q1
Q2
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
Q3
Q3
Q3
CLR
CLR
CLR
OE
OE
OR
OE
OR
5 V
5 V
Open
OR Open
UNCK
ORE
LDCK
LDCK
LDCK
UNCK
UNCK
IR
IR
IR
5 V
5 V
ORE
ORE
IRE
IRE
5 V
5 V
IRE
Q0
Q1
Q2
Q0
Q1
Q2
Q0
Q1
Q2
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
Q3
Q3
Q3
10 ns
≡ Noninverting delay ≥10 ns (e.g., two stages of ’LS04), two places
Figure 1. 48-Word by 16-Bit Expansion Using SN54LS222A
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS222A
16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
WITH 3-STATE OUTPUTS
SDLS959A – DECEMBER 2001 – REVISED APRIL 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
R
L
S1
TEST
S1
S2
From Output
Under Test
(see Note B)
t
Closed
Open
Open
PZL
C
L
t
Closed
Closed
Closed
PZH
(see Note A)
5 kΩ
t
/t
Closed
Closed
PLZ PHZ
/t
t
PLH PHL
S2
LOAD CIRCUIT
3 V
0 V
Timing
Input
High-Level
Pulse
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
t
t
h
w
t
su
3 V
0 V
Data
Input
Low-Level
Pulse
1.3 V
1.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3 V
0 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
3 V
Output
Control
1.3 V
1.3 V
t
t
PLZ
PZL
0.3 V
≈1.5 V
t
t
PLH
PHL
Waveform 1
(see Note B)
1.3 V
V
OH
OL
In-Phase
Output
1.3 V
1.3 V
1.3 V
V
OL
V
0.5 V
t
PHZ
t
t
t
PHL
PZH
PLH
V
OH
0.5 V
≈1.5 V
V
Out-of-Phase
Output
(see Note C)
Waveform 2
(see Note B)
OH
OL
1.3 V
1.3 V
V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR ≤ 1 MHz, t < 15 ns, t < 6 ns, Z ≈ 50 Ω.
r
f
O
D. All diodes are 1N916 or 1N3064.
E. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuits and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CDIP
Drawing
SN54LS222AJ
SNJ54LS222AJ
OBSOLETE
OBSOLETE
J
J
20
20
TBD
TBD
Call TI
Call TI
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54LS222A :
Catalog: SN74LS222A
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 1
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TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Audio
Automotive
Broadband
Digital Control
Medical
Amplifiers
Data Converters
DSP
Clocks and Timers
Interface
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/audio
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
Logic
Military
Power Mgmt
Microcontrollers
RFID
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
Optical Networking
Security
Telephony
Video & Imaging
Wireless
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
RF/IF and ZigBee® Solutions www.ti.com/lprf
www.ti.com/wireless
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