SN54LS224A [TI]
16 Ã 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES WITH 3-STATE OUTPUTS; 16 ？ 4同步FIRST -IN ，具有三态输出的先出MEMORIES
| 型号： | SN54LS224A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16 Ã 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES WITH 3-STATE OUTPUTS |
| 文件： | 总13页 (文件大小：355K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LS224A, SN74LS224A
16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
WITH 3-STATE OUTPUTS
SDLS023E – JANUARY 1991 – REVISED APRIL 2003
SN54LS224A . . . J PACKAGE
SN74LS224A . . . N PACKAGE
(TOP VIEW)
Independent Synchronous Inputs and
Outputs
16 Words by 4 Bits Each
3-State Outputs Drive Bus Lines Directly
Data Rates up to 10 MHz
Fall-Through Time 50 ns Typical
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
OE
IR
LDCK
D0
D1
D2
D3
GND
CC
UNCK
OR
Q0
Q1
Q2
Q3
CLR
Data Terminals Arranged for Printed Circuit
Board Layout
Expandable, Using External Gating
Packaged in Standard Plastic (N) and
Ceramic (J) 300-mil DIPs, and Ceramic Chip
Carriers (FK)
SN54LS224A . . . FK PACKAGE
(TOP VIEW)
description
The SN54LS224A and SN74LS224A 64-bit,
low-power Schottky memories are organized as
16 words by 4 bits each. They can be expanded
in multiples of 15m + 1 words or 4n bits, or both
(where n is the number of packages in the vertical
array and m is the number of packages in the
horizontal array); however, some external gating
is required. For longer words, the input-ready (IR)
signals of the first-rank packages and
output-ready (OR) signals of the last-rank
packages must be ANDed for proper
synchronization.
3
9
2
1
20 19
18
LDCK
D0
OR
Q0
NC
Q1
Q2
4
5
6
7
8
17
16
15
14
NC
D1
D2
10 11 12 13
NC – No internal connection
A first-in, first-out (FIFO) memory is a storage
device that allows data to be written to and read
from its array at independent data rates. These
FIFOs are designed to process data at rates up to
10 MHz in a bit-parallel format, word by word.
The load clock (LDCK) normally is held low, and data is written into memory on the high-to-low transition of
LDCK. The unload clock (UNCK) normally is held high, and data is read out on the low-to-high transition of
UNCK. The memory is full when the number of words clocked in exceeds by 16 the number of words clocked
out. When the memory is full, LDCK signals have no effect on the data residing in memory. When the memory
is empty, UNCK signals have no effect.
Status of the FIFO memory is monitored by the IR and OR flags that indicate not-full and not-empty conditions.
IR is high only when the memory is not full and LDCK is low. OR is high only when the memory is not empty
and UNCK is high.
A low level on the clear (CLR) input resets the internal stack-control pointers and also sets IR high and OR low
to indicate that old data remaining at the data outputs is invalid. Data outputs are noninverting, with respect to
the data inputs, and are at high impedance when the output-enable (OE) input is low. OE does not affect the
IR and OR outputs.
The SN74LS224A is characterized for operation from 0°C to 70°C. The SN54LS224A is characterized over the
full military temperature range of –55°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
unless otherwise noted. On all other products, production
testing of all parameters.
processing does not necessarily include testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS224A, SN74LS224A
16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
WITH 3-STATE OUTPUTS
SDLS023E – JANUARY 1991 – REVISED APRIL 2003
†
logic symbol
FIFO 16 × 4
CTR
1
9
OE
EN5
2
CT = 0
CT < 16
2
3
IR
CLR
&
+ /C1
Z2
3
LDCK
UNCK
14
OR
&
CT > 0
–
15
Z3
&
CT = 0
2
V4
4, 5
4
5
6
7
13
12
11
10
D0
D1
D2
D3
1D
Q0
Q1
Q2
Q3
†
This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12. This symbol is functionally accurate, but does
not show the details of implementation; for these details, see the logic diagram. The symbol represents the memory as if it were controlled by
a single counter whose content is the number of words stored at the time. Output data is invalid when the counter content (CT) is 0.
Pin numbers shown are for the J and N packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS224A, SN74LS224A
16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
WITH 3-STATE OUTPUTS
SDLS023E – JANUARY 1991 – REVISED APRIL 2003
logic diagram (positive logic)
1
OE
9
CLR
3
LDCK
Ring
Counter
S
CTR
DIV 16
1
1D
COMP
Q=P+1
2
3
4
5
6
7
8
C1
16
+
P
Write
Address
P=Q+1
P=Q
9
10
11
12
13
14
15
16
Q
S
EMPTY
CT = 1
2D
C2
2
IR
14
OR
15
UNCK
Ring
16
Counter
CTR
DIV 16
R
1
3D
16
2
3
4
5
6
7
8
C3
+
Read
RAM
16 × 4
1
Address
9
10
11
12
1A
16
13
14
15
16
CT = 1
R
16
1
4D
2A
16
C4
EN
C5
4
13
12
11
10
1A,5D 2A
≥1
Q0
D0
5
Q1
Q2
Q3
D1
6
7
D2
D3
Pin numbers shown are for the J and N packages.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS224A, SN74LS224A
16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
WITH 3-STATE OUTPUTS
SDLS023E – JANUARY 1991 – REVISED APRIL 2003
schematics of inputs and outputs
EQUIVALENT OF OTHER INPUTS
EQUIVALENT OF CLR INPUT
V
CC
V
CC
13 kΩ NOM
19 kΩ NOM
Input
Input
TYPICAL OF IR AND OR OUTPUTS
TYPICAL OF Q OUTPUTS
V
CC
V
CC
120 Ω NOM
100 Ω NOM
Output
Output
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS224A, SN74LS224A
16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
WITH 3-STATE OUTPUTS
SDLS023E – JANUARY 1991 – REVISED APRIL 2003
timing diagram
CLR
LDCK
UNCK
D0–D3
W1
W2
W1
W2
W15
W16
IR
OR
Invalid
Word 1
Word 2
Invalid
Word 1
Q0–Q3
Word 2
Load
Two Words
Unload
Two Words
Load Until Full
Initialize
Unload
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Off-state output voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Package thermal impedance, θ : N package (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
JA
N package (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-3.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS224A, SN74LS224A
16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
WITH 3-STATE OUTPUTS
SDLS023E – JANUARY 1991 – REVISED APRIL 2003
recommended operating conditions (see Note 4)
SN54LS224A
SN74LS224A
MIN NOM MAX
UNIT
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.75
2
5
5.25
V
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
0.7
–1
0.8
–2.6
–0.4
24
Q outputs
IR, OR
I
High-level output current
mA
OH
OL
–0.4
12
Q outputs
IR, OR
I
Low-level output current
mA
4
8
T
A
Operating free-air temperature
–55
125
0
70
°C
NOTE 4: To ensure proper operation of this high-speed FIFO device, it is necessary to provide a clean signal to the LDCK and UNCK clock inputs.
Any excessive noise or glitching on the clock inputs that violates the V , V , or minimum pulse-duration limits can cause a false clock
IL IH
or improper operation of the internal read and write pointers.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LS224A
SN74LS224A
†
PARAMETER
UNIT
TEST CONDITIONS
I = –18 mA
‡
‡
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
V
V
= MIN,
= MIN
= MIN,
= MIN
–1.5
–1.5
V
IK
CC
CC
CC
CC
I
I
I
I
I
I
I
I
= –2.6 mA
= –1 µA
= –0.4 mA
= 12 mA
= 24 mA
= 4 mA
2.4
2.7
3.4
OH
OH
OH
OL
OL
OL
OL
Q outputs
IR, OR
2.4
2.5
3.3
3.4
V
OH
3.4
0.25
0.35
0.25
0.35
0.25
0.4
0.4
0.4
0.5
Q outputs
V
OL
V
0.25
0.4
V
CC
= MIN
IR, OR
= 8 mA
0.5
I
I
I
I
I
Q outputs
Q outputs
V
V
V
V
V
= MAX,
= MAX,
= MAX,
= MAX,
= MAX,
V
= 2.7 V
20
–20
0.1
20
µA
µA
OZH
OZL
I
CC
CC
CC
CC
CC
O
O
V
= 0.4 V
–20
0.1
V = 7 V
I
mA
µA
V = 2.7 V
I
20
20
IH
V = 0.4 V
I
–0.4
–130
–100
135
155
155
–0.4
–130
–100
135
155
155
mA
IL
Q outputs
IR, OR
–30
–20
–30
–20
§
V
CC
= MAX
mA
I
OS
Outputs high
Outputs low
84
87
89
84
87
89
I
V
CC
= MAX
mA
CC
Outputs disabled
†
‡
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at V = 5 V, T = 25°C.
Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
CC
A
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS224A, SN74LS224A
16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
WITH 3-STATE OUTPUTS
SDLS023E – JANUARY 1991 – REVISED APRIL 2003
timing requirements over recommended operating conditions (see Note 4 and Figure 1)
SN54LS224A SN74LS224A
UNIT
MIN
60
15
30
30
20
50
50
50
10
MAX
MIN
60
15
30
30
20
50
50
50
10
MAX
LDCK high
LDCK low
t
Pulse duration
UNCK low
ns
w
UNCK high
CLR low
Data to LDCK↓
LDCK↓ before UNCK↓
UNCK↑ before LDCK↑
Data from LDCK↓
t
t
Setup time
Hold time
ns
ns
su
h
NOTE 4: To ensure proper operation of this high-speed FIFO device, it is necessary to provide a clean signal to the LDCK and UNCK clock inputs.
Any excessive noise or glitching on the clock inputs that violates the V , V , or minimum pulse-duration limits can cause a false clock
IL IH
or improper operation of the internal read and write pointers.
switching characteristics, V
= 5 V, T = 25°C (see Figure 1)
A
CC
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX
UNIT
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
LDCK↓
LDCK↑
LDCK↓
UNCK↑
UNCK↓
UNCK↑
25
36
48
29
28
49
36
25
34
54
45
22
21
16
18
40
50
70
45
45
70
55
40
50
80
70
35
35
30
30
PLH
PHL
PLH
PLH
PHL
PLH
PLH
PHL
PHL
PLH
PHL
PZL
PZH
PLZ
PHZ
IR
R
R
R
R
R
R
R
= 2 kΩ,
= 2 kΩ,
= 2 kΩ,
= 2 kΩ,
= 2 kΩ,
= 667 Ω,
= 667 Ω,
C
C
C
C
C
C
C
= 15 pF
= 15 pF
= 15 pF
= 15 pF
= 15 pF
= 45 pF
= 45 pF
ns
ns
ns
ns
ns
ns
ns
L
L
L
L
L
L
L
L
L
L
L
L
L
L
OR
OR
IR
IR
CLR↓
OR
Q
LDCK↓
Q
Q
Q
UNCK↑
OE↑
R
R
= 667 Ω,
= 667 Ω,
C
C
= 45 pF
= 5 pF
ns
ns
L
L
L
L
OE↓
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS224A, SN74LS224A
16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
WITH 3-STATE OUTPUTS
SDLS023E – JANUARY 1991 – REVISED APRIL 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
R
L
S1
TEST
S1
S2
From Output
Under Test
(see Note B)
t
Closed
Open
Open
PZL
C
L
t
Closed
Closed
Closed
PZH
(see Note A)
5 kΩ
t
/t
Closed
Closed
PLZ PHZ
/t
t
PLH PHL
S2
LOAD CIRCUIT
3 V
0 V
Timing
Input
High-Level
Pulse
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
t
t
h
w
t
su
3 V
0 V
Data
Input
Low-Level
Pulse
1.3 V
1.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3 V
0 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
3 V
Output
Control
1.3 V
1.3 V
t
t
PLZ
PZL
0.3 V
1.5 V
t
t
PLH
PHL
Waveform 1
(see Note B)
1.3 V
V
OH
OL
In-Phase
Output
1.3 V
1.3 V
1.3 V
V
OL
0.5 V
V
t
PHZ
t
t
t
PHL
PZH
PLH
V
OH
V
Out-of-Phase
Output
Waveform 2
(see Note B)
OH
OL
1.3 V
1.3 V
0.5 V
(see Note C)
V
1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR ≤ 1 MHz, t < 15 ns, t < 6 ns, Z ≈ 50 Ω.
r
f
O
D. All diodes are 1N916 or 1N3064.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
PDIP
PDIP
LCCC
CDIP
Drawing
SN54LS224AJ
SN74LS224AN
SN74LS224AN3
SNJ54LS224AFK
SNJ54LS224AJ
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
J
N
16
16
16
20
16
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
N
FK
J
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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