SN54AHCT16373_14 [TI]
16-Bit Transparent D-Type Latches With 3-State Outputs;
| 型号： | SN54AHCT16373_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-Bit Transparent D-Type Latches With 3-State Outputs |
| 文件： | 总7页 (文件大小：115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54AHCT16373, SN74AHCT16373
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS336H – MARCH 1996 – REVISED JANUARY 2000
SN54AHCT16373 . . . WD PACKAGE
SN74AHCT16373 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
EPIC (Enhanced-Performance Implanted
CMOS) Process
1OE
1Q1
1Q2
GND
1Q3
1Q4
1LE
1D1
1D2
GND
1D3
1D4
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Inputs Are TTL-Voltage Compatible
2
3
Distributed V
High-Speed Switching Noise
and GND Pins Minimize
CC
4
5
Flow-Through Architecture Optimizes PCB
Layout
6
V
V
7
CC
CC
Latch-Up Performance Exceeds 250 mA Per
JESD 17
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
8
9
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
V
V
CC
CC
2Q5
2Q6
GND
2Q7
2Q8
2OE
2D5
2D6
GND
2D7
2D8
2LE
description
The ’AHCT16373 devices are 16-bit transparent
D-type latches with 3-state outputs designed
specifically for driving highly capacitive or
relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high,
the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up
at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus
lines without need for interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54AHCT16373 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74AHCT16373 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 2000, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT16373, SN74AHCT16373
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS336H – MARCH 1996 – REVISED JANUARY 2000
FUNCTION TABLE
(each 8-bit latch)
INPUTS
OUTPUT
Q
LE
H
H
L
D
H
L
OE
L
H
L
L
L
X
X
Q
0
H
X
Z
†
logic symbol
1
1OE
1LE
2OE
2LE
1EN
C3
48
24
25
2EN
C4
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
2
3
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
3D
1
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
5
6
8
9
11
12
13
14
16
17
19
20
22
23
4D
2
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1
24
25
2OE
2LE
1OE
48
1LE
C1
1D
C1
2
13
2Q1
1Q1
47
36
2D1
1D1
1D
To Seven Other Channels
To Seven Other Channels
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT16373, SN74AHCT16373
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS336H – MARCH 1996 – REVISED JANUARY 2000
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
IK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through each V
Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
O
O
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±75 mA
CC
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
SN54AHCT16373 SN74AHCT16373
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
0.8
5.5
0.8
5.5
V
0
0
0
0
V
I
Output voltage
V
V
V
O
CC
–8
CC
–8
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
mA
mA
ns/V
°C
OH
8
8
20
85
OL
∆t/∆v
20
T
A
–55
125
–40
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT16373, SN74AHCT16373
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS336H – MARCH 1996 – REVISED JANUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
TYP
SN54AHCT16373 SN74AHCT16373
PARAMETER
TEST CONDITIONS
= –50
V
UNIT
V
CC
MIN
4.4
MAX
MIN
4.4
MAX
MIN
4.4
MAX
I
I
I
I
A
4.5
OH
OH
OL
OL
V
4.5 V
4.5 V
OH
OL
= –8 mA
= 50
= 8 mA
3.94
3.8
3.8
A
0.1
0.36
±0.1
±0.25
4
0.1
0.44
±1*
0.1
0.44
±1
V
V
I
I
I
V = V
or GND
0 V to 5.5 V
5.5 V
A
A
A
I
I
CC
V
= V
or GND
±2.5
40
±2.5
40
OZ
CC
O
CC
V = V
or GND,
I
O
= 0
5.5 V
I
CC
One input at 3.4 V,
Other inputs at V
†
5.5 V
1.35
10
1.5
1.5
10
mA
∆I
CC
or GND
CC
or GND
C
C
V = V
5 V
5 V
2.5
4.5
pF
pF
i
I
CC
= V or GND
CC
V
o
O
* On products compliant to MIL-PRF-38535, this parameter is not production tested at V
This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or V
CC
= 0 V.
CC
†
.
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V ± 0.5 V
CC
T
= 25°C
SN54AHCT16373 SN74AHCT16373
A
UNIT
MIN
6.5
1.5
3.5
MAX
MIN
6.5
1.5
3.5
MAX
MIN
6.5
1.5
3.5
MAX
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
ns
ns
ns
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT16373, SN74AHCT16373
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS336H – MARCH 1996 – REVISED JANUARY 2000
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
5.1*
5.1*
5*
SN54AHCT16373 SN74AHCT16373
FROM
(INPUT)
TO
LOAD
PARAMETER
UNIT
ns
(OUTPUT) CAPACITANCE
MIN
MAX
8.5*
8.5*
8.5*
8.5*
9.5*
9.5*
MIN
1*
1*
1*
1*
1*
1*
1*
1*
1
MAX
9.5*
9.5*
9.5*
9.5*
10.5*
10.5*
11*
MIN
1
MAX
9.5
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
sk(o)
D
Q
Q
Q
Q
Q
Q
Q
Q
C
C
C
C
C
C
C
= 15 pF
= 15 pF
= 15 pF
= 15 pF
= 50 pF
= 50 pF
= 50 pF
L
L
L
L
L
L
L
1
9.5
1
9.5
LE
ns
5*
1
9.5
5*
1
10.5
10.5
11
ns
OE
OE
D
5*
1
6* 10.2*
1
ns
6.8* 10.2*
11*
1
11
5.9
5.9
6.4
5.9
6
9.5
9.5
10.5
10.5
10.5
10.5
11.5
11.5
12
1
10.5
10.5
10.5
10.5
11.5
11.5
12
ns
1
1
9.5
1
1
LE
ns
9.5
1
1
10.5
10.5
11.2
11.2
1
1
ns
OE
OE
6
1
1
6.8
7.8
1
1
C
C
= 50 pF
= 50 pF
ns
ns
L
L
1
12
1
12
†
**
1
1
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
** On products compliant to MIL-PRF-38535, this parameter does not apply.
noise characteristics, V
= 5 V, C = 50 pF, T = 25°C (see Note 4)
CC
L
A
SN74AHCT16373
PARAMETER
UNIT
MIN
TYP
0.32
–0.1
4.7
MAX
0.8
V
V
V
V
V
Quiet output, maximum dynamic V
V
V
V
V
V
OL(P)
OL(V)
OH(V)
IH(D)
IL(D)
OL
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
–0.8
OL
OH
2
0.8
NOTE 4: Characteristics are for surface-mount packages only.
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
No load, f = 1 MHz
TYP
UNIT
C
Power dissipation capacitance
22
pF
pd
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT16373, SN74AHCT16373
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS336H – MARCH 1996 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
GND
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
3 V
0 V
1.5 V
Timing Input
t
w
t
h
3 V
t
su
3 V
0 V
1.5 V
1.5 V
Input
Input
1.5 V
1.5 V
Data Input
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
0 V
t
t
t
t
t
PZL
PLZ
PLH
PHL
Output
Waveform 1
V
≈V
OH
CC
In-Phase
Output
50% V
50% V
50% V
CC
50% V
CC
CC
V
S1 at V
(see Note B)
CC
V
V
+ 0.3 V
OL
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
OH
Out-of-Phase
Output
– 0.3 V
OH
50% V
50% V
CC
CC
CC
V
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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Copyright 2000, Texas Instruments Incorporated
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