SN54ACT86_15 [TI]
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES;![SN54ACT86_15](http://pdffile.icpdf.com/pdf1/p00085/img/icpdf/SN54ACT86_447447_icpdf.jpg)
型号: | SN54ACT86_15 |
厂家: | ![]() |
描述: | QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES 输入元件 |
文件: | 总6页 (文件大小:92K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
![](http://public.icpdf.com/style/img/ads.jpg)
SN54ACT86, SN74ACT86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCAS534A – AUGUST 1995 – REVISED APRIL 1996
SN54ACT86 . . . J OR W PACKAGE
SN74ACT86 . . . D, DB, N, OR PW PACKAGE
(TOP VIEW)
Inputs Are TTL-Voltage Compatible
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
Package Options Include Plastic
1A
1B
1Y
2A
2B
V
CC
1
2
3
4
5
6
7
14
13
12
11
10
9
Small-Outline (D), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK) and
Flatpacks (W), and Standard Plastic (N) and
Ceramic (J) DIPS
4B
4A
4Y
3B
3A
3Y
2Y
GND
8
description
The ’ACT86 are quadruple 2-input exclusive-OR
gates. The devices perform the Boolean functions
Y = A B or Y = AB + AB in positive logic.
SN54ACT86 . . . FK PACKAGE
(TOP VIEW)
A common application is as a true/complement
element. If one of the inputs is low, the other input
is reproduced in true form at the output. If one of
the inputs is high, the signal on the other input is
reproduced inverted at the output.
3
2
1
20 19
18
4A
NC
4Y
NC
3B
1Y
NC
2A
4
5
6
7
8
17
16
15
14
The SN54ACT86 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74ACT86 is characterized for
operation from –40°C to 85°C.
NC
2B
9 10 11 12 13
FUNCTION TABLE
(each gate)
NC – No internal connection
INPUTS
OUTPUT
Y
A
B
L
L
L
L
H
H
L
H
L
H
H
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT86, SN74ACT86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCAS534A – AUGUST 1995 – REVISED APRIL 1996
†
logic symbol
1
= 1
1A
1B
3
6
2
4
5
1Y
2Y
2A
2B
9
3A
3B
8
10
3Y
4Y
12
13
11
4A
4B
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N, PW, and W packages.
exclusive-OR logic
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic
symbols.
EXCLUSIVE-OR
= 1
These five equivalent exclusive-OR symbols are valid for an ’ACT86 gate in positive logic; negation may
be shown at any two ports.
LOGIC-IDENTITY ELEMENT
=
EVEN-PARITY ELEMENT
2k
ODD-PARITY ELEMENT
2k + 1
The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
The output is active (high)
if an odd number of inputs
(i.e., only 1 of the 2) are
active.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT86, SN74ACT86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCAS534A – AUGUST 1995 – REVISED APRIL 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Maximum power dissipation at T = 55°C (in still air) (see Note 2): D package . . . . . . . . . . . . . . . . . . 1.25 W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
A
DB package . . . . . . . . . . . . . . . . . . 0.5 W
N package . . . . . . . . . . . . . . . . . . . 1.1 W
PW package . . . . . . . . . . . . . . . . . . 0.5 W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero.
recommended operating conditions (see Note 3)
MIN
4.5
2
MAX
MIN
4.5
2
MAX
UNIT
V
V
V
V
V
V
Supply voltage
5.5
5.5
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
V
0.8
0.8
V
0
0
V
V
0
0
V
V
V
I
CC
CC
Output voltage
V
O
CC
CC
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
–24
24
–24
24
8
mA
mA
ns/V
°C
OH
OL
∆t/∆v
0
8
0
T
–55
125
–40
85
A
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT86, SN74ACT86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCAS534A – AUGUST 1995 – REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
TYP
SN54ACT86
SN74ACT86
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
4.4
MAX
MIN
4.4
MAX
MIN
4.4
MAX
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
4.49
I
I
= – 50 µA
OH
5.4
5.49
5.4
5.4
3.86
4.86
3.7
3.76
4.76
V
OH
= – 24 mA
V
OH
4.7
†
†
I
I
= – 50 mA
3.85
OH
= – 75 mA
3.85
OH
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
I
= 50 µA
OL
OL
0.36
0.36
0.5
0.44
0.44
V
OL
I
= 24 mA
V
0.5
†
†
I
I
= 50 mA
1.65
OL
= 75 mA
1.65
±1
OL
I
I
V = V
or GND
or GND,
±0.1
±1
µA
µA
I
I
CC
CC
V = V
I = 0
O
4
80
40
CC
I
One input at 3.4 V,
Other inputs at GND or V
‡
∆I
CC
5.5 V
5 V
0.6
2.6
1.6
1.5
mA
pF
CC
C
VI = V or GND
CC
i
†
‡
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or V
.
CC
switching characteristics over recommended operating free-air temperature range,
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
8.5
SN54ACT86
SN74ACT86
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1.5
MAX
9.5
MIN
1
MAX
10
MIN
1
MAX
10
t
t
PLH
A or B
Y
ns
1.5
7
9.5
1
10.5
1
10.5
PHL
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
Power dissipation capacitance
TEST CONDITIONS
= 50 pF, f = 1 MHz
TYP
25
UNIT
C
C
pF
pd
L
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT86, SN74ACT86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCAS534A – AUGUST 1995 – REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
3 V
0 V
TEST
S1
Input
(see Note B)
1.5 V
1.5 V
t
/t
Open
PLH PHL
t
t
PHL
PLH
PHL
2 × V
CC
V
OH
CC
S1
In-Phase
Output
500 Ω
50% V
50% V
50% V
CC
Open
From Output
Under Test
V
OL
t
PLH
t
C
= 50 pF
L
500 Ω
(see Note A)
V
OH
Out-of-Phase
Output
50% V
CC
CC
V
OL
LOAD CIRCUIT
C includes probe and jig capacitance.
L
VOLTAGE WAVEFORMS
NOTES: A.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t
2.5 ns, t
f
2.5 ns.
O
r
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
相关型号:
![](http://pdffile.icpdf.com/pdf1/p00085/img/page/SN54ACT8990_447448_files/SN54ACT8990_447448_1.jpg)
![](http://pdffile.icpdf.com/pdf1/p00085/img/page/SN54ACT8990_447448_files/SN54ACT8990_447448_2.jpg)
SN54ACT8990
TEST-BUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES
TI
![](http://pdffile.icpdf.com/pdf1/p00085/img/page/SN54ACT8990_447448_files/SN54ACT8990_447448_1.jpg)
![](http://pdffile.icpdf.com/pdf1/p00085/img/page/SN54ACT8990_447448_files/SN54ACT8990_447448_2.jpg)
SN54ACT8990GB
TEST-BUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES
TI
![](http://pdffile.icpdf.com/pdf1/p00085/img/page/SN54ACT8990_447448_files/SN54ACT8990_447448_1.jpg)
![](http://pdffile.icpdf.com/pdf1/p00085/img/page/SN54ACT8990_447448_files/SN54ACT8990_447448_2.jpg)
SN54ACT8990HV
TEST-BUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES
TI
![](http://pdffile.icpdf.com/pdf1/p00100/img/page/SN54ACT8990_538542_files/SN54ACT8990_538542_1.jpg)
![](http://pdffile.icpdf.com/pdf1/p00100/img/page/SN54ACT8990_538542_files/SN54ACT8990_538542_2.jpg)
SN54ACT8990_07
TEST-BUS CONTROLLERS IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES
TI
![](http://pdffile.icpdf.com/pdf1/p00085/img/page/SN54ACT8997_447449_files/SN54ACT8997_447449_1.jpg)
![](http://pdffile.icpdf.com/pdf1/p00085/img/page/SN54ACT8997_447449_files/SN54ACT8997_447449_2.jpg)
SN54ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES SCAN-CONTROLLED IEEE STD 1149.1 JTAG TAP CONCATENATORS
TI
![](http://pdffile.icpdf.com/pdf1/p00085/img/page/SN54ACT8997_447449_files/SN54ACT8997_447449_1.jpg)
![](http://pdffile.icpdf.com/pdf1/p00085/img/page/SN54ACT8997_447449_files/SN54ACT8997_447449_2.jpg)
SN54ACT8997FK
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES SCAN-CONTROLLED IEEE STD 1149.1 JTAG TAP CONCATENATORS
TI
![](http://pdffile.icpdf.com/pdf1/p00085/img/page/SN54ACT8997_447449_files/SN54ACT8997_447449_1.jpg)
![](http://pdffile.icpdf.com/pdf1/p00085/img/page/SN54ACT8997_447449_files/SN54ACT8997_447449_2.jpg)
SN54ACT8997JT
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES SCAN-CONTROLLED IEEE STD 1149.1 JTAG TAP CONCATENATORS
TI
![](http://pdffile.icpdf.com/pdf2/p00203/img/page/SN54AC_1150555_files/SN54AC_1150555_1.jpg)
![](http://pdffile.icpdf.com/pdf2/p00203/img/page/SN54AC_1150555_files/SN54AC_1150555_2.jpg)
SN54ACT8999
SCAN-PATH SELECTORS WITH 8-BIT BIDIRECTIONAL DATA BUSES SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP MULTIPLEXERS
TI
©2020 ICPDF网 联系我们和版权申明