SN54ACT8999_技术文档

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SCAS158D − JUNE 1990 − REVISED DECEMBER 1996

SN54ACT8999 . . . JT PACKAGE

SN74ACT8999 . . . DW OR NT PACKAGE

(TOP VIEW)

D

Members of theTexas Instruments

SCOPE  Family of Testability Products

Compatible With the IEEE Standard 1149.1

(JTAG) Serial Test Bus

DTDI

OTMS

DCO

DCI

MCI

ID1

ID2

ID3

ID4

ID5

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

Allow Partitioning of System Scan Paths

2

Can Be Cascaded Horizontally or Vertically

3

MCO

4

Select One of Four Secondary Scan Paths

to Be Included in a Primary Scan Path

DTDO

DTCK

GND

DTMS1

DTMS2

DTMS3

DTMS4

DTRST

TDO

5

6

Provide Communication Between Primary

and Remote Test Bus Controllers

7

V

8

CC

Include 8-Bit Programmable Binary Counter

to Count or Initiate Interrupt Signals

ID6

ID7

ID8

TRST

TDI

9

10

11

12

13

14

Include 8-Bit Identification Bus for Scan

Path Identification

D

Inputs Are TTL Compatible

TMS

TCK

D

EPIC  (Enhanced-Performance Implanted

CMOS) 1-µm Process

D

Package Options Include Plastic

SN54ACT8999 . . . FK PACKAGE

(TOP VIEW)

Small-Outline (DW) Packages, Ceramic

Chip Carriers (FK), and Standard Plastic

(NT) and Ceramic (JT) 300-mil DIPs

4

3

2 1 28 27 26

description

5

25 ID8

ID1

MCI

DCI

DTDI

OTMS

DCO

MCO

6

TRST

24

23

22

21

20

19

The ’ACT8999 are members of the Texas

7

TDI

Instruments SCOPE testability integrated-

circuit family. This family of components facilitates

testing of complex circuit-board assemblies.

8

TCK

TMS

TDO

DTRST

9

10

11

The ’ACT8999 enhance the scan capability of TI’s

SCOPE family by allowing augmentation of a

system’s primary scan path with secondary scan

paths (SSPs), which can be individually selected

by the ’ACT8999 for inclusion in the primary scan

path. The device also provides buffering of test

signals to reduce the need for external logic.

12 13 14 15 16 17 18

By loading the proper values into the instruction register and data registers, the user can select one of four

secondary scan paths. This has the effect of shortening the scan path to allow maximum test throughput when

an individual subsystem (board or box) is to be tested. Any of the device’s six data registers or the instruction

register can be placed in the device’s scan path, i.e., placed between test data input (TDI) and test data output

(TDO) for subsequent shift and scan operations.

All operations of the device except counting are synchronous to the test clock (TCK). The 8-bit programmable

up/down counter can be used to count transitions on the device condition input (DCI) and output interrupt signals

via the device condition output (DCO). The device can be configured to count on either the rising or falling edge

of DCI.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SCOPE and EPIC are trademarks of Texas Instruments Incorporated.

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Copyright  1996, Texas Instruments Incorporated

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1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SCAS158D − JUNE 1990 − REVISED DECEMBER 1996

description (continued)

If a system’s test architecture contains more than one test bus controller, the 8-bit bidirectional bus can be used

to interface a higher-level primary bus controller (PBC) with one or more lower-level remote bus controllers

(RBCs). A protocol allows the PBC to pass control of the ’ACT8999 to an RBC, freeing the PBC for other tasks.

The 8-bit bus also can be hardwired to provide one of 256 codes for subsystem identification. The test access

port (TAP) controller is a finite-state machine compatible with IEEE Standard 1149.1.

The SN54ACT8999 is characterized for operation over the full military temperature range of −55°C to 125°C.

The SN74ACT8999 is characterized for operation from 0°C to 70°C.

functional block diagram

8

9

V

CC

2

DTMS1

DTMS2

DTMS3

DTMS4

OTMS

Test

Mode

Select

Circuit

Remote

Test

Port

10

11

V

CC

1

DTDI

V

CC

16

TDI

DCI

5

3

DTDO

DCO

28

27

(3 state or

open drain)

4

MCO

MCI

Data

Registers

ID1−ID8

13

TDO

Instruction

Register

V

CC

14

Primary

Test Port

TMS

15

6

TCK

V

DTCK

CC

17

12

DTRST

TRST

Pin numbers shown are for the DW, JT, and NT packages.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SCAS158D − JUNE 1990 − REVISED DECEMBER 1996

functional block description

The ’ACT8999 implements two separate functions in one package. The primary function of the device is to

include a selected secondary scan path in the system’s primary scan path to enable a PBC to perform controlling

and observing test functions on the selected path. This is accomplished by driving the TMS terminal(s) of a

secondary scan path with one of the DTMS pins of the device. This approach allows a system to have built-in

testability at all levels without requiring that the primary-system scan path always include all subsystem scan

paths. As a result, test throughput is improved and the amount of test data that must be interpreted is reduced.

The device includes error-detection circuitry that prevents the user from inadvertently activating more than one

secondary scan path at a time.

Another function of the device is provided by the 8-bit identification bus. This bus can be hardwired with pullup

and pulldown resistors to supply an identification code to the test controller(s) to verify that test operations are

being performed on the proper portion of the system. The bus can also transfer data and instructions to another

device, such as a local or remote bus controller, and pass control of the scan-path select function to that device.

This frees the primary controller to activate another secondary scan path elsewhere in the system or perform

higher-level test control functions. When the RBC is ready to return control of the device, interrupt signals alert

the primary controller.

The least-significant bit (LSB) of any value scanned into any register of the device is the first bit shifted in

(nearest to TDO). The most-significant bit (MSB) is the last bit shifted in (nearest to TDI). The ’ACT8999 is

divided into functional blocks as detailed below.

test ports

The test ports decode the signals on TCK, TMS, OTMS, and TRST to control the operation of the circuit. Each

test port includes a TAP controller that issues the proper control instructions to the data registers according to

the IEEE Standard 1149.1 protocol. The TAP controller state diagram is shown in Figure 1. Two test ports are

included on the ’ACT8999, allowing different test controllers to command different sections of the device.

TMS circuit

The TMS circuit decodes bits in the select and control registers to determine which one, if any, of the DTMS

pins (which provide mode-select signals to the secondary scan path(s)) follow the TMS pin or OTMS pin. The

unselected DTMS pins are set by the circuit to a static high or low level.

instruction register

The instruction register (IR) is an 8-bit-wide serial-shift register that issues commands to the device. Data is

input to the instruction register via TDI or DTDI and shifted out via TDO. All device operations are initiated by

loading the proper instruction or sequence of instructions into the IR.

data registers

Six parallel data registers are included in the ’ACT8999: bypass, control, counter, boundary-scan, ID-bus, and

select. The ID bus register is a part of the boundary-scan register. Each data register is serially loaded via TDI

or DTDI and outputs data via TDO. Table 1 summarizes the registers in the ’ACT8999.

Table 1. Register Summary

REGISTER NAME

Instruction

Remote Instruction

Control

LENGTH (BITS)

FUNCTION

8

Issue command information to the device

Issue command information to the select register

Configuration and enable control

13

8

Counter

Count events on DCI, output interrupts via DCO

Select one of four DTMS pins to follow TMS or OTMS

Capture and force test data at device periphery

Pass test commands and data between a PBC and RBC(s)

Remove the ’ACT8999 from the scan path

Select

8

Boundary Scan

ID Bus

15

8

Bypass

1

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SCAS158D − JUNE 1990 − REVISED DECEMBER 1996

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

Device condition input. DCI receives interrupt and protocol signals from an RBC and/or the secondary scan path(s).

When the counter register is instructed to count up or down, DCI is configured as the counter clock.

DCI

I

Device condition output. DCO is configured by the control register to output protocol and interrupt signals to a PBC.

It also can be configured by the control register to output an error signal if the instruction register or select register are

loaded with invalid values. DCO is further configured by the control register as:

Active high or active low (reset condition = active low)

DCO

O

Open drain or 3-state (reset condition = open drain)

DTCK

DTDI

O

I

Device test clock. DTCK outputs the buffered test clock TCK to the secondary scan path(s).

Device test data input. DTDI receives the serial test data output of the selected secondary scan path. An internal pullup

forces DTDI to a high logic level if it is left unconnected.

DTDO

O

Device test data output. DTDO outputs serial test data to the TDI input(s) of the secondary scan path(s).

DTMS1

DTMS2

DTMS3

DTMS4

Device test mode select 1−4. Either one or none of these four outputs can be selected to follow TMS or OTMS to include

a secondary scan path in the primary scan path. The unselected DTMS outputs can be independently set to a static

high or low logic level. The TMS circuit monitors input from the select register to determine the configuration of the

DTMS outputs.

O

Device test reset. This active-low output transmits a reset signal to the secondary scan path(s). DTRST can be

asserted by a bit in the control register or by setting TRST low.

DTRST

GND

Ground

ID1

ID2

ID3

ID4

ID5

ID6

ID7

ID8

Identification 1−8. This 8-bit data bus can be used to communicate with an RBC and pass data and control instructions.

By wiring pullup and pulldown resistors to these terminals, one of 255 unique identification codes can be assigned to

the device to allow a test controller to determine the identity of the subsystem under test.

I/O

MCI

I

Master condition input. MCI receives interrupt and protocol singals from a PBC.

Master condition output. MCO transmits interrupt and protocol signals to an RBC and/or the secondary scan path(s).

MCO also outputs an active-low error signal during the Pause-DR TAP state if an RBC loads an invalid value in the

select register.

MCO

O

Optional test mode select. OTMS can be used instead of TMS to control the select register. This is useful when a

remote bus controller is available to control the secondary scan path(s). An internal pullup forces OTMS to a high level

if left unconnected.

OTMS

TCK

TDI

I

Test clock. One of four terminals required by IEEE Standard 1149.1. All operations of the ’ACT8999 except for the

count function are synchronous to TCK. Data on the device inputs is captured on the rising edge of TCK, and outputs

change on the falling edge of TCK.

Test data input. One of four terminals required by IEEE Standard 1149.1. TDI is the serial input for shifting information

into the instruction register or selected data register. TDI is typically driven by the TDO output of the primary bus

controller. An internal pullup forces TDI to a high level if it is left unconnected.

Test data output. One of four terminals required by IEEE Standard 1149.1. TDO is the serial output for shifting

information out of the instruction register or selected data register. TDO is typically connected to the TDI input of the

next scannable device in the primary scan path.

TDO

TMS

O

I

Test mode select. One of four terminals required by IEEE Standard 1149.1. The level of TMS at the rising edge of TCK

directs the ’ACT8999 through its TAP controller states. An internal pullup forces TMS to a high level if left unconnected.

Test reset. This active-low input inplements the optional reset terminal of IEEE Standard 1149.1. When asserted,

TRST causes the ’ACT8999 to go to the Test-Logic-Reset state and configure the instruction register and data

registers to their power-up values. TRST is also output without inversion via DTRST. An internal pullup forces TRST

to a high level if left unconnected.

TRST

I

V

CC

Supply voltage

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SCAS158D − JUNE 1990 − REVISED DECEMBER 1996

state diagram description

The TAP proceeds through the states in Figure 1 according to IEEE Standard 1149.1. There are six stable states

(indicated by a looping arrow) and ten unstable states in the diagram. A stable state is defined as a state the

TAP can retain for consecutive TCK cycles. Any state that does not meet this criterion is an unstable state.

There are two main paths through the state diagram: one to manipulate a data register and one to manipulate

the instruction register. No more than one register can be manipulated at a time.

Test-Logic-Reset

TMS = H

TMS = L

TMS = H

Run-Test/Idle

Select-DR-Scan

TMS = L

Select-IR-Scan

TMS = L

TMS = H TMS = H

Capture-DR

TMS = L

Capture-IR

TMS = L

Shift-DR

TMS = H

Exit1-DR

TMS = L

Shift-IR

TMS = L

TMS = H

Exit1-IR

TMS = L

Pause-DR

TMS = H

Pause-IR

TMS = L

TMS = H

TMS = L

Exit2-DR

Exit2-IR

TMS = H

Update-DR

Update-IR

TMS = L

TMS = H

Figure 1. TAP-Controller State Diagram

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SCAS158D − JUNE 1990 − REVISED DECEMBER 1996

Test-Logic-Reset

In this state, the test logic is inactive and an internal reset signal is applied to all registers in the device. During

device operation, the TAP returns to this state in no more than five TCK cycles if the test mode select (TMS)

input is high. The TMS pin has an internal pullup that forces it to a high level if it is left unconnected or if a board

defect causes it to be open circuited. The device powers up in the Test-Logic-Reset state.

Run-Test/Idle

The TAP must pass through this state before executing any test operations. The TAP may retain this state

indefinitely, and no registers are modified while in Run-Test/Idle. The 8-bit programmable up/down counter can

be operated in this state.

Select-DR-Scan, Select-IR-Scan

No specific function is performed in these states; the TAP exits either of them on the next TCK cycle.

Capture-DR

The selected data register is placed in the scan path (i.e., between TDI and TDO). Depending on the current

instruction, data may or may not be loaded or captured by that register on the rising edge of TCK, causing the

TAP state to change.

Shift-DR

In this state, data is serially shifted through the selected data register from TDI to TDO on each TCK cycle. The

first shift does not occur until the first TCK cycle after entering this state (i.e., no shifting occurs during the TCK

cycle in which the TAP changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR). On the falling edge

of TCK in Shift-DR, TDO goes from the high-impedance state to the active state. TDO enables to the value

present in the least-significant bit of the selected data register.

Exit1-DR, Exit2-DR

These are temporary states used to end the shifting process. It is possible to return to the Shift-DR state from

either Exit1-DR or Exit2-DR without recapturing the data register. The last shift occurs on the TCK cycle in which

the TAP state changes from Shift-DR to Exit1-DR. TDO changes from the active state to the high-impedance

state on the falling edge of TCK in Exit1-DR.

Pause-DR

The TAP can remain in this state indefinitely. The Pause-DR state suspends and resumes shift operations

without loss of data.

Update-DR

If the current instruction calls for the latches in the selected data register to be updated with current data, the

latches are updated only during this state.

Capture-IR

The instruction register is preloaded with the IR status word (see Table 4) and placed in the scan path.

Shift-IR

In this state, data is serially shifted through the instruction register from TDI to TDO on each TCK cycle. The

first shift does not occur until the first TCK cycle after entering this state (i.e., no shifting occurs during the TCK

cycle in which the TAP changes from Capture-IR to Shift-IR or from Exit2-IR to Shift-IR). On the falling edge of

TCK in Shift-IR, TDO goes from the high-impedance state to the active state, and will enable to a high level.

6

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SCAS158D − JUNE 1990 − REVISED DECEMBER 1996

Exit1-IR, Exit2-IR

These are temporary states used to end the shifting process. It is possible to return to the Shift-IR state from

either Exit1-IR or Exit2-IR without recapturing the instruction register. The last shift occurs on the TCK cycle in

which the TAP state changes from Shift-IR to Exit1-IR. TDO changes from the active state to the

high-impedance state on the falling edge of TCK in Exit1-IR.

Pause-IR

The TAP can remain in this state indefinitely. The Pause-IR state suspends and resumes shift operations without

loss of data.

Update-IR

In this state, the latches shadowing the instruction register are updated with the new instruction.

instruction register description

The instruction register (IR) is an 8-bit serial register that outputs control signals to the device. Table 2 lists the

instructions implemented in the ’ACT8999 and the data register selected by each instruction. The MSB of the

IR is an even-parity bit. If the value scanned into the IR during Shift-IR does not contain even parity, an error

signal (IRERR) is generated internally as shown in Table 3. The ’ACT8999 can be configured to output IRERR

via DCO if the TAP enters the Pause-IR state.

During the Capture-IR state, the IR status word is loaded. The IR status word contains information about the

most recently loaded values of the instruction and select registers and the logic level present at the DCI input.

The IR status word is encoded as shown in Table 4. Figure 2 shows the order of scan for the IR.

Bit 7

(MSB)

Bit 0

(LSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

TDI or DTDI

TDO

Figure 2. Instruction-Register Bits and Order of Scan

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ꢄ ꢁ ꢋꢌꢄꢆ ꢍ ꢀꢎꢏ ꢎ ꢅꢆꢐ ꢑꢀ ꢒ ꢓ ꢆꢍ ꢇ ꢋꢔꢓ ꢆ ꢔꢓ ꢕꢓꢑꢎ ꢅꢆ ꢓꢐ ꢁꢄꢏ ꢕꢄꢆꢄ ꢔꢖꢀ ꢎꢀ

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SCAS158D − JUNE 1990 − REVISED DECEMBER 1996

Table 2. Instruction-Register Opcodes

BINARY CODE

BIT 7 → BIT 0

MSB → LSB

HEX

VALUE

SELECTED DATA

REGISTER

SCOPE OPCODE

DESCRIPTION

MODE

00000000

10000001

10000010

00000011

10000100

00000101

00000110

10000111

10001000

00001001

00001010

10001011

00001100

10001101

10001110

00001111

11111010

01111011

11111100

01111101

01111110

All others

00

81

82

03

84

05

06

87

88

09

0A

8B

0C

8D

8E

0F

FA

7B

FC

7D

7E

EXTEST

BYPASS

Boundary scan

Bypass scan

Boundary scan

Bypass

Test

Normal

Test

SAMPLE/PRELOAD

INTEST

Sample boundary

Boundary scan

Bypass scan

Boundary scan

Bypass

†

BYPASS

Normal

Bypass scan

Bypass

Bypass scan

Bypass

Bypass scan

Bypass

COUNT

Count

Bypass

Count

Bypass

†

BYPASS

Bypass scan

Bypass

†

Bypass scan

Bypass

Bypass scan

Bypass

BYPASS

SCANCN

SCANCNT

READCNT

SCANIDB

READIDB

SCANSEL

BYPASS

Bypass scan

Bypass

Control register scan

Counter scan

Counter read

Control

Counter

ID bus

ID bus register scan

ID bus register read

Select register scan

Bypass scan

ID bus

Select

Bypass

†

A SCOPE opcode exists but is not supported by the ’ACT8999.

Table 3. IRERR Function Table

NO. OF INSTRUCTION

REGISTER BITS = 1

IRERR

0, 2, 4, 6, 8

1, 3, 5, 7

1

0

Table 4. Instruction-Register Status Word

‡

VALUE

IR BIT

7

6

5

4

3

2

1

0

IRERR (see Table 3)

0

Level present at DCI input (1 = H, 0 = L)

SRERR (see Table 8)

0

1

‡

This value is loaded in the instruction register during

the Capture-IR TAP state.

8

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SCAS158D − JUNE 1990 − REVISED DECEMBER 1996

instruction-register opcode description

The operation of the ’ACT8999 is dependent on the instruction loaded into the instruction register. Each

instruction selects one of the data registers to be placed between TDI or DTDI and TDO during the Shift-DR

TAP state. All the required instructions of IEEE Standard 1149.1 are implemented in the ’ACT8999.

boundary scan

This instruction implements the required EXTEST and optional INTEST operations of IEEE Standard 1149.1.

The boundary-scan register (which includes the ID-bus register) is placed in the scan path. Data appearing at

input pins included in the boundary-scan register is captured. Data previously loaded into the output pins

included in the boundary-scan register is forced through the outputs.

bypass scan

This instruction implements the required BYPASS operation of IEEE Standard 1149.1. The bypass register is

placed in the scan path and preloads with a logic 0 during Capture-DR.

sample boundary

This instruction implements the required SAMPLE/PRELOAD operation of IEEE Standard 1149.1. The

boundary-scan register is placed in the scan path, and data appearing at the inputs and outputs included in the

boundary-scan register is sampled on the rising edge of TCK in Capture-DR.

count

The counter register begins counting on each DCI transition. The count begins from the value present in the

register before the count instruction was loaded. The counter can be configured by the control register to count

up or down on either the low-to-high or high-to-low transition of DCI. Counting occurs only while in the

Run-Test/Idle TAP state.

control-register scan

The control register is placed in the scan path for a subsequent shift operation. The register is not preloaded

during Capture-DR.

counter-register scan

The counter register is placed in the scan path. During Capture-DR, the current value of the counter is loaded

in the counter register. At Update-DR, the newly shifted value is preloaded to the counter.

counter-register read

The counter register is placed in the scan path. During Capture-DR, the prior preload value of the counter is

loaded into the counter register. At Update-DR, the newly shifted value is preloaded to the counter.

ID-bus-register scan

The ID-bus register (a subset of the boundary-scan register) is placed in the scan path for a subsequent shift

operation. The data appearing on the ID bus is loaded into the ID-bus register on the rising edge of TCK in

Capture-DR.

ID-bus register read

The ID-bus register is placed in the scan path for a subsequent shift operation. The register is not preloaded

during Capture-DR.

select-register scan

The select register is placed in the scan path for a subsequent shift operation. The register is not preloaded

during Capture-DR.

9

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SCAS158D − JUNE 1990 − REVISED DECEMBER 1996

control-register description

The control register (CTLR) is a 13-bit serial register that controls the enable and select functions of the

’ACT8999. A reset operation forces all bits to a logic 0. The contents of the control register are latched and

decoded during the Update-DR TAP state. The specific function of each bit is listed in Table 5. The enable and

select functions of the control register bits are mapped as follows:

Table 5. Control-Register Bit Mapping

BIT

VALUE

FUNCTION

0

1

Configure counter to count up

Configure counter to count down

12

0

Do not stop counting when the count reaches 00000000

Stop counting when the count reaches 00000000 (count down only)

Configure DCO as an active-low output

11

10

1

0

1

Configure DCO as an active-high output

00

01

DCO = Inactive (level depends on CTLR bit 10)

DCO = (IRERR • SRERR)

9, 8

10

11

0

DCO = CE, an internal logic 0 generated when the count is 00000000 (count down) or 11111111 (count up)

DCO = DCI

Do not mask IRERR and SRERR from DCO

7

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Mask IRERR and SRERR from DCO

Configure DCO as an open-drain output

Configure DCO as a 3-state output

Disable DCO

6

5

4

3

2

1

Enable DCO

Configure DCI as an active-low input

Configure DCI as an active-high input

Enable DTCK, DTDO, and DTMS(1−4)

Disable DTCK, DTDO, and DTMS(1−4)

Disable ID(1−8)

Enable ID(1−8)

Disable RBC

Enable RBC

DTRST = TRST

DTRST = L

0

1

Bit 12 − Up/Down

This bit sets the count mode of the counter register (reset condition = count up).

Bit 11 − Latch on Zero

The counter register can be configured to stop counting when its value is 00000000 and ignore subsequent

transitions on the counter clock, DCI. The latch-on-zero option is valid only in the count-down mode

(reset condition = do not latch on zero). The value of this bit has no effect on the operation of the counter if

CTLR bit 12 = 0.

Bit 10 − DCO Polarity Select

DCO can be configured as an active-low or active-high output (reset condition = active low).

10

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SCAS158D − JUNE 1990 − REVISED DECEMBER 1996

Bit 9/Bit 8 − DCO Source Select 1/DCO Source Select 0

DCO can be used to output two error signals generated by the ’ACT8999: IRERR (see Table 3) and SRERR

(see Table 8). Bits 9 and 8 can be set to output IRERR via DCO on the falling edge of TCK in the Pause-IR state

and SRERR via DCO on the falling edge of TCK in the Pause-DR state. DCO also can be configured to become

active when the value of the counter is 00000000, to follow DCI, or be set to a static high or low level (reset

condition = static high level).

Bit 7 − Parity Mask

The internal error signals can be masked from appearing on DCO even if bits 9 and 8 are set such that IRERR

and SRERR are output in the Pause-IR and Pause-DR states (reset condition = do not mask IRERR or SRERR).

Bit 6 − DCO Drive Select

DCO can be configured as either an open-drain or 3-state output (reset condition = open drain). The open-drain

configuration allows multiple DCO outputs to be used in a wired-OR or wired-AND application. The 3-state

configuration allows the DCO output to be connected to a bus.

Bit 5 − DCO Enable

When configured as

a

3-state output, DCO can be placed in the high-impedance state

(reset condition = disabled). If configured as an open-drain output and disabled, DCO outputs a high level.

Bit 4 − DCI Polarity Select

DCI can be configured as an active-low or active-high input (reset condition = active low).

Bit 3 − Device Test Pins Output Enable (active low)

DTCK, DTDO, and DTMS(1−4) pins can be placed in the high-impedance state (disabled) with this bit

(reset condition = enabled).

Bit 2 − ID Bus Enable

The ID bus (ID1−8) is a bidirectional bus. The output buffers are enabled and disabled with this bit

(reset condition = output buffers disabled).

Bit 1 − Remote-Bus-Controller (RBC) Enable

An RBC can issue protocol and data instructions to the select register if the ’ACT8999 is configured to allow

it (reset condition = RBC disabled). When an RBC is enabled, the TAP in the select register operates according

to the OTMS signal.

Bit 0 − Device Test Reset

DTRST can be configured to output a reset signal independently of the level on TRST (reset condition = no reset

signal issued).

Several control-register bits affect the functionality of the DCO output. The DCO function table is given

in Table 6. Figure 3 shows the order of scan for the control register.

TDI

or

DTDI

Bit 12

(MSB)

Bit 0

(LSB)

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

TDO

Figure 3. Control-Register Bits and Order of Scan

11

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ꢈ

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SCAS158D − JUNE 1990 − REVISED DECEMBER 1996

Table 6. DCO Function Table

†

‡

INTERNAL SIGNALS

CONTROL REGISTER BITS

DCI

DCO

IRERR

SRERR

CE

X

BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4

X

0

X

0

1

0

1

0

X

0

X

0

1

X

1

0

1

0

1

X

H

Z

H

L

X

H

L

X

1

§

X

0

L in Pause-IR , H otherwise

§

X

1

0

1

X

0

1

0

1

0

X

1

X

L in Pause-DR , H otherwise

H

§

X

H in Pause-IR , L otherwise

§

X

L

X

1

0

1

X

0

1

0

1

0

1

0

1

0

1

0

1

0

X

1

X

0

1

0

1

0

1

0

1

H in Pause-DR , L otherwise

L

X

0

H

L

1

X

H

L

H

L

H

L

†

‡

§

These signals are generated as described elsewhere in this data sheet.

The control register must contain these values after the TAP has passed through its most recent Update-DR state.

DCO becomes active on the falling edge of TCK as the TAP enters the appropriate pause state (Pause-IR or Pause-DR) and becomes inactive

on the falling edge of TCK as the TAP enters the appropriate exit2 state (Exit2-IR or Exit2-DR).

select register description

The select register (SR) is an 8-bit serial register that determines which one, if any, of the DTMS lines follows

the TMS or OTMS input. A reset operation forces all bits to a logic 0. The register is divided into four 2-bit

sections, each of which controls one DTMS output. Figure 4 shows the mapping of the bits to the DTMS outputs

and the order of scan. For each DTMS pin, the higher-order bit is the MSB and the lower-order bit is the LSB

(e.g., bit 3 is the MSB of DTMS2 and bit 2 is the LSB of DTMS2).

Bit 7

(MSB)

Bit 0

(LSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

TDI or DTDI

TDO

DTMS4

DTMS3

DTMS2

DTMS1

Figure 4. Select Register Bits and Order of Scan

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ꢀ ꢅꢄꢁ ꢋꢌꢄꢆꢍ ꢀꢎ ꢏꢎ ꢅꢆꢐ ꢑꢀ ꢒ ꢓꢆ ꢍ ꢇ ꢋꢔꢓ ꢆ ꢔꢓ ꢕꢓꢑꢎ ꢅꢆ ꢓꢐ ꢁꢄꢏ ꢕꢄꢆꢄ ꢔ ꢖꢀ ꢎ

ꢀ

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ꢊ

ꢃ

ꢄ

ꢅ

ꢆ

ꢇ

ꢈ

ꢀ

ꢅ

ꢄ

ꢁ

ꢋ

ꢅ

ꢐ

ꢁ

ꢆ

ꢑ

ꢐ

ꢏ

ꢎ

ꢕ

ꢓ

ꢎ

ꢀ

ꢆ

ꢕ

ꢗ

ꢃ

ꢈ

ꢘ

ꢗ

ꢙ

ꢚ

ꢆ

ꢄ

ꢛ

ꢜ

ꢆ

ꢄ

ꢌ

ꢝ

ꢖ

ꢏ

ꢆ

ꢓ

ꢌ

ꢏꢎ

ꢞꢎ

ꢑ

SCAS158D − JUNE 1990 − REVISED DECEMBER 1996

select register description (continued)

Only one of the four DTMS outputs can be selected to drive a secondary scan path with TMS or OTMS. If the

SR is loaded with an invalid value, an error signal (SRERR) is generated internally as shown in Table 8. If the

TAP enters the Pause-DR state, SRERR may be output via DCO (see Table 8). If the TAP enters the Update-DR

state while an invalid value is in the SR, all four DTMS outputs are set to a high level.

When a new 8-bit value is loaded into the SR, the configuration of one or more DTMS pins may change. If the

new value of the SR configures a DTMS pin to a static (high or low) level, it assumes that level on the falling

edge of TCK in the Update-DR TAP state. This condition is independent of any previous SR configurations. If

the new value of the SR forces a DTMS pin to follow TMS (i.e., select a single secondary scan path) and a DTMS

pin is currently in the TMS/OTMS-follow mode, the transfer of the DTMS line occurs on the falling edge of TCK

in the Update-DR TAP state. However, if the new configuration forces a DTMS pin to follow TMS/OTMS while

no other DTMS pin is selected, the DTMS pin does begin following TMS/OTMS until the falling edge of TCK

in the Run-Test/Idle TAP state; therefore, when an SSP is initially selected, the TAP state should travel from

Update-DR to Run-Test/Idle, not from Update-DR to Select-DR-Scan. Additionally, when deselecting from any

DTMS output the TAP state must proceed back through Capture-DR to fully disconnect from SSP operations.

The SR can also be accessed from an RBC. A test port in the register contains a TAP that can be enabled by

the control register to monitor the values of TCK and OTMS to perform scan operations on the SR. The SR bit

decoding is shown in Table 7.

Table 7. Select-Register Bit Decoding

DTMS

SOURCE

MSB

LSB

0

1

0

1

0

1

H

L

OTMS

TMS

Table 8. SRERR Function Table

SELECT REGISTER BITS

SRERR

BIT 7

BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

0

1

0

1

X

0

1

0

1

X

1

X

0

1

0

X

1

X

1

X

1

X

0

1

X

1

X

1

X

1

0

13

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ꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢈꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢆ ꢇ ꢈꢈ ꢈ

ꢄ ꢁ ꢋꢌꢄꢆ ꢍ ꢀꢎꢏ ꢎ ꢅꢆꢐ ꢑꢀ ꢒ ꢓ ꢆꢍ ꢇ ꢋꢔꢓ ꢆ ꢔꢓ ꢕꢓꢑꢎ ꢅꢆ ꢓꢐ ꢁꢄꢏ ꢕꢄꢆꢄ ꢔꢖꢀ ꢎꢀ

ꢄ

ꢁ

ꢋ

ꢅ

ꢐ

ꢁ

ꢆ

ꢑ

ꢐ

ꢏ

ꢎ

ꢕ

ꢓ

ꢎ

ꢀ

ꢆ

ꢕ

ꢗ

ꢃ

ꢈ

ꢘ

ꢗ

ꢙ

ꢚ

ꢆ

ꢄ

ꢛ

ꢜ

ꢆ

ꢄ

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ꢏ

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SCAS158D − JUNE 1990 − REVISED DECEMBER 1996

boundary-scan register/ID-bus register description

The boundary-scan register (BSR) is a 15-bit serial register that can be used to capture data appearing at

selected device inputs, force data through device outputs, and apply data to the device’s internal logic. The BSR

is made up of boundary-scan cells (BSCs). Table 9 lists the device signal for each of the 15 BSCs that comprise

the BSR. A reset operation does not affect the contents of the BSR.

Table 9. Boundary-Scan Register Bit Mapping

TERMINAL

NAME

BIT

SIGNAL DESCRIPTION

Master condition in

14

13

12

11

10

9

MCI

MCO

Master condition out

DCI

Device condition in

†

DCOTS

DCOOD

DCO

Enable control for DCO in 3-state configuration (active low)

Enable control for DCO in open-drain configuration (active low)

Device condition out

†

8

IDBOE

Enable control for ID bus (active low)

Identification bus bit 8

7

ID8

6

ID7

Identification bus bit 7

5

ID6

Identification bus bit 6

4

ID5

Identification bus bit 5

3

ID4

Identification bus bit 4

2

ID3

Identification bus bit 3

1

ID2

Identification bus bit 2

0

ID1

Identification bus bit 1

†

This internal signal cannot be observed from the I/O pins of the device.

The eight BSCs connected to the ID(1−8) pins form a subset of the BSR called the ID-bus register (IDBR). The

IDBR can be scanned without accessing the remaining BSCs of the BSR. The IDBR is used when the ID bus

is enabled to allow communication between a PBC and one or more RBCs. Figure 5 shows the order of scan

for the BSR and IDBR.

TDI

or

DTDI

Bit 14

(MSB)

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

TDI

or

DTDI

BSR

Bit 0

(LSB)

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

TDO

IDBR

Figure 5. Boundary-Scan Register Bits and Order of Scan

14

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ꢀ

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ꢈ

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ꢁ

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ꢓ

ꢎ

ꢎꢎ

ꢀ

ꢆ

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ꢃ

ꢈ

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ꢚ

ꢆ

ꢄ

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ꢆ

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SCAS158D − JUNE 1990 − REVISED DECEMBER 1996

bypass register description

The bypass register (BR) is a 1-bit serial register. The function of the BR is to provide a means of effectively

removing the ’ACT8999 from the primary scan path when it is not needed for the current test operation or other

function of the PBC. A selected secondary scan path remains active in the primary scan path as described in

the data flow description. At power up, the BR is placed in the scan path. Figure 6 shows the order of scan for

the bypass register.

TDI or DTDI

Bit 0

TDO

Figure 6. Bypass-Register Bit and Order of Scan

counter register description

The counter register (CNTR) is an 8-bit serial register and an associated 8-bit parallel-load up/down counter.

A reset operation forces all bits of the shift register to logic 0 but does not affect the counter. The counter can

be preloaded with an initial value before counting begins, and the current value of the counter can be scanned

out via the shift register. The CNTR can be used to count events occurring on the secondary scan path(s) using

DCI as a counter clock and can output interrupt signals via DCO when the count has reached its end value.

An internal signal, CE, is generated as a logic 0 when the count reaches its end value (i.e., 00000000 for count

down, 11111111 for count up). For any other count value, CE is a logic 1. Many of the features of the CNTR are

configured by a bit in the CTLR, including:

−

Count direction up or down (control register bit 12; reset condition count up)

Stop counting upon counting down to 00000000 (control register bit 11; reset condition = do not latch on

zero)

−

Output CE signals at DCO (control register bits 8 and 9; reset condition = do not output CE at DCO)

Edge of DCI on which to trigger (control register bit 4, reset condition = positive edge)

Figure 7 shows the order of scan for the CNTR.

Bit 7

(MSB)

Bit 0

(LSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

TDI or DTDI

TDO

Figure 7. Counter-Register Bits and Order of Scan

15

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ꢀ

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ꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢈꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢆ ꢇ ꢈꢈ ꢈ

ꢄ ꢁ ꢋꢌꢄꢆ ꢍ ꢀꢎꢏ ꢎ ꢅꢆꢐ ꢑꢀ ꢒ ꢓ ꢆꢍ ꢇ ꢋꢔꢓ ꢆ ꢔꢓ ꢕꢓꢑꢎ ꢅꢆ ꢓꢐ ꢁꢄꢏ ꢕꢄꢆꢄ ꢔꢖꢀ ꢎꢀ

ꢄ

ꢁ

ꢋ

ꢅ

ꢐ

ꢁ

ꢆ

ꢑ

ꢐ

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ꢎ

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ꢓ

ꢎ

ꢀ

ꢆꢕ

ꢗ

ꢃ

ꢈ

ꢘ

ꢗ

ꢙ

ꢚ

ꢆ

ꢄ

ꢛ

ꢜ

ꢆ

ꢄ

ꢌ

ꢝ

ꢖ

ꢏ

ꢆ

ꢓ

ꢌ

ꢏ

ꢎ

ꢞꢎ

ꢑ

ꢀ

SCAS158D − JUNE 1990 − REVISED DECEMBER 1996

enabling a remote bus controller

Bit 1 in the control register allows a remote bus controller to control parts of the ’ACT8999. When an RBC is

enabled, the remote test port (RTP) in the select register is activated. The RTP operates according to the same

state diagram as the primary test port but only has access to the select register. Operation of the RTP is

synchronous to TCK. OTMS is the RTP mode-select pin.

The RTP contains an 8-bit instruction register. Data is shifted in via DTDI and shifted out via DTDO. As shown

in Table 10, only one instruction selects something other than the bypass register to be included in the scan path.

When SCANSEL is executed, the select register is placed between DTDI and DTDO. The function of the select

register and the decoding of the select register bits by the TMS circuit is identical, regardless of which test port

accesses the register.

Table 10. Remote-Test-Port Instruction-Register Opcodes

BINARY CODE

BIT 7 → BIT 0

MSB → LSB

SCOPE

OPCODE

SELECTED

DATA REGISTER

DESCRIPTION

01111110

All other

SCANSEL

BYPASS

Select-register scan

Bypass scan

Select

Bypass

An internal error signal (RSRERR) is generated if an RBC loads an invalid value in the select register, and the

MCO output goes low if the RSRERR is active and the remote TAP enters the Pause-DR state. The function

table for RSRERR is shown in Table 11.

Table 11. RSRERR Function Table

SELECT REGISTER BITS

†

RSRERR

MCO

BIT 7

BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

0

1

0

1

X

0

1

0

1

X

1

X

0

1

0

X

1

X

1

X

1

X

0

1

X

1

X

1

X

1

0

MCI

L

†

This table is valid only when the remote TAP is in the Pause-DR state. Under any other condition,

MCO = MCI.

The RTP does not have access to the control register, so it cannot disable itself. The PBC must reset bit 1 in

the control register to return control of the select register to the primary test port.

16

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ꢀ ꢅꢄꢁ ꢋꢌꢄꢆꢍ ꢀꢎ ꢏꢎ ꢅꢆꢐ ꢑꢀ ꢒ ꢓꢆ ꢍ ꢇ ꢋꢔꢓ ꢆ ꢔꢓ ꢕꢓꢑꢎ ꢅꢆ ꢓꢐ ꢁꢄꢏ ꢕꢄꢆꢄ ꢔ ꢖꢀ ꢎ

ꢀ

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ꢆ

ꢇ

ꢈ

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ꢁ

ꢋ

ꢅ

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ꢁ

ꢆ

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ꢐ

ꢏ

ꢎꢕ

ꢓ

ꢎ

ꢀ

ꢆ

ꢕ

ꢗ

ꢃ

ꢈ

ꢘ

ꢗ

ꢙ

ꢚ

ꢆ

ꢄ

ꢛ

ꢜ

ꢆ

ꢄ

ꢌ

ꢝ

ꢖ

ꢏ

ꢆ

ꢓ

ꢌ

ꢏ

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SCAS158D − JUNE 1990 − REVISED DECEMBER 1996

data flow description

The direction of serial data flow in the ’ACT8999 is dependent on the current instruction. Figure 8 shows the

data flow for the different operating modes of the device. When a secondary scan path is selected, the ’ACT8999

adds one bit of delay from TDI to DTDO.

’ACT8999

IR or

Selected DR

TDI

TDO

RBC DISABLED, NO SECONDARY SCAN PATH SELECTED

Selected Scan Path

’ACT8999

IR or

Selected DR

TDI

(1-bit delay)

DTDO

TDI

TDO

DTDI

TDO

RBC DISABLED, ONE SECONDARY SCAN PATH SELECTED

Remote Bus Controller

TDI TDO

Selected Scan Path

’ACT8999

Secondary IR

or Select Register

DTDI

TDI

DTDO

TDO

TDI

TDO

IR or

Selected DR

RBC ENABLED

Figure 8. Data Flow in the ’ACT8999

bus-communication protocol

The 8-bit identification bus [ID(1−8)] allows data transfer between a PBC and an RBC. Control register bit 2

configures the ’ACT8999 to transmit or receive command and test data via the IDBR. The DCI, DCO, MCI, and

MCO pins are used to signal the PBC and RBC(s) that a data transfer is required. The ’ACT8999 can

accommodate either local or global handshake protocol, depending on the number of DCO inputs that the PBC

can accommodate.

Figure 9 shows a protocol for local communication between the PBC and an RBC. In this mode, communication

is initiated by the PBC by driving the MCI input of the ’ACT8999 to a low level. MCI is buffered and output on

MCO, which notifies the RBC that control of a scan path is to be relinquished. Prior to activating the MCI signal,

the PBC scans the value 00000000 into the IDBR and enables the output buffers of ID(1−8). When the RBC

recognizes that MCO has gone low, it samples the ID bus and looks for the 00000000 value to verify that the

PBC is going to issue further commands. Upon verifying the value on the ID bus, the RBC drives DCI low, which

is buffered and output via DCO. (In this example, DCI is configured as noninverting and DCO is configured as

active low). When the PBC sees that DCO is active, it takes MCI high, forcing MCO high. When the RBC sees

that MCO is high, it takes DCO high (inactive) completing one handshake cycle. A similar operation can ensue

when the RBC initiates communication with the PBC as shown in Figure 9. Commands and test data can be

exchanged between two bus controllers via the ID bus.

Figure 10 shows one way of using the ID bus to interface a PBC to multiple RBCs. The timing is similar to the

local communication example in Figure 9, except that the PBC waits for all RBCs to acknowledge transmissions

before switching MCI.

17

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ꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢈꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢆ ꢇ ꢈꢈ ꢈ

ꢄ ꢁ ꢋꢌꢄꢆ ꢍ ꢀꢎꢏ ꢎ ꢅꢆꢐ ꢑꢀ ꢒ ꢓ ꢆꢍ ꢇ ꢋꢔꢓ ꢆ ꢔꢓ ꢕꢓꢑꢎ ꢅꢆ ꢓꢐ ꢁꢄꢏ ꢕꢄꢆꢄ ꢔꢖꢀ ꢎꢀ

ꢄ

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ꢃ

ꢈꢘ

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SCAS158D − JUNE 1990 − REVISED DECEMBER 1996

IDCODE

00000000

COMMAND

00000000

IDCODE

ID(1−8)

MCI

DCO

LOCAL PBC-TO-RBC HANDSHAKE PROTOCOL

COMMAND

IDCODE

00000000

IDCODE

ID(1−8)

DCI

MCO

LOCAL RBC-TO-PBC HANDSHAKE PROTOCOL

Figure 9. Local Bus-Communication Protocol

IDCODE

00000000

COMMAND

00000000

IDCODE

ID(1−8)

MCI

DCO1

DCO2

DCOn

GLOBAL PBC-TO-RBC HANDSHAKE PROTOCOL

IDCODE

00000000

COMMAND

00000000

IDCODE

ID(1−8)

DCI1

DCI2

DCIn

MCO

GLOBAL RBC-TO-PBC HANDSHAKE PROTOCOL

Figure 10. Global Bus-Communication Protocol

18

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ꢀ

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ꢋ

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ꢓ

ꢎ

ꢀ

ꢆ

ꢕ

ꢗ

ꢃ

ꢈ

ꢘ

ꢗ

ꢙ

ꢚ

ꢆ

ꢄ

ꢛ

ꢜ

ꢆ

ꢄ

ꢌ

ꢝ

ꢖ

ꢏ

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SCAS158D − JUNE 1990 − REVISED DECEMBER 1996

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

CC

Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V

+ 0.5 V

I

CC

Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V

O

Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

IK

I

CC

Output clamp current, I

(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

OK

I I CC

Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA

O

CC

Maximum power dissipation at T = 55°C (in still air) (see Note 2): DW package . . . . . . . . . . . . . . . . . . 1.7 W

A

NT package . . . . . . . . . . . . . . . . . . . 1.3 W

Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage rating may be exceeded if the input and output clamp-current rating are observed.

2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils,

except for the NT package, which has trace length of zero. For more information, refer to the Package Thermal Considerations

application note in the ABT Advanced BiCMOS Technology Data Book, literature number SCBD002.

recommended operating conditions

SN54ACT8999 SN74ACT8999

UNIT

MIN

4.5

2

MAX

MIN

4.5

2

MAX

V

Supply voltage

5.5

V

CC

IH

IL

I

High-level input voltage

Low-level input voltage

Input voltage

0.8

0

V

0

V

CC

Output voltage

O

CC

−2

ID(1−8)

−1.5

−7

TDO, DTDO, MCO

−10

−16

2

I

High-level output current

mA

OH

OL

−11

1.5

7

DTMS(1−4), DCO (3 state), DTRST, DTCK

ID(1−8)

TDO, DTDO, MCO

10

16

24

48

70

DTMS(1−4), DCO (3 state or open drain)

11

I

Low-level output current

mA

16

DTRST

DTCK

32

T

A

Operating free-air temperature

−55

125

0

°C

19

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ꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢈꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢆ ꢇ ꢈꢈ ꢈ

ꢄ ꢁ ꢋꢌꢄꢆ ꢍ ꢀꢎꢏ ꢎ ꢅꢆꢐ ꢑꢀ ꢒ ꢓ ꢆꢍ ꢇ ꢋꢔꢓ ꢆ ꢔꢓ ꢕꢓꢑꢎ ꢅꢆ ꢓꢐ ꢁꢄꢏ ꢕꢄꢆꢄ ꢔꢖꢀ ꢎꢀ

ꢄ

ꢁ

ꢋ

ꢅ

ꢐ

ꢁ

ꢆ

ꢑ

ꢐ

ꢏ

ꢎ

ꢕ

ꢓ

ꢎ

ꢀ

ꢆ

ꢕ

ꢗ

ꢃ

ꢈꢘ

ꢗ

ꢙ

ꢚ

ꢆ

ꢄ

ꢛ

ꢜ

ꢆ

ꢄ

ꢌ

ꢝ

ꢖ

ꢏ

ꢆ

ꢓ

ꢌ

ꢏ

ꢎ

ꢞ

ꢎ

ꢑꢀ

SCAS158D − JUNE 1990 − REVISED DECEMBER 1996

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

SN54ACT8999

SN74ACT8999

PARAMETER

TEST CONDITIONS

V

CC

UNIT

†

MIN

MAX

MIN TYP

MAX

I

= −1.5 mA

= −2 mA

= −7 mA

= −10 mA

= −11 mA

= −16 mA

= 1.5 mA

= 2 mA

4.5 V

3.6

OH

OL

ID(1−8)

3.7

3.6

V

TDO, DTDO, MCO

V

OH

DTMS(1−4), DCO (3 state),

DTRST, DTCK

0.5

ID(1−8)

0.5

= 7 mA

TDO, DTDO, MCO

= 10 mA

= 11 mA

= 16 mA

= 24 mA

= 32 mA

= 48 mA

DTMS(1−4), DCO

(3 state or open drain)

V

OL

V

DTRST

DTCK

0.5

5

ID(1−8), DTDO, DTMS(1−4),

DCO, DTCK

‡

I

OZ

V

= V

or GND

5.5 V

10

µA

O

CC

I

DCO (open drain)

MCI, DCI, TCK

V

= V

5.5 V

20

1

10

1

OH

O

V = V

I

or GND

CC

V = V

I

1

I

µA

TDI, DTDI, TMS, OTMS, TRST

V = GND

−0.1

−20

100

−0.1

−20

100

I

V = V

CC

or GND,

I = 0

O

µA

CC

I

One input at V = 3.4 V,

I

§

∆I

CC

5.5 V

1

mA

Other inputs at V

CC

or GND

C

V = V

CC

or GND

6

15

10

pF

i

I

V

O

V

O

V

O

= V

or GND

io

o

CC

MCI, DCI, TCK

DCO

= V

o

†

‡

§

Typical values are at V

= 5 V.

includes the input-leakage current. For DCO, the parameter I

CC

For I/O, the parameter I

OZ OZ

This is the increase in supply current for each input being driven at TTL levels rather than V

includes the open-drain output-leakage current.

or GND.

CC

20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

ꢇ

ꢈ

ꢉ

ꢀ ꢅꢄꢁ ꢋꢌꢄꢆꢍ ꢀꢎ ꢏꢎ ꢅꢆꢐ ꢑꢀ ꢒ ꢓꢆ ꢍ ꢇ ꢋꢔꢓ ꢆ ꢔꢓ ꢕꢓꢑꢎ ꢅꢆ ꢓꢐ ꢁꢄꢏ ꢕꢄꢆꢄ ꢔ ꢖꢀ ꢎ

ꢀ

ꢁ

ꢊ

ꢃ

ꢄ

ꢅ

ꢆ

ꢇ

ꢈ

ꢀ

ꢅ

ꢄ

ꢁ

ꢋ

ꢅ

ꢐ

ꢁ

ꢆ

ꢑ

ꢐ

ꢏ

ꢎ

ꢕ

ꢓ

ꢎ

ꢀꢆ

ꢕ

ꢗ

ꢃ

ꢈ

ꢘ

ꢗ

ꢙ

ꢚ

ꢆ

ꢄ

ꢛ

ꢜ

ꢆ

ꢄ

ꢌ

ꢝ

ꢖ

ꢏ

ꢆ

ꢓ

ꢌ

ꢏ

ꢎ

ꢞ

ꢎ

ꢑ

SCAS158D − JUNE 1990 − REVISED DECEMBER 1996

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (see Figures 11 and 12)

SN54ACT8999 SN74ACT8999

UNIT

MIN

0

MAX

20

MIN

0

MAX

20

TCK

f

t

Clock frequency

Pulse duration

MHz

ns

clock

DCI (count mode)

TCK high or low

DCI high or low (count mode)

TRST low

0

20

0

20

16

9

16

9

w

10

9

10

9

TMS before TCK↑

OTMS before TCK↑

TDI before TCK↑

DTDI before TCK↑

MCI before TCK↑

DCI before TCK↑

Any ID before TCK↑

TMS after TCK↑

OTMS after TCK↑

TDI after TCK↑

12

11

5

12

11

5

t

su

Setup time

ns

5

9

3

2

4

DTDI after TCK↑

MCI after TCK↑

DCI after TCK↑

4

t

Hold time

ns

h

5

Any ID after TCK↑

Power up to TCK↑

5

Delay time

100*

100

d

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

21

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

ꢀ

ꢁ

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ꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢈꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢆ ꢇ ꢈꢈ ꢈ

ꢄ ꢁ ꢋꢌꢄꢆ ꢍ ꢀꢎꢏ ꢎ ꢅꢆꢐ ꢑꢀ ꢒ ꢓ ꢆꢍ ꢇ ꢋꢔꢓ ꢆ ꢔꢓ ꢕꢓꢑꢎ ꢅꢆ ꢓꢐ ꢁꢄꢏ ꢕꢄꢆꢄ ꢔꢖꢀ ꢎꢀ

ꢄ

ꢁ

ꢋ

ꢅ

ꢐ

ꢁ

ꢆ

ꢑ

ꢐ

ꢏ

ꢎ

ꢕ

ꢓ

ꢎ

ꢀ

ꢆ

ꢕ

ꢗꢗ

ꢃ

ꢈ

ꢘ

ꢗ

ꢙ

ꢚ

ꢆ

ꢄ

ꢛ

ꢜ

ꢆ

ꢄ

ꢌ

ꢝ

ꢖ

ꢏ

ꢆ

ꢓ

ꢌ

ꢏ

ꢎ

ꢞ

ꢎ

ꢑ

ꢀ

SCAS158D − JUNE 1990 − REVISED DECEMBER 1996

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature (see Figures 11 and 12)

SN54ACT8999 SN74ACT8999

FROM

(INPUT)

TO

(OUTPUT)

PARAMETER

UNIT

MHz

ns

MIN

20

3

MAX

MIN

20

3

MAX

TCK

f

max

DCI (count mode)

t

16

19

14

17

PLH

PHL

PLH

PHL

PLH

PHL

PLH

PHL

PLH

PHL

PLH

PHL

PLH

PHL

TCK

DTCK

3

7

30

29

31

29

40

37

35

64

65

34

31

45

40

39

37

22

23

22

23

26

25

32

30

34

30

20

25

7

8

28

27

29

27

38

35

33

61

62

32

29

42

38

37

35

20

21

20

21

24

23

30

28

32

28

18

23

TCK↓

TDO

DTDO

ns

7

8

11

9

11

10

22

24

9

Any DTMS

DTRST

Any ID

9

20

22

9

MCO

9

DCO (open drain)

DCO (3 state)

14

10

5

18

11

6

t

PLH

PHL

TCK↓

ns

DCO (open drain)

DCO (3 state)

t

PLH

PHL

PLH

PHL

PLH

PHL

TMS

OTMS

MCI

Any DTMS

MCO

ns

4

5

6

4

5

7

8

6

7

DCO (open drain)

DCO (3 state)

8

9

t

PLH

PHL

8

10

9

DCI

ns

DCO (open drain)

DCO (3 state)

8

t

8

9

t

4

5

PLH

TRST

DTRST

5

6

PHL

22

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

ꢇ

ꢈ

ꢉ

ꢀ ꢅꢄꢁ ꢋꢌꢄꢆꢍ ꢀꢎ ꢏꢎ ꢅꢆꢐ ꢑꢀ ꢒ ꢓꢆ ꢍ ꢇ ꢋꢔꢓ ꢆ ꢔꢓ ꢕꢓꢑꢎ ꢅꢆ ꢓꢐ ꢁꢄꢏ ꢕꢄꢆꢄ ꢔ ꢖꢀ ꢎ

ꢀ

ꢁ

ꢊ

ꢃ

ꢄ

ꢅ

ꢆ

ꢇ

ꢈ

ꢀ

ꢅ

ꢄ

ꢁ

ꢋ

ꢅ

ꢐ

ꢁ

ꢆ

ꢑ

ꢐ

ꢏ

ꢎ

ꢕ

ꢓ

ꢎ

ꢀ

ꢆ

ꢕ

ꢗ

ꢃ

ꢈ

ꢘ

ꢗ

ꢙ

ꢚ

ꢆ

ꢄ

ꢛ

ꢜ

ꢆ

ꢄ

ꢌ

ꢝ

ꢖ

ꢏ

ꢆ

ꢓ

ꢌ

ꢏꢎ

ꢞ

ꢎ

ꢑ

SCAS158D − JUNE 1990 − REVISED DECEMBER 1996

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature (see Figures 11 and 12) (continued)

SN54ACT8999 SN74ACT8999

FROM

(INPUT)

TO

(OUTPUT)

PARAMETER

UNIT

ns

MIN

3

MAX

17

18

26

28

31

38

34

27

33

35

36

39

40

34

46

38

73

58

65

62

MIN

4

MAX

15

16

24

26

29

36

32

25

31

33

34

37

38

32

43

36

70

65

62

59

t

PHZ

PLZ

PHZ

PLZ

PHZ

PLZ

PHZ

PLZ

PHZ

PLZ

PHZ

PLZ

PZH

PZL

PZH

PZL

PZH

PZL

PZH

PZL

PZH

PZL

PZH

PZL

TCK↓

DCI

TDO

DTDO

Any DTMS

DCO

3

5

3

7

8

7

9

12

7

12

9

14

10

9

Any ID

TDO

8

10

9

15

9

TCK↓

MCI

9

11

12

9

10

8

DTDO

Any DTMS

DCO

8

9

12

10

20

22

18

20

14

11

22

24

20

Any ID

23

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

ꢀ

ꢁ

ꢅ

ꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢈꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢆ ꢇ ꢈꢈ ꢈ

ꢄ ꢁ ꢋꢌꢄꢆ ꢍ ꢀꢎꢏ ꢎ ꢅꢆꢐ ꢑꢀ ꢒ ꢓ ꢆꢍ ꢇ ꢋꢔꢓ ꢆ ꢔꢓ ꢕꢓꢑꢎ ꢅꢆ ꢓꢐ ꢁꢄꢏ ꢕꢄꢆꢄ ꢔꢖꢀ ꢎꢀ

ꢄ

ꢁ

ꢋꢅꢐ

ꢁ

ꢆ

ꢑ

ꢐ

ꢏ

ꢎ

ꢕ

ꢓ

ꢎ

ꢀ

ꢆ

ꢕ

ꢗ

ꢃ

ꢈ

ꢘ

ꢗ

ꢙ

ꢚ

ꢆ

ꢄ

ꢛ

ꢜ

ꢆ

ꢄ

ꢌ

ꢝ

ꢖ

ꢏ

ꢆ

ꢓ

ꢌ

ꢏ

ꢎ

ꢞ

ꢎ

ꢑ

ꢀ

SCAS158D − JUNE 1990 − REVISED DECEMBER 1996

APPLICATION INFORMATION

Subsystem

TDO

TCK

TMS

TRST

TDI

SSP4

SSP3

SSP2

SSP1

TRST

TDI

TDO

TCK

TMS

TRST

TDI

TDO

TCK

TMS

TDO

TCK

TMS

TRST

TDI

4

INT3

DCI

TDI

DTDO

MCO

RBC

’ACT8999

INT2

TMSOUT

OTMS

8

ID

ID(1−8)

TDO

INT1

RSTOUT

To Remainder

of Primary

Scan Path

TMSOUT

TCKOUT

PBC

INT2

TDI

24

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

ꢇ

ꢈ

ꢉ

ꢀ ꢅꢄꢁ ꢋꢌꢄꢆꢍ ꢀꢎ ꢏꢎ ꢅꢆꢐ ꢑꢀ ꢒ ꢓꢆ ꢍ ꢇ ꢋꢔꢓ ꢆ ꢔꢓ ꢕꢓꢑꢎ ꢅꢆ ꢓꢐ ꢁꢄꢏ ꢕꢄꢆꢄ ꢔ ꢖꢀ ꢎ

ꢀ

ꢁ

ꢊ

ꢃ

ꢄ

ꢅ

ꢆ

ꢇ

ꢈ

ꢀ

ꢅ

ꢄ

ꢁ

ꢋ

ꢅ

ꢐ

ꢁ

ꢆ

ꢑ

ꢐ

ꢏ

ꢎ

ꢕ

ꢓ

ꢎ

ꢀ

ꢆ

ꢕ

ꢗ

ꢃ

ꢈ

ꢘ

ꢗ

ꢙ

ꢚ

ꢆ

ꢄ

ꢛ

ꢜ

ꢆ

ꢄ

ꢌ

ꢝ

ꢖ

ꢏ

ꢆ

ꢓ

ꢌ

ꢏ

ꢎ

ꢞꢎ

ꢑ

SCAS158D − JUNE 1990 − REVISED DECEMBER 1996

PARAMETER MEASUREMENT INFORMATION

2 × V

CC

TEST

S1

t

/t

Open

PLH PHL

/t

500 Ω

Open

GND

From Output

Under Test

t

2 × V

CC

GND

PLZ PZL

t

/t

PHZ PZH

C

= 50 pF

L

500 Ω

(see Note A)

LOAD CIRCUIT

3 V

0 V

Timing Input

Data Input

1.5 V

t

w

t

h

t

3 V

0 V

su

3 V

0 V

Input

1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Output

Control

(low-level

enabling)

3 V

0 V

3 V

Input

1.5 V

0 V

t

PZL

t

PHL

PLH

PHL

t

PLZ

Output

Waveform 1

V

OH

[ V

CC

In-Phase

Output

50% V

CC

50% V

CC

V

CC

20% V

S1 at 2 × V

(see Note B)

CC

V

OL

t

PHZ

t

PLH

t

PZH

Output

Waveform 2

S1 at GND

V

OH

V

OH

Out-of-Phase

Output

80% V

CC

50% V

CC

[ 0 V

V

OL

(see Note B)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

NOTES: A. C includes probe and jig capacitance.

L

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.

O

r

f

For testing pulse duration: t = 1 to 3 ns, t = 1 to 3 ns. Pulse polarity may be either high-to-low-to-high or a low-to-high-to-low.

r

f

D. The outputs are measured one at a time with one input transition per measurement.

Figure 11. Load Circuit and Voltage Waveforms (For All Pins Except ID-Bus Pins)

25

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

ꢀ

ꢁ

ꢅ

ꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢈꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢆ ꢇ ꢈꢈ ꢈ

ꢄ ꢁ ꢋꢌꢄꢆ ꢍ ꢀꢎꢏ ꢎ ꢅꢆꢐ ꢑꢀ ꢒ ꢓ ꢆꢍ ꢇ ꢋꢔꢓ ꢆ ꢔꢓ ꢕꢓꢑꢎ ꢅꢆ ꢓꢐ ꢁꢄꢏ ꢕꢄꢆꢄ ꢔꢖꢀ ꢎꢀ

ꢄ

ꢁ

ꢋꢅꢐ

ꢁꢆ

ꢑ

ꢐ

ꢏ

ꢎ

ꢕ

ꢓ

ꢎ

ꢎꢎ

ꢀ

ꢆꢕ

ꢗꢗ

ꢃ

ꢈ

ꢘ

ꢗ

ꢙꢚ

ꢆ

ꢄ

ꢛ

ꢜ

ꢆ

ꢄ

ꢌ

ꢝ

ꢖꢏꢆ

ꢓ

ꢌ

ꢏ

ꢎ

ꢞ

ꢎ

ꢑ

ꢀ

SCAS158D − JUNE 1990 − REVISED DECEMBER 1996

PARAMETER MEASUREMENT INFORMATION

V

CC

TEST

S1

t

/t

Open

PLH PHL

/t

1k Ω

Open

From Output

Under Test

t

V

CC

GND

PLZ PZL

GND

t

/t

PHZ PZH

C

= 50 pF

L

(see Note A)

LOAD CIRCUIT

3 V

0 V

Timing Input

Data Input

1.5 V

t

w

t

h

t

3 V

su

3 V

0 V

Input

1.5 V

0 V

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Output

Control

(low-level

enabling)

3 V

0 V

3 V

1.5 V

Input

1.5 V

0 V

t

PZL

t

PHL

PLH

t

PLZ

Output

Waveform 1

V

OH

[ V

CC

In-Phase

Output

50% V

CC

50% V

CC

V

CC

10% V

S1 at 2 × V

(see Note B)

CC

V

OL

t

PHZ

t

PLH

t

PHL

PZH

Output

Waveform 2

S1 at GND

V

OH

V

OH

Out-of-Phase

Output

90% V

CC

50% V

CC

[ 0 V

V

OL

(see Note B)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

NOTES: A. C includes probe and jig capacitance.

L

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.

O

r

f

For testing pulse duration: t = 1 to 3 ns, t = 1 to 3 ns. Pulse polarity may be either high-to-low-to-high or a low-to-high-to-low.

r

f

D. The outputs are measured one at a time with one input transition per measurement.

Figure 12. Load Circuit and Voltage Waveforms (ID-Bus Pins)

26

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

PACKAGE OPTION ADDENDUM

www.ti.com

18-Sep-2008

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

SOIC

PDIP

Drawing

SN74ACT8999DW

SN74ACT8999NT

OBSOLETE

DW

28

TBD

Call TI

NT

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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Addendum-Page 1

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型号：	SN54ACT8999
厂家：	TEXAS INSTRUMENTS
描述：	SCAN-PATH SELECTORS WITH 8-BIT BIDIRECTIONAL DATA BUSES SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP MULTIPLEXERS 具有8位双向数据总线扫描路径SELECTORS扫描控IEEE 1149.1 （ JTAG ） TAP多路复用器复用器
文件：	总29页 (文件大小：435K)
中文：	中文翻译
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