SM74101/NOPB [TI]
SM74101/NOPB;
| 型号： | SM74101/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SM74101/NOPB |
| 文件： | 总12页 (文件大小：682K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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April 2006
LM5112
Tiny 7A MOSFET Gate Driver
General Description
Features
n Compound CMOS and bipolar outputs reduce output
current variation
The LM5112 MOSFET gate driver provides high peak gate
drive current in the tiny LLP-6 package (SOT23 equivalent
footprint) or an 8-Lead exposed-pad MSOP package, with
improved power dissipation required for high frequency op-
eration. The compound output driver stage includes MOS
and bipolar transistors operating in parallel that together sink
more than 7A peak from capacitive loads. Combining the
unique characteristics of MOS and bipolar devices reduces
drive current variation with voltage and temperature. Under-
voltage lockout protection is provided to prevent damage to
the MOSFET due to insufficient gate turn-on voltage. The
LM5112 provides both inverting and non-inverting inputs to
satisfy requirements for inverting and non-inverting gate
drive with a single device type.
n 7A sink/3A source current
n Fast propagation times (25 ns typical)
n Fast rise and fall times (14 ns/12 ns rise/fall with 2 nF
load)
n Inverting and non-inverting inputs provide either
configuration with a single device
n Supply rail under-voltage lockout protection
n Dedicated input ground (IN_REF) for split supply or
single supply operation
n Power Enhanced 6-pin LLP package (3.0mm x 3.0mm)
or thermally enhanced MSOP8-EP package
n Output swings from VCC to VEE which can be negative
relative to input ground
Block Diagram
20066801
Block Diagram of LM5112
© 2006 National Semiconductor Corporation
DS200668
www.national.com
Pin Configurations
20066817
MSOP8-EP
20066802
LLP-6
Ordering Information
NSC Package
Drawing
Order Number
LM5112MY
Package Type
Supplied As
Exposed DAP MSOP8-EP
Exposed DAP MSOP8-EP
LLP-6
MUY08A
MUY08A
SDE06A
1000 shipped in Tape & Reel
3500 shipped in Tape & Reel
1000 shipped in Tape & Reel
4500 shipped in Tape & Reel
LM5112MYX
LM5112SD
LM5112SDX
LLP-6
SDE06A
Pin Descriptions
Pin
Name
Description
Application Information
LLP-6
MSOP-8
1
4
IN
Non-inverting input pin
TTL compatible thresholds. Pull up to VCC when
not used.
2
3
VEE
Power ground for driver outputs
Connect to either power ground or a negative
gate drive supply for positive or negative voltage
swing.
3
4
5
6
7
1
VCC
Positive Supply voltage input
Gate drive output
Locally decouple to VEE. The decoupling
capacitor should be located close to the chip.
Capable of sourcing 3A and sinking 7A. Voltage
swing of this output is from VEE to VCC.
Connect to power ground (VEE) for standard
positive only output voltage swing. Connect to
system logic ground when VEE is connected to a
negative gate drive supply.
OUT
IN_REF
Ground reference for control
inputs
6
2
INB
Inverting input pin
TTL compatible thresholds. Connect to IN_REF
when not used.
- - -
- - -
5, 8
- - -
N/C
Not internally connected
Exposed Pad, underside of
package
Exposed
Pad
Internally bonded to the die substrate. Connect to
VEE ground pin for low thermal impedance.
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2
Absolute Maximum Ratings (Note 1)
IN_REF to VEE
−0.3V to 5V
−55˚C to +150˚C
+150˚C
Storage Temperature Range
Maximum Junction Temperature
Operating Junction Temperature
ESD Rating
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
−40˚C+125˚C
2kV
VCC to VEE
−0.3V to 15V
−0.3V to 15V
−0.3V to 15V
VCC to IN_REF
IN/INB to IN_REF
Electrical Characteristics TJ = −40˚C to +125˚C, VCC = 12V, INB = IN_REF = VEE = 0V, No Load on out-
put, unless otherwise specified.
SYMBOL
SUPPLY
VCC
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC Operating Range
VCC – IN_REF and VCC - VEE
3.5
2.4
14
V
V
UVLO
VCCH
VCC Under-voltage Lockout (rising) VCC – IN_REF
VCC Under-voltage Hysteresis
3.0
230
1.0
3.5
mV
mA
ICC
VCC Supply Current
2.0
CONTROL INPUTS
VIH
VIL
Logic High
2.3
V
V
Logic Low
0.8
2.3
2.0
VthH
VthL
HYS
IIL
High Threshold
Low Threshold
Input Hysteresis
Input Current Low
Input Current High
1.3
0.8
1.75
1.35
400
0.1
V
V
mV
µA
µA
IN = INB = 0V
IN = INB = VCC
-1
-1
1
1
IIH
0.1
OUTPUT DRIVER
ROH
Output Resistance High
IOUT = -10mA (Note 2)
IOUT = 10mA (Note 2)
OUT = VCC/2, 200ns pulsed
current
30
1.4
3
50
Ω
Ω
A
ROL
Output Resistance Low
Peak Source Current
2.5
ISOURCE
ISINK
Peak Sink Current
OUT = VCC/2, 200ns pulsed
current
7
A
SWITCHING CHARACTERISTICS
td1
Propagation Delay Time Low to
CLOAD = 2 nF, see Figure 1
CLOAD = 2 nF, see Figure 1
25
25
40
40
ns
ns
High,
IN/ INB rising ( IN to OUT)
Propagation Delay Time High to
Low,
td2
IN / INB falling (IN to OUT)
Rise time
tr
tf
CLOAD = 2 nF , see Figure 1
CLOAD = 2 nF , see Figure 1
14
12
ns
ns
Fall time
LATCHUP PROTECTION
AEC –Q100, METHOD 004
THERMAL RESISTANCE
TJ = 150˚C
500
mA
θJA
Junction to Ambient,
LLP-6 Package
40
60
˚C/W
˚C/W
0 LFPM Air Flow
Junction to Case
MSOP8-EP Package
LLP-6 Package
θJC
7.5
4.7
MSOP8-EP Package
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device
is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: The output resistance specification applies to the MOS device only. The total output current capability is the sum of the MOS and Bipolar devices.
3
www.national.com
Timing Waveforms
20066805
20066804
(b)
(a)
FIGURE 1. (a) Inverting, (b) Non-Inverting
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4
Typical Performance Characteristics
Supply Current vs Frequency
Supply Current vs Capacitive Load
20066808
20066807
Rise and Fall Time vs Supply Voltage
Rise and Fall Time vs Temperature
20066809
20066810
Rise and Fall Time vs Capacitive Load
Delay Time vs Supply Voltage
20066811
20066812
5
www.national.com
Typical Performance Characteristics (Continued)
Delay Time vs Temperature
RDSON vs Supply Voltage
20066813
20066814
UVLO Thresholds and Hysteresis vs Temperature
Peak Current vs Supply Voltage
20066816
20066815
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6
Simplified Application Block Diagram
20066803
FIGURE 2. Simplified Application Block Diagram
vide the option of single supply or split supply configurations.
When driving the MOSFET gates from a single positive
supply, the IN_REF and VEE pins are both connected to the
power ground.
Detailed Operating Description
The LM5112 is a high speed , high peak current (7A) single
channel MOSFET driver. The high peak output current of the
LM5112 will switch power MOSFET’s on and off with short
rise and fall times, thereby reducing switching losses con-
siderably. The LM5112 includes both inverting and non-
inverting inputs that give the user flexibility to drive the
MOSFET with either active low or active high logic signals.
The driver output stage consists of a compound structure
with MOS and bipolar transistor operating in parallel to opti-
mize current capability over a wide output voltage and oper-
ating temperature range. The bipolar device provides high
peak current at the critical Miller plateau region of the MOS-
FET VGS , while the MOS device provides rail-to-rail output
swing. The totem pole output drives the MOSFET gate be-
tween the gate drive supply voltage VCC and the power
ground potential at the VEE pin.
The isolated input and output stage grounds provide the
capability to drive the MOSFET to a negative VGS voltage for
a more robust and reliable off state. In split supply configu-
ration, the IN_REF pin is connected to the ground of the
controller which drives the LM5112 inputs. The VEE pin is
connected to a negative bias supply that can range from the
IN_REF potential to as low as 14 V below the Vcc gate drive
supply. For reliable operation, the maximum voltage differ-
ence between VCC and IN_REF or between VCC and VEE is
14V.
The minimum recommended operating voltage between Vcc
and IN_REF is 3.5V. An Under Voltage Lock Out (UVLO)
circuit is included in the LM5112 which senses the voltage
difference between VCC and the input ground pin, IN_REF.
When the VCC to IN_REF voltage difference falls below 2.8V
the driver is disabled and the output pin is held in the low
state. The UVLO hysteresis prevents chattering during
The control inputs of the driver are high impedance CMOS
buffers with TTL compatible threshold voltages. The nega-
tive supply of the input buffer is connected to the input
ground pin IN_REF. An internal level shifting circuit connects
the logic input buffers to the totem pole output drivers. The
level shift circuit and separate input/output ground pins pro-
7
www.national.com
Detailed Operating Description
(Continued)
brown-out conditions; the driver will resume normal opera-
tion when the VCC to IN_REF differential voltage exceeds
3.0V.
Layout Considerations
Attention must be given to board layout when using LM5112.
Some important considerations include:
1. A Low ESR/ESL capacitor must be connected close to
the IC and between the VCC and VEE pins to support
high peak currents being drawn from VCC during turn-on
of the MOSFET.
2. Proper grounding is crucial. The driver needs a very low
impedance path for current return to ground avoiding
inductive loops. Two paths for returning current to
ground are a) between LM5112 IN_REF pin and the
ground of the circuit that controls the driver inputs and b)
between LM5112 VEE pin and the source of the power
MOSFET being driven. Both paths should be as short as
possible to reduce inductance and be as wide as pos-
sible to reduce resistance. These ground paths should
be distinctly separate to avoid coupling between the high
current output paths and the logic signals that drive the
LM5112. With rise and fall times in the range of 10 to
30nsec, care is required to minimize the lengths of cur-
rent carrying conductors to reduce their inductance and
EMI from the high di/dt transients generated when driv-
ing large capacitive loads.
20066806
FIGURE 3.
The schematic above shows a conceptual diagram of the
LM5112 output and MOSFET load. Q1 and Q2 are the
switches within the gate driver. Rg is the gate resistance of
the external MOSFET, and Cin is the equivalent gate capaci-
tance of the MOSFET. The equivalent gate capacitance is a
difficult parameter to measure as it is the combination of Cgs
(gate to source capacitance) and Cgd (gate to drain capaci-
tance). The Cgd is not a constant and varies with the drain
voltage. The better way of quantifying gate capacitance is
the gate charge Qg in coloumbs. Qg combines the charge
required by Cgs and Cgd for a given gate drive voltage
Vgate. The gate resistance Rg is usually very small and
losses in it can be neglected. The total power dissipated in
the MOSFET driver due to gate charge is approximated by:
3. If either channel is not being used, the respective input
pin (IN or INB) should be connected to either VEE or VCC
to avoid spurious output signals.
PDRIVER = VGATE x QG x FSW
Where
Thermal Performance
FSW = switching frequency of the MOSFET.
For example, consider the MOSFET MTD6N15 whose gate
charge specified as 30 nC for VGATE = 12V.
INTRODUCTION
The primary goal of the thermal management is to maintain
the integrated circuit (IC) junction temperature (Tj) below a
specified limit to ensure reliable long term operation. The
maximum TJ of IC components should be estimated in worst
case operating conditions. The junction temperature can be
calculated based on the power dissipated on the IC and the
junction to ambient thermal resistance θJA for the IC pack-
age in the application board and environment. The θJA is not
a given constant for the package and depends on the PCB
design and the operating environment.
Therefore, the power dissipation in the driver due to charging
and discharging of MOSFET gate capacitances at switching
frequency of 300 kHz and VGATE of 12V is equal to
PDRIVER = 12V x 30 nC x 300 kHz = 0.108W.
In addition to the above gate charge power dissipation, -
transient power is dissipated in the driver during output
transitions. When either output of the LM5112 changes state,
current will flow from VCC to VEE for a very brief interval of
time through the output totem-pole N and P channel
MOSFETs. The final component of power dissipation in the
driver is the power associated with the quiescent bias cur-
rent consumed by the driver input stage and Under-voltage
lockout sections.
DRIVE POWER REQUIREMENT CALCULATIONS IN
LM5112
LM5112 is a single low side MOSFET driver capable of
sourcing / sinking 3A / 7A peak currents for short intervals to
drive a MOSFET without exceeding package power dissipa-
tion limits. High peak currents are required to switch the
MOSFET gate very quickly for operation at high frequencies.
Characterization of the LM5112 provides accurate estimates
of the transient and quiescent power dissipation compo-
nents. At 300 kHz switching frequency and 30 nC load used
in the example, the transient power will be 8 mW. The 1 mA
nominal quiescent current and 12V VGATE supply produce a
12 mW typical quiescent power.
Therefore the total power dissipation
PD = 0.118 + 0.008 + 0.012 = 0.138W.
We know that the junction temperature is given by
TJ = PD x θJA + TA
Or the rise in temperature is given by
TRISE = TJ − TA = PD x θJA
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8
surroundings, θJA as low as 40˚C / Watt is achievable with
the package. The resulting Trise for the driver example
above is thereby reduced to just 5.5 degrees.
Thermal Performance (Continued)
For LLP-6 package, the integrated circuit die is attached to
leadframe die pad which is soldered directly to the printed
circuit board. This substantially decreases the junction to
ambient thermal resistance (θJA). By providing suitable
means of heat dispersion from the IC to the ambient through
exposed copper pad, which can readily dissipate heat to the
Therefore TRISE is equal to
TRISE = 0.138 x 40 = 5.5˚C
For MSOP8-EP θJA is typically 60˚C/W.
9
www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted
6-Lead LLP Package
NS Package Number SDE06A
8-Lead eMSOP-8 Package
NS Package Number MUY08A
www.national.com
10
Notes
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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