SM320C25FJM [TI]
16-BIT, 40MHz, OTHER DSP, CQCC68, CERAMIC, LCC-68;
| 型号： | SM320C25FJM |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT, 40MHz, OTHER DSP, CQCC68, CERAMIC, LCC-68 |
| 文件： | 总38页 (文件大小：666K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢄ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄꢅ ꢆꢄ ꢇꢉ ꢇꢅ
ꢊꢋ ꢌꢋ ꢍꢎꢏ ꢀꢋ ꢌ ꢐꢎꢏ ꢑꢒ ꢓ ꢆꢔ ꢀ ꢀꢓ ꢒ
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
D
Military Temperature Range
– –55°C to 125°C
D
Single 5-V Supply
D
D
On-Chip Clock Generator
Packaging:
– 68-Pin Leaded Ceramic Chip Carrier (FJ
Suffix)
– 68-Pin Ceramic Grid Array (GB Suffix)
– 68-Pin Leadless Ceramic Chip Carrier
(FD Suffix)
D
100-ns or 80-ns Instruction Cycle Times
D
544 Words of Programmable On-Chip Data
RAM
D
D
D
D
D
4K Words of On-Chip Program ROM
128K Words of Data/Program Space
16 Input and 16 Output Channels
16-Bit Parallel Interface
68-Pin FJ and FD Packages
(Top View)
Directly Accessible External Data Memory
Space
– Global Data Memory Interface
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
D
D
D
D
D
D
D
16-Bit Instruction and Data Words
16 × 16-Bit Multiplier With a 32-Bit Product
32-Bit ALU and Accumulator
V
IACK
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SS
D7
D6
D5
59 MSC
58 CLKOUT1
57 CLKOUT2
56 XF
D4
D3
D2
Single-Cycle Multiply/Accumulate
Instructions
55
HOLDA
DX
FSX
X2 CLKIN
X1
54
D1
53
52
51
50
49
48
47
46
45
44
D0
0 to 16-Bit Scaling Shifter
SYNC
INT0
INT1
INT2
Bit Manipulation and Logical Instructions
BR
STRB
R/W
PS
IS
DS
Instruction Set Support for Floating-Point
Operations, Adaptive Filtering, and
Extended-Precision Arithmetic
V
CC
DR
FSR 25
A0 26
V
D
D
D
Block Moves for Data/Program
Management
SS
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Repeat Instructions for Efficient Use of
Program Space
Eight Auxiliary Registers and Dedicated
Arithmetic Unit for Indirect Addressing
68-Pin GB Package
(Top View)
D
Serial Port for Direct Code Interface
1
2 3 4 5 6 7 8 9 10 11
D
Synchronization Input for Synchronous
Multiprocessor Configurations
A
B
C
D
E
F
D
D
D
D
Wait States for Communication to
Slow-Off-Chip Memories/Peripherals
On-Chip Timer for Control Operations
Three External Maskable User Interrupts
Input Pin Polled by Software Branch
Instruction
G
H
J
D
1.6-µm CMOS Technology
D
Programmable Output Pin for Signaling
External Devices
K
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
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1
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ꢊ ꢋꢌ ꢋꢍꢎ ꢏ ꢀꢋ ꢌꢐ ꢎ ꢏ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
description
This data sheet provides design documentation for the SMJ320C25 and the SMJ320C25-50 digital signal
processor (DSP) devices in the SMJ320 family of VLSI digital signal processors and peripherals. The SMJ320
family supports a wide range of digital signal processing applications such as tactical communications,
guidance, military modems, speech processing, spectrum analysis, audio processing, digital filtering,
high-speed control, graphics, and other computation-intensive applications.
Differences between the SMJ320C25 and the SMJ320C25-50 are specifically identified, as in the following
paragraph and in the parameter tables on pages 18 through 24 of this data sheet. When not specifically
differentiated, the term SMJ320C25 is used to describe both devices.
The SMJ320C25 has a 100-ns instruction cycle time. The SMJ320C25-50 has an 80-ns instruction cycle time.
With these fast instruction cycle times and their innovative memory configurations, these devices perform
operations necessary for many real-time digital signal processing algorithms. Since most instructions require
only one cycle, the SMJ320C25 is capable of executing 12.5 million instructions per second. On-chip data RAM
of 544 16-bit words, on-chip program ROM of 4K words, direct addressing of up to 64K words of external data
memory space and 64K words of external program memory space, and multiprocessor interface features for
sharing global memory minimize unnecessary data transfers to take full advantage of the capabilities of the
instruction set.
Table 1. PGA/CLCC/LCCC Pin Assignments
FUNCTION
PIN
FUNCTION
A12
PIN
FUNCTION
D2
PIN
E1/16
D2/15
D1/14
C2/13
C1/12
B2/11
A2/9
FUNCTION
D14
PIN
FUNCTION
INT2
PIN
FUNCTION
PIN
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
K1/26
K2/28
L3/29
K3/30
L4/31
K4/32
L5/33
K5/34
K6/36
L7/37
K7/38
L8/39
K8/40
L9/41
A5/3
H1/22
J11/46
A6/1
V
V
H2/23
L6/35
CC
A13
D3
D15
B6/2
IS
CC
A14
K9/42
L10/43
B7/68
G11/50
C11/58
D10/57
B9/64
A9/63
F1/18
E2/17
D4
DR
J1/24
MP/MC
MSC
V
V
V
B1/10
K11/44
L2/27
SS
SS
SS
A15
D5
DS
K10/45
E11/54
J2/25
C10/59
J10/47
B8/66
A8/65
H11/48
H10/49
F2/19
BI0
D6
DX
PS
BR
D7
FSR
READY
RS
XF
X1
D11/56
G10/51
F11/52
CLKOUT1
CLKOUT2
CLKR
CLKX
D0
D8
FSX
F10/53
A7/67
E10/55
B11/60
G1/20
G2/21
D9
B3/8
HOLD
HOLDA
IACK
INT0
INT1
R/W
X2/CLKIN
D10
D11
D12
D13
A3/7
STRB
SYNC
B4/6
A4/5
V
V
A10/61
B10/62
CC
D1
85/4
CC
SMJ320 is a trademark of Texas Instruments Incorporated.
2
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ꢊꢋ ꢌꢋ ꢍꢎꢏ ꢀꢋ ꢌ ꢐꢎꢏ ꢑꢒ ꢓ ꢆꢔ ꢀ ꢀꢓ ꢒ
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
Terminal Functions
†
I/O/Z
DEFINITION
SIGNALS
V
V
I
I
5-V supply pins
Ground pins
CC
SS
X1
0
I
Output from internal oscillator for crystal
X2/CLKIN
CLKOUT1
CLKOUT2
D15–D0
A15–A0
PS,DS,IS
R/W
Input to internal oscillator from crystal or external clock
Master clock output (crystal or CLKIN frequency/4)
A second clock output signal
0
0
I/O/Z
16-bit data bus D15 (MSB) through D0 (LSB). Multiplexed between program, data, and I/0 spaces.
O/Z
16-bit address bus A15 (MSB) through A0 (LSB)
Program, data, and I/O space select signals
Read / write signal
O/Z
O/Z
STRB
O/Z
Strobe signal
RS
I
I
Reset input
INT2–INT0
MP/MC
MSC
External user interrupt inputs
Microprocessor/microcomputer mode select pin
Microstate complete signal
I
0
0
IACK
Interrupt acknowledge signal
Data ready input. Asserted by external logic when using slower devices to indicate that the current bus
transaction is complete.
READY
I
Bus request signal. Asserted when the SMJ320C25 requires access to an external global data memory
space.
BR
0
0
1
XF
External flag output (latched software-programmable signal)
Hold input. When asserted, SMJ320C25 goes into an idle mode and places the data, address, and
control lines in the high-impedance state.
HOLD
HOLDA
SYNC
BIO
0
Hold acknowledge signal
I
Synchronization input
I
Branch control input. Polled by BIOZ instruction
Serial data receive input
DR
I
CLKR
FSR
I
Clock for receive input for serial port
Frame synchronization pulse for receive input
Serial data transmit output
I
O/Z
I
DX
CLKX
FSX
Clock for transmit output for serial port
Frame synchronization pulse for transmit. Configurable as either an input or an output.
I/O/Z
†
I/O/Z denotes input/output/high-impedance state.
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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ꢊ ꢋꢌ ꢋꢍꢎ ꢏ ꢀꢋ ꢌꢐ ꢎ ꢏ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
block diagram
SYNC
IS
DS
Program Bus
16
PS
16
16
16
PFC(16)
QIR(16)
IR(16)
R/W
STRB
READY
BR
XF
HOLD
16
STO(16)
ST1(16)
RPTC(8)
IFR(6)
MUX
16
16
16
HOLDA
MSC
MCS(16)
PC(16)
DR
BIO
RS
IACK
CLKR
FSR
DX
CLKX
FSX
16
16
16
Address
Stack
16
16
16
MP/MC
(8 x 16)
3
RSR(16)
XSR(16)
DRR(16)
DXR(16)
TIM(16)
PRD(16)
IMR(6)
Program
ROM/
EPROM
INT(2-0)
16
16
16
(4096 × 16)
Instruction
16
A15-A0
D15-D0
16
16
16
6
16
16
8
GREG(8)
16
16
16
Program Bus
Data Bus
16
16
16
16
16
16
16
9
3
AR0(16)
AR1(16)
AR2(16)
AR3(16)
AR4(16)
AR5(16)
AR6(16)
AR7(16)
TR(16)
7 LSB
From IR
MUX
3
ARP(3)
DP(9)
16
Multiplier
Shifter(0-16)
32
9
3
PR(32)
32
16
ARB(3)
Shifter(-6, 0, 1, 4)
32
16
16
16
MUX
3
ARAU(16)
MUX
32
16
MUX
16
MUX
16
32
ALU(32)
32
Block B2
DATA/PROG
(32 × 16)
RAM (256 × 16)
C
Block B0
ACCH(16)
32
ACCL(16)
Data RAM
Block B1
(256 × 16)
16
MUX
16
†
Shifters (0-7)
16
16
16
Data Bus
LEGEND:
ACCH
ACCL
ALU
ARAU
ARB
ARP
DP
=
Accumulator high
Accumulator low
Arithmetic logic unit
Auxiliary register arithmetic unit
Auxiliary register pointer buffer
Auxiliary register pointer
Data memory page pointer
Serial port data receive register
Serial port data transmit register
IFR
IMR
IR
MCS
QIR
PR
PRD
TIM
TR
=
=
=
=
=
=
=
=
=
Interrupt flag register
Interrupt mask register
Instruction register
Microcall stack
Queue instruction register
Product register
Period register for timer
Timer
Temporary register
PC
PFC
RPTC
GREG
RSR
=
=
=
=
=
=
=
=
=
Program counter
Prefetch counter
Repeat instruction counter
Global memory allocation register
Serial port receive shift register
Serial port transmit shift register
Auxiliary registers
=
=
=
=
=
=
=
=
XSR
AR0-AR7
ST0, ST1
C
DRR
DXR
Status registers
Carry bit
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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ꢊꢋ ꢌꢋ ꢍꢎꢏ ꢀꢋ ꢌ ꢐꢎꢏ ꢑꢒ ꢓ ꢆꢔ ꢀ ꢀꢓ ꢒ
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
architecture
The SMJ320C25 increases performance of DSP algorithms through innovative additions to the SMJ320
architecture. Increased throughput on the SMJ320C25 for many DSP applications is accomplished by means
of single-cycle multiply/accumulate instructions with a data move option, eight auxiliary registers with a
dedicated arithmetic unit, and faster I/O necessary for data-intensive signal processing.
The architectural design of the SMJ320C25 emphasizes overall speed, communication, and flexibility in
processor configuration. Control signals and instructions provide floating-point support, block-memory
transfers, communication to slower off-chip devices, and multiprocessing implementations.
Two large on-chip RAM blocks, configurable either as separate program and data spaces or as two contiguous
data blocks, provide increased flexibility in system design. Programs of up to 4K words can be masked into the
internal program ROM. The remainder of the 64K-word program memory space is located externally. Large
programs can execute at full speed from this memory space. Programs can also be downloaded from slow
external memory to high-speed on-chip RAM. A total of 64K data memory address space is included to facilitate
implementation of DSP algorithms. The VLSI implementation of the SMJ320C25 incorporates all of these
features as well as many others, such as a hardware timer, serial port, and block data transfer capabilities.
32-bit ALU/accumulator
The SMJ320C25 32-bit arithmetic logic unit (ALU) and accumulator perform a wide range of arithmetic and
logical instructions, the majority of which execute in a single clock cycle. The ALU executes a variety of branch
instructions dependent on the status of the ALU or a single bit in a word. These instruction provide the following
capabilities:
D
D
D
Branch to an address specified by the accumulator
Normalize fixed-point numbers contained in the accumulator
Test a specified bit of a word in data memory.
One input to the ALU is always provided from the accumulator, and the other input can be provided from the
product register (PA) of the multiplier or the input scaling shifter which has fetched data from the RAM on the
data bus. After the ALU has performed the arithmetic or logical operations, the result is stored in the
accumulator.
The 32-bit accumulator is split into two 16-bit segments for storage in data memory. Additional shifters at the
output of the accumulator perform shifts while the data is being transferred to the data bus for storage. The
contents of the accumulator remain unchanged.
scaling shifter
The SMJ320C25 scaling shifter has a 16-bit input connected to the data bus and a 32-bit output connected to
the ALU. The scaling shifter produces a left shift of 0 to 16 bits on the input data, as programmed in the
instruction. The LSBs of the output are filled with zeroes, and the MSBs can be either filled with zeroes or
sign-extended, depending upon the status programmed into the SXM (sign-extension mode) bit of status
register ST1.
16 X 16-bit parallel multiplier
The SMJ320C25 has a 16 x 16-bit hardware multiplier, which is capable of computing a signed or unsigned
32-bit product in a single machine cycle. The multiplier has the following two associated registers:
D
D
A 16-bit temporary register (TR) that holds one of the operands for the multiplier, and
A 32-bit product register (PR) that holds the product.
Incorporated into the SMJ320C25 instruction set are single-cycle multiply/accumulate instruction that allow
both operands to be processed simultaneously. The data for these operations can reside anywhere in internal
or external memory and can be transferred to the multiplier each cycle via the program and data buses.
5
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ꢊ ꢋꢌ ꢋꢍꢎ ꢏ ꢀꢋ ꢌꢐ ꢎ ꢏ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
16 X 16-bit parallel multiplier (continued)
Four product shift modes are available at the product register (PR) output that are useful when performing
multiply/accumulate operations, fractional arithmetic, or justifying fractional products.
timer
The SMJ320C25 provides a memory-mapped 16-bit timer for control operations. The on-chip timer (TIM)
register is a down counter that is continuously clocked by CLKOUT1. A timer interrupt (TINT) is generated every
time the timer decrements to zero. The timer is reloaded with the value contained in the period (PRD) register
within the next cycle after it reaches zero so that interrupts can be programmed to occur at regular intervals of
PRD + 1 cycles of CLKOUT1.
memory control
The SMJ320C25 provides a total of 544 16-bit words of on-chip data RAM, divided into three separate blocks
(B0, B1, and B2). Of the 544 words, 288 words (blocks B1 and B2) are always data memory, and 256 words
(block B0) are programmable as either data or program memory. A data memory size of 544 words allows the
SMJ320C25 to handle a data array of 512 words (256 words if on-chip RAM is used for program memory), while
still leaving 32 locations for intermediate storage. When using block B0 as program memory, instructions can
be downloaded from external program memory into on-chip RAM and then executed.
When using on-chip program RAM, ROM, or high-speed external program memory, the SMJ320C25 runs at
full speed without wait states. However, the READY line can be used to interface the SMJ320C25 to slower,
less-expensive external memory. Downloading programs from slow off-chip memory to on-chip program RAM
speeds processing while cutting system costs.
The SMJ320C25 provides three separate address states for program memory, data memory, and I/O. The
on-chip memory is mapped into either the 64K-word data memory or program memory space, depending upon
the memory configuration. The CNF0 (configure block B0 as data memory) and CNFP (configure block B0 as
program memory) instruction allow dynamic configuration of the memory maps through software. Regardless
of the configuration, the user can still execute from external program memory.
The SMJ320C25 has six registers which are mapped into the data memory space: a serial port data receive
register, serial port data transmit register, timer register, period register, interrupt mask register, and global
memory allocation register.
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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ꢊꢋ ꢌꢋ ꢍꢎꢏ ꢀꢋ ꢌ ꢐꢎꢏ ꢑꢒ ꢓ ꢆꢔ ꢀ ꢀꢓ ꢒ
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
memory control (continued)
Program
Program
Data
0(0000h)
Interrupts
and Reserved
(External)
31(001Fh)
0(0000h)
0(0000h)
Interrupts
and Reserved
(On-Chip
On-Chip
Memory-Mapped
Registers
ROM/EPROM)
5(0005h)
6(0006h)
31(001Fh)
32(0020h)
32(0020h)
Page 0
Reserved
On-Chip
ROM/EPROM
95(005Fh)
96(0060h)
On-Chip
4015(0FAFh)
4016(0FB0h)
Block B2
127(007Fh)
Reserved
128(0080h)
4095(0FFFh)
4096(1000h)
Pages 1-3
Reserved
511(01FFh)
512(0200h)
External
On-Chip
Block B0
Pages 4-5
Pages 6 -7
767(02FFh)
768(0300h)
On-Chip
Block B1
External
1023(03FFh)
1024(0400h)
External
Pages 8 -511
65,535(0FFFFh)
65,535(0FFFFh)
65,535(FFFFh)
If MP/MC = 0
(Microcomputer Mode)
If MP/MC = 1
(Microprocessor Mode)
(a) Memory Maps After a CNFD Instruction
Program
Program
Data
0(0000h)
0(0000h)
0(0000h)
Interrupts
and Reserved
(On-Chip
Interrupts
and Reserved
(External)
On-Chip
Memory-Mapped
Registers
ROM/EPROM)
31(001Fh)
32(0020h)
5(0005h)
6(0006h)
31(001Fh)
32(0020h)
On-Chip
ROM/EPROM
Page 0
Reserved
95(005Fh)
96(0060h)
4015(0FAFh)
4016(0FB0h)
On-Chip
Block B2
Reserved
4095(0FFFh)
4096(1000h)
127(007Fh)
128(0080h)
Reserved
Pages 1-3
Pages 4-5
511(01FFh)
512(0200h)
External
Does Not
Exist
767(02FFh)
768(0300h)
External
On-Chip
Block B1
Pages 6 -7
1023(03FFh)
1024(0400h)
65,279(0FEFFh)
65,280(0FF00h)
On-Chip
65,279(0FEFFh)
65,280(0FF00h)
External
Pages 8 -511
On-Chip
Block B0
Block B0
65,535(0FFFFh)
65,535(0FFFFh)
65,535(0FFFFh)
If MP/MC = 1
If MP/MC = 0
(Microprocessor Mode)
(Microcomputer Mode)
(b) Memory Maps After a CNFP Instruction
Figure 1. Memory Maps
7
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SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
interrupts and subroutines
The SMJ320C25 has three external maskable user interrupts INT2–INT0, available for external devices that
interrupt the processor. Internal interrupts are generated by the serial port (RINT and XINT), by the timer (TINT),
and by the software interrupt (TRAP) instruction. Interrupts are prioritized with reset (RS) having the highest
priority and the serial port transmit interrupt (XINT) having the lowest priority. All interrupt locations are on
two-word boundaries so that branch instruction can be accommodated in those locations if desired.
A built-in mechanism protects multicycle instructions from interrupts. If an interrupt occurs during a multicycle
instruction, the interrupt is not processed until the instruction is completed. This mechanism applies both to
instructions that are repeated or become multicycle due to the READY signal.
external interface
The SMJ320C25 supports a wide range of system interfacing requirements. Program, data, and I/O address
spaces provide interface to memory and I/O. thus maximizing system throughout. I/O design is simplified by
having I/O treated the same way as memory. I/O devices are mapped into the I/O address space using the
processor’s external address and data buses in the same manner as memory-mapped devices. Interface to
memory and I/O devices of varying speeds is accomplished by using the READY line. When transitions are
made with slower devices, the SMJ320C25 processor waits until the other device completes its function and
signals the processor via the READY line. Then, the SMJ320C25 continues execution.
A full-duplex serial port provides communication with serial devices, such as codecs, serial A/D converters, and
other serial systems. The interface signals are compatible with codecs and many other serial devices with a
minimum of external hardware. The serial port can also be used for intercommunication between processors
in multiprocessing applications.
The serial port has two memory-mapped registers: the data transmit register (DXR) and the data receive register
(DRR). Both registers operate in either the byte mode or 16-bit word mode, any can be accessed in the same
manner as any other data memory location. Each register has an external clock, a framing synchronization
pulse, and associated shift registers. One method of multiprocessing can be implemented by programming one
device to transmit while the others are in the receive mode.
multiprocessing
The flexibility of the SMJ320C25 allows configurations to satisfy a wide range of system requirements. The
SMJ320C25 can be used as follows:
D
D
D
D
A standalone processor
A multiprocessor with devices in parallel
A slave/host multiprocessor with global memory space
A peripheral processor interfaced via processor-controlled signals to another device.
For multiprocessing applications, the SMJ320C25 has the capability of allocating global data memory space
and communicating with that space via the BR (bus request) and READY control signals. Global memory is data
memory shared by more than one processor. Global data memory access must be arbitrated. The 8-bit
memory-mapped GREG (global memory allocation register) specifies part of the SMJ320C25s data memory
as global external memory. The contents of the register determine the size of the global memory space. If the
current instruction addresses an operand within that space, BR is asserted to request control of the bus. The
length of the memory cycle is controlled by the READY line.
The SMJ320C25 supports DMA (direct memory access) to its external program/data memory using the HOLD
and HOLDA signals. Another processor can take complete control of the SMJ320C25s external memory by
asserting HOLD low. This causes the SMJ320C25 to place its address, data, and control lines in a
high-impedance state, and assert HOLDA. Program execution from on-chip memory can proceed concurrently
while the device is in the hold mode.
8
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SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
instruction set
The SMJ320C25 microprocessor implements a comprehensive instruction set that supports both
numeric-intensive signal processing operations as well as general-purpose applications, such as
multiprocessing and high-speed control.
For maximum throughput, the next instruction is prefetched while the current one is being executed. Since the
same data lines are used to communicate to external data/program or I/O space, the number of cycles may vary
depending upon whether the next data operand fetch is from internal or external program memory. Highest
throughput is achieved by maintaining data memory on-chip and using either internal or fast external program
memory.
addressing modes
The SMJ320C25 instruction set provides three memory addressing modes: direct, indirect, and immediate
addressing.
Both direct and indirect addressing can be used to access data memory. In direct addressing, seven bits of the
instruction word are concatenated with the nine bits of the data memory page pointer to form the 16-bit data
memory address. Indirect addressing accesses data memory through the eight auxiliary registers. In immediate
addressing, the data is based on a portion of the instruction word(s).
In direct memory addressing, the instruction word contains the lower seven bits of the data memory address.
This field is concatenated with the nine bits of the data memory page pointer to form the full 16-bit address. Thus,
memory is paged in the direct addressing mode with a total of 512 pages, each page containing 128 words.
Eight auxiliary register (AR0–AR7) provide flexible and powerful indirect addressing. To select a specific
auxiliary register, the Auxiliary Register Pointer (ARP) is loaded with a value from 0 through 7 for AR0–AR7,
respectively.
There are seven types of indirect addressing: auto-increment or auto-decrement, post-indexing by either adding
or subtracting the contents of AR0, or single indirect addressing with no increment or decrement and bit-reversal
addressing (used in FFTs) with increment or decrement. All operations are performed on the current auxiliary
register in the same cycle as the original instruction, followed by anew ARP value being loaded.
repeat feature
A repeat feature, used with instructions such as multiply/accumulates, block moves, I/O transfers, and table
read/writes, allows a single instruction to be performed up to 256 times. The repeat counter (RPTC) is loaded
with either a data memory value (RPT instruction) or an immediate value (RPTK instruction) .The value of this
operand is one less than the number of times that the next instruction is executed. Those instructions that are
normally multicycle are pipelined when using the repeat feature, and effectively become single-cycle
instructions.
instruction set summary
Table 1 lists the symbols and abbreviations used in Table 1, the instruction set summary, Table 2 consists
primarily of single-cycle,single-word instructions. Infrequently used branch, I/O, and CALL instructions are
multicycle. The instruction set summary is arranged according to function and alphabetized within each
functional grouping.
9
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SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
instruction set summary (continued)
Table 1. Instruction Symbols
SYMBOL
MEANING
B
CM
D
4-bit field specifying a bit code
2-bit field specifying compare mode
Data memory address field
Format status bit
F0
M
Addressing mode bit
K
Immediate operand field
PA
PM
R
Port address (PA0–PA15 are predefined assembler symbols equal to 0 through 15, respectively)
2-bit field specifying P register output shift code
3-bit operand field specifying auxiliary register
4-bit left-shift code
S
X
3-bit accumulator left-shift field
10
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SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
Table 2. SMJ320C25 Instruction Set Summary
ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS
INSTRUCTION BIT CODE
NO.
WORDS
MNEMONIC
DESCRIPTION
15 14 13 12 11 10
9
8
7
6
5
4
3
1
2
1
0
ABS
ADD
Absolute value of accumulator
Add to accumulator with shift
Add to accumulator with carry
Add to high accumulator
1
1
1
1
1
1
0
0
0
1
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
0
1
1
M
M
M
D
D
S
‡
ADDC
0
1
1
0
0
1
1
0
0
1
0
0
ADDH
D
‡
ADDK
ADDS
Add to accumulator short immediate
K
Add to low accumulator with sign
extension suppressed
1
1
0
0
1
1
0
0
0
0
1
1
0
0
0
1
1
0
M
M
D
D
Add to accumulator with shift specified by
T register
ADDT
†
S
ADLK
Add to accumulator long immediate with shift
AND with accumulator
2
1
2
1
1
1
1
0
1
1
0
1
1
1
1
1
0
1
0
0
0
0
1
0
1
0
1
0
0
0
0
M
0
0
0
0
0
D
0
0
0
1
0
AND
1
1
1
1
1
1
0
0
†
†
ANDK
CMPL
LAC
AND immediate with accumulator with shift
Complement accumulator
0
0
0
1
0
0
1
1
0
1
0
1
S
S
0
Load accumulator with shift
M
D
LACK
Load accumulator immediate short
1
0
0
0
1
1
0
0
K
Load accumulator with shift specified by
T register
†
LACT
1
0
1
0
0
M
D
†
LALK
Load accumulator long immediate with shift
Negate accumulator
2
1
1
1
2
1
1
1
1
1
1
1
0
1
1
1
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
S
S
†
NEG
1
1
1
1
1
1
1
1
0
0
0
1
†
NORM
Normalize contents of accumulator
OR with accumulator
1
D
OR
M
0
D
0
†
ORK
OR immediate with accumulator with shift
Rotate accumulator left
0
0
0
0
1
1
0
1
1
1
1
1
0
0
0
1
0
1
‡
ROL
1
1
1
0
1
1
1
1
0
0
0
0
0
‡
ROR
Rotate accumulator right
0
SACH
SACL
Store high accumulator with shift
Store low-order accumulator with shift
M
M
X
X
D
D
Subtract from accumulator long immediate
with shift
SBLK†
2
1
1
0
1
0
0
0
0
0
0
1
1
S
S
†
SFL
Shift accumulator left
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
†
SFR
Shift accumulator right
0
SUB
Subtract from accumulator with shift
Subtract from accumulator with borrow
Conditional subtract
M
M
M
M
D
D
D
D
‡
SUBB
1
0
0
1
1
1
1
1
1
1
0
0
1
1
0
1
SUBC
SUBH
Subtract from high accumulator
Subtract from accumulator short immediate
‡
SUBK
K
Subtract from low accumulator with sign
extension suppressed
SUBS
1
0
1
0
0
0
1
0
1
M
D
†
‡
These instructions are not included in the TMS320C1x instruction set.
These instructions are not included in the TMS32020 instruction set.
11
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SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
Table 2. SMJ320C25 Instruction Set Summary (continued)
ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS
INSTRUCTION BIT CODE
NO.
WORDS
MNEMONIC
DESCRIPTION
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Subtract from accumulator with shift specified by
T register
†
SUBT
1
1
2
0
0
1
1
1
1
0
0
0
0
0
1
0
1
1
1
1
0
M
D
XOR
Exclusive-OR with accumulator
0
0
M
0
D
0
Exclusive-OR immediate with accumulator with
shift
†
XORK
0
0
0
0
0
0
1
0
1
0
0
0
S
ZAC
Zero accumulator
1
1
1
0
1
1
0
0
0
0
1
0
0
0
1
0
0
0
0
0
ZALH
Zero low accumulator and load high accumulator
M
D
Zero low accumulator and load high accumulator
with rounding
‡
ZALR
1
1
0
0
1
1
1
0
1
0
1
0
0
0
1
0
1
1
M
M
D
D
Zero accumulator and load low accumulator with
sign extension suppressed
ZALS
AUXILIARY REGISTERS AND DATA PAGE POINTER INSTRUCTIONS
INSTRUCTION BIT CODE
NO.
WORDS
MNEMONIC
DESCRIPTION
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
‡
ADRK
Add to auxiliary register short immediate
1
1
0
1
1
1
1
1
1
0
K
Compare auxiliary register with auxiliary
register AR0
†
CMPR
1
1
0
0
1
1
1
0
0
1
0
1
0
0
CM
LAR
Load auxiliary register
1
1
1
1
1
2
1
1
1
0
1
0
0
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
0
1
1
0
1
1
1
1
0
0
0
0
1
0
0
0
1
M
R
R
0
D
LARK
LARP
LDP
Load auxiliary register short immediate
Load auxiliary register pointer
K
1
0
0
1
0
1
0
0
0
0
0
1
R
0
Load data memory page pointer
Load data memory page pointer immediate
Load auxiliary register long immediate
Modify auxiliary register
1
M
D
LDPK
0
DP
0
†
LRLK
MAR
SAR
0
0
0
0
R
0
1
1
1
1
M
M
D
D
Store auxiliary register
R
1
‡
SBRK
Subtract from auxiliary register short immediate
K
†
‡
These instructions are not included in the TMS320C1x instruction set.
These instructions are not included in the TMS32020 instruction set.
12
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SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
Table 2. SMJ320C25 Instruction Set Summary (continued)
T REGISTER, P REGISTER, AND MULTIPLY INSTRUCTIONS
INSTRUCTION BIT CODE
NO.
WORDS
MNEMONIC
DESCRIPTION
15 14 13 12 11 10
9
1
1
0
0
8
0
1
0
1
7
6
5
4
3
2
1
0
APAC
Add P register to accumulator
Load high P register
1
1
1
1
1
0
0
0
1
1
0
0
0
0
1
1
0
1
1
1
1
0
1
1
1
0
1
1
0
0
0
1
0
1
0
1
†
LPH
LT
M
M
M
D
Load T register
D
D
LTA
Load T register and accumulate previous product
Load T register, accumulate previous product,
and move data
LTD
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
M
M
D
D
Load T register and store P register in
accumulator
†
LTP
†
LTS
Load T register and subtract previous product
Multiply and accumulate
1
2
2
0
0
0
1
1
1
0
0
0
1
1
1
1
1
1
0
1
1
1
0
0
1
1
0
M
M
M
D
D
D
†
MAC
†
MACD
Multiply and accumulate with data move
Multiply (with T register, store product in
P register)
MPY
1
0
0
1
1
1
1
1
0
0
0
1
0
0
M
M
D
D
‡
MPYA
Multiply and accumulate previous product
Multiply immediate
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
1
0
0
1
0
0
0
0
0
1
1
1
1
1
1
0
1
1
1
1
0
0
0
1
1
0
1
0
MPYK
K
MPYS‡
MPYU‡
Multiply and subtract previous product
Multiply unsigned
1
0
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
0
1
1
1
0
0
1
0
0
1
0
M
M
0
D
D
PAC
Load accumulator with P register
Subtract P register from accumulator
Store high P register
0
0
0
0
1
1
0
1
1
0
1
0
0
SPAC
0
0
‡
SPH
M
M
0
D
‡
SPL
Store low P register
D
†
SPM
Set P register output shift mode
Square and accumulate
0
0
0
1
0
PM
†
†
SQRA
SQRS
M
M
D
D
Square and subtract previous product
†
‡
These instructions are not included in the TMS320C1x instruction set.
These instructions are not included in the TMS32020 instruction set.
13
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SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
Table 2. SMJ320C25 Instruction Set Summary (continued)
BRANCH/CALL INSTRUCTIONS
INSTRUCTION BIT CODE
NO.
WORDS
MNEMONIC
DESCRIPTION
15 14 13 12 11 10
9
1
1
1
0
0
1
0
0
1
1
1
1
1
0
0
1
1
1
1
8
1
0
1
1
0
0
0
1
0
0
1
1
1
1
0
0
0
0
0
7
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
6
5
4
3
2
1
0
B
Branch unconditionally
2
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
1
1
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
1
0
0
1
0
0
1
0
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
0
0
1
1
1
0
1
1
1
1
D
†
BACC
BANZ
Branch to address specified by accumulator
Branch on auxiliary register not zero
Branch if TC bit ≠ 0
0
1
0
0
1
0
1
D
†
BBNZ
D
D
D
D
D
D
D
D
D
D
†
BBZ
Branch if TC bit = 0
‡
BC
Branch on carry
BGEZ
BGZ
Branch if accumulator ≥ 0
Branch if accumulator > 0
Branch on I/O status = 0
Branch if accumulator ≤ 0
Branch if accumulator < 0
Branch on no carry
BIOZ
BLEZ
BLZ
‡
BNC
†
BNV
BNZ
BV
Branch if no overflow
Branch if accumulator ≠ 0
Branch on overflow
D
D
D
BZ
Branch if accumulator = 0
Call subroutine indirect
Call subroutine
CALA
CALL
RET
0
0
1
1
0
0
0
1
1
0
1
0
0
D
Return from subroutine
0
I/O AND DATA MEMORY OPERATIONS
INSTRUCTION BIT CODE
NO.
WORDS
MNEMONIC
DESCRIPTION
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
†
BLKD
Block move from data memory to data memory
2
2
1
1
1
1
1
1
0
1
1
1
1
1
0
1
M
D
Block move from program memory to data
memory
†
BLKP
0
0
M
D
D
DMOV Data move in data memory
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
1
0
0
M
0
†
FORT
IN
Format serial port registers
Input data from port
0
0
0
1
1
1
FO
M
M
0
PA
PA
D
D
OUT
RFSM
RTXM
Output data to port
‡
†
Reset serial port frame synchronization mode
Reset serial port transmit mode
Reset external flag
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
0
1
1
0
0
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
0
0
1
†
RXF
0
‡
†
SFSM
Set serial port frame synchronization mode
Set serial port transmit mode
Set external flag
0
STXM
0
†
SXF
0
TBLR
TBLW
Table read
M
M
D
Table write
D
†
‡
These instructions are not included in the TMS320C1x instruction set.
These instructions are not included in the TMS32020 instruction set.
14
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ꢊꢋ ꢌꢋ ꢍꢎꢏ ꢀꢋ ꢌ ꢐꢎꢏ ꢑꢒ ꢓ ꢆꢔ ꢀ ꢀꢓ ꢒ
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
Table 2. SMJ320C25 Instruction Set Summary (concluded)
CONTROL INSTRUCTIONS
INSTRUCTION BIT CODE
NO.
WORDS
MNEMONIC
DESCRIPTION
15 14 13 12 11 10
9
8
7
M
M
0
6
5
4
3
D
D
0
2
1
0
†
BIT
Test bit
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
0
1
0
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
0
1
1
0
0
0
0
B
†
BITT
Test bit specified by T register
Configure block as data memory
Configure block as program memory
Disable interrupt
0
1
1
1
1
1
0
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
0
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
†
CNFD
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
0
0
0
0
1
0
1
1
0
1
†
CNFP
DINT
EINT
0
0
0
0
Enable interrupt
0
0
†
IDLE
LST
Idle until interrupt
0
1
Load status register STO
Load status register ST1
No operation
M
M
0
D
†
LST1
NOP
POP
D
0
0
0
0
0
0
1
0
1
0
0
0
1
Pop top of stack to low accumulator
Pop top of stack to data memory
Push data memory value onto stack
Push low accumulator onto stack
Reset carry bit
0
1
†
POPD
M
M
0
D
†
PSHD
D
1
0
1
0
PUSH
0
0
0
0
0
1
1
0
1
1
1
0
1
0
0
0
0
0
0
1
0
0
0
0
‡
RC
0
0
0
‡
RHM
ROVM
Reset hold mode
Reset overflow mode
Repeat instruction as specified by data
memory value
†
RPT
1
1
0
1
1
1
0
0
0
0
1
1
0
0
1
1
1
1
M
D
Repeat instruction as specified by immediate
value
†
RPTK
K
†
RSXM
Reset sign-extension mode
Reset test/control flag
Set carry bit
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
1
0
0
0
0
1
0
1
0
0
0
0
1
1
0
0
1
0
0
1
1
1
‡
RTC
‡
SC
0
‡
SHM
Set hold mode
0
SOVM
SST
Set overflow mode
0
Store status register ST0
Store status register ST1
Set sign-extension mode
Set test/control flag
Software interrupt
M
M
0
D
†
SST1
D
0
†
SSXM
0
0
0
0
1
0
0
1
1
1
0
1
1
1
1
1
1
0
‡
STC
0
0
1
†
TRAP
0
†
‡
These instructions are not included in the TMS320C1x instruction set.
These instructions are not included in the TMS32020 instruction set.
15
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ꢊ ꢋꢌ ꢋꢍꢎ ꢏ ꢀꢋ ꢌꢐ ꢎ ꢏ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
development systems and software support
Texas Instruments offers concentrated development support and complete documentation for designing an
SMJ320C25-based microprocessor system. When developing an application, tools are provided to evaluate
the performance of the processor, to develop the algorithm implementation, and to fully integrate the design’s
software and hardware modules. When questions arise, additional support can be obtained by calling the
nearest Texas Instruments Regional Technology Center (RTC).
Sophisticated development operations are performed with the SMJ320C25 Macro Assembler/linker, Simulator,
and Emulator (XDS). The macro assembler and linker are used to translate program modules into object code
and link them together. This puts the program modules into a form which can be loaded into the SMJ320C25
Simulator or Emulator. The simulator provides a quick means for initially debugging SMJ320C25 software while
the emulator provides the real-time in-circuit emulation necessary to perform system level debug efficiently.
Table 3 gives a complete list of SMJ320C25 software and hardware development tools.
Table 3. SMJ/SMJ320C25 Software and Hardware Support
MACRO ASSEMBLERS/LINKERS
Host Computer
DECVAX
Operating System
VMS
Part Number
TMDS324210-08
TMDS3242810-02
TI/IBM PC
MS/PC-DOS
SIMULATORS
Operating System
VMS
Host Computer
DECVAX
Part Number
TMDS3242211-08
TMDS3242811-02
TI/IBM PC
MS/PC-DOS
EMULATORS
Power Supply
Included
Model
Part Number
XDS/22
TMDS3262221
16
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ꢊꢋ ꢌꢋ ꢍꢎꢏ ꢀꢋ ꢌ ꢐꢎꢏ ꢑꢒ ꢓ ꢆꢔ ꢀ ꢀꢓ ꢒ
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
CC
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 W
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
†
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to V
.
SS
‡
recommended operating conditions
SMJ320C25-50
SMJ320C25
MIN NOM
UNIT
MIN
NOM
MAX
MAX
V
V
Supply voltage
Supply voltage
4.75
5
0
5.25
4.5
5
0
5.5
V
V
CC
SS
READY
D15–D0
FSX
3.00
2.20
2.20
3.50
4.00
3.00
2.35
2.20
2.30
3.50
3.50
3.00
V
High-level input voltage
V
IH
IL
CLKR, CLKX
CLKIN
All others
D15–D0, FSX, CLKIN, CLKR, CLKX
0.80
0.70
0.80
300
2
0.80
0.70
0.70
300
2
HOLD
V
Low-level input voltage
V
All others
I
I
High-level output current
Low-level output current
Operating case temperature
mA
mA
°C
OH
OL
T
C
–55
125
–55
125
‡
T
C
MAX at maximum rated operating conditions at any point on case T MIN at initial (time zero) power up
C
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either V
or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for
CC
Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
17
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢄ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢄ ꢇꢉꢇ ꢅ
ꢊ ꢋꢌ ꢋꢍꢎ ꢏ ꢀꢋ ꢌꢐ ꢎ ꢏ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
electrical characteristics over specified free-air temperature range (unless otherwise noted)
SMJ320C25,
SMJ320C25-50
PARAMETER
TEST CONDITIONS
UNIT
§
MIN TYP
MAX
V
V
High-level output voltage
V
V
V
= MIN, I
= MIN, I
= MAX
= MAX
= MAX
24
3
V
V
OH
CC
CC
CC
OH
Low-level output voltage
Three-state current
0.3
0.6
20
OL
OL
I
Z
–20
–20
–10
mA
X2/CLKIN
All other pins
Normal
20
I
I
Input current
V = V
I SS
to V
CC
mA
10
185
100
I
Supply current
V
CC
= MAX, f = MAX
mA
CC
x
Idle/R5L5
C
C
Input capacitance
Output capacitance
15
15
pF
pF
i
o
§
All typical values are at V
CC
= 5 V, T = 25°C
A
CLOCK CHARACTERISTICS AND TIMING
The SMJ320C25 can use either its internal oscillator or an external frequency source for a clock.
internal clock option
The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 2). The frequency
of CLKOUT1 is one-fourth the crystal fundamental frequency. The crystal should be either fundamental or
overtone mode, and parallel resonant, with an effective series resistance of 30 Ω, a power dissipation of 1 mW,
and be specified at a load capacitance of 20 pF. Note that overtone of crystals require an additional tuned LC
circuit (see the application report, Hardware Interfacing to the TMS320C25).
SMJ320C25-50
SMJ320C25
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
50.0
MIN
TYP
MAX
†
6.7
†
f
x
Input clock frequency
T
= – 55°C MIN
= 125°C MAX
6.7
40.0
MHz
pF
A
C1, C2
T
C
10
10
†
These values are derived from characterization data and are not tested.
X1
X2/CLKIN
Crystal
C1
C2
Figure 2. Internal Clock Options
18
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢄ ꢇ ꢈ ꢀꢁ ꢂ ꢃꢄ ꢅꢆ ꢄꢇ ꢉꢇ ꢅ
ꢊꢋ ꢌꢋ ꢍꢎꢏ ꢀꢋ ꢌ ꢐꢎꢏ ꢑꢒ ꢓ ꢆꢔ ꢀ ꢀꢓ ꢒ
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
external clock option
An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left
unconnected. The external frequency injected must conform to the specifications listed in the following table.
switching characteristics over recommended operating conditions (see Note 1)
SMJ320C25-50
SMJ320C25
PARAMETER
UNIT
MIN
80
5
MAX
600
28
MIN NOM
MAX
600
30
t
t
Cycle time, CLKOUT1/CLKOUT2
100
5
ns
c(C)
Delay time, CLKIN high to CLKOUT1/CLKOUT2/STRB high/low
Delay time, CLKOUT1 high to CLKOUT2 low,
Delay time, CLKOUT2 high to CLKOUT1 high, etc.
Fall time, CLKOUT1/CLKOUT2/STRB
(1S
d(CIH–C)
t
Q – 6
Q + 3
Q – 6
Q
Q + 6
ns
d(C1–C2)
t
t
t
t
5
3
5
5
ns
ns
ns
ns
f(C)
Rise time, CLKOUT1/CLKOUT2/STRB
r(C)
Pulse duration, CLKOUT1/CLKOUT2 low
Pulse duration, CLKOUT1/CLKOUT2 high
2Q – 7 2Q + 5 2Q – 8
2Q – 5 2Q + 7 2Q – 8
2Q 2Q + 8
2Q 2Q + 8
w(CL)
w(CH)
†
.This parameter is not production tested
NOTE 1: Q = 1/4t
c(C)
timing requirements over recommended operating conditions (see Note 1 )
SMJ320C25-50
SMJ320C25
UNIT
MIN
20
8
MAX
MIN
25
10
10
5
MAX
150
15
t
t
t
t
t
Cycle time, CLKIN
150
ns
ns
ns
ns
ns
c(CI)
Pulse duration, CLKIN low, t
= 25 ns (see Note 2)
w(CIL)
w(CIH)
su(S)
h(S)
c(CI)
Pulse duration, CLKIN high, t
c(CI)
= 25 ns (see Note 2)
8
15
Setup time, SYNC before CLKIN low
Hold time, SYNC from CLKIN low
4
Q – 4
Q – 5
4
8
NOTES: 1: Q = 1/4t
c(C)
2. Rise and fall times, assuming a 40–60% duty cycle, are incorporated within this specification CLKIN rise and fall times must be less
than 5 ns
Figure 3. Test Load Circuit
19
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢄ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢄ ꢇꢉꢇ ꢅ
ꢊ ꢋꢌ ꢋꢍꢎ ꢏ ꢀꢋ ꢌꢐ ꢎ ꢏ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
2.0 V
2.4 V
V
(Min)
(Max)
V
(Min)
(Max)
IH
OH
1.88 V
0.92 V
2.2 V
0.8 V
V
IL
V
OL
0.80 V
0
0.6 V
0
(a) Input
(b) Output
Figure 4. Voltage Reference Levels
switching characteristics over recommended operating conditions (see Note 1)
SMJ320C25-50
SMJ320C25
PARAMETER
UNIT
MIN
Q – 5
MAX
MIN
Q – 6
TYP
Q
MAX
Q + 6
6
t
STRB from CLKOUT1 (if STRB is present)
Q + 3
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(C1–S)
t
CLKOUT2 to STRB (if STRB is present)
–2
–6
0
d(C2–S)
t
t
t
t
Address setup time before STRB low (see Note 3)
Address hold time after STRB high (see Note 3)
STRB low pulse duration (no wait states, see Note 4)
STRB high pulse duration (between consecutive cycles, see Note 4)
Data write setup time before STRB high (no wait states)
Data write hold time from STRB high
Q – 13
Q – 4
Q – 12
Q – 8
su(A)
h(A)
2Q – 5
2Q – 5
2Q – 17
Q – 5
2Q + 5
2Q + 5
2Q – 5
2Q – 5
2Q – 20
Q – 10
2Q
Q
2Q + 5
2Q + 5
w(SL)
w(SH)
t
su(D)W
t
h(D)W
en(D)
dis(D)
†
0
†
0
t
t
Data bus starts being driven after STRB low (write cycle)
Data bus three-state after STRB high (write cycle)
MSC valid from CLKOUT1
†
†
Q + 15
Q
0
Q + 15
t
–5
10
–10
10
d(MSC)
†
These values are derived from characterization data and not tested.
timing requirements over recommended operating conditions (see Note 1)
SMJ320C25-50
SMJ320C25
UNIT
MIN
MAX
MIN
MAX
t
t
t
t
t
t
t
t
t
Access time, read data from address time (read cycle, see Notes 3 and 5)
Setup time, data read before STRB high
3Q – 31
3Q – 35
ns
ns
ns
ns
ns
ns
ns
ns
ns
a(A)
17
0
23
0
su(D)R
h(D)R
Hold time, data read from STRB high
Delay time, READY valid after STRB low (no wait states)
Delay time, READY valid after CLKOUT2 high
Hold time, READY after STRB low (no wait states)
Hold time, READY after CLKOUT2 high
Q – 20
Q – 21
Q – 20
Q – 20
d(SL–R)
d(C2H–R)
h(SL–R)
h(C2H–R)
d(M–R)
h(M–R)
Q – 1
Q – 1
Q + 3
Q + 3
Delay time, READY valid after MSC valid
2Q – 25
2Q – 25
Hold time, READY after MSC valid
0
0
NOTES: 1: 0 = 1/4t
c(C)
3. A15–A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as ”address”
4. Delays between CLKOUT1 /CLKOUT2 edges and STRB edges track each other, resulting in tw(SL) and tw(SH) being 2Q with no
wait states.
5. Read data access time is defined as t .
= t
+ t
– t
+ t
a(A) su(A) w(SL) su(D)R r(C)
20
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢄ ꢇ ꢈ ꢀꢁ ꢂ ꢃꢄ ꢅꢆ ꢄꢇ ꢉꢇ ꢅ
ꢊꢋ ꢌꢋ ꢍꢎꢏ ꢀꢋ ꢌ ꢐꢎꢏ ꢑꢒ ꢓ ꢆꢔ ꢀ ꢀꢓ ꢒ
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
RS, INT, BIO, and XF timing
switching characteristics over recommended operating conditions (see Note 1)
SMJ320C25-50
SMJ320C25
PARAMETER
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
†
†
t
Delay time, CLKOUT1 low to reset state entered
Delay time, CLKOUT1 to IACK valid
22
22
ns
ns
ns
d(RS)
†
†
t
–5
0
7
–8
0
8
d(IACK)
t
Delay time, XF valid before falling edge of STRB
Q – 10
Q – 12
d(XF)
timing requirements over recommended operating conditions (see Note 1)
SMJ320C25-50
SMJ320C25
UNIT
MIN
25
0
MAX
MIN
32
0
MAX
t
t
t
t
Setup time, INT/BIO/RS before CLKOUT1 high
Hold time, INT/BIO/RS after CLKOUT1 high
Pulse duration, INT/BIO low
ns
ns
ns
ns
su(IN)
h(IN)
t
t
w(IN)
w(RS)
c(C)
c(C)
Pulse duration, RS low
3t
c(C)
3t
c(C)
switching characteristics over recommended operating conditions (see Note 1)
SMJ320C25-50
SMJ320C25
PARAMETER
UNIT
MIN
–1
TYP
MAX
11
MIN
TYP
MAX
t
Delay time, HOLDA low after CLKOUT1 low
Disable time, HOLDA low to address three-state
–1
10
ns
ns
d(C1L-AL)
t
0
0
dis(AL-A)
Disable time, address three-state after CLKOUT1 low (HOLD
mode, see Note 7 )
†
†
t
20
20
ns
ns
ns
dis(C1L-A)
t
Delay time, HOLD high to HOLDA high
19
25
d(HH-AH)
Enable time, address driven before CLKOUT1 low (HOLD mode,
see Note 7 )
†
8
†
8
t
en(A-C1L)
timing requirements over recommended operating conditions (see Note 1)
SMJ320C25-50
SMJ320C25
UNIT
UNIT
ns
MIN
MAX
MIN
MAX
t
Delay time, HOLD valid after CLKOUT2 high
These values are derived from characterization data and not tested.
NOTES: 1. Q = 1/4t
Q – 19
Q – 24
d(C2H-H)
†
c(C)
6. RS, INT, and BIO are asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is
met, the exact sequence shown in the timing diagram occurs. INT/BIO fall time must be less than 8 ns.
7. A15–A0, PS, DS, IS, STRB, and R/W timings are all included in timings referenced as ’”address”.
21
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢄ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢄ ꢇꢉꢇ ꢅ
ꢊ ꢋꢌ ꢋꢍꢎ ꢏ ꢀꢋ ꢌꢐ ꢎ ꢏ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
serial port timing
switching characteristics over recommended operating conditions (see Note 1)
SMJ320C25-50
PARAMETER
SMJ320C25
MIN MAX
UNIT
MIN
MAX
t
t
t
Delay time, DX valid after CLKX rising edge (see Note 8)
Delay time, DX valid after FSX falling edge (TXM = 0. see Note 8)
FSX valid after CLKX rising edge (TXM = 1 )
75
80
ns
ns
ns
d(CH-DX)
d(FL-DX)
d(CH-FS)
40
45
45
40
timing requirements over recommended operating conditions (see Note 1)
SMJ320C25-50
SMJ320C25
UNIT
MIN
MAX
MIN
MAX
5000
f
t
t
t
t
t
t
t
Serial port frequency
1.25
6250
1.25
kHz
ns
ns
ns
ns
ns
ns
ns
sx
Serial port clock (CLKX/CLKR) cycle time
160 800 000
200 800 000
c(SCK)
w(SCK1
w(SCK)
su(FS)
h(FS)
Serial port clock (CLKX/CLKR) low pulse duration (see Note 9)
Serial port clock (CLKX/CLKR) high pulse duration (see Note 9)
FSX/FSR setup time before CLKX/CLKR falling edge (TXM = 0)
FSX/FSR hold time after CLKX/CLKR falling edge (TXM = 0)
OR setup time before CLKR falling edge
64
64
5
80
80
18
20
10
20
10
5
su(DR)
h(DR)
OR hold time after CLKR falling edge
10
NOTES: 1: Q = 1/4t
c(C)
8. The last occurrence of FSX falling and CLKX rising.
9. The duty cycle of the serial port clock must be within 40–60% .Serial port clock (CLKX/CLKR) rise and fall times must be less than
25 ns.
22
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢄ ꢇ ꢈ ꢀꢁ ꢂ ꢃꢄ ꢅꢆ ꢄꢇ ꢉꢇ ꢅ
ꢊꢋ ꢌꢋ ꢍꢎꢏ ꢀꢋ ꢌ ꢐꢎꢏ ꢑꢒ ꢓ ꢆꢔ ꢀ ꢀꢓ ꢒ
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
TIMING DIAGRAMS
Timing measurements are referenced to and from a low voltage of 0.8 V and a high voltage of 2.2 V with the
exception of CLKOUT1, CLKOUT2, and STRB timing that are referenced from a falling edge low voltage of
1.1 V and a rising edge low voltage of 2.2 V.
t
c(CI)
t
f(CI)
t
r(CI)
X/2CLKIN
SYNC
t
w(CIH)
t
h(S)
su(S)
t
w(CIL)
t
t
su(S)
t
c(C)
t
w(CL)
d(CIH-C)
t
d(CIH-C)
t
CLKOUT1
STRB
t
w(CH)
t
t
f(C)
r(C)
t
d(CIH-C)
t
d(CIH-C)
t
c(C)
t
w(CL)
CLKOUT2
t
t
t
t
r(C)
d(C1-C2)
d(C1-C2)
f(C)
t
t
w(CH)
d(C1-C2)
t
d(C1-C2)
Figure 5. Clock Timing
23
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢄ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢄ ꢇꢉꢇ ꢅ
ꢊ ꢋꢌ ꢋꢍꢎ ꢏ ꢀꢋ ꢌꢐ ꢎ ꢏ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
t
d(C1-S)
CLKOUT1
t
d(C1-S)
CLKOUT2
STRB
t
t
d(C2-S)
d(C2-S)
t
w(SH)
t
t
h(A)
su(A)
t
w(SL)
Valid
A15-A0,
BR, PS, DS
or IS
t
a(A)
R/W
READY
D15-D0
t
d(SL-R)
t
su(D)R
t
t
h(D)R
h(SL-R)
Data In
Figure 6. Memory Read Timing
24
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢄ ꢇ ꢈ ꢀꢁ ꢂ ꢃꢄ ꢅꢆ ꢄꢇ ꢉꢇ ꢅ
ꢊꢋ ꢌꢋ ꢍꢎꢏ ꢀꢋ ꢌ ꢐꢎꢏ ꢑꢒ ꢓ ꢆꢔ ꢀ ꢀꢓ ꢒ
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
CLKOUT1
CLKOUT2
STRB
t
h(A)
t
su(A)
A15-A0,
BR, PS, DS
or IS
Valid
R/W
READY
D15-D0
t
su(D)W
t
h(D)W
Data Out
t
t
en(D)
dis(D)
Figure 7. Memory Write Timing
25
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢄ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢄ ꢇꢉꢇ ꢅ
ꢊ ꢋꢌ ꢋꢍꢎ ꢏ ꢀꢋ ꢌꢐ ꢎ ꢏ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
CLKOUT1
CLKOUT2
STRB
t
h(C2H-R)
A15-A0, BR,
PS, DS, R/W or
IS
Valid
t
h(C2H-R)
t
d(C2H-R)
t
d(C2H-R)
READY
t
t
d(M-R)
h(M-R)
t
t
h(M-R)
d(M-R)
D15-D0
(For Read
Operation)
Data In
D15-D0
(For Write
Operation)
Data Out
t
d(MSC)
t
d(MSC)
MSC
Figure 8. One Wait-State Memory Access Timing
26
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢄ ꢇ ꢈ ꢀꢁ ꢂ ꢃꢄ ꢅꢆ ꢄꢇ ꢉꢇ ꢅ
ꢊꢋ ꢌꢋ ꢍꢎꢏ ꢀꢋ ꢌ ꢐꢎꢏ ꢑꢒ ꢓ ꢆꢔ ꢀ ꢀꢓ ꢒ
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
CLKOUT1
t
su(IN)
t
d(RS)
t
su(IN)
t
h(IN)
RS
A15-A0
D15-D0
PS
t
w(RS)
Valid
Fetch
Location 0
Valid
Begin
Program
Execution
STRB
Control
†
Signals
IACK
Serial Port
‡
Control
†
‡
Control signals are DS, IS, R/W, and XF.
Serial port controls are DX and FSX.
Figure 9. Reset Timing
27
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢄ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢄ ꢇꢉꢇ ꢅ
ꢊ ꢋꢌ ꢋꢍꢎ ꢏ ꢀꢋ ꢌꢐ ꢎ ꢏ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
CLKOUT1
STRB
t
t
su(IN)
h(IN)
t
w(IN)
INT2-INT0
A15-A0
IACK
t
t
d(IACK)
f(IN)
FETCH N
FETCH N + 1
FETCH I
FETCH I + 1
t
d(IACK)
Figure 10. Interrupt Timing
CLKOUT1
STRB
FETCH Branch Address
PC = N + 1
FETCH Next Instruction
FETCH
BIOZ
A15-A0
PC = N
PC = N + 2
or Branch Address
t
su(IN)
t
h(IN)
BIO
Valid
Figure 11. BIO Timing
28
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢄ ꢇ ꢈ ꢀꢁ ꢂ ꢃꢄ ꢅꢆ ꢄꢇ ꢉꢇ ꢅ
ꢊꢋ ꢌꢋ ꢍꢎꢏ ꢀꢋ ꢌ ꢐꢎꢏ ꢑꢒ ꢓ ꢆꢔ ꢀ ꢀꢓ ꢒ
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
CLKOUT1
STRB
t
d(XF)
FETCH
SXF/RXF
A15-A0
XF
Valid
Valid
Valid
PC = N
PC = N + 1
PC = N + 2
PC = N + 3
Valid
Figure 12. External Flag Timing
29
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢄ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢄ ꢇꢉꢇ ꢅ
ꢊ ꢋꢌ ꢋꢍꢎ ꢏ ꢀꢋ ꢌꢐ ꢎ ꢏ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
CLKOUT1
CLKOUT2
STRB
†
t
d(C2H-H)
HOLD
A15-A0
N
N + 1
Valid
N + 2
PS, DS,
or IS
Valid
R/W
D15-D0
HOLDA
t
dis(C1L-A)
In
In
t
t
dis(AL-A)
d(C1L-AL)
N
N + 1
–
–
–
FETCH
N – 2
N – 1
N
EXECUTE
†
HOLD is an asynchronous input and can occur at any time during a clock cycle. If the specified timing is met, the exact sequence shown occurs;
otherwise, a delay of one CLKOUT2 cycle occurs.
Figure 13. HOLD Timing (part A)
30
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢄ ꢇ ꢈ ꢀꢁ ꢂ ꢃꢄ ꢅꢆ ꢄꢇ ꢉꢇ ꢅ
ꢊꢋ ꢌꢋ ꢍꢎꢏ ꢀꢋ ꢌ ꢐꢎꢏ ꢑꢒ ꢓ ꢆꢔ ꢀ ꢀꢓ ꢒ
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
CLKOUT1
CLKOUT2
STRB
t
en(A-C1L)
†
t
d(C2H-H)
HOLD
PS, DS,
or IS
Valid
R/W
D15-D0
HOLDA
A15-A0
In
t
d(HH-AH)
N + 2
N + 2
–
–
–
–
–
–
N + 2
N + 1
FETCH
EXECUTE
†
HOLD is an asynchronous input and can occur at any time during a clock cycle. If the specified timing is met, the exact sequence shown occurs;
otherwise, a delay of one CLKOUT2 cycle occurs.
Figure 14. HOLD Timing (part B)
31
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢄ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢄ ꢇꢉꢇ ꢅ
ꢊ ꢋꢌ ꢋꢍꢎ ꢏ ꢀꢋ ꢌꢐ ꢎ ꢏ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
t
c(SCK)
t
r(SCK)
t
w(SCK)
CLKR
t
h(DR)
t
f(SCK)
t
h(FS)
t
w(SCK)
FSR
DR
t
su(FS)
t
su(DR)
Figure 15. Serial Port Receive Timing
t
c(SCK)
t
t
r(SCK)
w(SCK)
CLKX
t
d(CH-DX)
t
f(SCK)
t
w(SCK)
t
h(FS)
FSX
(Input,
TXM = 0)
t
t
d(CH-DX)
su(FS)
t
d(FL-DX)
DX
N = 1
N = 8,16
t
d(CH-FS)
t
d(CH-FS)
FSX
(Output,
TXM = 1)
Figure 16. Serial Port Transmit Timing
32
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢄ ꢇ ꢈ ꢀꢁ ꢂ ꢃꢄ ꢅꢆ ꢄꢇ ꢉꢇ ꢅ
ꢊꢋ ꢌꢋ ꢍꢎꢏ ꢀꢋ ꢌ ꢐꢎꢏ ꢑꢒ ꢓ ꢆꢔ ꢀ ꢀꢓ ꢒ
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
MECHANICAL DATA
FD (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
44 TERMINAL SHOWN
NO. OF
TERMINALS
**
A
B
18
28
MIN
MAX
MIN
MAX
29
17
0.342
(8,69)
0.358
(9,09)
0.064
0.080
20
28
44
52
68
84
(1,63) (2,03)
0.064 0.080
(1,63) (2,03)
0.069 0.120
(1,75) (3,05)
0.442
0.458
(11,23) (11,63)
0.640 0.660
(16,26) (16,76)
A SQ
0.761
(19,33)
0.739
(18,78)
0.082
(2,08)
0.120
(3,05)
0.120
(3,05)
0.938
0.962
0.082
(2,08)
(28,83) (24,43)
1.135 1.165
(28,83) (29,59)
0.082
(2,08) (3,05)
0.120
39
7
40
1
6
0.095 (2,41)
0.075 (1,91)
B
0.025 (0,64)
0.015 (0,38)
ꢀ 45°
0.025 ꢀ 0.050
(0,64 ꢀ 1,27)
35 Places
0.015 (0,38)
0.003 (0,08)
R
0.025 (0,64)
TYP
0.028 (0,71)
0.022 (0,56)
TYP
0.015 (0,38) TYP
0.045 (1,14)
0.035 (0,89)
ꢀ 45° 3 Places
0.055 (1,40)
0.045 (1,14)
0.050 (1,27)
4040136/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
33
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢄ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢄ ꢇꢉꢇ ꢅ
ꢊ ꢋꢌ ꢋꢍꢎ ꢏ ꢀꢋ ꢌꢐ ꢎ ꢏ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
FJ (S-CQCC-J**)
J-LEADED CERAMIC CHIP CARRIER
44 PINS SHOWN
A
B
Index Mark
(Optional)
6
1
40
7
39
0.043 (1,09)
0.033 (0,84)
C
0.025 (0,64)
0.015 (0,38)
29
29
17
17
0.015 (0,38) MIN
E
0.058 (1,47)
0.042 (1,07)
0.025 (0,64)
0.011 (0,28)
0.007 (0,18)
RAD
0.036 (0,89)
18
28
0.085 (2,16)
0.065 (1,65)
D
0.050 (1,27)
0.050 (1,27)
0.030 (0,76)
× 45°
3 Places
0.020 (0,51)
0.010 (0,25)
39
7
6
1
40
0.145 (3,68)
0.100 (2,54)
A
B
C
D
E
DIM
MAX
0.700
MIN
MAX
MIN
BSC
BSC
0.630
MAX
MIN
PINS **
0.680
0.659
0.641
0.500
0.080
0.058
44
(17,78) (17,27) (16,74) (16,28) (12,70) (16,00) (2,03) (1,47)
1.000 0.980 0.960 0.940 0.800 0.930 0.095 0.072
(25,40) (24,89) (24,38) (23,88) (20,32) (23,62) (2,41) (1,83)
68
4040139/C 10/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. The index mark may appear on top or bottom depending on package vendor.
D. This package is hermetically sealed with a metal lid.
34
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢄ ꢇ ꢈ ꢀꢁ ꢂ ꢃꢄ ꢅꢆ ꢄꢇ ꢉꢇ ꢅ
ꢊꢋ ꢌꢋ ꢍꢎꢏ ꢀꢋ ꢌ ꢐꢎꢏ ꢑꢒ ꢓ ꢆꢔ ꢀ ꢀꢓ ꢒ
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
GB (S-CPGA-P68)
CERAMIC PIN GRID ARRAY PACKAGE
0.970 (24,63)
0.950 (24,13)
0.536 (13,61)
0.524 (13,31)
0.800 (20,32) TYP
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9
0.088 (2,23)
0.072 (1,83)
0.100 (2,54)
0.194 (4,98)
0.166 (4,16)
0.055 (1,39)
0.045 (1,14)
0.050 (1,27) DIA
4 Places
0.018 (0,46) DIA TYP
4040114-14/C 04/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Index mark may appear on top or bottom depending vendor.
D. Pins are located within 0.010 (0,25) diameter of true position relative to each other at maximum material condition and within
0.030 (0,76) diameter relative to the edges of the ceramic.
E. This package can be hermetically sealed with metal lids or with ceramic lids using glass frit.
F. The pins can be gold plated or solder dipped.
G. Falls within MIL STD 1835 CMGA1-PN, CMGA13-PN and JEDEC MO-067 AA, MO-066 AA respectively
35
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CPGA
LCCC
JLCC
CPGA
JLCC
JLCC
CPGA
JLCC
CPGA
LCCC
JLCC
CPGA
Drawing
GB
FD
5962-8861901XA
5962-8861901YA
5962-8861901ZA
5962-8861902XA
5962-8861902ZA
SM320C25FJM
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
68
68
68
68
68
68
68
68
68
68
68
68
1
1
1
1
1
1
1
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
FJ
GB
FJ
FJ
SM320C25GBM
SMJ320C25-50FJM
SMJ320C25-50GBM
SMJ320C25FDM
SMJ320C25FJM
SMJ320C25GBM
GB
FJ
GB
FD
FJ
GB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SMJ320C25 :
Catalog: TMS320C25
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 1
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