SM320C26BFJM [TI]
DIGITAL SIGNAL PROCESSOR; 数字信号处理器
| 型号： | SM320C26BFJM |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DIGITAL SIGNAL PROCESSOR |
| 文件： | 总40页 (文件大小：616K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢈꢉ ꢊꢉ ꢋꢌꢍ ꢀꢉ ꢊ ꢎꢌꢍ ꢏꢐ ꢑ ꢆꢒ ꢀ ꢀꢑ ꢐ
SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
68-PIN GB
PIN GRID ARRAY CERAMIC PACKAGE
(TOP VIEW)
D
D
100-ns Instruction Cycle Time
†
1568 Words of Configurable On-Chip
Data/Program RAM
1
2
3
4
5
6
7
8
9
10 11
D
D
D
D
D
D
D
D
D
D
256 Words of On-Chip Program ROM
128K Words of Data/Program Space
Pin-for-Pin Compatible with the SMJ320C25
16 Input and 16 Output Channels
16-Bit Parallel Interface
A
B
C
D
E
F
Directly Accessible External Data Memory
Space
G
H
J
Global Data Memory Interface
16-Bit Instruction and Data Words
32-Bit ALU and Accumulator
K
L
Single-Cycle Multiply/Accumulate
Instructions
†
D
D
D
0 to 16-Bit Scaling Shifter
See Pin Assignments Table (Page 2) and Pin
Nomenclature Table (Page 3) for location and
description of all pins.
Bit Manipulation and Logical Instructions
Instruction Set Support for Floating-Point
Operations, Adaptive Filtering, and
Extended-Precision Arithmetic
D
D
D
D
D
D
D
D
D
Input Pin Polled by Software Branch
Instruction
Programmable Output Pin for Signalling
External Devices
D
D
D
Block Moves for Data/Program
Management
1.6-µm CMOS Technology
Single 5-V Supply
Packaging:
Repeat Instructions for Efficient Use of
Program Space
Eight Auxiliary Registers and Dedicated
Arithmetic Unit for Indirect Addressing
68-Pin Leaded Ceramic Chip Carrier
(FJ Suffix)
D
Serial Port for Direct Codec Interface
D
Synchronization Input for Multiprocessor
Configurations
68-Pin Leadless Ceramic Chip Carrier (FD
Suffix)
D
Wait States for Communications to Slow
Off-Chip Memories/Peripherals
68-Pin Grid Array Ceramic Package
(GB Suffix)
D
On-Chip Timer for Control Operations
Three External Maskable User Interrupts
Military Operating Temperature
Range . . . – 55° to 125°C
D
description
The SMJ320C26 Digital Signal Processor is a member of the TMS320 family of VLSI digital signal processors
and peripherals. The TMS320 family supports a wide range of digital signal processing applications, such as
telecommunications, modems, image processing, speech processing, spectrum analysis, audio processing,
digital filtering, high-speed control, graphics, and other computation intensive applications.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
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1
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SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
description
68-PIN FJ AND FD
LEADED AND LEADLESS
CERAMIC CHIP CARRIER PACKAGES
(TOP VIEW)
†
With a 100-ns instruction cycle time and an
innovative
memory
configuration,
the
SMJ320C26 performs operations necessary for
many real time digital signal processing algo-
rithms. Since most instructions require only one
cycle, the SMJ320C26 is capable of executing ten
million instructions per second. On-chip program-
mable data/program RAM of 1568 words of 16
bits, on-chip program ROM of 256-words, direct
addressing of up to 64K-words of external
program and 64K-words of data memory space,
and multiprocessor interface features for sharing
global memory minimize unnecessary data
transfers to take full advantage of the capabilities
of the processor.
9
8
7
6
5
4
3
2
1 6867 66 65 6463 62 61
60
V
10
11
12
13
14
15
16
SS
D7
IACK
59
58
57
56
55
54
MSC
D6
D5
D4
D3
D2
D1
D0
CLKOUT1
CLKOUT2
XF
HOLDA
DX
17
18
19
20
21
22
23
53 FSX
X2/CLKIN
X1
BR
STRB
52
51
50
49
48
47
SYNC
INT0
INT1
INT2
R/W
PS
V
CC
DR
FSR
A0
IS
DS
24
25
26
46
45
44
V
SS
The SMJ320C26 scaling shifter has a 16-bit input
connected to the data bus and a 32-bit output
connected to the ALU. The scaling shifter
produces a left shift of 0 to 16 bits on the input
data, as programmed in the instruction. The LSBs
of the output are filled with zeroes, and the MSBs
may be either filled with zeroes or sign-extended,
depending upon the status programmed into the
SXM (sign-extension mode) bit of status register
ST1.
27 28 2930 31 32 3334 35 3637 38 39 4041 42 43
†
See Pin Assignments Table (Page 2) and Pin
Nomenclature Table (Page 3) for location and
description of all pins.
PGA/LCCC/JLCC PIN ASSIGNMENTS
FUNCTION
PIN
FUNCTION
A12
PIN
FUNCTION
D2
PIN
E1/16
D2/15
D1/14
C2/13
C1/12
B2/11
A2/9
FUNCTION
D14
PIN
FUNCTION
INT2
PIN
FUNCTION
PIN
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
K1/26
K2/28
L3/29
K3/30
L4/31
K4/32
L5/33
K5/34
K6/36
L7/37
K7/38
L8/39
K8/40
L9/41
K9/42
L10/43
B7/68
G11/50
C11/58
D10/57
B9/64
A9/63
F1/18
E2/17
A5/3
H1/22
J11/46
A6/1
V
CC
V
CC
V
SS
V
SS
V
SS
H2/23
L6/35
A13
D3
D15
B6/2
IS
A14
D4
DR
J1/24
MP/MC
MSC
B1/10
K11/44
L2/27
A15
D5
DS
K10/45
E11/54
J2/25
C10/59
J10/47
B8/66
A8/65
H11/48
H10/49
F2/19
BIO
D6
DX
PS
BR
D7
FSR
READY
RS
XF
D11/56
G10/51
F11/52
CLKOUT1
CLKOUT2
CLKR
CLKX
D0
D8
FSX
F10/53
A7/67
E10/55
B11/60
G1/20
G2/21
X1
D9
B3/8
HOLD
HOLDA
IACK
INT0
INT1
R/W
X2/CLKIN
D10
D11
D12
D13
A3/7
STRB
SYNC
B4/6
A4/5
V
V
A10/61
B10/62
CC
D1
B5/4
CC
2
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SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
PIN NOMENCLATURE
†
I/O/Z
NAME
DEFINITION
V
V
I
I
5-V supply pins.
Ground pins.
CC
SS
X1
O
I
Output from internal oscillator for crystal.
X2/CLKIN
CLKOUT1
CLKOUT2
D15–D0
A15–A0
PS, DS, IS
R/W
Input to internal oscillator from crystal or external clock.
Master clock output (crystal or CLKIN frequency/4).
A second clock output signal.
O
O
I/O/Z
O/Z
O/Z
O/Z
O/Z
I
16-bit data bus D15 (MSB) through D0 (LSB). Multiplexed between program, data and I/O spaces.
16-bit address bus A15 (MSB) through A0 (LSB).
Program, data and I/O space select signals.
Read/write signal.
STRB
Strobe signal.
RS
Reset input.
INT2, INT1, INT0
MP/MC
MSC
I
External user interrupt inputs.
Microprocessor/microcomputer mode select pin.
Microstate complete signal.
I
O
IACK
O
Interrupt acknowledge signal.
Data ready input. Asserted by external logic when using slower devices to indicate that the current bus transaction
is complete.
READY
I
BR
XF
O
O
Bus request signal. Asserted when the SMJ320C26 requires access to an external global data memory space.
External flag output (latched software – programmable signal).
Hold input. When asserted, SMJ320C26 goes into an idle mode and places the data address and control lines
in the high-impedance state.
HOLD
I
HOLDA
SYNC
BIO
O
Hold acknowledge signal.
I
Synchronization input.
I
Branch control input. Polled by BIOZ instruction.
Serial data receive input.
DR
I
CLKR
FSR
I
Clock input for serial port receiver.
I
O/Z
I
Frame synchronization pulse for receive input.
Serial data transmit output.
DX
CLKX
FSX
Clock input for serial port transmitter.
Frame synchronization pulse for transmit. May be configured as either an input or an output.
I/O/Z
†
I/O/Z denotes input/output/high-impedance state.
3
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SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
functional block diagram
PROGRAM BUS
16
16
QIR(16)
IR(16)
16
16
ST0(16)
ST1(16)
RPTC(8)
IFR(6)
16
R/W
STRB
READY
BR
PFC(16)
16
16
DR
MUX
16
XF
16
CLKR
FSR
DX
HOLD
HOLDA
MSC
BIO
MCS(16)
PC(16)
CLKX
FSX
16
16
16
16
RS
STACK
(8 - 16)
IACK
RSR(16)
XSR(16)
DRR(16)
DXR(16)
TIM(16)
PRD(16)
IMR(6)
ADDRESS
MP/MC
16
PROGRAM
ROM
(256 x 16)
3
16
16
16
INT(2-0)
16
16
INSTRUCTION
A15–A0
6
8
16
GREG(8)
16
16
D15–D0
16
16
16
PROGRAM BUS
DATA BUS
16
16
16
16
SHIFTER(0–16)
3
16
16
MUX
16
AR0(16)
AR1(16)
AR2(16)
AR3(16)
AR4(16)
AR5(16)
AR6(16)
AR7(16)
TR(16)
9
3
ARP(3)
MULTIPLIER
DP(9)
3
7 LSB
FROM
IR
PR(32)
9
32
32
ARS(3)
16
16
3
SHIFTER (6.0.1.4)
MUX
ARAU(16)
16
MUX
32
MUX
16
MUX
16
MUX
16
MUX
16
ALU(32)
32
DATA/PROG
RAM (512 x 16)
BLOCK B3
DATA/PROG
RAM (512 x 16)
BLOCK B1
DATA
RAM (32 x 16)
BLOCK B2
DATA/PROG
RAM (512 x 16)
BLOCK B0
32
C
ACCH(16)
ACCL(16)
32
MUX
MUX
MUX
SHIFTERS (0–7)
16
16
16
16
16
16
DATA BUS
LEGEND:
ACCH
ACCL
ALU
=
=
=
=
=
=
=
=
=
Accumulator high
IFR
IMR
IR
MCS
QIR
PR
PRD
TIM
TR
=
=
=
=
=
=
=
=
=
Interrupt flag register
PC
=
=
=
=
=
=
=
=
=
Program counter
Accumulator low
Interrupt mask register
Instruction register
Microcall stack
PFC
Prefetch counter
Arithmetic logic unit
RPTC
GREG
RSR
XSR
AR0–AR7
ST0, ST1
C
Repeat instruction counter
Global memory allocation register
Serial port receive shift register
Serial port to transmit shift register
Auxiliary registers
Status registers
Carry bit
ARAU
ARS
ARP
DP
Auxiliary register arithmetic unit
Auxiliary register pointer buffer
Auxiliary register pointer
Queue instruction register
Product register
Data memory page pointer
Serial port data receive register
Serial port data trademark register
Product register for timer
Timer
DRR
DXR
Temporary register
4
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SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
architecture
The SMJ320C26 architecture is based on the SMJ320C25 with a different internal RAM and ROM configuration.
The SMJ320C26 integrates 256 words of on-chip ROM and 1568 words of on-chip RAM compared to 4K words
of on-chip ROM and 544 words of on-chip RAM for the SMJ320C25. The SMJ320C26 is pin for pin compatible
with the SMJ320C25.
Increased throughput on the SMJ320C26 for many DSP applications is accomplished by means of single cycle
multiply/accumulate instructions with a data move option, eight auxiliary registers with a dedicated arithmetic
unit, and faster I/O necessary for data intensive signal processing.
The architectural design of the SMJ320C26 emphasizes overall speed, communication, and flexibility in the
processor configuration. Control signals and instructions provide floating point support, block memory transfers,
communication to slower off-chip devices, and multiprocessing implementations.
Three large on-chip RAM blocks, configurable either as separate program and data spaces or as three
contiguous data blocks, provide increased flexibility in system design. Programs of up to 256 words can be
masked into the internal program ROM. The remainder of the 64K-word program memory space is located
externally. Large programs can execute at full speed from this memory space. Programs can also be
downloaded from slow external memory to high speed on-chip RAM. A data memory address space of 64K
words is included to facilitate implementation of DSP algorithms. The VLSI implementation of the SMJ320C26
incorporates all of these features as well as many others, including a hardware timer, serial port, and block data
transfer capabilities.
32-bit ALU accumulator
The SMJ320C26 32-bit Arithmetic Logic Unit (ALU) and accumulator perform a wide range of arithmetic and
logic instructions, the majority of which execute in a single clock cycle. The ALU executes a variety of branch
instructions dependent on the status of the ALU or a single bit in a word. These instructions provide the following
capabilities:
D
D
D
Branch to an address specified by the accumulator.
Normalize fixed point numbers contained in the accumulator.
Test a specified bit of a word in data memory.
One input to the ALU is always provided from the accumulator, and the other input may be provided from the
Product Register (PR) of the multiplier or the input scaling shifter which has fetched data from the RAM on the
data bus. After the ALU has performed the arithmetic or logical operations, the result is stored in the
accumulator.
The 32-bit accumulator is split into two 16-bit segments for storage in data memory. Additional shifters at the
output of the accumulator perform shifts while the data is being transferred to the data bus for storage. The
contents of the accumulator remain unchanged.
scaling shifter
The SMJ320C26 scaling shifter has a 16-bit input connected to the data bus and a 32-bit output connected to
the ALU. The scaling shifter produces a left shift of 0 to 16-bits on the input data, as specified in the instruction
word. The LSBs of the output are filled with zeroes, and the MSBs may be either filled with zeroes or sign
extended, depending upon the value of the SXM (sign extension mode) bit of status register STO.
16 × 16 bit parallel multiplier
The SMJ320C26 has a 16 × 16 bit-hardware multiplier, which is capable of computing a signed or unsigned
32-bit product in a single machine cycle. The multiplier has the following two associated registers:
D
D
A 16-bit Temporary Register (TR) that holds one of the operands for the multiplier, and
A 32-bit Product Register (PR) that holds the product.
5
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SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
16 × 16 bit parallel multiplier (continued)
Incorporated into the SMJ320C26 instruction set are single-cycle multiply/accumulate instructions that allow
both operands to be fetched simultaneously. The data for these operations may reside anywhere in internal or
external memory, and can be transferred to the multiplier each cycle via the program and data buses.
Four product shift modes are available at the Product Register (PR) output that are useful when performing
multiply/accumulate operations, fractional arithmetic, or justifying fractional products.
timer
The SMJ320C26 provides a memory mapped 16-bit timer for control operations. The on-chip timer (TIM)
register is a down counter that is continuously clocked by CLKOUT1. A timer interrupt (TINT) is generated every
time the timer decrements to zero, provided the timer interrupt is enabled. The timer is reloaded with the value
contained in the period (PRD) register within the next cycle after it reaches zero so that interrupts may be
programmed to occur at regular intervals of PRD + 1 cycles of CLKOUT1.
memory control
The SMJ320C26 provides a total of 1568 words of 16 bit on-chip RAM, divided into four separate blocks (B0,
B1, B2, and B3). Of the 1568 words, 32 words (block B2) are always data memory, and all other blocks are
programmable as either data or program memory. A data memory size of 1568 words allows the SMJ320C26
to handle a data array of 1536 words, while still leaving 32 locations for intermediate storage. When using B0,
B1, or B3 as program memory, instructions can be downloaded from external memory into on-chip RAM, and
then executed.
When using on-chip program RAM, ROM, or high speed external program memory, the SMJ320C26 runs at
full speed without wait states. However, the READY line can be used to interface the SMJ320C26 to slower,
less expensive external memory. Downloading programs from slow off-chip memory to on-chip program RAM
speeds processing and cuts overall system costs.
The SMJ320C26 provides three separate address spaces for program memory, data memory, and I/O. The
on-chip memory is mapped into either the data memory or program memory space, depending upon the choice
of memory configuration.
The instruction configuration (parameter) is used as follows to configure the blocks B0, B1, and B3 as program
or as data memory.
CONFIGURATION
B0
B1
B3
0
1
2
3
Data
Data
Data
Program
Program
Data
Data
Data
Program
Program
Program
Program
Regardless of the configuration, the user may still execute from external program memory.
The SMJ320C26 provides a ROM of 256 words. The ROM is sufficient to allow the programming of a bootstrap
program and interrupt handler, or to implement self test routines.
The SMJ320C26 has six registers that are mapped into the data memory space at the locations 0–5; a serial
port data receive register, serial port data transmit register, timer register, period register, interrupt mask register,
and global memory allocation register.
6
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SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
memory control (continued)
MEMORY MAPS AFTER A RESET OR CONF 0
1 MP/MC = 1
PROGRAM
DATA
I/O
0 (0000h)
0 (0000h)
0
INTERRUPTS
ON-CHIP
MMRs
EXTERNAL
AND RESERVED
(EXTERNAL)
5 (0005h)
6 (0006h)
15
31 (001Fh)
32 (0020h)
RESERVED
PAGE 0
95 (005Fh)
96 (0060h)
ON-CHIP
BLOCK B2
127 (007Fh)
128 (0080h)
PAGE 1-3
PAGE 4-7
RESERVED
511 (01FFh)
512 (0200h)
ON-CHIP
BLOCK B0
EXTERNAL
1023 (03FFh)
1024 (0400h)
ON-CHIP
BLOCK B1
PAGE 8-11
1535 (05FFh)
1536 (0600h)
ON-CHIP
PAGE 12-15
PAGE 16-511
BLOCK B3
2047 (07FFh)
2048 (0800h)
EXTERNAL
65535 (FFFFh)
65535 (FFFFh)
2 MP/MC = 0
0 (0000h)
PROGRAM
DATA
I/O
0 (0000h)
0
ON-CHIP
MMRs
INTERRUPTS
AND RESERVED
BOOTLOAD ROM
EXTERNAL
5 (0005h)
6 (0006h)
15
RESERVED
PAGE 0
255 (00FFh)
256 (0100h)
95 (005Fh)
96 (0060h)
ON-CHIP
BLOCK B2
RESERVED
127 (007Fh)
128 (0080h)
4095 (0FFFh)
4096 (1000h)
PAGE 1-3
PAGE 4-7
RESERVED
511 (01FFh)
512 (0200h)
ON-CHIP
BLOCK B0
1023 (03FFh)
1024 (0400h)
ON-CHIP
BLOCK B1
PAGE 8-11
EXTERNAL
1535 (05FFh)
1536 (0600h)
ON-CHIP
PAGE 12-15
PAGE 16-511
BLOCK B3
2047 (07FFh)
2048 (0800h)
EXTERNAL
65535 (FFFFh)
65535 (FFFFh)
Figure 1A. Memory Maps
7
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SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
memory control (continued)
MEMORY MAPS AFTER CONF 1
1 MP/MC = 1
PROGRAM
DATA
I/O
0 (0000h)
0
0 (0000h)
ON-CHIP
MMRs
INTERRUPTS
AND RESERVED
(EXTERNAL)
EXTERNAL
5 (0005h)
6 (0006h)
15
31 (001Fh)
32 (0020h)
RESERVED
PAGE 0
95 (005Fh)
96 (0060h)
ON-CHIP
BLOCK B2
127 (007Fh)
128 (0080h)
EXTERNAL
PAGE 1-3
PAGE 4-7
RESERVED
511 (01FFh)
512 (0200h)
DOES NOT
EXIST
63999 (F9FFh)
64000 (FA00h)
1023 (03FFh)
1024 (0400h)
ON-CHIP
BLOCK B0
ON-CHIP
BLOCK B1
PAGE 8-11
64511 (FBFFh)
64512 (FC00h)
1535 (05FFh)
1536 (0600h)
EXTERNAL
ON-CHIP
BLOCK B3
PAGE 12-15
65023 (FDFFh)
65024 (FE00h)
2047 (07FFh)
2048 (0800h)
EXTERNAL
EXTERNAL
PAGE 16-511
65535 (FFFFh)
65535 (FFFFh)
2 MP/MC = 0
DATA
I/O
PROGRAM
0 (0000h)
0
0 (0000h)
INTERRUPTS
AND RESERVED
BOOTLOAD ROM
ON-CHIP
MMRs
EXTERNAL
5 (0005h)
6 (0006h)
15
255 (00FFh)
256 (0100h)
RESERVED
PAGE 0
RESERVED
EXTERNAL
95 (005Fh)
96 (0060h)
4095 (0FFFh)
4096 (1000h)
ON-CHIP
BLOCK B2
127 (007Fh)
128 (0080h)
PAGE 1-3
PAGE 4-7
RESERVED
511 (01FFh)
512 (0200h)
DOES NOT
EXIST
1023 (03FFh)
1024 (0400h)
63999 (F9FFh)
64000 (FA00h)
ON-CHIP
BLOCK B1
PAGE 8-11
ON-CHIP
BLOCK B0
1535 (05FFh)
1536 (0600h)
64511 (FBFFh)
64512 (FC00h)
ON-CHIP
BLOCK B3
PAGE 12-15
EXTERNAL
EXTERNAL
2047 (07FFh)
2048 (0800h)
65023 (FDFFh)
65024 (FE00h)
EXTERNAL
PAGE 16-511
65535 (FFFFh)
65535 (FFFFh)
Figure 1B. Memory Maps
8
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SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
memory control (continued)
MEMORY MAPS AFTER CONF 2
1 MP/MC = 1
PROGRAM
DATA
I/O
0
0 (0000h)
0 (0000h)
ON-CHIP
MMRs
INTERRUPTS
AND RESERVED
(EXTERNAL)
EXTERNAL
5 (0005h)
6 (0006h)
15
31 (001Fh)
32 (0020h)
RESERVED
PAGE 0
95 (005Fh)
96 (0060h)
ON-CHIP
BLOCK B2
127 (007Fh)
128 (0080h)
EXTERNAL
PAGE 1-3
PAGE 4-7
RESERVED
511 (01FFh)
512 (0200h)
DOES NOT
EXIST
63999 (F9FFh)
64000 (FA00h)
1023 (03FFh)
1024 (0400h)
ON-CHIP
BLOCK B0
DOES NOT
EXIST
PAGE 8-11
64511 (FBFFh)
64512 (FC00h)
1535 (05FFh)
1536 (0600h)
ON-CHIP
BLOCK B1
ON-CHIP
BLOCK B3
PAGE 12-15
PAGE 16-511
65023 (FDFFh)
65024 (FE00h)
2047 (07FFh)
2048 (0800h)
EXTERNAL
EXTERNAL
65535 (FFFFh)
65535 (FFFFh)
2 MP/MC = 0
PROGRAM
DATA
I/O
0
0 (0000h)
0 (0000h)
INTERRUPTS
AND RESERVED
BOOTLOAD ROM
ON-CHIP
MMRs
EXTERNAL
5 (0005h)
6 (0006h)
15
255 (00FFh)
256 (0100h)
RESERVED
95 (005Fh)
96 (0060h)
RESERVED
PAGE 0
4095 (0FFFh)
4096 (1000h)
ON-CHIP
BLOCK B2
127 (007Fh)
128 (0080h)
EXTERNAL
PAGE 1-3
PAGE 4-7
RESERVED
511 (01FFh)
512 (0200h)
DOES NOT
EXIST
1023 (03FFh)
1024 (0400h)
63999 (F9FFh)
64000 (FA00h)
DOES NOT
EXIST
ON-CHIP
BLOCK B0
PAGE 8-11
64511 (FBFFh)
64512 (FC00h)
1535 (05FFh)
1536 (0600h)
ON-CHIP
BLOCK B1
ON-CHIP
BLOCK B3
PAGE 12-15
PAGE 16-511
65023 (FDFFh)
65024 (FE00h)
2047 (07FFh)
2048 (0800h)
EXTERNAL
EXTERNAL
65535 (FFFFh)
65535 (FFFFh)
Figure 1C. Memory Maps
9
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SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
memory control (continued)
MEMORY MAPS AFTER CONF 3
1 MP/MC = 1
PROGRAM
DATA
I/O
0
0 (0000h)
0 (0000h)
ON-CHIP
MMRs
INTERRUPTS
AND RESERVED
(EXTERNAL)
EXTERNAL
5 (0005h)
6 (0006h)
15
31 (001Fh)
32 (0020h)
RESERVED
PAGE 0
95 (005Fh)
96 (0060h)
ON-CHIP
BLOCK B2
127 (007Fh)
128 (0080h)
EXTERNAL
PAGE 1-3
PAGE 4-7
RESERVED
511 (01FFh)
512 (0200h)
DOES NOT
EXIST
63999 (F9FFh)
64000 (FA00h)
1023 (03FFh)
1024 (0400h)
ON-CHIP
BLOCK B0
DOES NOT
EXIST
PAGE 8-11
64511 (FBFFh)
64512 (FC00h)
1535 (05FFh)
1536 (0600h)
ON-CHIP
BLOCK B1
DOES NOT
EXIST
PAGE 12-15
65023 (FDFFh)
65024 (FE00h)
2047 (07FFh)
2048 (0800h)
ON-CHIP
BLOCK B3
EXTERNAL
PAGE 16-511
65535 (FFFFh)
65535 (FFFFh)
2 MP/MC = 0
PROGRAM
DATA
I/O
0 (0000h)
0
0 (0000h)
INTERRUPTS
AND RESERVED
BOOTLOAD ROM
ON-CHIP
MMRs
EXTERNAL
5 (0005h)
6 (0006h)
15
255 (00FFh)
256 (0100h)
RESERVED
95 (005Fh)
96 (0060h)
RESERVED
PAGE 0
4095 (0FFFh)
4096 (1000h)
ON-CHIP
BLOCK B2
EXTERNAL
127 (007Fh)
128 (0080h)
PAGE 1-3
PAGE 4-7
RESERVED
511 (01FFh)
512 (0200h)
DOES NOT
EXIST
63999 (F9FFh)
64000 (FA00h)
1023 (03FFh)
1024 (0400h)
ON-CHIP
DOES NOT
EXIST
PAGE 8-11
BLOCK B0
64511 (FBFFh)
64512 (FC00h)
1535 (05FFh)
1536 (0600h)
ON-CHIP
BLOCK B1
DOES NOT
EXIST
PAGE 12-15
65023 (FDFFh)
65024 (FE00h)
2047 (07FFh)
2048 (0800h)
ON-CHIP
BLOCK B3
EXTERNAL
PAGE 16-511
65535 (FFFFh)
65535 (FFFFh)
Figure 1D. Memory Maps
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SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
interrupts and subroutines
The SMJ320C26 has three external maskable user interrupts INT2–INT0, available for external devices that
interrupt the processor. Internal interrupts are generated by the serial port (RINT and XINT), by the timer (TINT),
and by the software interrupt (TRAP) instruction. Interrupts are prioritized with reset (RS) having the highest
priority and the serial port transmit interrupt (XINT) having the lowest priority. All interrupt locations are on
two-words boundaries so that branch instructions can be accommodated in those locations if desired.
A built in mechanism protects multicycle instructions from interrupts. If an interrupt occurs during a multicycle
instruction, the interrupt is not processed until the instruction is completed. This mechanism applies both to
instructions that are repeated or become multicycle due to the READY signal.
external interface
The SMJ320C26 supports a wide range of system interfacing requirements. Program, data, and I/O address
spaces provide interface to memory and I/O, thus maximizing system throughput. I/O design is simplified by
having I/O treated the same way as memory. I/O devices are mapped into the I/O address space using the
processor’s external address and data busses in the same manner as memory-mapped devices. Interface to
memory and I/O devices of varying speeds is accomplished by using the READY line. When transactions are
made with slower devices, the SMJ320C26 processor waits until the other device completes its function and
signals the processor via the READY line, the SMJ320C26 then continues execution.
A serial port provides communication with serial devices, such as codecs, serial A/D converters, and other serial
systems. The interface signals are compatible with codecs and many other serial devices with a minimum of
external hardware. The serial port may also be used for intercommunication between processors in
multiprocessing applications.
The serial port has two memory mapped registers; the data transmit register (DXR) and the data receive register
(DRR). Both registers operate in either the byte mode or 16-bit word mode, and may be accessed in the same
manner as any other data memory location. Each register has an external clock, a framing signal, and
associated shift registers. One method of multiprocessing may be implemented by programming one device
to transmit while the others are in the receive mode.
multiprocessing
The flexibility of the SMJ320C26 allows configurations to satisfy a wide range of system requirements. The
SMJ320C26 can be used as follows:
D
D
D
D
A standalone processor.
A multiprocessor with devices in parallel.
A multiprocessor with global memory space.
A peripheral processor interfaced via processor controlled signals to another device.
For multiprocessing applications, the SMJ320C26 has the capability of allocating global data memory space
and communicating with that space via the BR (bus request) and READY control signals. Global memory is data
memory shared by more than one processor. Global data memory access must be arbitrated. The 8-bit memory
mapped GREG (global memory allocation register) specifies part of the SMJ320C26’s data memory as global
external memory. The contents of the register determine the size of the global memory space. If the current
instruction addresses a location within that space, BR is asserted to request control of the data bus. The length
of the memory cycle is controlled by the READY line.
The SMJ320C26 supports DMA (direct memory access) to its external program/data memory using the HOLD
and HOLDA signals. Another processor can take complete control of the SMJ320C26’s external memory by
asserting HOLD low. This causes the SMJ320C26 to place its address, data, and control lines in a high
impedance state, and assert HOLDA.
11
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SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
addressing modes
The SMJ320C26 instruction set provides three memory addressing modes; direct, indirect, and immediate
addressing.
Both direct and indirect addressing can be used to access data memory. In direct addressing, seven bits of the
instruction word are concatenated with the nine bits of the data memory page pointer to form the 16-bit data
memory address. Indirect addressing accesses data memory through the eight auxiliary registers. In immediate
addressing, the data is embedded in the instruction word(s).
In direct addressing, the instruction word contains the lower seven bits of the data memory address. This field
is concatenated with the nine bits of the data memory page pointer to form the full 16-bit address. Thus, memory
is paged in the direct addressing mode with a total of 512 pages, each page containing 128 words.
Eight auxiliary registers (AR0–AR7) provide flexible and powerful indirect addressing. To select a specific
auxiliary register, the Auxiliary Register Pointer (ARP) is loaded with a value from 0 through 7 for AR0 through
AR7 respectively.
There are seven types of indirect addressing: auto increment, auto decrement, post indexing by either adding
or subtracting the contents of AR0, single indirect addressing with no increment or decrement and bit reversal
addressing (used in FFTs) with increment or decrement. All operations are performed on the current auxiliary
register in the same cycle as the original instruction, followed by an ARP update.
repeat feature
A repeat feature, used with instructions such as multiply/accumulates, block moves, I/O transfers, and table
read/writes, allows a single instruction to be executed up to 256 times. The repeat counter (RPTC) is loaded
with either a data memory value (RPT instruction) or an immediate value (RPTK instruction). The value of this
operand is one less than the number of times that the next instruction is executed. Those instructions that are
normally multicycle are pipelined when using the repeat feature, and effectively become single-cycle
instructions.
instruction set
The SMJ320C26 microprocessor implements a comprehensive instruction set that supports both numeric
intensive signal processing operations as well as general purpose applications, such as multiprocessing and
high speed control.
For maximum throughput, the next instruction is prefetched while the current one is being executed. Since the
same data lines are used to communicate to external data/program or I/O space, the number of cycles may vary
depending upon whether the next data operand fetch is from internal or external program memory. Highest
throughput is achieved by maintaining data memory on-chip and using either internal or fast program memory.
Table 1 lists the symbols and abbreviations used in Table 2, the instruction set summary. Table 2 consists
primarily of single-cycle, single-word instructions. Infrequently used branch, I-O, and CALL instructions are
multicycle. The instruction set summary is arranged according to function and alphabetized within each
‡
functional grouping. The symbol ( ) indicates instructions that are not included in the SMJ320C25 instruction
set.
12
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SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
instruction set (continued)
Table 1. Instruction Symbols
SYMBOL
MEANING
4-bit field specifying a bit code
2-bit field specifying compare mode
Data memory address field
Format status bit
B
CM
D
FO
M
Addressing mode bit
K
Immediate operand field
Port address (PA0 through PA 15 are predefined assembler
symbols equal to 0 through 15 respectively).
PA
PM
R
2-bit field specifying P register output shift code
3-bit operand field specifying auxiliary register
4-bit left-shift code
S
CNF
X
Internal RAM configuration bits
3-bit accumulator left-shift field
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SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
instruction set (continued)
Table 2. Instruction Set Summary
ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS
INSTRUCTION BIT CODE
NO.
MNEMONIC
DESCRIPTION
WORDS
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
ABS
Absolute value of accumulator
1
1
1
1
1
1
1
2
1
2
1
1
1
1
2
1
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
0
0
0
1
0
0
1
0
1
1
0
1
0
1
1
1
0
1
1
1
0
0
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
0
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
1
0
0
1
0
1
1
1
0
0
0
0
1
1
0
1
1
D
D
ADD
Add to accumulator with shift
S
M
M
M
ADDC
ADDH
ADDK
ADDS
Add to accumulator with carry
0
1
1
1
1
0
0
1
0
0
S
1
1
0
0
0
1
1
0
0
1
0
0
0
D
Add to high accumulator
D
D
D
Add to accumulator short immediate
Add to low accumulator with sign extension suppressed
Add to accumulator with shift specified by T register
Add to accumulator long immediate with shift
AND with accumulator
M
M
0
†
ADDT
†
ADLK
AND
0
0
0
0
0
1
0
D
1
1
1
1
M
0
†
†
ANDK
CMPL
LAC
AND immediate with accumulator with shift
Complement accumulator
0
0
0
1
0
0
0
1
1
0
1
0
1
S
S
1
0
0
0
D
D
Load accumulator with shift
M
K
LACK
Load accumulator immediate short
Load accumulator with shift specified by T register
Load accumulator long immediate with shift
Negate accumulator
1
0
0
0
1
1
0
1
†
LACT
M
0
†
LALK
S
S
0
0
X
0
1
X
0
0
X
0
0
0
0
0
0
0
1
1
1
1
0
†
NEG
1
1
1
1
1
1
1
1
0
0
0
1
0
†
NORM
OR
Normalize contents of accumulator
OR with accumulator
M
M
0
D
†
ORK
OR immediate with accumulator with shift
Rotate accumulator left
0
0
0
0
1
1
0
1
1
0
0
0
1
1
1
0
0
0
1
0
1
ROL
1
1
1
0
1
1
1
1
0
0
0
ROR
SACH
SACL
Rotate accumulator right
0
D
D
X
Store high accumulator with shift
M
M
0
X
Store low accumulator with shift
†
SBLK
Subtract from accumulator long immediate with shift
Shift accumulator left
S
S
0
0
0
0
0
0
0
1
1
0
1
1
0
0
0
1
0
0
1
0
1
†
SFL
1
1
1
1
1
1
0
0
0
†
SFR
Shift accumulator right
0
D
D
SUB
Subtract from accumulator with shift
Subtract from accumulator with borrow
Conditional subtract
M
M
M
M
SUBB
SUBC
SUBH
SUBK
SUBS
1
0
0
1
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
1
1
0
1
1
0
0
D
D
Subtract from high accumulator
K
Subtract from accumulator short immediate
Subtract from low accumulator with sign extension suppressed
Subtract from accumulator with shift specified by T register
Exclusive-OR with accumulator
D
M
M
M
0
†
D
D
SUBT
XOR
†
S
XORK
ZAC
Exclusive-OR immediate with accumulator with shift
Zero accumulator
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
1
1
0
D
ZALH
ZALR
ZALS
Zero low accumulator and load high accumulator
Zero low accumulator and load high accumulator with rounding
Zero accumulator and load low accumulator with sign extension suppressed
M
M
M
D
D
†
These instructions are not included in the SMJ32010 instruction set.
14
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SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
instruction set (continued)
Table 2. Instruction Set Summary (continued)
AUXILIARY REGISTERS AND DATA PAGE POINTER INSTRUCTIONS
INSTRUCTION BIT CODE
NO.
MNEMONIC
DESCRIPTION
WORDS
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
D
ADRK
Add to auxiliary register short immediate
Compare auxiliary register with auxiliary register AR0
Load auxiliary register
1
1
1
1
1
1
1
2
1
1
1
0
1
0
1
0
0
1
1
0
0
0
1
1
0
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
1
1
1
0
0
†
CM
CMPR
0
1
0
1
0
1
0
0
LAR
M
K
R
K
LARK
LARP
LDP
Load auxiliary register short immediate
Load auxiliary register pointer
R
R
0
1
0
0
0
1
0
M
M
0
0
0
0
0
Load data memory page pointer
1
0
LDPK
Load data memory page pointer immediate
Load auxiliary register long immediate
Modify auxiliary register
D
†
LRLK
MAR
SAR
R
0
0
0
0
DP
1
1
0
1
1
M
M
D
D
Store auxiliary register
R
SBRK
Subtract from auxiliary register short immediate
1
K
T REGISTER, P REGISTER, AND MULTIPLY INSTRUCTIONS
INSTRUCTION BIT CODE
NO.
MNEMONIC
DESCRIPTION
WORDS
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
APAC
Add P register to accumulator
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
0
0
1
0
0
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
1
1
0
1
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
1
0
0
0
1
0
1
0
1
1
0
1
1
0
0
0
0
0
0
1
0
1
0
1
†
LPH
LT
Load high P register
M
M
M
M
M
M
M
M
M
M
D
D
D
Load T register
LTA
LTD
Load T register and accumulator previous product
Load T register, accumulate previous product, and move data
Load T register and store P register in accumulator
Load T register and subtract previous product
Multiply and accumulate
D
D
D
D
D
D
†
LTP
LTS
†
†
MAC
†
MACD
MPY
Multiply and accumulate with data move
Multiply (with T register, store product in P register)
Multiply and accumulate previous product
Multiply immediate
K
D
D
MPYA
MPYK
MPYS
MPYU
PAC
K
Multiply and subtract previous product
Multiply unsigned
1
0
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
0
1
1
1
0
0
1
0
0
1
0
M
M
0
D
D
Load accumulator with P register
Subtract P register from accumulator
Store high P register
0
0
0
0
1
1
0
1
1
0
1
0
0
SPAC
SPH
0
0
D
D
M
M
0
SPL
Store low P register
†
SPM
Set P register output shift mode
Square and accumulate
0
0
0
1
0
PM
†
†
D
SQRA
SQRS
M
M
D
Square and subtract previous product
†
These instructions are not included in the SMJ32010 instruction set.
15
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SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
instruction set (continued)
Table 2. Instruction Set Summary (continued)
BRANCH/CALL INSTRUCTIONS
INSTRUCTION BIT CODE
NO.
MNEMONIC
DESCRITPION
WORDS
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
D
B
Branch unconditionally
2
1
2
1
1
1
1
1
1
1
0
1
1
0
1
1
1
1
1
1
0
1
1
1
1
0
1
1
0
1
†
BACC
BANZ
Branch to address specified by accumulator
Branch on auxiliary register not zero
0
1
0
0
1
0
1
D
†
D
BBNZ
2
1
1
1
1
1
0
0
1
1
Branch if TC bit ≠ 0
Branch if TC bit = 0
Branch on carry
†
BBZ
BC
2
2
1
0
1
1
1
0
1
1
1
1
0
1
0
1
0
0
1
1
D
D
BGEZ
2
1
1
1
1
0
1
0
0
1
Branch if accumulator ≥ 0
D
D
BGZ
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
1
1
1
0
0
1
1
1
Branch if accumulator > 0
BIOZ
BLEZ
Branch on I/O status = 0
D
D
D
Branch if accumulator ≤ 0
BLZ
2
1
1
1
1
0
0
1
1
1
Branch if accumulator < 0
Branch on no carry
D
D
BNC
2
2
0
1
1
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
†
BNV
Branch if no overflow
D
BNZ
2
1
1
1
1
0
1
0
1
1
Branch if accumulator ≠ 0
Branch on overflow
D
D
BV
2
2
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
0
1
0
0
0
1
1
1
0
1
1
1
1
0
1
1
1
1
0
0
0
0
0
1
1
0
1
0
BZ
Branch if accumulator = 0
Call subroutine indirect
Call subroutine
CALA
CALL
RET
0
0
1
1
0
0
0
1
1
0
1
0
0
D
Return from subroutine
0
I/O AND DATA MEMORY OPERATIONS
INSTRUCTION BIT CODE
NO.
MNEMONIC
DESCRITPION
WORDS
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
BLKD
Block move from data memory to data memory
Block move from program memory to data memory
Data move in data memory
Format serial port registers
Input data from port
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
0
0
M
M
M
0
D
D
D
†
BLKP
DMOV
FO
0
†
FORT
IN
0
0
1
1
1
D
D
M
M
0
PA
PA
OUT
RFSM
RTXM
Output data to port
Reset serial port frame synchronization mode
Reset serial port transmit mode
Reset external flag
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
1
1
0
1
0
0
1
0
0
0
0
1
0
0
1
1
0
1
1
0
1
1
0
0
1
0
0
0
0
0
1
1
1
†
0
†
RXF
0
SFSM
STXM
Set serial port frame synchronization mode
Set serial port transmit mode
Set external flag
0
†
0
†
SXF
0
TBLR
TBLW
Table read
M
M
D
D
Table write
†
These instructions are not included in the SMJ32010 instruction set.
16
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SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
instruction set (continued)
Table 2. Instruction Set Summary (concluded)
CONTROL INSTRUCTIONS
INSTRUCTION BIT CODE
NO.
MNEMONIC
DESCRIPTION
15
1
0
1
1
1
1
0
0
0
1
0
0
1
1
1
1
0
1
1
1
1
1
1
0
0
1
1
1
14
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
13
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
12
1
1
0
0
0
0
1
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
11
10
9
8
7
M
M
0
6
5
4
3
2
1
0
WORDS
†
BIT
Test bit
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D
D
†
D
BITT
Test bit specified by T register
Configure RAM blocks as Data or program
Disable interrupt
0
1
1
1
1
0
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
1
1
1
1
0
0
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
0
‡
CNF
CONF
DINT
EINT
IDLE†
LST
0
0
0
0
1
0
0
0
1
0
0
1
1
1
0
0
1
0
0
0
0
0
1
1
0
1
Enable interrupt
0
Idle until interrupt
0
1
D
Load status register ST0
Load status register ST1
No operation
M
M
0
†
LST1
NOP
POP
D
0
0
0
0
0
1
0
1
0
1
0
0
0
1
Pop top of stack to low accumulator
Pop top of stack to data memory
Push data memory value onto stack
Push low accumulator onto stack
Reset carry bit
0
†
POPD
M
M
0
D
†
PSHD
PUSH
RC
D
1
0
1
0
0
0
0
0
0
1
1
0
1
1
1
0
1
0
0
0
0
0
0
1
0
0
0
0
0
RHM
ROVM
Reset hold mode
0
Reset overflow mode
0
†
RPT
Repeat instruction as specified by data memory value
Repeat instruction as specified by immediate value
Reset sign-extension mode
Reset test/control flag
M
D
†
K
RPTK
†
RSXM
RTC
SC
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
1
0
0
0
0
1
0
1
0
0
0
0
1
1
0
0
1
0
0
1
1
1
Set carry bit
0
SHM
Set hold mode
0
SOVM
SST
Set overflow mode
0
Store status register ST0
Store status register ST1
Set sign-extension mode
Set test/control flag
M
M
0
D
D
†
SST1
†
SSXM
STC
0
0
0
0
1
0
0
1
1
0
0
1
1
0
1
1
1
1
1
1
0
0
†
TRAP
Software interrupt
0
†
‡
These instructions are not included in the SMJ32010 instruction set.
This instruction replaces CNFD and CNFP in the SMJ320C25 instruction set.
17
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SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
development support
Together, Texas Instruments and its authorized third-party suppliers offer an extensive line of development
support products to assist the user in all aspects of TMS320 second-generation-based design and
development. These products range from development and application software to complete hardware
development and evaluation systems. Table 3 lists the development support products for the second-generation
TMS320 devices.
System development may begin with the use of the simulator, Software Development System (SWDS), or
emulator (XDS) along with an assembler/linker. These tools give the TMS320 user various means of evaluation,
from software simulation of the second-generation TMS320s (simulator) to full-speed in-circuit emulation with
hardware and software breakpoint trace and timing capabilities (XDS).
Software and hardware can be developed simultaneously by using the macro assembler/linker, C compiler, and
simulator for software development, the XDS for hardware development, and the Software Development
System for both software development and limited hardware development.
Many third-party vendors offer additional development support for the second-generation TMS320s, including
assembler/linkers, simulators, high-level languages, applications software, algorithm development tools,
applications boards, software development boards, and in-circuit emulators. Refer to the TMS320 Family
Development Support Reference Guide (SPRU011A) for further information about TMS320 development
support products offered by both Texas Instruments and its third-party suppliers.
Additional support for the TMS320 products consists of an extensive library of product and applications
documentation. Three-day DSP design workshops are offered by the TI Regional Technology Centers (RTCs).
These workshops provide insight into the architecture and the instruction set of the second-generation
TMS320s as well as hands-on training with the TMS320 development tools. When technical questions arise
regarding the TMS320 family, contact the Texas Instruments TMS320 Hotline at (713) 274–2320. Or, keep
informed on the latest TI and third-party development support tools by accessing the DSP Bulletin Board Service
(BBS) at (713) 274–2323. The BBS serves 2400-, 1200-, and 300-bps modems. Also, TMS320 application
source code may be downloaded from the BBS.
Table 3 gives a complete list of SMJ320C26 software and hardware development tools.
18
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SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
development support (continued)
Table 3. Software and Hardware Support
MACRO ASSEMBLER/LINKER
HOST COMPUTER
DEC VAX
IBM PC
OPERATING SYSTEMS
PART NUMBER
TMDS3242250-08
TMDS3242850-02
TMDS3242260-08
TMDS3242550-08
VMS
MS/PS DOS
VAX
ULTRIX
SUN 3
UNIX
C COMPILER AND MACRO ASSEMBLER/LINKER
HOST COMPUTER
DEC VAX
IBM PC
OPERATING SYSTEMS
PART NUMBER
TMDS3242255-08
TMDS3242855-02
TMDS3242265-08
TMDS3242555-08
VMS
MS/PC DOS
VAX
ULTRIX
SUN 3
UNIX
SIMULATOR
HOST COMPUTER
DEC VAX
OPERATING SYSTEMS
VMS
PART NUMBER
TMDS3242251-08
TMDS3242851-02
IBM PC
MS/PC DOS
EMULATOR
MODEL
POWER SUPPLY
INCLUDED
PART NUMBER
XDS/22
TMDS3262292
SOFTWARE DEVELOPMENT SYSTEM ON PC
OPERATING SYSTEMS
MS/PC DOS
HOST COMPUTER
IBM PC
PART NUMBER
TMDX3268828
†
TMDX3268821
IBM PC
MS/PC DOS
†
Includes assembler/linker
19
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SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
†
absolute maximum ratings over specified temperature range (unless otherwise noted)
‡
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
CC
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 W
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
†
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the “recommended operating conditions” section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to V
.
SS
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either V
or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for
Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
CC
recommended operating conditions
MIN NOM
MAX
UNIT
V
V
V
Supply voltage
Supply voltage
4.5
5
0
5.5
CC
V
SS
D15–D0, FSX
2.2
3.50
3.00
CLKIN, CLKR, CLKX
All others
V
High-level input voltage
Low-level input voltage
V
IH
D15–D0, FSX, CLKIN, CLKR, CLKX
All others
0.8
0.7
300
2
V
IL
µA
I
I
High-level output current
µA
mA
°C
OH
Low-level output current
OL
T
A
Minimum operating free-air temperature
Maximum operating case temperature
–55
T
C
125
°C
electrical characteristics over specified free-air temperature range (unless otherwise noted)
§
PARAMETER
High-level output voltage
Low-level output voltage
High-impedance-state output leakage current
Input current
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
V
V
V
= MIN, I
= MIN, I
= MAX
= MAX
= MAX
2.4
3
OH
CC
CC
CC
OH
0.3
0.6
± 20
± 10
185
100
V
OL
OL
I
I
µA
µA
OZ
V = V
I SS
to V
CC
I
Normal
I
Supply current
V
= MAX, f = MAX
mA
CC
CC
x
Idle/HOLD
C
C
Input capacitance
Output capacitance
15
15
pF
pF
I
O
§ All typical values are at V
= 5 V, T = 25°C.
A
CC
20
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SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
CLOCK CHARACTERISTICS AND TIMING
The SMJ320C26 can use either its internal oscillator or an external frequency source for a clock.
internal clock option
The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 2). The frequency
of CLKOUT1 is one-fourth the crystal fundamental frequency. The crystal should be either fundamental or
overtone mode, and parallel resonant, with an effective series resistance of 30 Ω, a power dissipation of
1 mW, and be specified at a load capacitance of 20 pF. Note that overtone crystals require an additional tuned
LC circuit (see the application report, Hardware Interfacing to the TMS320C25).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
pF
†
f
x
Input clock frequency
T
= –55°C MIN
= 125°C MAX
6.7
40.0
A
C1, C2
T
C
10
†
This parameter is not production tested.
X1
X2/CLKIN
CRYSTAL
C1
C2
Figure 1. Internal Clock Option
external clock option
An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left
unconnected. The external frequency injected must conform to the specifications listed in the table below.
switching characteristics over recommended operating conditions (see Note 1)
†
PARAMETER
MIN TYP
MAX
600
32
5
UNIT
ns
t
t
t
t
t
t
t
CLKOUT1/CLKOUT2 cycle time
100
5
c(C)
CLKIN high to CLKOUT1/CLKOUT2/STRB high/low
CLKOUT1/CLKOUT2/STRB fall time
ns
d(CIH-C)
f(C)
ns
CLKOUT1/CLKOUT2/STRB rise time
5
ns
r(C)
CLKOUT1/CLKOUT2 low pulse duration
2Q–8
2Q–8
Q–6
2Q 2Q+8
2Q 2Q+8
ns
w(CL)
w(CH)
d(C1-C2)
CLKOUT1/CLKOUT2 high pulse duration
ns
CLKOUT1 high to CLKOUT2 low, CLKOUT2 high to CLKOUT1 high, etc.
Q
Q+6
ns
†
This parameter is not production tested.
NOTE 1: Q = 1/4t
c(C)
21
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ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢄ ꢇ
ꢈ ꢉꢊ ꢉꢋꢌ ꢍ ꢀꢉ ꢊꢎ ꢌ ꢍ ꢏ ꢐꢑ ꢆꢒ ꢀꢀ ꢑꢐ
SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
timing requirements over recommended operating conditions (see Note 1)
MIN
25
10
10
5
MAX
150
15
UNIT
ns
t
t
t
t
t
CLKIN cycle time
c(CI)
CLKIN low pulse duration, t
= 25 ns (see Note 2)
ns
w(CIL)
w(CIH)
su(S)
h(S)
c(C)
CLKIN high pulse duration, t
c(CI)
= 25 ns (see Note 2)
15
ns
SYNC setup time before CLKIN low
SYNC hold time from CLKIN low
Q–5
ns
8
ns
NOTES: 1. Q = 1/4t
c(C)
2. CLKIN duty cycle [t
+ t
]/t
must be within 40-60%. CLKIN rise and fall times must be less than 5 ns.
r(CI) w(CIH) c(CI)
I
/I
OH OL
From Output
Under Test
Test
Point
C
= 80 pF
L
Figure 2. Test Load Circuit
V
V
(MIN)
IH
90%
10%
(MAX)
IL
0
(a) Input
2.4 V
V
V
(MIN)
OH
2.2 V
0
0.8 V
0.6 V
(MAX)
OL
(b) Outputs
Figure 3. Voltage Reference Levels
22
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SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
MEMORY AND PERIPHERAL INTERFACE TIMING
switching characteristics over recommended operating conditions (see Note 1)
PARAMETER
STRB from CLKOUT1 (if STRB is present)
MIN
Q–6
–6
TYP
Q
MAX
Q+6
6
UNIT
ns
t
t
t
t
t
t
t
t
t
t
t
d(C1-S)
d(C2-S)
su(A)
CLKOUT2 to STRB (if STRB is present)
0
ns
Address setup time before STRB low (see Note 3)
Address hold time after STRB high (see Note 3)
STRB low pulse duration (no wait states, see Note 4)
STRB high pulse duration (between consecutive cycles, see Note 4)
Data write setup time before STRB high (no wait states)
Data write hold time from STRB high
Q–12
Q–8
2Q–5
ns
ns
h(A)
2Q
2Q
2Q+5
ns
w(SL)
w(SH)
su(D)W
h(D)W
en(D)
ns
2Q–20
Q–10
ns
Q
ns
†
0
Data bus starts being driven after STRB low (write cycle)
Data bus three-state after STRB high (write cycle)
MSC valid from CLKOUT1
ns
†
Q
0
Q+15
ns
dis(D)
d(MSC)
†
– 10
10
ns
†
This parameter is not production tested.
timing requirements over recommended operating conditions (see Note 1)
MIN
MAX
UNIT
ns
t
t
t
t
t
t
t
t
t
Read data access time from address time (read cycle) (see Notes 3 and 5)
Data read setup time before STRB high
Data read hold time from STRB high
3Q–40
a(A)
23
0
ns
su(D)R
h(D)R
ns
READY valid after STRB low (no wait states)
READY valid after CLKOUT2 high
Q–22
ns
d(SL-R)
d(C2H-R)
h(SL-R)
h(C2H-R)
d(M-R)
h(M-R)
†
Q – 22
ns
READY hold time after STRB low (no wait states)
READY hold after CLKOUT2 high
Q+3
ns
†
Q + 3
ns
†
READY valid after MSC valid
2Q –25
ns
†
0
READY hold time after MSC valid
ns
†
This parameter is not production tested.
RS, INT, BIO, AND XF TIMING
switching characteristics over recommended operating conditions (see Note 1)
PARAMETER
CLKOUT1 low to reset state entered
MIN
TYP
MAX
UNIT
ns
†
22
t
t
t
d(RS)
†
– 8
CLKOUT1 to IACK valid
0
8
ns
d(IACK)
d(XF)
XF valid before falling edge of STRB
Q–12
ns
23
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SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
timing requirements over recommended operating conditions (see Note 1)
MIN
32
0
MAX
UNIT
ns
t
t
t
t
INT/BIO/RS setup before CLKOUT1 high (see Note 6)
INT/BIO/RS hold after CLKOUT1 high (see Note 6)
NT/BIO low pulse duration
su(IN)
ns
h(IN)
t
ns
w(IN)
w(RS)
c(C)
RS low pulse duration
3t
ns
c(C)
NOTES: 1. Q = 1/4t
c(C)
3. A15–A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as “address.”
4. Delays between CLKOUT1/CLKOUT2 edges and STRB edges track each other, resulting in t
states.
and t
being 2Q with no wait
w(SL)
w(SH)
5. Read data access time is defined as t .
= t
+ t
– t
a(A) su(A) w(SL) su(D)R
6. RS, INT, and BIO are asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is
met, the exact sequence shown in the timing diagram will occur. INT/BIO fall time must be less than 8 ns.
24
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SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
HOLD TIMING
switching characteristics over recommended operating conditions (see Note 1)
PARAMETER
HOLDA low after CLKOUT1 low
MIN
TYP
MAX
UNIT
ns
†
–1
t
t
t
t
t
10
d(C1L-AL)
dis(AL-A)
dis(C1L-A)
d(HH-AH)
en(A-C1L)
HOLDA low to address three-state
0
ns
†
20
Address three-state after CLKOUT1 low (HOLD mode) (see Note 7)
HOLD high to HOLDA high
ns
25
ns
†
8
Address driven before CLKOUT1 low (HOLD mode) (see Note 7)
ns
†
This parameter is not production tested.
timing requirements over recommended operating conditions (see Note 1)
MIN
MAX
UNIT
t
HOLD valid after CLKOUT2 high
Q–24
ns
d(C2H-H)
NOTES: 1. Q = 1/4t
c(C)
7. A15–A0, PS, DS, IS, STRB, and R/W timings are all included in timings referenced as “address.”
25
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SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
SERIAL PORT TIMING
switching characteristics over recommended operating conditions (see Note 1)
PARAMETER
MIN
MAX
80
UNIT
ns
t
t
t
DX valid after CLKX rising edge (see Note 8)
DX valid after FSX falling edge (TXM = 0) (see Note 8)
FSX valid after CLKX rising edge (TXM = 1)
d(CH-DX)
d(FL-DX)
d(CH-FS)
45
ns
45
ns
timing requirements over recommended operating conditions (see Note 1)
MIN
MAX
5,000
UNIT
kHz
ns
f
t
t
t
t
t
t
t
Serial port frequency
1.25
200
80
sx
Serial port clock (CLKX/CLKR) cycle time
800,000
c(SCK)
w(SCK)
w(SCK)
su(FS)
h(FS)
Serial port clock (CLKX/CLKR) low pulse duration (see Note 9)
Serial port clock (CLKX/CLKR) high pulse duration (see Note 9)
FSX/FSR setup time before CLKX/CLKR falling edge (TXM = 0)
FSX/FSR hold time after CLKX/CLKR falling edge (TXM = 0)
DR setup time before CLKR falling edge
ns
80
ns
18
ns
20
ns
10
ns
su(DR)
h(DR)
DR hold time after CLKR falling edge
20
ns
NOTES: 1. Q = 1/4t
c(C)
8. The last occurrence of FSX falling and CLKX rising.
9. The duty cycle of the serial port clock must be within 40–60%. Serial port clock (CLKX/CLKR) rise and fall times must be less than
25 ns.
26
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ꢈꢉ ꢊꢉ ꢋꢌꢍ ꢀꢉ ꢊ ꢎꢌꢍ ꢏꢐ ꢑ ꢆꢒ ꢀ ꢀꢑ ꢐ
SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
PARAMETER MEASUREMENT INFORMATION
Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.2 volts unless
otherwise noted.
t
c(CI)
t
f(CI)
t
r(CI)
X/2CLKIN
SYNC
t
t
w(CIL)
h(S)
su(S)
t
su(S)
t
t
w(CIH)
t
c(C)
t
d(CIH-C)
t
d(CIH-C)
t
w(CL)
CLKOUT1
t
t
w(CH)
d(CIH-C)
t
t
f(C)
r(C)
STRB
t
c(C)
t
t
w(CL)
d(CIH-C)
CLKOUT2
t
t
d(C1-C2)
t
d(C1-C2)
w(CH)
d(C1-C2)
t
t
t
t
r(C)
d(C1-C2)
f(C)
Figure 4. Clock Timing
27
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SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
PARAMETER MEASUREMENT INFORMATION
t
d(C1-S)
CLKOUT1
CLKOUT2
STRB
t
d(C1-S)
t
t
d(C2-S)
d(C2-S)
t
w(SH)
t
w(SL)
t
t
su(A)
h(A)
A15–A0,
BR, PS, DS,
OR IS
VALID
t
a(A)
R/W
READY
D15–D0
t
su(D)R
t
d(SL-R)
t
t
h(D)R
h(SL-R)
DATA IN
Figure 5. Memory Read Timing
28
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SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
PARAMETER MEASUREMENT INFORMATION
CLKOUT1
CLKOUT2
STRB
t
t
h(A)
su(A)
A15–A0,
BR, PS, DS,
OR IS
VALID
R/W
READY
D15–D0
t
h(D)W
t
su(D)W
DATA OUT
t
t
dis(D)
en(D)
Figure 6. Memory Write Timing
29
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SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
PARAMETER MEASUREMENT INFORMATION
CLKOUT1
CLKOUT2
STRB
A15–A0, BR
PS, DS, R/W,
OR IS
VALID
t
t
h(C2H-R)
h(C2H-R)
t
d(C2H-R)
t
d(C2H-R)
READY
t
h(M-R)
t
d(M-R)
t
d(M-R)
D15–D0,
(FOR READ
OPERATION)
t
h(M-R)
DATA IN
D15–D0,
(FOR WRITE
OPERATION)
MSC
t
t
d(MSC)
d(MSC)
Figure 7. One Wait-State Memory Access Timing
30
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SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
PARAMETER MEASUREMENT INFORMATION
CLKOUT1
RS
t
t
su(IN)
h(IN)
t
su(IN)
d(RS)
t
t
w(RS)
A15–A0
FETCH
LOCATION 0
D15–D0
VALID
PS
BEGIN
PROGRAM
EXECUTION
STRB
CONTROL
†
SIGNALS
IACK
SERIAL PORT
‡
CONTROLS
†
‡
Control signals are DS, IS, R/W, and XF.
Serial port controls are DX and FSX.
Figure 8. Reset Timing
CLKOUT1
STRB
t
t
h(IN)
su(IN)
t
w(N)
INT2–INT0
t
f(IN)
A15–A0
FETCH N
FETCH N + 1
FETCH N + 2
d(IACK)
FETCH 1
t
t
d(IACK)
IACK
Figure 9. Interrupt Timing
31
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SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
PARAMETER MEASUREMENT INFORMATION
CLKOUT1
STRB
FETCH BRANCH
ADDRESS
FETCH NEXT
INSTRUCTION
FETCH BIOZ
A15–A0
PC = N
PC = N + 1
PC = N + 2
PC = N + 3
OR BRANCH ADDRESS
t
h(IN)
t
su(IN)
BIO
VALID
Figure 10. BIO Timing
CLKOUT1
STRB
t
d(XF)
FETCH
SXF/RXF
A15–A0
VALID
VALID
VALID
PC = N
PC = N + 1
PC = N + 2
PC = N + 3
XF
VALID
Figure 11. External Flag Timing
32
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SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
PARAMETER MEASUREMENT INFORMATION
CLKOUT1
CLKOUT2
STRB
t
(see note A)
d(C2H-H)
HOLD
A15–A0
N
N + 1
N + 2
PS, DS,
OR IS
VALID
VALID
R/W
D15–D0
HOLDA
t
dis(C1L-A)
IN
IN
t
t
dis(AL-A)
d(C1L-AL)
N
N + 1
–
–
–
FETCH
N – 2
N – 1
N
EXECUTE
NOTE A: HOLD is an asynchronous input that can occur at any time during a clock cycle. If the specified timing is met, the exact sequence shown
will occur; otherwise, a delay of one CLKOUT2 cycle will occur.
Figure 12. HOLD Timing (Part A)
33
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SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
PARAMETER MEASUREMENT INFORMATION
CLKOUT1
CLKOUT2
STRB
t
en(A-C1L)
t
(see note A)
d(C2H-H)
HOLD
PS, DS,
OR IS
VALID
R/W
D15–D0
HOLDA
IN
t
d(HH-AH)
A15–A0
FETCH
N + 2
N + 2
N + 2
–
–
–
–
–
–
N + 1
EXECUTE
NOTE A: HOLD is an asynchronous input that can occur at any time during a clock cycle. If the specified timing is met, the exact sequence shown
will occur; otherwise, a delay of one CLKOUT2 cycle will occur.
Figure 13. HOLD Timing (Part B)
34
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SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
PARAMETER MEASUREMENT INFORMATION
t
c(SCK)
t
w(SCK)
r(SCK)
t
CLKR
FSR
DR
t
h(FS)
t
f(SCK)
t
h(DR)
t
w(SCK)
t
su(FS)
t
su(DR)
N = 8, 16
Figure 14. Serial Port Receive Timing
t
c(SCK)
t
r(SCK)
t
w(SCK)
CLKX
FSX
t
w(SCK)
f(SCK)
d(CH-DX)
t
h(FS)
t
t
(INPUT, TXM = 0)
t
d(FL-DX)
t
d(CH-DX)
t
su(FS)
t
su(FS)
DX
N = 1
N = 8, 16
t
d(CH-FS)
t
d(CH-FS)
FSX
(OUTPUT, TXM = 1)
Figure 15. Serial Port Transmit Timing
35
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PACKAGE OPTION ADDENDUM
www.ti.com
13-Jun-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
5962-8861903XA
5962-8861903YA
SM320C26BFJM
SM320C26BGBM
SMJ320C26BFDM
SMJ320C26BGBM
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
CPGA
LCCC
JLCC
CPGA
LCCC
CPGA
GB
FD
FJ
68
68
68
68
68
68
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
N / A for Pkg Type
Call TI
GB
FD
GB
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SMJ320C26B :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
13-Jun-2012
Catalog: TMS320C26B
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
MECHANICAL DATA
MCPG023A – OCTOBER 1997 – REVISED DECEMBER 2001
GB (S-CPGA-P68)
CERAMIC PIN GRID ARRAY
0.970 (24,63)
0.950 (24,13)
0.536 (13,61)
0.524 (13,31)
0.800 (20,32) TYP
J
H
G
F
E
D
C
B
A
A1 Corner
1
2
3
4
5
6
7
8
9
Bottom View
0.088 (2,23)
0.072 (1,83)
0.100 (2,54)
0.194 (4,98)
0.166 (4,16)
0.055 (1,39)
0.045 (1,14)
0.050 (1,27) DIA
4 Places
0.018 (0,46) DIA TYP
4040114-14/D 11/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Index mark may appear on top or bottom depending vendor.
D. Pins are located within 0.010 (0,25) diameter of true position relative to each other at maximum material condition and within
0.030 (0,76) diameter relative to the edges of the ceramic.
E. This package can be hermetically sealed with metal lids or with ceramic lids using glass frit.
F. The pins can be gold plated or solder dipped.
G. Falls within MIL STD 1835 CMGA1-PN, CMGA13-PN and JEDEC MO-067 AA, MO-066 AA respectively
1
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