S4MF04207SPZQQ1_技术文档

TMS470MF04207

TMS470MF03107

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SPNS159C –JANUARY 2012

TMS470MF04207/TMS470MF03107 16/32-Bit RISC Flash

Microcontroller

Check for Samples: TMS470MF04207, TMS470MF03107

1 Features

1

• High-Performance Automotive Grade

• Two External Clock Prescale (ECP) Modules

Microcontroller with Safety Features

– Programmable Low-Frequency External

– Full Automotive Temperature Range

– ECC on Flash and SRAM

– CPU and Memory BIST (Built-In Self Test)

• ARM Cortex™-M3 32-Bit RISC CPU

– Efficient 1.2 DMIPS/MHz

Clock (ECLK)

– One Dedicated Pin and One Muxed

ECLK/HET pin

• Communication Interfaces

– Two CAN Controllers

•

One with 32 mailboxes, one with 16

Parity on mailbox RAM

– Optimized Thumb2 Instruction Set

– Memory Protection Unit (MPU)

– Open Architecture With Third-Party Support

– Built-In Debug Module

– Two Multi-buffered Serial Peripheral

Interface (MibSPI)

•

12 total chip selects

64 buffers with parity on each

• Operating Features

– Up to 80MHz System Clock

– Single 3.3V Supply Voltage

• Integrated Memory

– Two UART (SCI) interfaces

•

H/W Support for Local Interconnect

Network (LIN 2.1 master mode)

– 448KB Total Program Flash with ECC

– Support for Flash EEPROM Emulation

– 24K-Byte Static RAM (SRAM) with ECC

• Key Peripherals

– High-End Timer, MibADC, CAN, MibSPI

• Common TMS470M/570 Platform Architecture

– Consistent Memory Map across the family

– Real-Time Interrupt Timer (RTI)

– Digital Watchdog

– Vectored Interrupt Module (VIM)

– Cyclic Redundancy Checker (CRC)

• Frequency-Modulated Zero-Pin Phase-Locked

Loop (FMzPLL)-Based Clock Module

– Oscillator and PLL clock monitor

• Up to 49 Peripheral IO pins

• High-End Timer (HET)

– Up to 16 Programmable I/O Channels

– 128-Word High-End Timer RAM with Parity

• 16-Channel 10-Bit Multi-Buffered ADC

(MibADC)

– 64-Word FIFO Buffer with Parity

– Single- or Continuous-Conversion Modes

– 1.55 µs Minimum Sample/Conversion Time

– Calibration Mode and Self-Test Features

• On-Chip Scan-Base Emulation Logic

– IEEE Standard 1149.1 (JTAG) Test-Access

Port and Boundary Scan

• Packages supported

– 100-Pin Plastic Quad Flatpack (PZ Suffix)

– Green/Lead-Free

• Development Tools Available

– Development Boards

– 4 Dedicated GIO - w/ External Interrupts

– Code Composer Studio™ Integrated

Development Environment (IDE)

– HET Assembler and Simulator

– nowFlash™ Flash Programming Tool

• Community Resources

– TI E2E Community

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to

specifications per the terms of the Texas Instruments standard warranty. Production

processing does not necessarily include testing of all parameters.

TMS470MF04207

TMS470MF03107

SPNS159C –JANUARY 2012

www.ti.com

1.1 PZ Package Views

ADIN[7]

ADIN[8]

ADIN[9]

ADIN[10]

ADIN[11]

ADIN[12]

AD_REFHI

AD_REFLO

V_SSAD

76

77

78

79

80

81

82

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

HET[3]

HET[2]

TRST

TMS

TDI

TDO

TCK

83

84

85

86

V_CCIOR

V_SS

V_CC

V_CCAD

HET[1]

ADIN[13]

ADIN[14]

ADIN[15]

PORRST

MIBSPI2ENA

ENZ

87

88

89

90

91

92

93

94

95

96

97

98

99

100

HET[0]

CAN2SRX

CAN2STX

MIBSPI1SOMI

MIBSPI1SIMO

MIBSPI1CLK

MIBSPI1SCS[0]

MIBSPI1SCS[1]

MIBSPI1SCS[2]

MIBSPI1SCS[3]

MIBSPI1SCS[4]

MIBSPI1SCS[5]

MIBSPI1SCS[6]

MIBSPI1SCS[7]

V_CC

V_SS

V_CCIOR

V_CCP

ECLK

TEST

RST

FLTP1

V_SS

Figure 1-1. TMS470MF04207 and TMS470MF03107 100-Pin PZ Package (Top View)

2

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1.2 Description

The TMS470MF04207/03107 devices are members of the Texas Instruments TMS470M family of

Automotive Grade 16/32-bit reduced instruction set computer (RISC) microcontrollers. The TMS470M

microcontrollers offer high performance utilizing the high efficiency Cortex™-M3 16/32-bit RISC central

processing unit (CPU), resulting in a high instruction throughput while maintaining greater code efficiency.

The TMS470M devices utilize the big-endian format where the most-significant byte of a word is stored at

the lowest numbered byte and the least-significant byte is stored at the highest numbered byte.

High-end embedded control applications demand more performance from their controllers while

maintaining low costs. The TMS470M microcontroller architecture offers solutions to these performance

and cost demands while maintaining low power consumption.

The TMS470MF04207/03107 device contains the following:

•

16/32-Bit RISC CPU Core

TMS470MF04207 Up to 448K-Byte Program Flash with SECDED ECC

TMS470MF03107 Up to 320K-Byte Program Flash with SECDED ECC

64K-Byte Flash with SECDED ECC for additional program space or EEPROM Emulation

Up to 24K-Byte Static RAM (SRAM) with SECDED ECC

Real-Time Interrupt Timer (RTI)

Vectored Interrupt Module (VIM)

Hardware built-in self-test (BIST) checkers for SRAM (MBIST) and CPU (LBIST)

64-bit Cyclic Redundancy Checker (CRC)

Frequency-Modulated Zero-Pin Phase-Locked Loop (FMzPLL)-Based Clock Module With Prescaler

Two Multi-buffered Serial Peripheral Interfaces (MibSPI)

Two UARTs (SCI) with Local Interconnect Network Interfaces (LIN)

Two CAN Controller (DCAN)

High-End Timer (HET)

External Clock Prescale (ECP) Module

One 16-Channel 10-Bit Multi-Buffered ADC (MibADC)

Error Signaling Module (ESM)

Four Dedicated General-Purpose I/O (GIO) Pins and 45 Additional Peripheral I/Os (100-Pin Package)

The TMS470M memory includes general-purpose SRAM supporting single-cycle read/write accesses in

byte, half-word, and word modes. The SRAM on the TMS470M devices can be protected by means of

ECC. This feature utilizes a single error correction and double error detection circuit (SECDED circuit) to

detect and optionally correct single bit errors as well as detect all dual bit and some multi-bit errors. This is

achieved by maintaining an 8-bit ECC checksum/code for each 64-bit double-word of memory space in a

separate ECC RAM memory space.

The flash memory on this device is a nonvolatile, electrically erasable and programmable memory. It is

implemented with a 144-bit wide data word (128-bit without ECC) and a 64-bit wide flash module interface.

The flash operates with a system clock frequency of up to 28 MHz. Pipeline mode, which allows linear

prefetching of flash data, enables a system clock of up to 80 MHz.

The enhanced real-time interrupt (RTI) module on the TMS470M devices has the option to be driven by

the oscillator clock. The digital watchdog (DWD) is a 25-bit resetable decrementing counter that provides a

system reset when the watchdog counter expires.

The TMS470M devices have six communication interfaces: two LIN/SCIs, two DCANs, and two MibSPIs.

The LIN is the Local Interconnect Network standard and also supports an SCI mode. SCI can be used in a

full-duplex, serial I/O interface intended for asynchronous communication between the CPU and other

peripherals using the standard non-return-to-zero (NRZ) format. The DCAN uses a serial, multimaster

communication protocol that efficiently supports distributed real-time control with robust communication

Features

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rates of up to 1 megabit per second (Mbps). The DCAN is ideal for applications operating in noisy and

harsh environments (e.g., automotive and industrial fields) that require reliable serial communication or

multiplexed wiring. The MibSPI provides a convenient method of serial interaction for high-speed

communications between similar shift-register type devices. The MibSPI provides the standard SOMI,

SIMO, and SPI clock interface as well as up to eight chip select lines.

The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time

applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer

micromachine and an attached I/O port. The HET can be used for compare, capture, or general-purpose

I/O. It is especially well suited for applications requiring multiple sensor information and drive actuators

with complex and accurate time pulses. The TMS470M HET peripheral contains the XOR-share feature.

This feature allows two adjacent HET high- resolution channels to be XORed together, making it possible

to output smaller pulses than a standard HET.

The TMS470M devices have one 10-bit-resolution, sample-and-hold MibADC. Each of the MibADC

channels can be grouped by software for sequential conversion sequences. There are three separate

groupings, all three of which can be triggered by an external event. Each sequence can be converted

once when triggered or configured for continuous conversion mode.

The frequency-modulated zero-pin phase-locked loop (FMzPLL) clock module contains a phase-locked

loop, a clock-monitor circuit, a clock-enable circuit, and a prescaler. The function of the FMzPLL is to

multiply the external frequency reference to a higher frequency for internal use. The FMzPLL provides the

input to the global clock module (GCM). The GCM module subsequently provides system clock (HCLK),

real-time interrupt clock (RTICLK), CPU clock (GCLK), HET clock (VCLK2), DCAN clock (AVCLK1), and

peripheral interface clock (VCLK) to all other TMS470M device modules.

The TMS470MF04207/TMS470MF03107 devices also have two external clock prescaler (ECP) modules

that when enabled, output a continuous external clock (ECLK). The ECLK1 frequency is a

user-programmable ratio of the peripheral interface clock (VCLK) frequency. The second ECLK output can

be selected in place of HET15 output. It shares the same source clock as ECLK1 but can be

independently programmed for a separate output frequency from ECLK1.

An error signaling module (ESM) provides a common location within the device for error reporting allowing

efficient error checking and identification.

4

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1.3 Functional Block Diagram

Figure 1-2 shows the functional block diagram of the TMS470M devices.

TMS

TCK

TRST

TDI

TMS470MF04207/

TMS470MF03107

JTAG-DP

ICEPICK

LBIST

TDO

Cortex™

Boundary

M3

Scan

with MPU

HET

128 Words

w/Parity

M3VIM

I

D

SYS

HET[15:0]

ESM

RST

PORRST

TEST

ECLK

SYS

BMM

LIN/SCI1TX

LIN/SCI1RX

LIN/SCI2TX

LIN/SCI2RX

LIN/SCI1

LIN/SCI2

A2V

Flash

Up to 384KB

w/ECC

RAM

Up to 24KB

w/ECC

V_CCP

PSA

MIBSPI1SIMO

MIBSPI1SOMI

MIBSPI1CLK

MibSPI1

64 Words/

16TGs w/Parity

FLTP1

MIBSPI1SCS[7:0]

MBIST

Flash

64KB

w/ECC

MIBSPI2SIMO

MIBSPIP2SOMI

MIBSPI2CLK

MIBSPI2SCS[3:0]

MIBSPI2ENA

MibSPI2

64 Words/

8TGs w/Parity

PCR

RAM

OSC

PLL

CLK

ADIN[15:0]

ADEVT

V_CCAD

OSCIN1

ADC

64 Words

w/Parity

Flash

Wrapper

RTI/

DWD

OSCOUT1

Monitor

V_SSAD

AD_REFHI

AD_REFLO

Wrapper

DCAN1

16 Mailboxes

w/Parity

1.5-V

P-Ch

VREG

CANS1RX

CANS1TX

V_CCIOR

ENZ

DCAN2

32 Mailboxes

w/Parity

V_CCOUT

CANS2RX

CANS2TX

V_CC

Passgate1

Passgate2

Passgate3

Passgate4

GIO

GIOOA[7:4]/INTA[7:4]

Figure 1-2. TMS470M Functional Block Diagram

Features

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1.4 Terms and Acronyms

Table 1-1. Terms and Acronyms

Terms and Acronyms

Description

Comments

A2V

AHB to VBUSP Bridge

The A2V bridge provides the memory interface between the

proprietary TI VBUSP and the ARM AHB bus in the TMS470

platform devices.

ADC

AHB

BMM

Analog To Digital Converter

Advanced High-performance Bus

Bus Matrix Master

Part of the M3 core

The BMM provides connectivity between different bus slave

modules to different bus master modules. Accesses from

different master modules are executed in parallel if no resource

conflict occurs or if the master modules are kept in series

through arbitration

CRC

DAP

Cyclic Redundancy Check Controller

Debug Access Port

DAP is an implementation of an ARM Debug Interface.

DCAN

DWD

ECC

Controller Area Network

Digital Watchdog

Error Correction Code

Error Signaling Module

General-Purpose Input/Output

High-End Timer

ESM

GIO

HET

ICEPICK

In Circuit Emulation TAP (Test Access Port)

Selection Module

ICEPick can connect or isolate a module level TAP to or from a

higher level chip TAP. ICEPick was designed with both

emulation and test requirements in mind.

JTAG

Joint Test Access Group

JTAG Debug Port

IEEE Committee responsible for Test Access Ports

JTAG-DP

JTAG-DP contains a debug port state machine (JTAG) that

controls the JTAG-DP operation, including controlling the scan

chain interface that provides the external physical interface to

the JTAG-DP. It is based closely on the JTAG TAP State

Machine, see IEEE Std 1149.1-2001.

LBIST

LIN

Logic Built-In Self Test

Local Interconnect Network

Cortex-M3 Vectored Interrupt Manager

Memory Built-In Self Test

Multi-Buffered Serial Peripheral Interface

Protection Unit

Test the integrity of M3 CPU

Test the integrity of SRAM

Part of the M3 core

M3VIM

MBIST

MibSPI

MPU

NVIC

OSC

Nested Vectored Interrupt Controller

Oscillator

PCR

Peripheral Central Resource

Phase-Locked Loop

PLL

PSA

Parallel Signature Analysis

Real-Time Interrupt

RTI

SCI

Serial Communication Interface

SECDED

Single Error Correction and Double Error

Detection

STC

SYS

Self Test Controller

System Module

Virtual Bus

VBUS

One of the protocols that comprises CBA (Common Bus

Architecture)

VBUSP

VREG

Virtual Bus-Pipelined

Voltage Regulator

One of the protocols that comprises CBA (Common Bus

Architecture)

6

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1

Features ................................................... 1

3.12 Device Part Numbers ............................... 33

1.1 PZ Package Views ................................... 2

1.2 Description ........................................... 3

1.3 Functional Block Diagram ............................ 5

1.4 Terms and Acronyms ................................ 6

Device Overview ........................................ 8

2.1 Memory Map Summary .............................. 9

2.2 Terminal Functions ................................. 14

2.3 Device Support ..................................... 18

Device Configurations ................................ 20

3.1 Reset/Abort Sources ............................... 20

3.2 Lockup Reset Module .............................. 21

3.3 ESM Assignments .................................. 21

4

5

Device Operating Conditions ....................... 34

4.1

Absolute Maximum Ratings Over Operating

Free-Air Temperature Range, Q Version ........... 34

4.2

4.3

Device Recommended Operating Conditions ...... 34

Electrical Characteristics Over Recommended

2

3

Operating Free-Air Temperature Range, Q Version

...................................................... 35

Peripheral Information and Electrical

Specifications .......................................... 36

5.1 RST and PORRST Timings ........................ 36

5.2 PLL and Clock Specifications ...................... 39

5.3 SPIn Master Mode Timing Parameters ............. 50

5.4 SPIn Slave Mode Timing Parameters .............. 54

5.5

CAN Controller (DCANn) Mode Timings ........... 58

5.6 High-End Timer (HET) Timings ..................... 58

Multi-Buffered A-to-D Converter (MibADC) ......... 59

3.4 Interrupt Priority (M3VIM) ........................... 22

3.5 MibADC ............................................. 23

3.6 MibSPI .............................................. 24

5.7

6

7

Revision History ....................................... 63

Mechanical Data ....................................... 64

7.1 Thermal Data ....................................... 64

7.2 Packaging Information .............................. 64

3.7 JTAG ID ............................................ 25

3.8 Scan Chains ........................................ 25

3.9 Adaptive Impedance 4 mA IO Buffer ............... 25

3.10 Built-In Self Test (BIST) Features .................. 29

3.11 Device Identification Code Register ................ 32

Contents

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2 Device Overview

The TMS470MF04207/03107 device is a TMS470M Platform Architecture implemented in F035 130-nm TI

technology. Table 2-1 identifies all the characteristics of the TMS470MF04207/03107 device except the

SYSTEM and CPU, which are generic.

Table 2-1. Device Characteristics

DEVICE DESCRIPTION

TMS470MF04207/03107

CHARACTERISTICS

COMMENTS FOR TMS470M

MEMORY

INTERNAL MEMORY

Pipeline/Non-Pipeline

2 Banks with up to 448K-Byte

Flash with ECC

Flash is pipeline-capable

Up to 24K-Byte SRAM with ECC

CRC, 1-channel

PERIPHERALS

For the device-specific interrupt priority configurations, see Table 3-4.

For the peripheral address ranges and their peripheral selects, see Table 2-7.

CLOCK

FMzPLL

4 I/O

Frequency-modulated zero-pin PLL has no external loop filter pins.

GENERAL-PURPOSE I/Os

The GIOA port has up to four (4) external pins with external interrupt

capability.

LIN/SCI

DCAN

2 LIN/SCI

2 DCAN

2 MibSPI

Each with 16/32 mailboxes, respectively.

MibSPI

One MibSPI with eight chip select pins, 16 transfer groups, and a 64

word buffer with parity. A second MibSPI with four chip select pins, 1

enable pin, 8 transfer groups, and a 64 word buffer with parity.

HET with XOR Share

16 I/O

The high-resolution (HR) SHARE feature allows even-numbered HR

pins to share the next higher odd-numbered HR pin structures. This

HR sharing is independent of whether or not the odd pin is available

externally. If an odd pin is available externally and shared, then the

odd pin can only be used as a general-purpose I/O. HET RAM with

parity checking capability.

HET RAM

MibADC

128-Instruction Capacity

10-bit, 16-channel

64-word FIFO

MibADC RAM includes parity support.

CORE VOLTAGE

1.55 V

The core voltage is supplied and regulated by the device's internal

voltage regulator. There is not need for an externally supplied core

voltage.

I/O VOLTAGE

PINS

3.3 V

100

Available in a 100-pin package.

PACKAGE

PZ (100 pin)

The 100-pin package designator is PZ.

8

Device Overview

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2.1 Memory Map Summary

2.1.1 Memory Map

Figure 2-1 and Figure 2-2 show the TMS470MF04207 and TMS470MF03107 memory maps.

0xFFFFFFFF

SYSTEM Module

0xFFF80000

0xFFF7FFFF

Peripherals

0xFF000000

0xFEFFFFFF

PSA

0xFE000000

0x08405FFF

RAM - ECC

0x08400000

0x08105FFF

RAM - CLR Space^(A)(24KB)

0x08100000

RAM - SET Space^(A)(24KB)

0x08085FFF

0x08080000

0x08005FFF

RAM (24KB)

0x08000000

0x0047FFFF

0x00440000

FLASH - ECC (Bank 1)

0x0042FFFF

0x00400000

0x0008FFFF

FLASH - ECC (Bank 0)

FLASH (64KB - Bank 1)

0x00080000

0x0005FFFF

FLASH (384KB - Bank 0)

0x00000000

A. The RAM supports bit access operation which allows set/clear to dedicated bits without disturbing the other bits; for

detailed description, see the Architecture Specification.

Figure 2-1. TMS470MF04207 Memory Map

Device Overview

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0xFFFFFFFF

0xFFF80000

0xFFF7FFFF

SYSTEM Module

Peripherals

0xFF000000

0xFEFFFFFF

0xFE000000

PSA

0x08403FFF

0x08400000

RAM - ECC

0x08103FFF

0x08100000

RAM - CLR Space^(A)(16KB)

RAM - SET Space^(A)(16KB)

RAM (16KB)

0x08083FFF

0x08080000

0x08003FFF

0x08000000

0x00447FFF

0x00440000

0x0041FFFF

0x00400000

FLASH - ECC (Bank 1)

FLASH - ECC (Bank 0)

0x0008FFFF

0x00080000

0x0003FFFF

FLASH (64KB - Bank 1)

FLASH (256KB - Bank 0)

0x00000000

A. The RAM supports bit access operation which allows set/clear to dedicated bits without disturbing the other bits; for

detailed description, see the Architecture Specification.

Figure 2-2. TMS470MF03107 Memory Map

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2.1.2 Memory Selects

Memories in the TMS470M devices are located at fixed addresses. Table 2-2 through Table 2-7 detail the

mapping of the memory regions.

Table 2-2. TMS470MF04207-Specific Memory Frame Assignment

MEMORY FRAME NAME

START ADDRESS

0x0000 0000

0x0008 0000

0x0810 0000

0x0808 0000

0x0800 0000

0x0840 0000

ENDING ADDRESS

0x0005 FFFF

0x0008 FFFF

0x0810 5FFF

0x0808 5FFF

0x0800 5FFF

0x0840 5FFF

MEMORY TYPE

Flash

ACTUAL MEMORY

384K Bytes

64K Bytes

nCS0⁽¹⁾

Flash

RAM-CLR

RAM-SET

Internal RAM

Internal RAM-ECC

24K Bytes

CSRAM0⁽¹⁾

24K Bytes

(1) Additional address mirroring could be present resulting in invalid but addressable locations beyond those listed above. TI recommends

the use of the MPU for protecting access to addresses outside the intended range of use.

Table 2-3. TMS470MF03107-Specific Memory Frame Assignment

MEMORY FRAME NAME

START ADDRESS

0x0000 0000

0x0008 0000

0x0810 0000

0x0808 0000

0x0800 0000

0x0840 0000

ENDING ADDRESS

0x0003 FFFF

0x0008 FFFF

0x0810 3FFF

0x0808 3FFF

0x0800 3FFF

0x0840 3FFF

MEMORY TYPE

Flash

ACTUAL MEMORY

256K Bytes

64K Bytes

nCS0⁽¹⁾

Flash

RAM-CLR

RAM-SET

Internal RAM

Internal RAM-ECC

16K Bytes

CSRAM0⁽¹⁾

16K Bytes

(1) Additional address mirroring could be present resulting in invalid but addressable locations beyond those listed above. TI recommends

the use of the MPU for protecting access to addresses outside the intended range of use.

Table 2-4. Memory Initialization and MBIST

ADDRESS RANGE

BASE ADDRESS

MEMORY INITIALIZATION

CHANNEL

MBIST CONTROLLER

ENABLE CHANNEL

CONNECTING MODULE

ENDING ADDRESS

0x0800 5FFF

0x0800 3FFF

0xFF0F FFFF

0xFF0D FFFF

0xFF1F FFFF

0xFF1D FFFF

0xFF3F FFFF

0xFF47 FFFF

Not Applicable

System RAM (TMS470MF04207)

System RAM (TMS470MF03107)

MibSPI1 RAM

0x0800 0000

0xFF0E 0000

0xFF0C 0000

0xFF1E 0000

0xFF1C 0000

0xFF3E 0000

0xFF46 0000

Not Applicable

0

1

1 or 2⁽¹⁾

3 or 4⁽¹⁾

MibSPI2 RAM

2

DCAN1 RAM

3

DCAN2 RAM

4

ADC RAM

5

6

7

HET RAM

Not Available

Not Applicable

STC ROM

(1) There are single MBIST controllers for both MibSPI RAMs and both DCAN RAMs. The MBIST controller for both MibSPI RAMs is

mapped to channels 1 and 2 and the MBIST controller for both DCAN RAMs is mapped to channels 3 and 4. MBIST on these modules

can be initiated by selecting one of the 2 channels or both.

Table 2-5. Peripheral Memory Chip Select Assignment

ADDRESS RANGE

PERIPHERAL

SELECTS

CONNECTING MODULE

BASE ADDRESS

ENDING ADDRESS

0xFF0F FFFF

MibSPI1 RAM

MibSPI2 RAM

DCAN1 RAM

DCAN2 RAM

0xFF0E 0000

0xFF0C 0000

0xFF1E 0000

0xFF1C 0000

PCS[7]

PCS[6]

0xFF0D FFFF

0xFF1F FFFF

PCS[14]

PCS[15]

0xFF1D FFFF

Device Overview

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Table 2-5. Peripheral Memory Chip Select Assignment (continued)

ADDRESS RANGE

PERIPHERAL

SELECTS

CONNECTING MODULE

BASE ADDRESS

ENDING ADDRESS

0xFF3F FFFF

ADC RAM

HET RAM

0xFF3E 0000

0xFF46 0000

PCS[31]

PCS[35]

0xFF47 FFFF

NOTE

All used peripheral memory chip selects should decode down to the smallest possible

address for this particular peripheral configuration, starting from 4kB upwards. Unused

addresses should generate an illegal address error when accessed.

Table 2-6. System Peripheral Registers

ADDRESS RANGE

FRAME NAME

FRAME START ADDRESS FRAME ENDING ADDRESS

PSA

0xFE00 0000

0xFFF8 7000

0xFFFF E000

0xFFFF E100

0xFFFF E400

0xFFFF F500

0xFFFF F900

0xFFFF FC00

0xFFFF FE00

0xFFFF FF00

0xFEFF FFFF

0xFFF8 7FFF

0xFFFF E0FF

0xFFFF E1FF

0xFFFF E4FF

0xFFFF F5FF

0xFFFF F9FF

0xFFFF FCFF

0xFFFF FEFF

0xFFFF FFFF

Flash Wrapper Registers

PCR Register

System Frame 2 Registers

CPU STC (LBIST)

ESM Register

RAM ECC Register

RTI Register

VIM Register

System Registers

Table 2-7. Peripheral Select Map with Address Range

PERIPHERAL

SELECTS

CONNECTING MODULE

BASE ADDRESS

END ADDRESS

MibSPI2

MibSPI1

LIN/SCI1

LIN/SCI2

DCAN2

DCAN1

ADC

0xFFF7 F600

0xFFF7 F400

0xFFF7 E500

0xFFF7 E400

0xFFF7 DE00

0xFFF7 DC00

0xFFF7 C000

0xFFF7 BC00

0xFFF7 B800

0xFFF7 F7FF

0xFFF7 F5FF

0xFFF7 E5FF

0xFFF7 E4FF

0xFFF7 DFFF

0xFFF7 DDFF

0xFFF7 C1FF

0xFFF7 BCFF

0xFFF7 B8FF

PS[2]

PS[6]

PS[8]

PS[15]

PS[16]

PS[17]

GIO

HET

2.1.3 Flash Memory

When in pipeline mode, the Flash operates with a system clock frequency of up to 80 MHz (versus a

system clock in non-pipeline mode of up to 28 MHz). Flash in pipeline mode is capable of accessing

128-bit words and provides four 32-bit pipelined words to the CPU.

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NOTE

1. After a system reset, pipeline mode is disabled [FRDCNTL[2:0] is 000b, see the Flash

chapter in the TMS470M Series Technical Reference Manual (literature number

SPNU495)]. In other words, the device powers up and comes out of reset in

non-pipeline mode.

2. The flash external pump voltage (V_CCP) is required for all operations (program,

erase, and read).

2.1.4 Flash Program and Erase

The TMS470MF04207/TMS470MF03107 devices flash contain one 384/256K-byte memory array (or

bank) and one 64K-byte bank for a total of up to 12 sectors. Table 2-8 and Table 2-9 show the

TMS470MF04207 and TMS470MF03107 flash memory banks and sectors.

The minimum size for an erase operation is one sector. The maximum size for a program operation is one

32-bit word.

Table 2-8. TMS470MF04207 Flash Memory Banks and Sectors

SECTOR

NO.

MEMORY ARRAYS (OR

BANKS)

SEGMENT

LOW ADDRESS

HIGH ADDRESS

0

1

2

3

4

5

6

7

0

1

2

3

16k

32k

64k

16k

0x0000 0000

0x0000 4000

0x0000 8000

0x0001 0000

0x0002 0000

0x0003 0000

0x0004 0000

0x0005 0000

0x0008 0000

0x0008 4000

0x0008 8000

0x0008 C000

0x0000 3FFF

0x0000 7FFF

0x0000 FFFF

0x0001 FFFF

0x0002 FFFF

0x0003 FFFF

0x0004 FFFF

0x0005 FFFF

0x0008 3FFF

0x0008 7FFF

0x0008 BFFF

0x0008 FFFF

BANK 0

(384K Bytes)

BANK 1⁽¹⁾

(64K Bytes)

(1) Bank 1 can be used as either EEPROM emulation space or as program space.

Table 2-9. TMS470MF03107 Flash Memory Banks and Sectors

SECTOR

NO.

MEMORY ARRAYS (OR

BANKS)

SEGMENT

LOW ADDRESS

HIGH ADDRESS

0

1

2

3

4

5

0

1

2

3

16k

32k

64k

16k

0x0000 0000

0x0000 4000

0x0000 8000

0x0001 0000

0x0002 0000

0x0003 0000

0x0008 0000

0x0008 4000

0x0008 8000

0x0008 C000

0x0000 3FFF

0x0000 7FFF

0x0000 FFFF

0x0001 FFFF

0x0002 FFFF

0x0003 FFFF

0x0008 3FFF

0x0008 7FFF

0x0008 BFFF

0x0008 FFFF

BANK 0

(256K Bytes)

BANK 1⁽¹⁾

(64K Bytes)

(1) Bank 1 can be used as either EEPROM emulation space or as program space.

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2.2 Terminal Functions

The terminal functions table (Table 2-10) identifies the pin names, the associated pin numbers, input

voltage, output voltage, whether the pin has any internal pullup/pulldown resistors and a functional pin

description. The TMS470MF04207 and TMS470MF03107 devices have the same pin out.

Table 2-10. Terminal Functions

TERMINAL

NAME

INPUT

OUTPUT

VOLTAGE⁽¹⁾

IPU/IPD⁽⁴⁾

DESCRIPTION

CURRENT⁽³⁾

(2)

100 PIN

HIGH-END TIMER (HET)

HET[0]

HET[1]

HET[2]

HET[3]

HET[4]

HET[5]

HET[6]

HET[7]

HET[8]

HET[9]

39

40

49

50

53

54

55

56

57

58

59

60

61

62

63

64

Timer input capture or output compare. The

HET[15:0] applicable pins can be programmed as

general-purpose input/output (GIO) pins.

The high-resolution (HR) SHARE feature allows

even HR pins to share the next higher odd HR pin

structure. The next higher odd HR pin structure is

always implemented, even if the next higher odd

HR pad and/or pin itself is not.

Adaptive

impedance 4

mA

Programmable

IPD (100 µA)

Note: HET[15] is muxed with ECLK2 output. If

ECLK2 output is enabled (through SYSPC1 register

at 0xFFFFFF00), ECLK2 is output on this pin and

HET[15] becomes an internal only HET channel.

3.3-V I/O

HET[10]

HET[11]

HET[12]

HET[13]

HET[14]

Note: ECLK2 source select must be programmed

the same as ECLK1 due to device specific

implementation details.

Note: ECLK2 is enabled and ECLK2 divider is

programmed through ECP control register

System Frame 2 Registers (0xFFFFE128).

1 in

HET[15]/ECLK2

CAN CONTROLLER 1 (DCAN1)

CAN1STX

CAN1SRX

7

8

Adaptive

Programmable

impedance 4

IPU (100 µA)

mA

DCAN1 transmit pin or GIO pin.

DCAN1 receive pin or GIO pin.

3.3-V I/O

CAN CONTROLLER 2 (DCAN2)

CAN2STX

CAN2SRX

37

38

Adaptive

Programmable

impedance 4

IPU (100 µA)

mA

DCAN2 transmit pin or GIO pin

DCAN2 receive pin or GIO pin

GENERAL-PURPOSE I/O (GIO)

GIOA[4]/INT[4]

GIOA[5]/INT[5]

GIOA[6]/INT[6]

GIOA[7]/INT[7]

5

6

General-purpose input/output pins.

They are interrupt-capable pins.

Adaptive

Programmable

impedance 4

IPD (100 µA)

mA

3.3-V I/O

15

16

(1) PWR = power, GND = ground, REF = reference voltage, NC = no connect

(2) All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.

(3) The TMS470M device utilizes adaptive impedance 4 mA buffers that default to an adaptive impedance mode of operation. As a fail-safe,

the adaptive impedance features of the buffer may be disabled and revert the buffer to a standard buffer mode.

(4) IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are inactive on input pins when PORRST is asserted)

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Table 2-10. Terminal Functions (continued)

TERMINAL

NAME

INPUT

OUTPUT

VOLTAGE⁽¹⁾

IPU/IPD⁽⁴⁾

DESCRIPTION

CURRENT⁽³⁾

(2)

100 PIN

MULTI-BUFFERED SERIAL PERIPHERAL INTERFACE 1 (MIBSPI1)

MIBSPI1CLK

34

MIBSPI1 clock. MIBSPI1CLK can be programmed

as a GIO pin.

MIBSPI1SCS[0]

MIBSPI1SCS[1]

MIBSPI1SCS[2]

MIBSPI1SCS[3]

MIBSPI1SCS[4]

MIBSPI1SCS[5]

MIBSPI1SCS[6]

MIBSPI1SCS[7]

MIBSPI1SIMO

33

32

31

30

29

28

27

26

35

MIBSPI1 slave chip select. MIBSPI1SCS[7:0] can

be programmed as a GIO pins.

Adaptive

impedance 4

mA

Programmable

IPU (100 µA)

3.3-V I/O

MIBSPI1 data stream. Slave in/master out.

MIBSPI1SIMO can be programmed as a GIO pin.

MIBSPI1SOMI

MibSPI2CLK

36

17

MIBSPI1 data stream. Slave out/master in.

MIBSPI1SOMI can be programmed as a GIO pin.

MULTI-BUFFERED SERIAL PERIPHERAL INTERFACE 2 (MibSPI2)

MibSPI2 clock. MibSPI2CLK can be programmed

as a GIO pin.

MibSPI2SCS[0]

MibSPI2SCS[1]

MibSPI2SCS[2]

MibSPI2SCS[3]

MibSPI2ENA

1

2

MibSPI2 slave chip select MibSPI2SCS[3:0] can be

programmed as GIO pins.

3

4

Adaptive

impedance 4

mA

Programmable

IPU (100 µA)

3.3-V I/O

90

MibSPI2 enable pin. MibSPI2ENA can be

programmed as a GIO pin.

MibSPI2SIMO[0]

MibSPI2SOMI[0]

18

19

MibSPI2 data stream. Slave in/master out.

MibSPI2SIMO pins can be programmed as a GIO

pins.

MibSPI2 data stream. Slave out/master in.

MibSPI2SOMI pins can be programmed as GIO

pins.

LOCAL INTERCONNECT NETWORK/SERIAL COMMUNICATIONS INTERFACE (LIN/SCI)

LIN/SCI1RX

LIN/SCI1TX

LIN/SCI2RX

LIN/SCI2TX

23

22

25

24

LIN/SCI1 data receive. Can be programmed as a

GIO pin.

Adaptive

impedance 4

mA

Programmable

IPU (100 µA)

3.3-V I/O

LIN/SCI1 data transmit. Can be programmed as a

GIO pin.

LIN/SCI2 data receive. Can be programmed as a

GIO pin.

Adaptive

impedance 4

mA

Programmable

IPU (100 µA)

LIN/SCI2 data transmit. Can be programmed as a

GIO pin.

MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER (MIBADC)

ADEVT

68

3.3-V I/O

Adaptive

impedance 4

mA

Programmable

IPD (100 µA)

MibADC event input. Can be programmed as a GIO

pin.

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Table 2-10. Terminal Functions (continued)

TERMINAL

NAME

INPUT

OUTPUT

VOLTAGE⁽¹⁾

IPU/IPD⁽⁴⁾

DESCRIPTION

CURRENT⁽³⁾

(2)

100 PIN

ADIN[0]

ADIN[1]

ADIN[2]

ADIN[3]

ADIN[4]

ADIN[5]

ADIN[6]

ADIN[7]

ADIN[8]

ADIN[9]

ADIN[10]

ADIN[11]

ADIN[12]

ADIN[13]

ADIN[14]

ADIN[15]

AD_REFHI

AD_REFLO

V_CCAD

69

70

71

72

73

74

75

76

77

78

79

80

81

86

87

88

82

83

85

84

3.3 V

MibADC analog input pins.

3.3-V REF

GND REF

3.3-V PWR

GND

MibADC module high-voltage reference input.

MibADC module low-voltage reference input.

MibADC analog supply voltage.

V_SSAD

MibADC analog ground reference.

OSCILLATOR (OSC)

OSCIN

10

11

1.55-V I

Crystal connection pin or external clock input.

External crystal connection pin.

OSCOUT

1.55-V O

SYSTEM MODULE (SYS)

PORRST

RST

89

98

3.3-V I

IPD (100 µA)

Input master chip power-up reset. External V_CC

monitor circuitry must assert a power-on reset.

Bidirectional reset. The internal circuitry can assert

a reset, and an external system reset can assert a

device reset.

On this pin, the output buffer is implemented as an

open drain (drives low only).

To ensure an external reset is not arbitrarily

generated, TI recommends that an external pullup

resistor be connected to this pin.

Adaptive

impedance 4

mA

3.3-V I/O

3.3-V I

IPU (100 µA)

ECLK

96

Adaptive

impedance 4

mA

Programmable

IPD (100 µA)

Bidirectional pin. ECLK can be programmed as a

GIO pin.

TEST/DEBUG (T/D)

TCK

TDI

44

46

IPD (100 µA)

Test clock. TCK controls the test hardware (JTAG).

Test data in pin. TDI inputs serial data to the test

instruction register, test data register, and

programmable test address (JTAG).

IPU (100 µA)

TDO

45

Adaptive

impedance 4

mA

Test data out pin. TDO outputs serial data from the

test instruction register, test data register,

identification register, and programmable test

address (JTAG).

3.3-V I/O

3.3-V I

IPD (100 µA)

TMS

47

48

Serial input pin for controlling the state of the CPU

test access port (TAP) controller (JTAG).

IPU (100 µA)

IPD (100 µA)

TRST

Test hardware reset to TAP. IEEE Standard 1149-1

(JTAG) Boundary-Scan Logic.

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Table 2-10. Terminal Functions (continued)

TERMINAL

NAME

INPUT

OUTPUT

VOLTAGE⁽¹⁾

IPU/IPD⁽⁴⁾

DESCRIPTION

CURRENT⁽³⁾

(2)

100 PIN

TEST

ENZ

97

Test enable. Reserved for internal use only. TI

recommends that this pin be connected to ground

or pulled down to ground by an external resistor.

3.3-V I

IPD (100 µA)

91

Enables/disables the internal voltage regulator.

0V - Enables internal voltage regulator.

3.3V-Disables internal voltage regulator.

IPD (100 µA)

Note: The ENZ pin is provided to facilitate

testing across the core voltage range and is not

intended for disabling the on chip voltage

regulator during application use.

FLASH

FLTP1

99

Flash Test Pad 1 pin. For proper operation, this

pin must connect only to a test pad or not be

connected at all [no connect (NC)]. The test pad

must not be exposed in the final product where

it might be subjected to an ESD event.

V_CCP1

V_CCP2

95

Flash external pump voltage (3.3 V). This pin is

required for both Flash read and Flash program and

erase operations. V_CCP1and V_CCP2are double

bonded to the same pin.

3.3-V PWR

SUPPLY VOLTAGE CORE (1.55 V)

V_CC

12

41

67

92

Vreg output voltage when Vreg is enabled. V_CC

input when Vreg is disabled.

1.55-V PWR

SUPPLY VOLTAGE DIGITAL I/O AND REGULATOR (3.3 V)

V_CCIOR

14

20

43

52

65

94

3.3-V PWR

Digital I/O and internal regulator supply voltage.

SUPPLY GROUND

V_SS

9

13

21

42

51

66

93

100

GND

Digital I/O and core supply ground reference.

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2.3 Device Support

2.3.1 Device and Development-Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

devices and support tools. Each commercial family member has one of three prefixes: TMX, TMP, or TMS

(e.g.,TMS470MF04207). Texas Instruments recommends two of three possible prefix designators for its

support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development

from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).

Device development evolutionary flow:

TMX

TMP

TMS

Experimental device that is not necessarily representative of the final device's electrical

specifications.

Final silicon die that conforms to the device's electrical specifications but has not completed

quality and reliability verification.

Fully-qualified production device.

Support tool development evolutionary flow:

TMDX

Development-support product that has not yet completed Texas Instruments internal

qualification testing.

TMDS

Fully qualified development-support product.

TMX and TMP devices and TMDX development-support tools are shipped against the following

disclaimer:

"Developmental product is intended for internal evaluation purposes."

TMS devices and TMDS development-support tools have been characterized fully, and the quality and

reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard

production devices. Texas Instruments recommends that these devices not be used in any production

system because their expected end-use failure rate still is undefined. Only qualified production devices are

to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the

package type (for example, PZ), the temperature range (for example, "Blank" is the commercial

temperature range), and the device speed range in megahertz.

Figure 2-3 illustrates the numbering and symbol nomenclature for the TMS470M family.

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2

Q

Q1

Full Part Number

TMS

S

470

4

MF

04

07

B

S

PZ

R

Orderable Part Number

Prefix: TM

S = TMS Qualified

P = TMP Prototype

X = TMX Samples

Core Technology:

4 = 470 Cortex M3

Architecture:

MF = M3 Flash

Flash Memory Size:

04 = 448K Bytes

03 = 320K Bytes

RAM Memory Size:

2 = 24K Bytes

1 = 16K Bytes

Peripheral Configuration:

Die Revision:

Blank = Initial Die

A = First Die Revision

B = Second Die Revision

Technology/Core Voltage:

S = F035 (130 nm), 1.5-V Nominal Core Voltage

Package Type:

PZ = 100-Pin QFP Package (Green)

Temperature Range:

Q = -40°C to +125°C

Quality Designator:

Q1 = Automotive

Shipping Options:

R = Tape and Reel

NOTE: The part number given above is for illustrative purposes only and does not necessarily represent the specific

part number or silicon revision to which this document applies.

Figure 2-3. TMS470M Device Numbering Conventions

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3 Device Configurations

3.1 Reset/Abort Sources

Resets/aborts are handled as shown in Table 3-1.

Table 3-1. Reset/Abort Sources

ESM HOOKUP,

GROUP.CHANNEL

ERROR SOURCE

SYSTEM MODE

ERROR RESPONSE

1) CPU TRANSACTIONS

Precise write error (NCNB/Strongly Ordered)

Precise read error (NCB/Device or Normal)

Imprecise write error (NCB/Device or Normal)

User/Privilege

Precise Abort (CPU)

Imprecise Abort (CPU)

ESM

n/a

External imprecise error (Illegal transaction with ok

response)

2.17

Illegal instruction

User/Privilege

Undefined Instruction Trap

(CPU)⁽¹⁾

n/a

M3 Lockup

User/Privilege

ESM => NMI

2.16

n/a

MPU access violation

Abort (CPU)

2) SRAM

ECC single error (correctable)

ECC double error (uncorrectable)

User/Privilege

ESM

1.26

2.6

ESM => NMI

3) FLASH WITH ECC

ECC single error (correctable)

ECC double error (uncorrectable)

User/Privilege

ESM

1.6

2.4

ESM => NMI

8) HET

HET Memory parity error

User/Privilege

ESM

1.7

9) MIBSPI

MibSPI1 memory parity error

MibSPI2 memory parity error

User/Privilege

ESM

1.17

1.18

10) MIBADC

Memory parity error

User/Privilege

ESM

1.19

11) DCAN/CAN

DCAN1 memory parity error

DCAN2 memory parity error

User/Privilege

ESM

1.21

1.23

13) PLL

PLL slip error

User/Privilege

n/a

ESM

1.10

1.11

n/a

14) CLOCK MONITOR

Clock monitor interrupt

19) VOLTAGE REGULATOR

Vcc out of range

Reset

ESM

20) CPU SELFTEST (LBIST)

CPU Selftest (LogicBIST) error

User/Privilege

n/a

1.27

n/a

21) ERRORS REFLECTED IN THE SYSESR REGISTER

Power-Up Reset/Vreg out of voltage⁽²⁾

Reset

(1) The undefined instruction trap is NOT detected outside of the CPU. The trap is taken only if the code reaches the execute stage of the

CPU.

(2) Both a power-on reset and Vreg out-of-range reset are indicated by the PORST bit in the SYSESR register.

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Table 3-1. Reset/Abort Sources (continued)

ESM HOOKUP,

GROUP.CHANNEL

ERROR SOURCE

SYSTEM MODE

ERROR RESPONSE

Oscillator fail / PLL slip⁽³⁾

M3 Lockup/LRM

n/a

Reset

n/a

Watchdog time limit exceeded

CPU Reset

Software Reset

External Reset

(3) Oscillator fail/PLL slip can be configured in the system register (SYS.PLLCTL1) to generate a reset.

3.2 Lockup Reset Module

The lockup reset module (LRM) is implemented to communicate a lockup condition by the core. The LRM

provides a small watchdog timer which can generate a system reset in case a lockup condition that is

identified by the core cannot be cleared by software.

3.3 ESM Assignments

The ESM module is intended for the communication critical system failures in a central location. The error

indication is by an error interrupt when the failure is recognized from any detection unit. The ESM module

consist of three error groups with 32 inputs each. The generation of the interrupts is shown in Table 3-2.

ESM assignments are listed in Table 3-3.

Table 3-2. ESM Groups

ERROR GROUP

Group1

INTERRUPT, LEVEL

maskable, low/high

non-maskable, high

Not Used

Group2

Group3

Table 3-3. ESM Assignments

ERROR SOURCES

GROUP 1

CHANNEL

Reserved

Flash - ECC Single Bit

HET memory parity error

Reserved

0 - 5

6

7

8-9

10

PLL Slip Error

Clock Monitor interrupt

Reserved

11

12-16

17

MibSPI1 memory parity error

MibSPI2 memory parity error

MibADC memory parity error

Reserved

18

19

20

DCAN1 memory parity error

Reserved

21

22

DCAN2 memory parity error

Reserved

23

24-25

26

SRAM - single bit

CPU LBIST - selftest error

27

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Table 3-3. ESM Assignments (continued)

ERROR SOURCES

CHANNEL

Reserved

28-31

GROUP 2

Reserved

Flash - Double-Bit Error (uncorrectable)

Reserved

0-3

4

5

SRAM - Double-Bit Error (uncorrectable)

Reserved

6

7-15

16

M3 Lockup

M3 External Imprecise Abort

Reserved

17

18-31

3.4 Interrupt Priority (M3VIM)

The TMS470M platform interrupt architecture includes a vectored interrupt manager (M3VIM) that provides

hardware assistance for prioritizing and controlling the many interrupt sources present on a device.

Table 3-4 communicates the default interrupt request assignments.

Table 3-4. Interrupt Request Assignments

DEFAULT VIM

INTERRUPT REQUEST

MODULES

INTERRUPT SOURCES

ESM

Reserved

ESM

ESM High level interrupt (NMI)

(NMI)

0

1

ESM Low level interrupt

Software interrupt (SSI)

RTI compare interrupt 0

RTI compare interrupt 1

RTI compare interrupt 2

RTI compare interrupt 3

RTI overflow interrupt 0

RTI overflow interrupt 1

Reserved

2

SYSTEM

RTI

3

4

RTI

5

RTI

6

RTI

7

RTI

8

RTI

9

Reserved

GIO

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

GIO Interrupt A

GIO

GIO Interrupt B

HET

HET level 0 interrupt

HET level 1 interrupt

MibSPI1 level 0 interrupt

MibSPI1 level 1 interrupt

Reserved

HET

MibSPI1

Reserved

LIN/SCI2

LIN/SCI1

DCAN1

ADC

LIN/SCI2 level 0 interrupt

LIN/SCI2 level 1 Interrupt

LIN/SCI1 level 0 interrupt

LIN/SCI1 level 1 Interrupt

DCAN1 level 0 Interrupt

DCAN1 level 1 Interrupt

ADC event group interrupt

ADC sw group 1 interrupt

ADC sw group 2 interrupt

ADC

22

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Table 3-4. Interrupt Request Assignments (continued)

DEFAULT VIM

INTERRUPT REQUEST

MODULES

INTERRUPT SOURCES

MibSPI2

DCAN2

ADC

MibSPI2 level 0 interrupt

MibSPI2 level 1 interrupt

DCAN2 level 0 interrupt

DCAN2 level 1 interrupt

ADC magnitude threshold interrupt

Reserved

27

28

29

30

31

Reserved

DCAN1

DCAN2

Reserved

32

Reserved

33

DCAN1 IF3 interrupt

DCAN2 IF3 interrupt

Reserved

34

35

36-47

3.5 MibADC

The multi-buffered analog-to-digital converter (MibADC) accepts an analog signal and converts the signal

to a 10-bit digital value.

The TMS470M MibADC module stores its digital results in one of three FIFO buffers. There is one FIFO

buffer for each conversion group [event, group1 (G1), and group2 (G2)], and the total MibADC FIFO on

the device is divided amongst these three regions. The size of the individual group buffers are software

programmable. MibADC buffers can be serviced by interrupts.

Device Configurations

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3.5.1 MibADC Event Triggers

All three conversion groups can be configured for event-triggered operation, providing up to three

event-triggered groups.

The trigger source and polarity can be selected individually for group 1, group 2 and the event group from

the options identified in Table 3-5.

Table 3-5. MibADC Event Hookup Configuration

SOURCE SELECT BITS for G1 or EVENT

EVENT NO.

SIGNAL PIN NAME

(G1SRC[2:0] or EVSRC[2:0])

1

2

3

4

5

6

7

8

000

001

010

011

100

101

110

111

ADEVT

HET[1]

HET[3]

HET[16]⁽¹⁾

HET[18]⁽¹⁾

HET[24]⁽¹⁾

HET[26]⁽¹⁾

HET[28]⁽¹⁾

(1) These channels are available as internal signals even if they are not included as pins (Section 1.1).

3.6 MibSPI

The multi-buffered serial peripheral interface module allows CPU independent SPI communications with

system peripherals.

The MibSPI1 module can support up to 16 transfer groups and 8 chip selects. In addition, up to 4 data

formats can be supported allowing assignment of various formats to each transfer group.

The MibSPI2 module can support up to 8 transfer groups, 4 chip selects, and up to 4 data formats.

3.6.1 MibSPI Event Trigger

The MibSPI module has the ability to automatically trigger SPI events based on internal and external

event triggers.

The trigger sources can be selected individually for each transfer group from the options identified in

Table 3-6.

Table 3-6. MibSPI1 and MibSPI2 Event Hookup Configuration

SOURCE SELECT BITS FOR MIBSPI

EVENT NO.

EVENTS

SIGNAL PIN NAME

TGXCTRL TRIGSRC[3:0]

Disabled

EVENT0

EVENT1

EVENT2

EVENT3

EVENT4

EVENT5

EVENT6

EVENT7

EVENT8

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

No trigger source

GIOA[0]⁽¹⁾

GIOA[1]⁽¹⁾

GIOA[2]⁽¹⁾

GIOA[3]⁽¹⁾

GIOA[4]

GIOA[5]

HET[20]⁽¹⁾

HET[21]⁽¹⁾

HET[22]⁽¹⁾

(1) These channels are available as internal signals even if they are not included as pins (Section 1.1).

Device Configurations

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Table 3-6. MibSPI1 and MibSPI2 Event Hookup Configuration (continued)

SOURCE SELECT BITS FOR MIBSPI

EVENTS

EVENT NO.

SIGNAL PIN NAME

TGXCTRL TRIGSRC[3:0]

EVENT9

EVENT10

EVENT11

EVENT12

EVENT13

EVENT14

1010

1011

1100

1101

1110

1111

HET[23]⁽¹⁾

HET[28]⁽¹⁾

HET[29]⁽¹⁾

HET[30]⁽¹⁾

HET[31]⁽¹⁾

Internal Tick Counter

3.7 JTAG ID

The 32-bit JTAG ID code for this device is 0x0B8D802F.

3.8 Scan Chains

The device contains an ICEPICK module to access the debug scan chains; see Figure 3-1. Debug scan

chain #0 handles the access to the CPU. The ICEPICK scan ID is 0x00366D05, which is the same as the

device ID.

TDI

DAP

CPU

TDO

Boundary Scan Chain #0

Boundary

Scan

Boundary Scan Interface

Figure 3-1. Debug Scan Chains

3.9 Adaptive Impedance 4 mA IO Buffer

The adaptive impedance 4 mA buffer is a buffer that has been explicitly designed to address the issue of

decoupling EMI sources from the pins which they drive. This is accomplished by adaptively controlling the

impedance of the output buffer and should be particularly effective with capacitive loads.

The adaptive impedance 4 mA buffer features two modes of operation: Impedance Control Mode, and

Low-Power Mode/Standard Buffer Mode as defined below:

•

Impedance Control Mode is enabled in the design by default. This mode adaptively controls the

impedance of the output buffer.

Device Configurations

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•

Standard Buffer Mode is used to configure the buffer back into a generic configuration. This buffer

mode is used when it is necessary to drive the output at very high speeds, or when EMI reduction is

not a concern.

Table 3-7. Adaptive Impedance 4 mA Buffer Mode Availability

MODULE OR PIN NAME

SYS.ECLK

SYS.nRST

SYS.TDI/TDO

SYS.TMSC

HET

STANDARD BUFFER ENABLE (SBEN)⁽¹⁾

GPREG1.0

GPREG1.1

Standard Buffer Enabled

GPREG1.2

SCI1

GPREG1.3

LIN/SCI2

GPREG1.4

MIBSPI1

GPREG1.5

MibSPI2

GPREG1.6

Reserved

MIBADC.ADEVT

DCAN1

GPREG1.7

GPREG1.8

GPREG1.9

DCAN2

GPREG1.10

GIOA

GPREG1.11

(1) SBEN configuration can be achieved using the GPREG register within the system frame(0xFFFFFFA0).

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3.9.1 Standard Buffer Enable Register (GPREG1)

A general purpose register with the system frame has been utilized to control the enabling of standard

buffer mode. This register is shown in Figure 3-2 and described in Table 3-8

NOTE

In general, all device registers are defined within the TRM (SPNU450); however, in cases

where the register definition is device specific, the register is defined within the device

specific datasheet.

31

16

Reserved

R-0

15

7

12

4

11

GIOA_SBEN

RW-0

10

9

8

ADC.ADEVT_

SBEN

Reserved

R-0

DCAN2_SBEN DCAN1_SBEN

RW-0

2

RW-0

1

RW-0

0

6

5

3

MibSPI2_

SBEN

MIBSPI1_

SBEN

LIN2SCI2_

SBEN

LIN1SCI1_

SBEN

Reserved

RW-0

HET_SBEN

RW-0

RST_SBEN

RW-0

ECLK_SBEN

RW-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Figure 3-2. General-Purpose Register 1 (GPREG1)

Table 3-8. General-Purpose Register 1 (GPREG1) Field Descriptions

Bit

Field

Value Description

31-12 Reserved

These bits are reserved. Reads return 0 and writes have no effect.

11

10

9

GIOA_SBEN

GIOA port standard buffer enable bit.

This bit enables/disables standard buffer mode for all GIOA pins

0

1

Standard buffer mode is not enabled.

Standard buffer mode is enabled for all associated module pins.

DCAN2_SBEN

DCAN2 standard buffer enable bit.

This bit enables/disables standard buffer mode for all DCAN2 pins.

0

1

Standard buffer mode is not enabled.

Standard buffer mode is enabled for all associated module pins.

DCAN1_SBEN

DCAN1 standard buffer enable bit.

This bit enables/disables standard buffer mode for all DCAN1 pins.

0

1

Standard buffer mode is not enabled.

Standard buffer mode is enabled for all associated module pins.

8

ADC.ADEVT_SBEN

ADC.ADEVT standard buffer enable bit.

This bit enables/disables standard buffer mode for the ADC.ADEVT pin.

0

1

Standard buffer mode is not enabled.

Standard buffer mode is enabled for the ADEVT pin.

These bits are reserved. Reads return 0 and writes have no effect.

7

6

Reserved

MibSPI2_SBEN

MibSPI2 standard buffer enable bit.

This bit enables/disables standard buffer mode for all MibSPI2 pins.

0

1

Standard buffer mode is not enabled.

Standard buffer mode is enabled for all associated module pins.

5

MIBSPI1

MIBSPI1 standard buffer enable bit.

This bit enables/disables standard buffer mode for all MIBSPI1 pins.

0

1

Standard buffer mode is not enabled.

Standard buffer mode is enabled for all associated module pins.

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Table 3-8. General-Purpose Register 1 (GPREG1) Field Descriptions (continued)

Bit

Field

Value Description

4

LIN2SCI2_SBEN

LIN/SCI2 standard buffer enable bit.

This bit enables/disables standard buffer mode for all LIN/SCI2 pins.

Standard buffer mode is not enabled.

0

1

Standard buffer mode is enabled for all associated module pins.

3

2

1

0

LIN1SCI1_SBEN

HET_SBEN

LIN/SCI1 standard buffer enable bit.

This bit enables/disables standard buffer mode for all LIN/SCI1 pins.

0

1

Standard buffer mode is not enabled.

Standard buffer mode is enabled for all associated module pins.

HET standard buffer enable bit.

This bit enables/disables standard buffer mode for all HET pins.

0

1

Standard buffer mode is not enabled.

Standard buffer mode is enabled for all associated module pins.

RST_SBEN

RST standard buffer enable bit.

This bit enables/disables standard buffer mode for the RST pin.

0

1

Standard buffer mode is not enabled.

Standard buffer mode is enabled for the RST pin.

ECLK_SBEN

ECLK standard buffer enable bit.

This bit enables/disables standard buffer mode for the ECLK pin.

0

1

Standard buffer mode is not enabled.

Standard buffer mode is enabled for the ECLK pin.

3.9.2 Coresight Components/Debug ROM

Coresight registers are memory-mapped and accessible via the CPU and JTAG.

Table 3-9. Debug Component Memory Map

FRAME START

ADDRESS

FRAME END

ADDRESS

COMPONENT

FRAME SIZE

MEMORY TYPE

M3 INTEGRATION FRAME

0xE000_1FFF

DWT

FPB

0xE000_1000

0xE000_2000

0xE000_E000

0xE00F_F000

4K

Control Registers for

debug and trace

modules

0xE000_2FFF

NVIC

0xE000_EFFF

Debug ROM 1

0xE00F_FFFF

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Table 3-10. Debug ROM contents for Debug ROM 1 (M3 ROM)

ADDRESS OFFSET

see Table 3-9

DESCRIPTION

VALUE

0x000

0x004

0x008

0x00C

0x010

0x014

0x018

NVIC

DWT

0xFFF0_F003

0xFFF0_2003

0xFFF0_3003

0xFFF0_1003

0xFFF4_1002

0xFFF4_2002

0x0000_0000

FPB

ITM

TPIU⁽¹⁾

ETM⁽¹⁾

End of Table

(1) Cortex™-M3 debug ROM always will have entries for optional components TPIU and ETM. Whether or

not these components are present is determined by bit number 0 of the entry value.

3.10 Built-In Self Test (BIST) Features

3.10.1 STC/LBIST

The TMS470M family supports a logic built-in self test (LBIST or CPUBIST) of the M3 CPU.

LBIST testing can be performed in two modes of operation:

•

Full Execution. In this mode, the full suite of test patterns is run without interruption. This test is

started via CPU control and is well suited for use at device start up.

Cyclic Execution. During cyclic execution, a small percentage of time will be dedicated to running a

subset of the self-test (STC Intervals). This mode is well suited for executing on a periodic basis to

minimize the bandwidth use. After all STC intervals are executed, all test patterns will have been run.

NOTE

1. The application will need to disable peripherals and or interrupts to avoid missing

interrupts.

2. No debugger interaction is possible with the CPU during self test. This includes access to

memory and registers since access is through the CPU.

The default value of the LBIST clock prescaler (STCDIV) is divide-by-1 and the device will support STC

frequencies up to and including HCLK frequency. In order to minimize the current consumption during

LBIST execution, the LBIST clock prescalar (STCDIV) may be configured to reduce the LBIST frequency.

Device Configurations

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100

2500.00

2000.00

1500.00

1000.00

500.00

0.00

³ 90%

coverage

90

80

70

60

50

40

30

20

10

0

50

100 150 200 250 300 350 400 450 500 550

No. of Intervals

555 total

intervals

Test Coverage

Test Time (µs)

A. A single LBIST interval is 158 STC CLK cycles in duration, excluding clock transition timing of 20 cycles.

B. This device has 555 total intervals.

Figure 3-3. CPU BIST Intervals vs Coverage

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3.10.2 MBIST

The TMS470M supports memory built-in self test (MBIST) of the SRAM. The MBIST is accessible via the

application in order to facilitate memory self test by the application by enabling the MBIST controllers

associated with the specific RAMs to be tested. (For device-specific MBIST controller assignments, see

Table 2-4.)

The MBIST controller:

•

Supports testing of all system and peripheral RAM.

Captures the MBIST results in the MBIST status register (MSTFAIL).

Supports execution of each Memory BIST controller in parallel (MSINENA).

For MSIENA bit assignments, see Table 2-4

•

Supports execution of each Memory BIST controller individually (MSINENA).

For MSIENA bit assignments, see Table 2-4

The MBIST controller selection is mapped to the MBIST controller/memory initialization enable register

(MSIENA) within the SYS register frame. Each MBIST controller is enabled by setting the corresponding

bit within this register and then enabling memory self-test via the memory self-test global enable within the

global control register (MSTGCR.MSTGENA[3:0]).

The MBIST controllers support execution of the following tests:

Table 3-11. MBIST Algorithms and Cycle Counts⁽¹⁾

Module

Algorithm (Cycle Counts)

March11N March13N

Background Background Background

Checker

Board

March13N

PMOS Open

Address

ROM2

0

A

3/0F/69

4033

3745

79873

24193

9985

-

Decode

ADC RAM

DCAN RAM

SRAM

1427

1503

26835

7539

3583

-

1555

1503

26835

8307

3583

-

1089

1057

22529

6529

2817

-

4225

3265

147457

29185

10753

-

HET RAM

MibSPI RAM

STC ROM

-

18433

(1) Cycle times provided are for the execution of the specific algorithms and do not include overhead from

the BIST statemachine.

NOTE

The algorithm to be applied is selectable via the memory self-test global control register algo

selection field (MSTGCR.MBIST_ALGSEL[7:0]).

Device Configurations

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3.11 Device Identification Code Register

The device identification code register identifies the coprocessor status, an assigned device-specific part

number, the technology family (TF), the I/O voltage, whether or not parity is supported, the levels of flash

and RAM error detection, and the device version. The TMS470M device identification code base register

value is 0X00366D05 and is subject to change based on the silicon version.

31

CP15

R-0

30

17

16

TF

PART NUMBER

R-00000000011011

R-0

15

7

13

12

I/O VOLT

R-0

11

PP

R-1

10

9

8

TF

FLASHECC

R-10

RAMECC

R-1

R-011

3

2

1

0

1

VERSION

R-0000

R-1

R-0

R-1

LEGEND: R = Read only; -n = value after reset

Figure 3-4. TMS470 Device ID Bit Allocation Register

Table 3-12. TMS470 Device ID Bit Allocation Register Field Descriptions

Bit

Field

Value Description

31

CP15

This bit indicates the presence of coprocessor (CP15).

0

1

No coprocessor present in the device.

Coprocessor present in the device.

30-17 PART NUMBER

16-13 TF

These bits indicate the assigned device-specific part number.

The assigned device-specific part number for the TMS470M device is 00000000011011.

Technology family bit.

These bits indicate the technology family (C05, F05, F035, C035).

0011 F035

12

11

10

I/O VOLT

I/O voltage bit.

This bit identifies the I/O power supply.

0

1

3.3 V

5 V

PP

Peripheral parity bit.

This bit indicates whether parity is supported.

0

1

No parity on peripheral.

Parity on peripheral.

FLASHECC

Flash ECC bits.

These bits indicate the level of error detection and correction on the flash memory.

00

01

10

11

No error detection/correction.

Program memory with parity.

Program memory with ECC.

Reserved

8

RAMECC

RAM ECC bits.

This bit indicates the presence of error detection and correction on the CPU RAM.

0

1

RAM ECC not present.

RAM ECC present.

7-3

2-0

VERSION

101

These bits identify the silicon version of the device.

Bits 2:0 are set to 101 by default to indicate a platform device.

32

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3.12 Device Part Numbers

Table 3-13 lists all the available TMS470MF04207/TMS470MF03107 device configurations.

Table 3-13. Device Part Numbers

PROGRAM

MEMORY

TEMPERATURE

RANGE

PACKAGE TYPE

100-PIN LQFP

PbFREE/

GREEN⁽¹⁾

DEVICE PART NUMBER

SAP PART NUMBER

FLASH

EEPROM

-40°C to 125°C

TMS470MF04207PZQ

TMS470MF03107PZQ

S4MF04207SPZQQ1

S4MF03107SPZQQ1

X

(1) RoHS compliant products are compatible with the current RoHS requirements for all six substances, including the requirement that lead

not exceed 0.1% by weight in homogeneous materials, unless exempt. Pb-Free products are RoHS Compliant, plus suitable for use in

higher temperature lead-free solder processes (typically 245 to 260°C). Green products are RoHS and Pb-Free, plus also free of

Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material).

Device Configurations

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4 Device Operating Conditions

4.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range, Q Version⁽¹⁾

(2)

V_CC

-0.5 V to 2.1 V

Supply voltage range:

Input voltage range:

V_CCIOR, V_CCAD, V_CC(Flash pump)⁽²⁾

-0.5 V to 4.1 V

±20 mA

All input pins

I_IK(V_I< 0 or V_I> V_CCIOR

)

All pins, except ADIN[0:15]

Input clamp current:

I_IK(V_I< 0 or V_I> V_CCIOR

)

±10 mA

ADIN[0:15]

Operating free-air temperature range, T_A:

Operating junction temperature range, T_J:

Storage temperature range, T_stg

Q version

Standard

-40°C to 125°C

-40°C to 150°C

-65°C to 150°C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only. Functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to their associated grounds.

4.2 Device Recommended Operating Conditions⁽¹⁾

MIN

3

NOM

3.3

1.55

3.3

0

MAX UNIT

V_CCIOR

V_CC

Digital I/O and internal regulator supply voltage

Voltage regulator output voltage

MibADC supply voltage

3.6

1.70

3.6

V

1.40

3

V_CCAD

V_CCP

V_SS

V

Flash pump supply voltage

3

3.6

V

Digital logic supply ground

V

V_SSAD

T_A

MibADC supply ground

-0.1

-40

0.1

125

150

V

Operating free-air temperature

Operating junction temperature

Q version

°C

T_J

(1) All voltages are with respect to V_SS, except V_CCAD, which is with respect to V_SSAD

.

34

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4.3 Electrical Characteristics Over Recommended Operating Free-Air Temperature

Range, Q Version⁽¹⁾⁽²⁾

PARAMETER

Input hysteresis

TEST CONDITIONS

MIN

150

-0.3

TYP

MAX

UNIT

mV

V

V_hys

V_IL

All inputs⁽³⁾

OSCIN

All inputs⁽³⁾

0.8

Low-level input voltage

High-level input voltage

0.2 V_CC

V

2

V_CCIOR+ 0.3

V_IH

V

OSCIN

0.8 V_CC

I_OL= I_OLMAX

0.2 V_CCIOR

0.2

I_OL= 50 µA

Standard mode

V_OL

Low-level output voltage

High-level output voltage

V

I_OL= 50 µA

Impedance Control

mode

0.2 V_CCIOR

I_OH= I_OHMAX

0.8 V_CCIOR

V_CCIOR-0.2

I_OH= 50 µA

Standard mode

V_OH

V

I_OH= 50 µA

Impedance Control

mode

0.8 V_CCIOR

V_I< V_SSIO- 0.3 or V_I

> V_CCIOR+ 0.3

-2

2

I_IC

Input clamp current (I/O pins)⁽⁴⁾

Input current (I/O pins)

mA

I_IHPulldown

I_ILPullup

V_I= V_CCIOR

V_I= V_SS

40

-190

-1

190

-40

1

I_I

µA

No pullup or

pulldown

All other pins

Adaptive impedance V_OL= V_OLMAX

4 mA Buffer

4

I_OL

I_OH

Low-level output tcurrent

High-level output current

mA

Adaptive impedance V_OH= V_OHMIN

4 mA Buffer

-4

HCLK = 80 MHz,

110

115

V_CCdigital supply current (operating mode, internal

regulator disabled)

I_CC

VCLK = 80 MHz,

mA

V_CC= 1.70 V⁽⁵⁾

HCLK = 80 MHz,

VCLK = 80 MHz,

No DC load,

V_CCIORIO and digital supply current (operating

mode, internal regulator enabled)

V_CCIOR= 3.6 V⁽⁵⁾⁽⁶⁾

HCLK = 80 MHz,

VCLK = 80 MHz,

STCCLK = 80 MHz,

No DC load,

155

130

V_CCIORIO and digital supply current (LBIST

execution, internal regulator enabled)⁽⁷⁾

I_CCIOR

mA

V_CCIOR= 3.6 V⁽⁶⁾

HCLK = 80 MHz,

VCLK = 80 MHz,

No DC load, V_CCIOR

= 3.6 V⁽⁶⁾

V_CCIORIO and digital supply current (MBIST

execution, internal regulator enabled)⁽⁸⁾

(1) Source currents (out of the device) are negative while sink currents (into the device) are positive.

(2) "All frequencies" will include all specified device configuration frequencies.

(3) The V_ILhere does not apply to the OSCIN, OSCOUT and PORRST pins; the V_IHhere does not apply to the OSCIN, OSCOUT and RST

pins; For RST and PORRST exceptions, see Section 5.1.

(4) Parameter does not apply to input-only or output-only pins.

(5) Maximum currents are measured using a system-level test case. This test case exercises all of the device peripherals concurrently

(excluding MBIST and STC LBIST).

(6) I/O pins configured as inputs or outputs with no load. All pulldown inputs ≤ 0.2 V. All pullup inputs ≥ V_CCIO- 0.2 V. ECLK output ≤

2 MHz.

(7) LBIST current specified is peak current for the maximum supported operating clock (HCLK = 80 MHz) and STC CLK = HCLK. Lower

current consumption can be achieved by configuring a slower STC Clock frequency. The current peak duration can last for the duration

of 1 LBIST test interval.

(8) MBIST currents specified are for execution of MBIST on all RAMs in parallel. Lower current consumption can be achieved by sequenced

execution of MBIST on each of the RAM spaces available.

Device Operating Conditions

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Electrical Characteristics Over Recommended Operating Free-Air Temperature Range, Q

Version⁽¹⁾⁽²⁾(continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

All frequencies,

V_CCAD= 3.6 V

8

I_CCAD

V_CCADsupply current (operating mode)

mA

V_CCP= 3.6 V read

operation⁽⁵⁾

10

75

I_CCP

V_CCPpump supply current

V_CCP= 3.6 V

program⁽⁹⁾

mA

V_CCP= 3.6 V erase

75

HCLK = 80 MHz,

VCLK = 80 MHz,

No DC load,

125

V_CCIOR+ V_CCAD+ V_CCPtotal digital supply current

(operating mode, internal regulator enabled)

(10)

I_CCTOTAL

mA

V_CCIOR= 3.6 V⁽⁵⁾⁽⁶⁾

C_I

Input capacitance

Output capacitance

6

7

pF

C_O

(9) Assumes reading from one bank while programming a different bank.

(10) Total device operating current is derived from the total I_CCIOR, I_CCAD, and I_CCPin normal operating mode excluding MBIST and LBIST

execution. It is expected that the total will be less than the sums of the values of the individual components due to statistical calculations

involved in producing the specification values.

5 Peripheral Information and Electrical Specifications

5.1 RST and PORRST Timings

Table 5-1. Timing Requirements for PORRST⁽¹⁾

(see Figure 5-1)

NO.

MIN

MAX

UNIT

V_CCPORL

V_CClow supply level when RST becomes active

1.30

V

V_CCPORH

V_CCIOPORL

V_CCIOPORH

V_CChigh supply level when RST becomes active

1.80

1.1

V_CCIOlow supply level when PORRST must be active during power up

V_CCIOhigh supply level when PORRST must remain active during power up

and become active during power down

3.0

V

(2)

V_IL

Low-level input voltage after V_CCIOR> V_CCIOPORH

0.2 V_CCIOR

V

(3)

V_OH

High-level output voltage after V_CCIOR> V_CCIOPORH

0.8 V_CCIOR

V

V_IL(PORRST)

t_su(PORRST)r

t_su(VCCIOR)r

t_h(PORRST)r

t_su(PORRST)f

t_h(PORRST)rio

t_h(PORRST)d

Low-level input voltage of PORRST before V_CCIOR> V_CCIOPORL

Setup time, PORRST active before V_CCIOR> V_CCIOPORLduring power up

Setup time, V_CCIOR> V_CCIOPORLbefore V_CC> V_CCPORL

Hold time, PORRST active after V_CC> V_CCPORH

0.5

V

3

5

6

7

8

9

0

1

8

1

0

ms

µs

ms

ns

Setup time, PORRST active before V_CC≤ V_CCPORHduring power down

Hold time, PORRST active after V_CCIOR> V_CCIOPORH

Hold time, PORRST active after V_CCIOR< V_CCIORPORL

Setup time, PORRST active before V_CC≤ V_CCIOPORHduring power down

10 t_{su(PORRST)fio}

11 t_su(VCCIO)f

t_f(PORRST)

Setup time, V_CC

< _VCCPOREbefore V_CCIO< V_CCIOPORL

Filter time PORRST, pulses less than MIN get filtered out; pulses greater

than MAX generate a reset.

30

40

185

150

ns

t_f(RST)

Filter time RST, pulses less than MIN get filtered out; pulses greater than

MAX generate a reset.

(1) When the V_CCtiming requirements for PORRST are satisfied, there are no timing requirements for V_CCP

.

(2) Corresponds to PORRST.

(3) Corresponds to RST.

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V_CCIOR

V_CCIOPORH

V_CCIOR

8

6

11

V_CC

V_CCPORH

7

6

10

V_CCIOPORL

V_CCPORL

5

3

9

V_IL(PORRST)

V_IL

PORRST

V_CC(1.55 V)

V_CCP/V_CCIOR(3.3 V)

Note: V_CCis provided by the on-chip voltage regulator during normal application run time. It is not recommended to

use the device in an application with the Vreg disabled due to potential glitching issues; however, if used in this mode,

the application should ensure that the specified voltage ranges for V_CCare maintained.

Figure 5-1. PORRST Timing Diagram

Table 5-2. Switching Characteristics Over Recommended Operating Conditions for RST and PORRST⁽¹⁾

PARAMETER

Valid time, RST active after PORRST inactive

Valid time, RST active (all others)

MIN

MAX

UNIT

1024t_c(OSC)

8t_c(VCLK)

t_v(RST)

ns

Vccio low supply level when PORRST must be active during power-up and

power-down

V_CCIOPORL

1.1

V

(1) Specified values do NOT include rise/fall times. For rise and fall timings, see Table 5-13.

Table 5-3. Internal Voltage Regulator Specifications

PARAMETER

MIN

12

1

MAX

UNIT

µs

t_D(VCCIOR)0-3

t_V(PORRST)L

Delay time, input supply to ramp from 0 V to 3 V

Valid time, PORRST active after input supply becomes ≥ 3.0 V

1000

ms

Minimum input voltage, when PORRST must be made active during power

down or brown out

V_{CCIORmin(PORRST)f}

3.0

V

C_(VCC)core

Capacitance distributed over core V_CCpins for voltage regulator stability

Total combined ESR of stabilization capacitors on core V_CCpins

1.2

0

6.0

µF

ESR_(max)core

0.75

Ω

3 V

V_{CCIORmin(PORRST)f}

t_V(PORRST)L

t_D(VCCIOR)0-3

V_CC

PORRST

Figure 5-2. PORRST Timing Requirements

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Table 5-4. VREG Recommended Operation Conditions

PARAMETER

CONDITIONS

MIN

MAX

UNIT

Normal mode, regulator

active

0

200

mA

I_CC

V_CCLoad Rating

Off, enable forced off

-

µA

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5.2 PLL and Clock Specifications

Table 5-5. Timing Requirements for PLL Circuits Enabled or Disabled

PARAMETER

Input clock frequency

MIN

5

MAX

UNIT

MHz

ns

f_(OSC)

20

t_c(OSC)

Cycle time, OSCIN

50

15

t_w(OSCIL)

t_w(OSCIH)

Pulse duration, OSCIN low

Pulse duration, OSCIN high

ns

5.2.1 External Reference Resonator/Crystal Oscillator Clock Option

The oscillator is enabled by connecting the appropriate fundamental 5-20 MHz resonator/crystal and load

capacitors across the external OSCIN and OSCOUT pins as shown in Figure 5-3(a). The oscillator is a

single stage inverter held in bias by an integrated bias resistor.

TI strongly encourages each customer to submit samples of the device to the resonator/crystal

vendors for validation. Vendors are equipped to determine which load capacitors will best tune their

resonator/crystal to the microcontroller device for optimum start-up and operation over

temperature/voltage extremes.

5.2.2 External Clock Source

An external oscillator source can be used by connecting a 1.55-V clock signal to the OSCIN pin and

leaving the OSCOUT pin unconnected (open) as shown in Figure 5-3(b).

OSCIN

OSCOUT

OSCIN

OSCOUT

External

Clock Signal

(toggling 0-1.55 V)

C1^(A)

C2^(A)

Crystal

(a)

(b)

A. The values of C1 and C2 should be provided by the resonator/crystal vendor.

Figure 5-3. Recommended Crystal/Clock Connection

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5.2.3 Validated FMPLL Settings

The following table includes the validated FMPLL settings.

Table 5-6. Validated FMPLL Settings

Mode

OSCIN

PLLCTL1⁽¹⁾

PLLCTL2⁽¹⁾

FMPLL Output

Modulation

Frequency (MHz)

Frequency (MHz) Bandwidth (KHz)

Depth

10

0x20048B00

0x20026100

0x20058B00

0x20055F00

0x20068B00

0x20036100

0x20078B00

0x20098B00

0x20049F00

0x20055F00

0x20059F00

0x20065F00

0x20069F00

0x20075F00

0x20079F00

0x20099F00

0x20049F00

0x20026300

0x20059F00

0x20067700

0x20069F00

0x20036300

0x20079F00

0x20099F00

0x00007800

0x00007C00

0x00007800

0x00007600

0x00007800

0x00007C00

0x00007800

0x00007400

0x00007800

0x00007400

0x00007800

0x00007400

0x00007800

0x00007600

0x00007800

0x00007600

0x00007400

0x00007600

0x00007800

0x00007600

12

Non-Modulated⁽²⁾14

16

56

64

80

-

20

10

12

Non-Modulated⁽²⁾14

16

-

20

10

12

Non-Modulated⁽²⁾14

-

16

20

(1) The recommended PLLCTL1 and PLLCTL2 values make no assumption of the intended use of ROS, BPOS, and ROF fields within the

PLL control registers. For these settings, the application should set these as appropriate for the specific application requirements.

(2) Non-Modulated settings provided show FM related bit fields as 0. When initializing the PLLCTL registers for non-modulated use, the FM

related bit fields should be masked such that reset/default values are retained.

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Mode

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Table 5-6. Validated FMPLL Settings (continued)

OSCIN

PLLCTL1⁽¹⁾

PLLCTL2⁽¹⁾

FMPLL Output

Modulation

Depth

Frequency (MHz)

Frequency (MHz) Bandwidth (KHz)

0x20048B00

0x20058B00

0x20068B00

0x20078B00

0x20098B00

0x20049F00

0x20059F00

0x20069F00

0x20079F00

0x20099F00

0x8300B844

0x8300B889

0x82409859

0x824098B2

0x8300B844

0x8300B889

0x82409859

0x824098B2

0x8300B844

0x8300B889

0x82409859

0x824098B2

0x8300B844

0x8300B889

0x82409859

0x824098B2

0x8300B844

0x8300B889

0x82409859

0x824098B2

0x8300C83B

0x8300C878

0x8240A84D

0x8240A89C

0x8300C83B

0x8300C878

0x8240A84D

0x8240A89C

0x8300C83B

0x8300C878

0x8240A84D

0x8240A89C

0x8300C83B

0x8300C878

0x8240A84D

0x8240A89C

0x8300C83B

0x8300C878

0x8240A84D

0x8240A89C

0.50%

1.00%

0.50%

1.00%

0.50%

1.00%

0.50%

1.00%

0.50%

1.00%

0.50%

1.00%

0.50%

1.00%

0.50%

1.00%

0.50%

1.00%

0.50%

1.00%

0.50%

1.00%

0.50%

1.00%

0.50%

1.00%

0.50%

1.00%

0.50%

1.00%

0.50%

1.00%

0.50%

1.00%

0.50%

1.00%

0.50%

1.00%

0.50%

1.00%

76.92

100

10

12

14

16

20

10

12

14

16

20

76.92

100

76.92

Frequency

Modulated

56

100

76.92

100

76.92

100

76.92

100

76.92

100

76.92

Frequency

Modulated

64

100

76.92

100

76.92

100

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Table 5-6. Validated FMPLL Settings (continued)

Mode

OSCIN

PLLCTL1⁽¹⁾

PLLCTL2⁽¹⁾

FMPLL Output

Modulation

Frequency (MHz)

Frequency (MHz) Bandwidth (KHz)

Depth

0.50%

1.00%

0.50%

1.00%

0.50%

1.00%

0.50%

1.00%

0.50%

1.00%

0.50%

1.00%

0.50%

1.00%

0.50%

1.00%

0.50%

1.00%

0.50%

1.00%

0x20049F00

0x20059F00

0x20069F00

0x20079F00

0x20099F00

0x8300C63B

0x8300C678

0x8240A64D

0x8240A69C

0x8300C63B

0x8300C678

0x8240A64D

0x8240A69C

0x8300C63B

0x8300C678

0x8240A64D

0x8240A69C

0x8300C63B

0x8300C678

0x8240A64D

0x8240A69C

0x8300C63B

0x8300C678

0x8240A64D

0x8240A69C

76.92

10

100

76.92

100

12

14

16

20

76.92

Frequency

Modulated

80

100

76.92

100

76.92

100

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5.2.4 LPO and Clock Detection

The LPOCLKDET module consists of a clock monitor (CLKDET) and 2 low-power oscillators (LPO): a

low-frequency (LF) and a high-frequency (HF) oscillator. The CLKDET is a supervisor circuit for an

externally supplied clock signal. In case the externally supplied clock frequency falls out of a frequency

window, the clock detector flags this condition and switches to the HF LPO clock (limp mode). The

OSCFAIL flag and clock switch-over remain, regardless of the behavior of the oscillator clock signal. The

only way OSCFAIL can be cleared (and OSCIN be again the driving clock) is a power-on reset.

Table 5-7. LPO and Clock Detection

PARAMETER

Lower threshold

MIN

1.5

TYP

MAX

5.0

UNIT

MHz

invalid frequency

Higher threshold

20.0

50.0

limp mode frequency

(HFosc)

7.6

12

14.0

MHz

LFosc frequency

HFosc frequency

50

90

12

124

kHz

7.6

14.0

MHz

upper

threshold

lower

threshold

guaranteed fail

guaranteed pass

guaranteed fail

1.5

5.0

20.0

50.0

f (MHz)

Figure 5-4. LPO and Clock Detection

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5.2.5 Device Clock Domains Block Diagram

The clock domains block diagram and GCM clock source assignments are given in Figure 5-5 and

Table 5-8.

OSCOUT

0

1

OSC

OSCIN

(5-20 MHz)

FM_ZPLL

GCLK (to CPU)^(A)

RCLK

/1..64 x92..184

/1..8

/1..32

HCLK (to SYSTEM)^(A)

LF OSC

HF OSC

4

5

LPO

/1,2,4,8

RTICLK (to RTI)^(A)

/1..16

VCLK (to Peripherals)^(A)

VCLK2 (to HET)^(A)

AVCLK1

HRP

/1..64

/2,3..2²⁴

/1,2..256

/1,2..65536

/1,..1024

SPI Baud Rate LIN Baud Rate

£ 20 kB/s

ADCLK

£ 20 MHz

LRP

/2⁰..2⁵

£ VCLK/2

ECLK1

£ 20 MHz

ECLK2

£ 20 MHz

Phase_

seg2

Prop_

seg

SCI Baud Rate

£ 115.2 kB/s

MibSPI

ADC

HET

Loop

CLK

HET

HiRes

CLK

External Clock

LIN/SCI

Phase_

seg1

HET

CAN Baud Rate

£ 1M Baud

8-MHz OSCIN

CAN (DCAN1)

A. See Table 5-9.

Figure 5-5. Device Clock Domains Block Diagram

Table 5-8. GCM Clock Source Assignments

GCM SOURCE NUMBER

CLOCK SOURCE

OSCIN

0

1

2

3

4

5

6

7

F035 FMzPLL

Reserved

LF OSC

HF OSC

Reserved

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Table 5-9. Switching Characteristics Over Recommended Operating Conditions for Clocks^{(1)(2)(3)(4)(5)}

PARAMETER

TEST CONDITIONS⁽⁶⁾

MIN

MAX

UNIT

Pipeline mode enabled

80

f_(HCLK)

System clock frequency

MHz

Pipeline mode disabled, 0

flash wait states

28

System clock frequency Flash

programming/erase

f_(PROG/ERASE)

f_(VCLK/VCLK2)

f_(ECLK)

80

f_(HCLK)

20

MHz

Peripheral VBUS clock frequency

External clock output frequency for ECP

Module

RCLK - Frequency out of PLL macro into

R-divider (Post ODPLL divider)

f_(RCLK)

145

MHz

ns

Pipeline mode enabled

12.50

35.71

t_c(HCLK)

Cycle time, system clock

Pipeline mode disabled, 0

flash wait states

Cycle time, system clock - Flash

programming/erase

t_{c(PROG/ERASE)}

12.50

ns

t_{c(VCLK/VCLK2)}

t_c(ECLK)

Cycle time, peripheral clock

t_c(HCLK)

50.0

ns

Cycle time, ECP module external clock output

Cycle time, RCLK minimum input cycle time

out of PLL macro into R-divider

t_c(RCLK)

6.90

ns

(1) f_(HCLK)= f_(OSC)/ NR *NF /ODPLL/PLLDIV; for details, see the PLL documentation. TI strongly recommends selection of NR and NF

parameters such that NF ≤ 120 and (f_(OSC)/ NR *NF) ≤ 400.

f_(VCLK)= f_(HCLK)/ X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the peripheral VBUS clock divider ratio determined by the

VCLKR[3:0] bits in the SYS module.

(2) Enabling FM mode can reduce maximum rated operating frequencies. The degree of impact is application-specific and the specific

settings, as well as the impact of the settings, should be discussed and agreed upon prior to using FM modes. Use of FM modes do not

impact the maximum rated external clock output, f_(ECLK), for the ECP module.

(3) Pipeline mode enabled or disabled is determined by FRDCNTL[2:0].

(4) f_(ECLK)= f_(VCLK)/ N, where N = {1 to 65536}. N is the ECP prescale value defined by the ECPCTRL.[15:0] register bits in the ECP

module.

(5) ECLK output will increase radiated emissions within the system that is used. Rated emissions at the device level do not include

emissions due to ECLK output.

(6) All test conditions assume FM Mode disabled and RAM ECC enabled with 0 waitstates for RAM.

RAM

0

Address Waitstates

0MHz

f(HCLK)

Data Waitstates

0

Flash

0

1

Address Waitstates

0MHz

f(HCLK)

Data Waitstates

0

2

28MHz

56MHz

Figure 5-6. Timing - Wait States

NOTE

If FMzPLL frequency modulation is enabled, special care must be taken to ensure that the

maximum system clock frequency f(HCLK) and peripheral clock frequency f(VCLK) are not

exceeded. The speed of the device clocks may need be derated to accommodate the

modulation depth when FMzPLL frequency modulation is enabled.

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5.2.5.1 ECLK Specification

Table 5-10. Switching Characteristics Over Recommended Operating Conditions for External Clocks⁽¹⁾⁽²⁾

(see Figure 5-7)

NO.

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Under all prescale factor

combinations (X and N)

1

t_w(EOL)

t_w(EOH)

Pulse duration, ECLK low

0.5_tc(ECLK)- t_f

ns

Under all prescale factor

combinations (X and N)

2

Pulse duration, ECLK high

0.5t_c(ECLK)- t_r

ns

(1) X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the VBUS interface clock divider ratio determined by the CLKCNTL.[19:16] bits in the

SYS module.

(2) N = {1 to 65536}. N is the ECP prescale value defined by the ECPCNTL.[15:0] register bits in the SYS module.

2

ECLK

1

Figure 5-7. ECLK Timing Diagram

5.2.6 TEST Pin Glitch Filter Timing

Table 5-11. Test Pin Glitch Filter Timing

NO.

PARAMETER

MIN

MAX

UNIT

Filter time TEST, high pulses less than MIN will be

filtered out.

t_f(TEST)

40

ns

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5.2.7 JTAG Timing

Table 5-12. JTAG Scan Interface Timing (JTAG Clock specification 10-MHz and 50-pF Load on TDO

Output)

(see Figure 5-8

NO.

1

MIN

50

5

MAX

UNIT

ns

t_c(JTAG)

Cycle time, JTAG low and high period

Setup time, TDI, TMS before TCK rise (TCKr)

Hold time, TDI, TMS after TCKr

2

t_{su(TDI/TMS - TCKr)}

t_{h(TCKr -TDI/TMS)}

t_{h(TCKf -TDO)}

t_{d(TCKf -TDO)}

ns

3

5

ns

4

Hold time, TDO after TCKf

5

ns

5

Delay time, TDO valid after TCK fall (TCKf)

45

ns

TCK

1

TMS

TDI

2

3

TDO

4

5

Figure 5-8. JTAG Scan Timings

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5.2.8 Output Timings

Table 5-13. Switching Characteristics for Output Timings Versus Load Capacitance (C_L)⁽¹⁾

(see Figure 5-9)

PARAMETER

MAX

4

UNIT

C_L= 15 pF

C_L= 50 pF

C_L= 100 pF

C_L= 150 pF

C_L= 15 pF

C_L= 50 pF

C_L= 100 pF

C_L= 150 pF

8

t_r

Adaptive impedance 4 mA pins

ns

15

21

5

8

t_f

Adaptive impedance 4 mA pins

ns

12

17

(1) Peripheral output timings given within this document are measured in either standard buffer or impedance control mode.

t_r

t_f

V_CCIO

80%

Output

20%

0

Figure 5-9. CMOS-Level Outputs

5.2.9 Input Timings

Table 5-14. Timing Requirements for Input Timings⁽¹⁾

(see Figure 5-10)

MIN

MAX

UNIT

t_pw

Input minimum pulse width

t_c(VCLK)+ 10

ns

(1) t_c(VCLK)= peripheral VBUS clock cycle time = 1 / f_(VCLK)

.

t_pw

V_CC

80%

Input

20%

0

Figure 5-10. CMOS-Level Inputs

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5.2.10 Flash Timings

Table 5-15. Timing Requirements for Program Flash

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX UNIT

From Sleep Mode to

Standby Mode

20

Flash pump stabilization time

Flash bank stabilization time

From Standby Mode to

Active Mode

1

1.9

0.1

t_{acc_delay}

µs

From Sleep Mode to

Standby Mode

From Standby Mode to

Active Mode

t_prog(32-bit)

t_prog(Total)

t_{erase(sector)}

Half-word (32-bit) programming time

384k-byte programming time⁽¹⁾

448k-byte programming time⁽¹⁾

Sector erase time

37.5

3.7

4.3

1.5

300

29.5

34.4

15

µs

s

Write/erase cycles at TA = -40 to 125°C with

15-year Data Retention requirement

1000⁽²⁾cycles

N_wec

Write/erase cycles at TA = -40 to 125°C

EEPROM emulation requirement for 16k flash

sectors in Bank 1

25000⁽²⁾⁽³⁾cycles

(1) t_prog(Total)programming time includes overhead of state machine, but does not include data transfer time.

(2) Flash write/erase cycles and data retention specifications are based on a validated implementation of the TI flash API. Non-TI flash API

implementation is not supported. For detailed description see the F035 Flash Validation Procedure (SPNA127).

(3) Flash write/erase cycle and data retention specifications are based on an assumed distribution of write/erase cycles over the life of the

product including an even distribution over the rated temperature range and time between cycles. The EEPROM emulation bank has

been qualified as outlined in the JEDEC specification JESD22-A117C.

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5.3 SPIn Master Mode Timing Parameters

Table 5-16. SPIn Master Mode External Timing Parameters (CLOCK PHASE = 0, SPInCLK = output,

SPInSIMO = output, and SPInSOMI = input)^(1)(2)(3)

(see Figure 5-11 and Figure 5-12)

NO.

MIN

90

MAX UNIT

256t_c(VCLK)

1

t_c(SPC)M

Cycle time, SPICLK⁽⁴⁾

Pulse duration, SPICLK high

(clock polarity = 0)

0.5t_c(SPC)M- t_r-8

0.5t_c(SPC)M+ 5

t_w(SPCH)M

2⁽⁵⁾

t_w(SPCL)M

Pulse duration, SPICLK low (clock polarity = 1)

Pulse duration, SPICLK low (clock polarity = 0)

0.5t_c(SPC)M- t_f-8

0.5t_c(SPC)M- t_r-8

0.5t_c(SPC)M+ 5

3⁽⁵⁾

Pulse duration, SPICLK high

(clock polarity = 1)

t_w(SPCH)M

Delay time, SPISIMO data valid before

SPICLK low (clock polarity = 0)

0.5t_c(SPC)M- 10

0.5t_c(SPC)M- t_f(SPC)-5

0.5t_c(SPC)M- t_r(SPC)-5

t_r(SPC)+4

t_{d(SIMO-SPCL)M}

t_{d(SIMO-SPCH)M}

t_{v(SPCL-SIMO)M}

t_{v(SPCH-SIMO)M}

t_{su(SOMI-SPCL)M}

t_{su(SOMI-SPCH)M}

t_{h(SPCL-SOMI)M}

t_{h(SPCH-SOMI)M}

4⁽⁵⁾

5⁽⁵⁾

6⁽⁵⁾

7⁽⁵⁾

Delay time, SPISIMO data valid before

SPICLK high (clock polarity = 1)

Valid time, SPISIMO data valid

(clock polarity = 0)

Valid time, SPISIMO data valid

(clock polarity = 1)

Setup time, SPISOMI before SPICLK low

(clock polarity = 0)

Setup time, SPISOMI before SPICLK high

(clock polarity = 1)

t_f(SPC)+4

ns

Hold time, SPISOMI data valid after SPICLK

low (clock polarity = 0)

10

Hold time, SPISOMI data valid after SPICLK

high (clock polarity = 1)

10

(C2TDELAY+CSHOLD+ (C2TDELAY+CSHOLD+

2)*t_c(VCLK)- t_f(SPICS)2)*t_c(VCLK)- t_f(SPICS)

t_r(SPICLK)-21 t_r(SPICLK)+6

Setup time CS active until SPICLK high

(clock polarity = 0)

+

8⁽⁵⁾⁽⁶⁾t_C2TDELAY

(C2TDELAY+CSHOLD+ (C2TDELAY+CSHOLD+

2)*t_c(VCLK)- t_f(SPICS)2)*t_c(VCLK)- t_f(SPICS)

Setup time CS active until SPICLK low

(clock polarity = 1)

+

t_f(SPICLK)-21

t_f(SPICLK)+6

9⁽⁵⁾⁽⁶⁾

0.5*t_c(SPC)M

Hold time SPICLK low until CS inactive

(clock polarity = 0)

+T2CDELAY*t_c(VCLK)

t_c(VCLK)- t_f(SPICLK)

+

+T2CDELAY*t_c(VCLK)

t_c(VCLK)- t_f(SPICLK)

+

t_r(SPICS)-4

t_r(SPICS)+17

t_T2CDELAY

0.5*t_c(SPC)M

Hold time SPICLK high until CS inactive

(clock polarity = 1)

+T2CDELAY*t_c(VCLK)

t_c(VCLK)- t_r(SPICLK)

+

+T2CDELAY*t_c(VCLK)

t_c(VCLK)- t_r(SPICLK)

+

t_r(SPICS)-4

C2TDELAY * t_c(VCLK)

t_f(SPICS)-25

t_r(SPICS)+17

10

-

C2TDELAY * t_c(VCLK)

t_SPIENA

SPIENAn sample point

ns

(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is clear.

(2) t_c(VCLK)= interface clock cycle time = 1 / f_(VCLK)

(3) For rise and fall timings, see Table 5-13.

.

(4) When the SPI is in Master mode, the following must be true:

•

For PS values from 1 to 255: t ≥ (PS +1)t_c(VCLK)≥ 90 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.

For PS values of 0: t_c(SPC)M= 2t_c(VCLK)≥ 90 ns.

(5) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

(6) C2TDELAY and T2CDELAY are programmed in the SPIDELAY register.

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1

SPICLK

(clock polarity = 0)

2

3

SPICLK

(clock polarity = 1)

4

5

SPISIMO

SPISOMI

Master Out Data is Valid

6

7

Master In Data

Must Be Valid

Figure 5-11. SPI Master Mode External Timing (CLOCK PHASE = 0)

SPICLK

(clock polarity = 0)

SPICLK

(clock polarity = 1)

SPISIMO

Master Out Data is Valid

8

9

SPICSn

10

SPIENAn

Figure 5-12. SPI Master Mode Chip Select Timing (CLOCK PHASE = 0)

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Table 5-17. SPIn Master Mode External Timing Parameters (CLOCK PHASE = 1, SPInCLK = output,

SPInSIMO = output, and SPInSOMI = input)^(1)(2)(3)

(see Figure 5-13 and Figure 5-14)

NO.

MIN

90

MAX UNIT

256t_c(VCLK)

1

t_c(SPC)M

Cycle time, SPICLK⁽⁴⁾

Pulse duration, SPICLK high

(clock polarity = 0)

0.5t_c(SPC)M- t_r-8

0.5t_c(SPC)M+ 5

t_w(SPCH)M

2⁽⁵⁾

t_w(SPCL)M

Pulse duration, SPICLK low (clock polarity = 1)

Pulse duration, SPICLK low (clock polarity = 0)

0.5t_c(SPC)M- t_f-8

0.5t_c(SPC)M- t_r-8

0.5t_c(SPC)M+ 5

3⁽⁵⁾

Pulse duration, SPICLK high

(clock polarity = 1)

t_w(SPCH)M

Valid time, SPISIMO data valid before SPICLK

high (clock polarity = 0)

0.5t_c(SPC)M- 10

0.5t_c(SPC)M- t_r(SPC)-5

0.5t_c(SPC)M- t_f(SPC)-5

t_r(SPC)+4

t_{v(SIMO-SPCH)M}

t_{v(SIMO-SPCL)M}

t_{v(SPCH-SIMO)M}

t_{v(SPCL-SIMO)M}

t_{su(SOMI-SPCH)M}

t_{su(SOMI-SPCL)M}

t_{h(SPCH-SOMI)M}

t_{h(SPCL-SOMI)M}

4⁽⁵⁾

5⁽⁵⁾

6⁽⁵⁾

7⁽⁵⁾

Valid time, SPISIMO data valid before SPICLK

low (clock polarity = 1)

Valid time, SPISIMO data valid after SPICLK

high (clock polarity = 0)

Valid time, SPISIMO data valid after SPICLK

low (clock polarity = 1)

Setup time, SPISOMI before SPICLK high

(clock polarity = 0)

ns

Setup time, SPISOMI before SPICLK low

(clock polarity = 1)

t_f(SPC)+4

Hold time, SPISOMI data valid after SPICLK

high (clock polarity = 0)

10

Hold time, SPISOMI data valid after SPICLK

low (clock polarity = 1)

10

0.5t_c(SPC)M+(C2TDELAY 0.5t_c(SPC)M+(C2TDELAY

+CSHOLD+2)*t_c(VCLK)+CSHOLD+2)*t_c(VCLK)

t_f(SPICS)+ t_r(SPICLK)-21 t_f(SPICS)+ t_r(SPICLK)+6

Setup time CS active until SPICLK high

(clock polarity = 0)

-

8⁽⁵⁾⁽⁶⁾t_C2TDELAY

0.5t_c(SPC)M+(C2TDELAY 0.5t_c(SPC)M+(C2TDELAY

+CSHOLD+2)*t_c(VCLK)+CSHOLD+2)*t_c(VCLK)

t_f(SPICS)+ t_f(SPICLK)-21 t_f(SPICS)+ t_f(SPICLK)+6

Setup time CS active until SPICLK low

(clock polarity = 1)

-

T2CDELAY*t_c(VCLK)

t_c(VCLK)- t_f(SPICLK)

+

T2CDELAY*t_c(VCLK)

t_c(VCLK)- t_f(SPICLK)

+

Hold time SPICLK low CS until inactive

(clock polarity = 0)

t_r(SPICS)-4

t_r(SPICS)+17

9⁽⁵⁾⁽⁶⁾t_T2CDELAY

T2CDELAY*t_c(VCLK)

t_c(VCLK)- t_r(SPICLK)

t_r(SPICS)-4

C2TDELAY * t_c(VCLK)

t_f(SPICS)-25

+

T2CDELAY*t_c(VCLK)

t_c(VCLK)- t_r(SPICLK)

+

Hold time SPICLK high until CS inactive

(clock polarity = 1)

t_r(SPICS)+17

10⁽⁷⁾

-

C2TDELAY * t_c(VCLK)

t_SPIENA

SPIENAn Sample Point

ns

(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is clear.

(2) t_c(VCLK)= interface clock cycle time = 1 / f_(VCLK)

(3) For rise and fall timings, see Table 5-13.

.

(4) When the SPI is in Master mode, the following must be true:

•

For PS values from 1 to 255: t ≥ (PS +1)t_c(VCLK)≥ 90 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.

For PS values of 0: t_c(SPC)M= 2t_c(VCLK)≥ 90 ns.

(5) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

(6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register.

(7) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register.

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1

SPICLK

(clock polarity = 0)

2

3

SPICLK

(clock polarity = 1)

4

5

SPISIMO

SPISOMI

Master Out Data is Valid

Data Valid

6

7

Master In Data

Must Be Valid

Figure 5-13. SPI Master Mode External Timing (CLOCK PHASE = 1)

SPICLK

(clock polarity = 0)

SPICLK

(clock polarity = 1)

SPISIMO

Master Out Data is Valid

8

9

SPICSn

10

SPIENAn

Figure 5-14. SPI Master Mode Chip Select timing (CLOCK PHASE = 1)

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5.4 SPIn Slave Mode Timing Parameters

Table 5-18. SPIn Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPInCLK = input,

SPInSIMO = input, and SPInSOMI = output)^(1)(2)(3)(4)

(see Figure 5-15 and Figure 5-16)

NO.

MIN

90

MAX UNIT

1

t_c(SPC)S

Cycle time, SPInCLK⁽⁵⁾

t_w(SPCH)S

Pulse duration, SPInCLK high (clock polarity = 0)

Pulse duration, SPInCLK low (clock polarity = 1)

Pulse duration, SPInCLK low (clock polarity = 0)

Pulse duration, SPInCLK high (clock polarity = 1)

Delay time, SPInCLK high to SPInSOMI valid (clock polarity = 0)

Delay time, SPInCLK low to SPInSOMI valid (clock polarity = 1)

30

2⁽⁶⁾

3⁽⁶⁾

4⁽⁶⁾

t_w(SPCL)S

30

t_w(SPCL)S

30

t_w(SPCH)S

30

t_{d(SPCH-SOMI)S}

t_{d(SPCL-SOMI)S}

t_rf(SOMI)+17

Valid time, SPInSOMI data valid after SPInCLK high

(clock polarity = 0)

0

t_{v(SPCH-SOMI)S}

t_{v(SPCL-SOMI)S}

ns

5⁽⁶⁾

6⁽⁶⁾

7⁽⁶⁾

Valid time, SPInSOMI data valid after SPInCLK low

(clock polarity = 1)

t_{su(SIMO-SPCL)S}

t_{su(SIMO-SPCH)S}

Setup time, SPInSIMO before SPInCLK low (clock polarity = 0)

Setup time, SPInSIMO before SPInCLK high (clock polarity = 1)

5

6

Valid time, SPInSIMO data valid after SPInCLK low

(clock polarity = 0)

t_{v(SPCL-SIMO)S}

t_{v(SPCH-SIMO)S}

t_{d(SPCL-SENAH)S}

t_{d(SPCH-SENAH)S}

t_{d(SCSL-SENAL)S}

Valid time, SPInSIMO data valid after SPInCLK high

(clock polarity = 1)

6

1.5t_c(VCLK)

t_f(ENAn)

2.5t_c(VCLK)

t_r(ENAn)+20

+

Delay time, SPIENAn high after last SPICLK low (clock polarity = 0)

Delay time, SPIENAn high after last SPICLK high (clock polarity = 1)

8

9

ns

2.5t_c(VCLK)

t_r(ENAn)+20

+

Delay time, SPIENAn low after SPICSn low (if new data has been

written to the SPI buffer)

t_c(VCLK)

t_f(ENAn)+18

+

(1) The MASTER bit (SPIGCR1.0) is clear and the CLOCK PHASE bit (SPIFMTx.16) is clear.

(2) When the SPI is in Slave mode, the following must be true: t_c(SPC)S> 2t_c(VCLK)and t_c(SPC)S≥ 90 ns.

(3) For rise and fall timings, see Table 5-13.

(4) t_c(VCLK)= interface clock cycle time = 1 / f_(VCLK)

.

(5) When the SPI is in Slave mode, the following must be true: t_w(SPCL)S> t_c(VCLK), t_w(SPCL)S≥ 30, t_w(SPCH)S> t_c(VCLK)ns and t_w(SPCH)S≥ 30

ns.

(6) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

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1

SPICLK

(clock polarity = 0)

2

3

SPICLK

(clock polarity = 1)

5

4

SPISOMI Data Is Valid

SPISOMI

SPISIMO

6

7

SPISIMO Data

Must Be Valid

Figure 5-15. SPI Slave Mode External Timing (CLOCK PHASE = 0)

SPICLK

(clock polarity = 0)

SPICLK

(clock polarity = 1)

8

SPIENAn

9

SPICSn

Figure 5-16. SPI Slave Mode Enable Timing (CLOCK PHASE = 0)

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Table 5-19. SPIn Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPInCLK = input,

SPInSIMO = input, and SPInSOMI = output)^(1)(2)(3)(4)

(see Figure 5-17 and Figure 5-18)

NO.

MIN

90

MAX UNIT

1

t_c(SPC)S

Cycle time, SPInCLK⁽⁵⁾

t_w(SPCH)S

t_w(SPCL)S

t_w(SPCH)S

Pulse duration, SPInCLK high (clock polarity = 0)

Pulse duration, SPInCLK low (clock polarity = 1)

Pulse duration, SPInCLK low (clock polarity = 0)

Pulse duration, SPInCLK high (clock polarity = 1)

30

2⁽⁶⁾

30

3⁽⁶⁾

30

Delay time, SPInSOMI data valid after SPInCLK high

(clock polarity = 0)

t_rf(SOMI)+17

t_{d(SPCH-SOMI)S}

t_{d(SPCL-SOMI)S}

t_{v(SOMI-SPCH)S}

t_{v(SOMI-SPCL)S}

4⁽⁶⁾

Delay time, SPInSOMI data valid after SPInCLK low

(clock polarity = 1)

ns

Valid time, SPInCLK high after SPInSOMI data valid

(clock polarity = 0)

0

5⁽⁶⁾

6⁽⁶⁾

7⁽⁶⁾

Valid time, SPInCLK low after SPInSOMI data valid

(clock polarity = 1)

t_{su(SIMO-SPCH)S}

t_{su(SIMO-SPCL)S}

Setup time, SPInSIMO before SPInCLK high (clock polarity = 0)

Setup time, SPInSIMO before SPInCLK low (clock polarity = 1)

5

6

Valid time, SPInSIMO data valid after SPInCLK high

(clock polarity = 0)

t_{v(SPCH-SIMO)S}

t_{v(SPCL-SIMO)S}

t_{d(SPCH-SENAH)S}

t_{d(SPCL-SENAH)S}

t_{d(SCSL-SENAL)S}

Valid time, SPInSIMO data valid after SPInCLK low

(clock polarity = 1)

6

1.5t_c(VCLK)

t_f(ENAn)

2.5t_c(VCLK)

+

Delay time, SPIENAn high after last SPICLK high (clock polarity = 0)

Delay time, SPIENAn high after last SPICLK low (clock polarity = 1)

tr(ENAn)+20

8

9

ns

2.5t_c(VCLK)

+

t_r(ENAn)+20

Delay time, SPIENAn low after SPICSn low (if new data has been

written to the SPI buffer)

t_c(VCLK)

+

ns

t_f(ENAn)+18

Delay time, SOMI valid after SPICSn low (if new data has been

written to the SPI buffer)

t_c(VCLK)

2t_c(VCLK)

t_rf(SOMI)+17

+

10 t_{d(SCSL-SOMI)S}

(1) The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is set.

(2) When the SPI is in Slave mode, the following must be true: t_c(SPC)S> 2t_c(VCLK)and t_c(SPC)S≥ 90 ns.

(3) For rise and fall timings, see Table 5-13.

(4) t_c(VCLK)= interface clock cycle time = 1 /f(VCLK).

(5) When the SPI is in Slave mode, the following must be true: t_w(SPCL)S> t_c(VCLK), t_w(SPCL)S≥ 30, t_w(SPCH)S> t_c(VCLK)ns and t_w(SPCH)S≥ 30

ns.

(6) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

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1

SPICLK

(clock polarity = 0)

2

3

SPICLK

(clock polarity = 1)

4

5

SPISOMI

SPISIMO

SPISOMI Data is Valid

Data Valid

6

7

SPISIMO Data

Must Be Valid

Figure 5-17. SPI Slave Mode External Timing (CLOCK PHASE = 1)

SPICLK

(clock polarity = 0)

SPICLK

(clock polarity = 1)

8

SPIENAn

SPICSn

9

10

SPISOMI

Slave Out is Valid

Figure 5-18. SPI Slave Mode Enable Timing (CLOCK PHASE = 1)

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5.5 CAN Controller (DCANn) Mode Timings

Table 5-20. Dynamic Characteristics for the CANnSTX and CANnSRX Pins

PARAMETER

Delay time, transmit shift register to CANnSTX pin⁽¹⁾

MIN

MAX

15

UNIT

ns

t_d(CANnSTX)

t_d(CANnSRX)

Delay time, CANnSRX pin to receive shift register

6

ns

(1) These values do not include rise/fall times of the output buffer.

5.6 High-End Timer (HET) Timings

Table 5-21. Dynamic Characteristics for the HET Pins

PARAMETER

MIN

MAX

UNIT

ns

t_opw(HET)

t_ipw(HET)

Output pulse width, this is the minimum pulse width that can be generated⁽¹⁾

Input pulse width, this is the minimum pulse width that can be captured⁽²⁾

1/f_(VCLK2)

ns

(1) t_opw(HET)_min= HRP_(min)= hr_(min)/ VCLK2.

(2) t_ipw(HET) = LRP_(min)= hr_(min)* lr_(min)/ VCLK2.

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5.7 Multi-Buffered A-to-D Converter (MibADC)

The multi-buffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that

enhances the A-to-D performance by preventing digital switching noise on the logic circuitry which could

be present on VSS and VCC from coupling into the A-to-D analog stage. All A-to-D specifications are

given with respect to ADREFLO unless otherwise noted.

Resolution

10 bits (1024 values)

Assured

Monotonic

Output conversion code

00h to 3FFh [00 for V_AI≤ AD_REFLO; 3FF for V_AI≥ A_DREFHI

]

Table 5-22. MibADC Recommended Operating Conditions⁽¹⁾

MIN

3.0

MAX

V_CCAD

0.3

UNIT

AD_REFHI

AD_REFLO

V_AI

A-to-D high -voltage reference source

A-to-D low-voltage reference source

Analog input voltage

V

V_SSAD

AD_REFLO

AD_REFHI

I_AIC

Analog input clamp current⁽²⁾

(V_AI< V_SSAD- 0.3 or V_AI> V_CCAD+ 0.3)

- 2

2

mA

(1) For V_CCADand V_SSADrecommended operating conditions, see .

(2) Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.

Table 5-23. MibADC Operating Characteristics Over Full Range of Recommended Operating

Conditions⁽¹⁾

PARAMETER

DESCRIPTION/CONDITIONS

See Figure 5-19

MIN

NOM

125

MAX

1.5K

16

UNIT

Ω

R_mux

R_samp

C_mux

C_samp

I_AIL

Analog input mux on-resistance

ADC sample switch on-resistance

Input mux capacitance

See Figure 5-19

150

Ω

See Figure 5-19

pF

nA

mA

ADC sample capacitance

Analog input leakage current

AD_REFHIinput current

See Figure 5-19

8

Input leakage per ADC input pin

AD_REFHI= 3.6 V, AD_REFLO= V_SSAD

ADREFHI - ADREFLO

-200

3

200

5

I_ADREFHI

CR

Conversion range over which

specified accuracy is maintained

3.6

V

E_DNL

Differential non-linearity error

Difference between the actual step

width and the ideal value (see

Figure 5-20).

± 2

LSB

E_INL

Integral non-linearity error

Maximum deviation from the best

straight line through the MibADC.

MibADC transfer characteristics,

excluding the quantization error (see

Figure 5-21).

± 2

LSB

E_TOT

Total error/Absolute accuracy

Maximum value of the difference

between an analog value and the

ideal midstep value (see Figure 5-22).

(1) 1 - LSB = (AD_REFHI– AD_REFLO)/ 2¹⁰for the MibADC.

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5.7.1 MibADC Input Model

Smux Rmux

I_AIL

Smux Rmux

Ssamp Rsamp

I_AIL

Cmux

Csamp

Figure 5-19. MibADC Input Equivalent Circuit

Table 5-24. Multi-Buffer ADC Timing Requirements

PARAMETER

Cycle time, MibADC clock

MIN

0.05

1

NOM

MAX

UNIT

µs

t_c(ADCLK)

t_d(SH)

Delay time, sample and hold time

µs

t_d(C)

Delay time, conversion time

0.55

1.55

µs

(1)

t_d(SHC)

Delay time, total sample/hold and conversion time

µs

(1) This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors.

60

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The differential non-linearity error shown in Figure 5-20 (sometimes referred to as differential linearity) is

the difference between an actual step width and the ideal value of 1 LSB.

0 ... 110

0 ... 101

0 ... 100

0 ... 011

Differential Linearity

Error (1/2 LSB)

1 LSB

0 ... 010

0 ... 001

0 ... 000

Differential Linearity

Error (-1/2 LSB)

1 LSB

0

1

2

3

4

5

Analog Input Value (LSB)

A. 1 LSB = (AD_REFHI– AD_REFLO)/2¹⁰

Figure 5-20. Differential Non-linearity (DNL)

The integral non-linearity error shown in Figure 5-21 (sometimes referred to as linearity error) is the

deviation of the values on the actual transfer function from a straight line.

0 ... 111

0 ... 110

Ideal

Transition

0 ... 101

0 ... 100

0 ... 011

0 ... 010

0 ... 001

0 ... 000

Actual

Transition

At Transition

011/100

(-1/2 LSB)

End-Point Lin. Error

At Transition

001/010 (-1/4 LSB)

6

0

1

2

3

4

5

7

Analog Input Value (LSB)

A. 1 LSB = (AD_REFHI– AD_REFLO)/2¹⁰

Figure 5-21. Integral Non-linearity (INL) Error

The absolute accuracy or total error of an MibADC as shown in Figure 5-22 is the maximum value of the

difference between an analog value and the ideal midstep value.

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0 ... 111

0 ... 110

0 ... 101

0 ... 100

0 ... 011

0 ... 010

0 ... 001

0 ... 000

Total Error

At Step 0 ... 101

(-1 1/4 LSB)

Total Error

at Step 0 ... 001

(1/2 LSB)

6

0

1

2

3

4

5

7

Analog Input Value (LSB)

A. 1 LSB = (AD_REFHIµ– AD_REFLO)/2¹⁰

Figure 5-22. Absolute Accuracy (Total) Error

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6 Revision History

This data sheet revision history highlights the technical changes made to the device or the datasheet.

Date

Additions, Deletions, And Modifications

Revision

August 2011

Added descriptions for the ENZ pin.

A

December 2011

Corrected number of GIO pins available from 8 to 4 in Device Characteristics table

Updated LBIST section to include support for STCCLK = HCLK

Added additional detail about MBIST cycle counts

Operating Conditions and electrical specs upated with characterized values

Added upper limit to Vreg ramp specification

B

Removed support for low power modes

Added TEST Pin Glitch Filter Timing specification

Added note about back to back write/erase cycling in the EEPROM emulation bank.

Added FMPLL validated settings table

January 2012

Updated programming times in the Flash Timings table.

Corrected programming word size from 16-bit to 32-bit in the Flash Timings table to accurately

reflect the default FSM configuration.

C

Added assumed use case and qualification standards for EEPROM emulation use in an

application in the Flash Timings table.

Revision History

63

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7 Mechanical Data

7.1 Thermal Data

Table 7-1 shows the thermal resistance characteristics for the PQFP - PZ mechanical packages.

Table 7-1. Thermal Resistance Characteristics

(S-PQFP Package) [PZ]

PARAMETER

R_θJA

°C/W

48

R_θJC

5

7.2 Packaging Information

The following packaging information reflects the most current released data available for the designated

device(s). This data is subject to change without notice and without revision of this document.

64

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MECHANICAL DATA

MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996

PZ (S-PQFP-G100)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

75

M

0,08

51

50

76

26

100

0,13 NOM

1

25

12,00 TYP

Gage Plane

14,20

SQ

13,80

0,25

16,20

SQ

0,05 MIN

0°–7°

15,80

1,45

1,35

0,75

0,45

Seating Plane

0,08

1,60 MAX

4040149/B 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

1

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型号：	S4MF04207SPZQQ1
厂家：	TEXAS INSTRUMENTS
描述：	TMS470MF04207/TMS470MF03107 16/32-Bit RISC Flash Microcontroller TMS470MF04207 / TMS470MF03107 16位/ 32位RISC闪存微控制器闪存微控制器和处理器外围集成电路装置时钟
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