PINA350ABSIDDFR_技术文档

INA350

SBOSAA0A – NOVEMBER 2021 – REVISED DECEMBER 2021

INA350 Cost and Size Optimized, Low Power, 1.8-V to 5.5-V Selectable Gain

Instrumentation Amplifier

1 Features

3 Description

•

Ideal for size, cost, and power conscious designs

Selectable gain options

INA350 is a selectable-gain instrumentation amplifier

that offers four gain options across INA350ABS and

INA350CDS variants available in small packages.

INA350ABS has gain options of 10 or 20 and

INA350CDS has gain options of 30 or 50. These

gain options can be selected by toggling the gain

select (GS) pin. INA350 is ideal for bridge-type

sensing and for differential to single-ended conversion

applications.

– G = 10 or G = 20 (INA350ABS)

– G = 30 or G = 50 (INA350CDS)

Space saving ultra-small package options

– 10-pin X2QFN (RUG) – 3 mm²

– 8-pin WSON (DSG) – 4 mm²

•

– 8-pin SOT23-THN (DDF) – 4.64 mm²

Optimized performance for 10-bit to 14-bit systems

– CMRR: 95 dB (typ) across all gains

– Offset voltage: 0.2 mV (typ) across all gains

– Gain error (typ):

Built with precision matched integrated resistors,

INA350 saves on BOM costs, pick-and-place machine

handling costs, and board space by removing

the need for precise or closely-matched external

resistors. The device interface directly to low-speed,

10-bit to 14-bit, analog-to-digital converters (ADC)

and is ideal for replacing discrete implementation

of instrumentation amplifiers built with commodity

amplifiers and discrete resistors.

•

0.05% for G = 10; 0.06% for G = 20

0.075% for G = 30; 0.082% for G = 50

•

Bandwidth: 100 kHz for G = 10 (typ)

Drives 500 pF with less than 20% overshoot (typ)

Optimized quiescent current: 100 µA (typ)

Shutdown option for power conscious applications

Supply range: 1.8 V (±0.9 V) to 5.5 V (±2.75 V)

Specified temperature range: –40°C to 125°C

Designed with the three-amplifier architecture, INA350

is optimized for delivering performance. It achieves

85 dB of minimum CMRR and 0.6% of maximum

gain error, along with 1.2 mV of maximum offset

across all gain options, while consuming just 125 µA

of maximum quiescent current. It has an integrated

shutdown option to turn off the amplifier when idle

for additional power savings in battery powered

applications.

2 Applications

•

Bridge network sensing

Differential to single-ended conversion

Weigh scale

Analog input module

Flow transmitter

Wearable fitness and activity monitor

Blood glucose monitor

Pressure and temperature sensing

Device Information

PART NUMBER

PACKAGE⁽¹⁾

BODY SIZE (NOM)

2.00 mm × 2.00 mm

1.60 mm × 2.90 mm

1.50 mm × 2.00 mm

V+

WSON (8)

INA350ABS,

SOT-23 (8)

INA350CDS⁽³⁾

IN

60 k

+

–

60 k

X2QFN (10)⁽²⁾

(1) For all available packages, see the package option

addendum at the end of the data sheet.

(2) This package is preview only.

–

+

90 k / 145 k

R_G

GS

OUT

REF

(3) INA350CDS part number is on preview.

–

+

60 k

+IN

_____

SHDN

V

Note: 90 kΩ for INA350ABS and 145 kΩ for INA350CDS

Simplified Internal Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

INA350

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SBOSAA0A – NOVEMBER 2021 – REVISED DECEMBER 2021

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 6

7.1 Absolute Maximum Ratings........................................ 6

7.2 ESD Ratings .............................................................. 6

7.3 Recommended Operating Conditions.........................6

7.4 Thermal Information....................................................6

7.5 Electrical Characteristics.............................................7

7.6 Typical Characteristics................................................9

8 Detailed Description......................................................19

8.1 Overview...................................................................19

8.2 Functional Block Diagram.........................................19

8.3 Feature Description...................................................20

8.4 Device Functional Modes..........................................24

9 Application and Implementation..................................25

9.1 Application Information............................................. 25

9.2 Typical Applications.................................................. 27

10 Power Supply Recommendations..............................30

11 Layout...........................................................................30

11.1 Layout Guidelines................................................... 30

11.2 Layout Example...................................................... 31

12 Device and Documentation Support..........................32

12.1 Device Support....................................................... 32

12.2 Documentation Support.......................................... 32

12.3 Receiving Notification of Documentation Updates..32

12.4 Support Resources................................................. 32

12.5 Trademarks.............................................................32

12.6 Electrostatic Discharge Caution..............................32

12.7 Glossary..................................................................32

13 Mechanical, Packaging, and Orderable

Information.................................................................... 33

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (November 2021) to Revision A (December 2021)

Page

•

Changed the device status from Advance Information to Production Data ....................................................... 1

2

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5 Device Comparison Table

PACKAGE LEADS

NO. OF

CHANNELS

DEVICE

SOT-23-8

DDF

WSON

DSG

X2QFN

RUG⁽²⁾

INA350ABS

1

8

INA350CDS⁽¹⁾

(1) Device is preview only.

(2) Package is preview only.

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6 Pin Configuration and Functions

GS

IN–

IN+

V–

1

2

3

4

8

7

6

5

SHDN

V+

GS

IN–

IN+

V–

1

2

3

4

8

7

6

5

SHDN

V+

Thermal

Pad

OUT

REF

OUT

REF

Not to scale

Figure 6-1. DDF Package

8-Pin SOT-23

Note: Connect Thermal Pad to (V−)

Figure 6-2. DSG Package

8-Pin WSON With Exposed Thermal Pad

(Top View)

Table 6-1. Pin Functions

I/O

DESCRIPTION

NAME

IN–

NO.

2

3

6

5

I

Negative (inverting) input

Positive (non-inverting) input

Output

IN+

O

—

OUT

REF

Reference input. This pin must be driven by a low impedance source.

Gain select – logic low (G = 10 for INA350ABS and G = 30 for INA350CDS)

Gain select – logic high (G = 20 for INA350ABS and G = 50 for INA350CDS)

Gain select – no connect (G = 20 for INA350ABS and G = 50 for INA350CDS)

GS

1

8

I

Shutdown – logic high (device enabled)

Shutdown – logic low (device disabled)

Shutdown – no connect (device enabled)

SHDN

V–

V+

4

7

—

Negative supply

Positive supply

4

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GS

IN–

IN+

V–

1

2

3

4

9

8

7

6

SHDN

V+

OUT

REF

Not to scale

Figure 6-3. RUG Package

10-Pin X2QFN

(Top View)

Table 6-2. Pin Functions

I/O

DESCRIPTION

NAME

IN–

NO.

2

I

Negative (inverting) input

IN+

3

O

—

Positive (noninverting) input

OUT

REF

7

Output

6

Reference input. This pin must be driven by a low impedance source.

Gain select – logic low (G = 10 for INA350ABS and G = 30 for INA350CDS)

Gain select – logic high (G = 20 for INA350ABS and G = 50 for INA350CDS)

Gain select – no connect (G = 20 for INA350ABS and G = 50 for INA350CDS)

GS

1

9

I

Shutdown – logic high (device enabled)

Shutdown – logic low (device disabled)

Shutdown – no connect (device enabled)

SHDN

V–

V+

NC

4

8

—

Negative supply

Positive supply

No connect

5, 10

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

0

MAX

6

UNIT

V

Supply voltage, V_S= (V+) – (V–)

Common mode voltage⁽²⁾

(V–) – 0.5

(V+) + 0.5

V_S+ 0.2

10

V

Signal input pins

Differential voltage⁽³⁾

Current⁽²⁾

V

–10

mA

Output short-circuit⁽⁴⁾

Continuous

Operating Temperature, T_A

Junction Temperature, T_J

Storage Temperature, T_stg

–55

150

°C

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be

current limited to 10 mA or less

(3) Differential input voltages greater than 0.5 V applied continuously can result in a shift to the input offset voltage above the maximum

specification of this parameter. The magnitude of this effect increases as the ambient operating temperature rises.

(4) Short-circuit to V_S/ 2.

7.2 ESD Ratings

VALUE

±2000

±1000

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.8

MAX

5.5

UNIT

Single-supply

Dual-supply

Supply voltage V_S= (V+) – (V–)

V

±0.9

(V–)

–40

±2.75

(V+)

125

Input Voltage Range

Specified temperature

V

Specified temperature

°C

7.4 Thermal Information

INA350ABS, INA350CDS

DDF (SOT-23-

THERMAL METRIC⁽¹⁾

DSG (WSON)

RUG (X2QFN)

UNIT

THN)

8 PINS

169.1

101.7

84.8

8 PINS

89.2

111.8

55.8

9.3

10 PINS

TBD

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

Junction-to-top characterization parameter

°C/W

R_θJC(top)

R_θJB

TBD

ψ_JT

12.6

TBD

ψ_JB

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

84.3

55.7

31.0

TBD

R_θJC(bot)

n/a

TBD

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6

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7.5 Electrical Characteristics

For V_S= (V+) – (V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V) at T_A= 25°C, V_REF= V_S/2, G = 10, R_L= 10 kΩ connected to V_S/ 2,

V_CM= [(V_IN+) + (V_IN–)] / 2 = V_S/ 2, V_IN= (V_IN+) – (V_IN–) = 0 V and V_OUT= V_S/ 2 (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT

V_OSI

Offset Voltage, RTI^{(7) (1)}

V_S= 5.5 V, G = 10, 20, 30, 50

T_A= 25°C

±0.2

±1.2

±1.3

mV

Offset Voltage over T,

RTI^{(7) (1)}

V_OSI

T_A= –40°C to 125°C

T_A= 25°C

V_OSI

Offset temp drift, RTI^{(7) (2)}V_S= 5.5 V, G = 10, 20, 30, 50

±0.6

20

µV/°C

µV/V

Power-supply rejection

G = 10, 20, 30, 50

ratio⁽⁷⁾

PSRR

Z_IN-DM

Z_IN-CM

75

Differential Impedance

100 || 5

100 || 9

GΩ || pF

Common Mode

Impedance

Input Stage Common

Mode Range⁽³⁾

V_CM

(V–)

85

(V+)

V

CMRR

DC

Common-mode rejection G = 10, 20, 30, 50, V_CM= (V–) + 0.1

V_S= 5.5 V, V_REF= V_S/2

V_S= 3.3 V, V_REF= V_S/2

V_S= 5.5 V, V_REF= V_S/2

95

94

75

dB

ratio, RTI⁽⁷⁾

V to (V+) – 1 V, High CMRR Region

CMRR

DC

Common-mode rejection G = 10, 20, 30, 50, V_CM= (V–) + 0.1

ratio, RTI⁽⁷⁾

V to (V+) – 1 V, High CMRR Region

CMRR

DC

Common-mode rejection G = 10, 20, 30, 50, V_CM= (V–) + 0.1

62

ratio, RTI⁽⁷⁾

V to (V+) – 0.1 V

BIAS CURRENT

I_B

Input bias current

Input offset current

V_CM= V_S/ 2

±0.65

±0.25

pA

I_OS

NOISE VOLTAGE

Input referred voltage

e_NI

E_NI

G = 10, 20, 30, 50

f = 1 kHz

43

41

nV/√Hz

noise density^{(7) (5)}

Input referred voltage

noise density^{(7) (5)}

f = 10 kHz

Input referred voltage

noise⁽⁵⁾

G = 10, f_B= 0.1 Hz to 10 Hz

f = 1 kHz

4

µV_PP

i_n

Input current noise

f = 1 kHz

22

fA/√Hz

GAIN

G = 10, V_REF= V_S/2

G = 20, V_REF= V_S/2

G = 30, V_REF= V_S/2

G = 50, V_REF= V_S/2

±0.05

±0.06

±0.50

±0.60

Gain error⁽⁴⁾

V_O= (V–) + 0.1 V to

(V+) – 0.1V

GE

%

±0.075

±0.082

Gain error^{(4) (7)}

OUTPUT

V_OH

Positive rail headroom

Negative rail headroom

R_L= 10 kΩ to V_S/2

15

30

mV

pF

V_OL

R_L= 10 kΩ to V_S/2

C_LDrive Load capacitance drive

V_O= 100 mV step, Overshoot < 20%

500

Closed-loop output

impedance

Z_O

f = 10 kHz

V_S= 5.5 V

51

Ω

I_SC

Short-circuit current

±20

mA

FREQUENCY RESPONSE

G = 10

G = 20

G = 30

G = 50

100

50

Bandwidth, –3 dB

BW

V_IN= 10 mV_pk-pk

kHz

%

40

Bandwidth, –3 dB⁽⁷⁾

25

Total harmonic distortion + V_S= 5.5 V, V_CM= 2.75 V, V_O= 1 V_RMS, G = 10, R_L= 100 kΩ

THD + N

0.040

noise

ƒ = 1 kHz, 80-kHz measurement BW

Electro-magnetic

interference rejection ratio

EMIRR

SR

f = 1 GHz, V_{IN_EMIRR}= 100 mV

96

dB

Slew rate⁽⁷⁾

V_S= 5 V, V_O= 2 V step, G = 10, 20, 30, 50

0.24

V/µs

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7.5 Electrical Characteristics (continued)

For V_S= (V+) – (V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V) at T_A= 25°C, V_REF= V_S/2, G = 10, R_L= 10 kΩ connected to V_S/ 2,

V_CM= [(V_IN+) + (V_IN–)] / 2 = V_S/ 2, V_IN= (V_IN+) – (V_IN–) = 0 V and V_OUT= V_S/ 2 (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

17

38

20

27

40

57

53

60

16

MAX

UNIT

G = 10, To 0.1%, V_S= 5.5 V, V_STEP= 2 V, C_L= 10 pF

G = 10, To 0.01%, V_S= 5.5 V, V_STEP= 2 V, C_L= 10 pF

G = 20, To 0.1%, V_S= 5.5 V, V_STEP= 2 V, C_L= 10 pF

G = 20, To 0.01%, V_S= 5.5 V, V_STEP= 2 V, C_L= 10 pF

G = 30, To 0.1%, V_S= 5.5 V, V_STEP= 2 V, C_L= 10 pF

G = 30, To 0.01%, V_S= 5.5 V, V_STEP= 2 V, C_L= 10 pF

G = 50, To 0.1%, V_S= 5.5 V, V_STEP= 2 V, C_L= 10 pF

G = 50, To 0.01%, V_S= 5.5 V, V_STEP= 2 V, C_L= 10 pF

V_IN= 1 V, G = 10

Settling time

t_S

µs

Settling time⁽⁷⁾

Overload recovery

µs

REFERENCE INPUT

R_INInput impedance

60

kΩ

V

Voltage range

(V–)

(V+)

Gain to output

1

V/V

%

Reference gain error

±0.004

POWER SUPPLY

V_S

Power-supply voltage

Single-supply

Dual-supply

1.7

5.5

±2.75

125

V

Power-supply voltage

±0.85

V_IN= 0 V

100

I_Q

Quiescent current

µA

T_A= –40°C to 125°C

135

Quiescent current per

amplifier

I_QSD

V_IL

V_IH

t_ON

All amplifiers disabled, SHDN = V–

0.70

1.25

µA

V

Logic low threshold

G = 10 for INA350ABS, G = 30 for INA350CDS

G = 20 for INA350ABS, G = 50 for INA350CDS

(V–) + 0.2 V

voltage (Gain Select)⁽⁷⁾

Logic high threshold

(V–) + 1 V

V

voltage (Gain Select)⁽⁷⁾

Amplifier enable time (full G = 10, V_CM= V_S/ 2, V_O= 0.9 × V_S/ 2,

100

5

µs

nA

shutdown) ⁽⁶⁾

R_Lconnected to V–

G = 10, V_CM= V_S/ 2, V_O= 0.1 × V_S/ 2,

R_Lconnected to V–

t_OFF

Amplifier disable time ⁽⁶⁾

SHDN pin input bias

current (per pin)

(V+) ≥ SHDN ≥ (V–) + 1 V

(V–) ≤ SHDN ≤ (V–) + 0.2 V

10

SHDN pin input bias

current (per pin)

175

(1) Total offset, referred-to-input (RTI): V_OS= (V_OSI) + (V_OSO/ G).

(2) Offset drifts are uncorrelated. Input-referred offset drift is calculated using: ΔV_OS(RTI)= √[ΔV_OSI²+ (ΔV_OSO/ G)²]

(3) Input common mode voltage range of the just the input stage of the instrumentation amplifier. The entire INA350x input range depends

on the combination input common-mode voltage, differential voltage, gain, reference voltage and power supply voltage. Typical

Characteristic curves will be added with more information.

(4) Min and Max values are specified by characterization.

(5) Total RTI voltage noise is equal to: e_N(RTI)= √[e_NI²+ (e_NO/ G)²]

(6) Disable time (t_OFF) and enable time (t_ON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin

and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.

(7) G = 30 and G = 50 data are provided as advance information

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7.6 Typical Characteristics

at T_A= 25°C, V_S= (V+) – (V–) = 5.5 V, V_IN= (V_IN+) – (V_IN–) = 0 V, R_L= 10 kΩ, C_L= 10 pF, V_REF= V_S/ 2, V_CM= [(V_IN+) +

(V_IN–)] / 2 = V_S/ 2, V_OUT= V_S/ 2 and G = 10 (unless otherwise noted)

27.5

25

22.5

20

22.5

20

17.5

15

17.5

15

12.5

10

12.5

10

7.5

5

7.5

5

2.5

0

2.5

0

H05_

H06_

Input Offset Voltage Drift (µV/°C)

Input Offset Voltage (µV)

G = 10, 20 N = 72

μ = 0.35 μV/°C

σ = 0.25 μV/°C

G = 10, 20

N = 72

μ = –24 μV

σ = 0.2 mV

Figure 7-2. Typical Distribution of Input Referred Offset Drift

Figure 7-1. Typical Distribution of Input Referred Offset Voltage

45

40

35

30

25

20

15

10

5

50

45

40

35

30

25

20

15

10

5

0

H13_

H15_

Input Bias Current (pA)

Input Offset Current (pA)

T_A= 25°C

N = 72

μ = 0.40 pA

σ = 0.15 pA

T_A= 25°C

N = 36

μ = –0.03 pA

σ = 0.23 pA

Figure 7-3. Typical Distribution of Input Bias Current

Figure 7-4. Typical Distribution of Input Offset Current

30

25

20

15

10

5

25

20

15

10

5

0

H14_

H16_

Input Offset Current (pA)

N = 36 μ = –1 pA

Input Bias Current (pA)

T_A= 85°C

σ = 1 pA

T_A= 85°C

N = 72

μ = 22 pA

σ = 0.95 pA

Figure 7-6. Typical Distribution of Input Offset Current

Figure 7-5. Typical Distribution of Input Bias Current

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7.6 Typical Characteristics (continued)

at T_A= 25°C, V_S= (V+) – (V–) = 5.5 V, V_IN= (V_IN+) – (V_IN–) = 0 V, R_L= 10 kΩ, C_L= 10 pF, V_REF= V_S/ 2, V_CM= [(V_IN+) +

(V_IN–)] / 2 = V_S/ 2, V_OUT= V_S/ 2 and G = 10 (unless otherwise noted)

36

32

28

24

20

16

12

8

20

18

16

14

12

10

8

6

4

2

0

H17_

H18_

Input Common-Mode Rejection Ratio (mV/V)

G = 20

N = 36

μ = 2.33 μV/V σ = 8.45 μV/V

G = 10

N = 36

μ = 2.50 μV/V σ = 8.92 μV/V

Figure 7-8. Typical Distribution of CMRR

Figure 7-7. Typical Distribution of CMRR

1200

1000

800

1200

1000

800

600

400

200

0

-200

-400

-600

-800

-1000

-1200

-200

-400

-600

-800

-1000

-1200

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

T01_

T02_

G = 10

G = 20

Figure 7-9. Input Referred Offset Voltage vs Temperature

Figure 7-10. Input Referred Offset Voltage vs Temperature

0.4

20

I_B-

I_B+

0.3

16

12

8

0.2

0.1

0

4

-0.1

0

-0.2

-4

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

T05_

T06_

Figure 7-11. Input Bias Current vs Temperature

Figure 7-12. Input Offset Current vs Temperature

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7.6 Typical Characteristics (continued)

at T_A= 25°C, V_S= (V+) – (V–) = 5.5 V, V_IN= (V_IN+) – (V_IN–) = 0 V, R_L= 10 kΩ, C_L= 10 pF, V_REF= V_S/ 2, V_CM= [(V_IN+) +

(V_IN–)] / 2 = V_S/ 2, V_OUT= V_S/ 2 and G = 10 (unless otherwise noted)

100

1650

1500

1350

1200

1050

900

Vs = 1.8 V

Vs = 3.3 V

Vs = 5.5 V

95

90

750

600

85

450

Vs = 1.8 V

Vs = 3.3 V

Vs = 5.5 V

300

80

150

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

T07_

T08_

Figure 7-13. Quiescent Current vs Temperature

Figure 7-14. Shutdown Quiescent Current vs Temperature

55

45

35

25

15

5

0.45

Isc(-), Vs = 3.3 V

Isc(-), Vs = 5.5 V

Isc(+), Vs = 3.3 V

Isc(+), Vs = 5.5 V

G = 10

G = 20

0.4

0.35

0.3

0.25

0.2

0.15

0.1

0.05

0

-0.05

-0.1

-0.15

-0.2

-0.25

-0.3

-0.35

-5

-15

-25

-35

-45

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

t09_

T13_

Figure 7-16. Gain Error vs Temperature

Figure 7-15. Short Circuit Current vs Temperature

125

2000

1600

1200

800

100

75

50

25

0

400

0

-400

-800

-1200

-1600

-2000

G = 10

G = 20

-2.75

-1.75

-0.75

0.25

Input Common-Mode Voltage (V)

1.25

2.25

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

C01_

T11_

V+ = 2.75 V and V– = –2.75 V

Figure 7-18. Input Referred Offset Voltage vs Input Common-

Mode Voltage

Figure 7-17. CMRR vs Temperature

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7.6 Typical Characteristics (continued)

at T_A= 25°C, V_S= (V+) – (V–) = 5.5 V, V_IN= (V_IN+) – (V_IN–) = 0 V, R_L= 10 kΩ, C_L= 10 pF, V_REF= V_S/ 2, V_CM= [(V_IN+) +

(V_IN–)] / 2 = V_S/ 2, V_OUT= V_S/ 2 and G = 10 (unless otherwise noted)

2000

1600

1200

800

5

0

-5

400

0

-10

-15

-20

-400

-800

-1200

-1600

-2000

I_B-

I_B+

-2.75

-2

-1.25

-0.5

0.25

1

Input Common-Mode Voltage (V)

1.75

2.5

-1.65

-1.15

-0.65

-0.15

0.35

Input Common-Mode Voltage (V)

0.85

1.35 1.65

C04_

C02_

V+ = 2.75 V and V– = –2.75 V

V+ = 1.65 V and V– = –1.65 V

Figure 7-20. Input Bias Current vs Input Common-Mode Voltage

Figure 7-19. Input Referred Offset Voltage vs Input Common-

Mode Voltage

2

1.75

1.5

1.25

1

0.75

0.5

0.25

0

-0.25

-0.5

-0.75

-1

-1.25

-1.5

-1.75

-2

135

130

125

120

115

110

105

100

95

90

-2.75

-2

-1.25

Input Common-Mode Voltage (V)

-0.5

0.25

1

1.75

2.5

-2.75

-2

-1.25

Input Common-Mode Voltage (V)

-0.5

0.25

1

1.75

2.5

C05_

C03_

V+ = 2.75 V and V– = –2.75 V

Figure 7-21. Input Offset Current vs Input Common-Mode

Voltage

Figure 7-22. Quiescent Current vs Input Common-Mode Voltage

1200

1000

800

100

600

95

90

85

400

200

0

-200

-400

-600

-800

-1000

-1200

80

1.75

2.25

2.75

3.25

3.75

Supply Voltage (V)

4.25

4.75

5.25

1.7 2.1 2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3

Supply Voltage (V)

C06_

C07_

G = 10

Figure 7-23. Input Referred Offset Voltage vs Supply Voltage

Figure 7-24. Quiescent Current vs Supply Voltage

12

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7.6 Typical Characteristics (continued)

at T_A= 25°C, V_S= (V+) – (V–) = 5.5 V, V_IN= (V_IN+) – (V_IN–) = 0 V, R_L= 10 kΩ, C_L= 10 pF, V_REF= V_S/ 2, V_CM= [(V_IN+) +

(V_IN–)] / 2 = V_S/ 2, V_OUT= V_S/ 2 and G = 10 (unless otherwise noted)

3

2.5

2

4

3.5

3

Vs = 1.8 V

Vs = 5.5 V

1.5

1

2.5

2

0.5

0

1.5

1

-0.5

-1

0.5

0

-1.5

-2

-0.5

-1

-2.5

-3

-1.5

-2

Vs = 1.8 V

Vs = 5.5 V

-3.5

-4

-2.5

-3

0

5

10

15

Output Current (mA)

20

25

30

0

5

10

15

Output Current (mA)

20

25

30

C10_

C11_

Figure 7-25. Output Voltage vs Output Current (Sourcing)

Figure 7-26. Output Voltage vs Output Current (Sinking)

30

120

G = 10

G = 20

G = 10

G = 20

26

100

80

22

18

14

10

6

60

2

40

-2

-6

20

-10

10

100

1k 10k

Frequency (Hz)

100k

1M

10

100

1k 10k

Frequency (Hz)

100k

1M

A02_

A01_

Figure 7-28. CMRR (Referred to Input) vs Frequency

Figure 7-27. Closed-Loop Gain vs Frequency

120

100

80

60

40

20

0

120

G = 10

G = 20

G = 10

G = 20

100

80

60

40

20

0

10

100

1k 10k

Frequency (Hz)

100k

1M

10

100

1k 10k

Frequency (Hz)

100k

1M

A04_

A05_

Figure 7-29. PSRR+ (Referred to Input) vs Frequency

Figure 7-30. PSRR– (Referred to Input) Vs Frequency

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7.6 Typical Characteristics (continued)

at T_A= 25°C, V_S= (V+) – (V–) = 5.5 V, V_IN= (V_IN+) – (V_IN–) = 0 V, R_L= 10 kΩ, C_L= 10 pF, V_REF= V_S/ 2, V_CM= [(V_IN+) +

(V_IN–)] / 2 = V_S/ 2, V_OUT= V_S/ 2 and G = 10 (unless otherwise noted)

3

100

90

80

70

60

50

40

30

20

10

0

G = 10

G = 20

2

1

0

-1

-2

-3

10

100

1k

Frequency (Hz)

10k

100k

Time (1s/div)

A06_

A07_

Figure 7-31. Input Referred Voltage Noise Spectral Density

Figure 7-32. 0.1 Hz to 10 Hz Voltage Noise in Time Domain

3

2000

G = 10

1000

G = 20

2

1

500

200

100

50

0

20

10

5

-1

-2

2

1

-3

100

1k

10k

Frequency (Hz)

100k

Time (1s/div)

A08_

A12_

Figure 7-33. 0.1 Hz to 10 Hz Voltage Noise in Time Domain

Figure 7-34. Closed-Loop Output Impedance vs Frequency

6

-40

Vs = 5.5 V

Vs = 3.3 V

G = 10

G = 20

-45

5.4

4.8

4.2

3.6

3

-50

-55

-60

-65

-70

2.4

1.8

1.2

0.6

0

1

10

100

1k

Frequency (Hz)

10k

100k

1M

100

1k

Frequency (Hz)

10k

A13_

A15_

V_S= 5.5 V

R_L= 10 kΩ

BW = 80 kHz

V_CM= 2.75 V

V_OUT= 0.5 V_RMS

Figure 7-35. Maximum Output Voltage vs Frequency

Figure 7-36. THD + N Frequency

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7.6 Typical Characteristics (continued)

at T_A= 25°C, V_S= (V+) – (V–) = 5.5 V, V_IN= (V_IN+) – (V_IN–) = 0 V, R_L= 10 kΩ, C_L= 10 pF, V_REF= V_S/ 2, V_CM= [(V_IN+) +

(V_IN–)] / 2 = V_S/ 2, V_OUT= V_S/ 2 and G = 10 (unless otherwise noted)

-35

-40

-45

-50

-55

-60

-65

-70

-75

150

140

130

120

110

100

90

G = 10

G = 20

G = 10

G = 20

80

70

60

50

40

30

1M

10M

100M

Frequency (Hz)

1G

100

1k

Frequency (Hz)

10k

A14_

A16_

V_S= 5.5 V

BW = 80 kHz

V_CM= 2.75 V

R_L= 100 kΩ

V_OUT= 1 V_RMS

Figure 7-38. Electromagnetic Interference Rejection Ratio

Referred to Noninverting Input (EMIRR+) vs Frequency

Figure 7-37. THD + N Frequency

60

50

40

30

20

10

0

30

R_ISO= 0W, Overshoot (+)

R_ISO= 0W, Overshoot(-)

R_ISO= 50W, Overshoot (+)

R_ISO= 50W, Overshoot(-)

R_ISO= 0W, Overshoot (+)

R_ISO= 0W, Overshoot(-)

25

R_ISO= 50W, Overshoot (+)

R_ISO= 50W, Overshoot(-)

20

15

10

5

0

150

300

450 600

Capacitive Load (pF)

750

900

1050

0

150

300

450 600

Capacitive Load (pF)

750

900

1050

TR01

TR02

V_S= 5.5 V

G = 10

V_OUT= 100 mV_PP

V_S= 5.5 V

G = 20

V_OUT= 100 mV_PP

Figure 7-39. Small-Signal Overshoot vs Capacitive Load

Figure 7-40. Small-Signal Overshoot vs Capacitive Load

2.5

V_IN

V_OUT

2

1.5

1

0.5

0

-0.5

-1

-1.5

-2

-2.5

-3

Time (200 µs/div)

Time (5µs/div)

TR05

TR14

V+ = 2.75 V V– = –2.75 V

G = 10

V_OUT= 4 V_PP

V+ = 2.75 V V– = –2.75 V

G = 10

V_OUT= 4 V_PP

Figure 7-41. Large Signal Step Response

Figure 7-42. Large Signal Settling Time (Falling Edge)

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7.6 Typical Characteristics (continued)

at T_A= 25°C, V_S= (V+) – (V–) = 5.5 V, V_IN= (V_IN+) – (V_IN–) = 0 V, R_L= 10 kΩ, C_L= 10 pF, V_REF= V_S/ 2, V_CM= [(V_IN+) +

(V_IN–)] / 2 = V_S/ 2, V_OUT= V_S/ 2 and G = 10 (unless otherwise noted)

2.5

V_IN

V_OUT

2

1.5

1

0.5

0

-0.5

-1

-1.5

-2

-2.5

-3

Time (200 µs/div)

Time (5µs/div)

TR06

TR13

V+ = 2.75 V V– = –2.75 V

G = 20

V_OUT= 4 V_PP

V+ = 2.75 V V– = –2.75 V

G = 10

V_OUT= 4 V_PP

Figure 7-44. Large Signal Step Response

Figure 7-43. Large Signal Settling Time (Rising Edge)

0.075

0.05

V_IN

V_OUT

V_IN

V_OUT

0.05

0.025

0

0.025

0

-0.025

-0.05

-0.025

-0.05

-0.075

Time (200 µs/div)

TR07

TR08

V+ = 2.75 V V– = –2.75 V

G = 10

V_OUT= 0.1 V_PP

V+ = 2.75 V V– = –2.75 V

G = 20

V_OUT= 0.1 V_PP

Figure 7-45. Small-Signal Step Response

Figure 7-46. Small-Signal Step Response

4

3

4

3

2

1

0

-1

-2

-3

-1

-2

-3

V_IN

V_OUT

V_IN

V_OUT

Time (10 µs/div)

TR11

V+ = 2.75 V V– = –2.75 V

G = 10

V_IN= 1 V_PP

V+ = 2.75 V V– = –2.75 V

G = 10

V_IN= 1 V_PP

Figure 7-47. Over-Load Recovery (Rising Edge)

Figure 7-48. Over-Load Recovery (Falling Edge)

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7.6 Typical Characteristics (continued)

at T_A= 25°C, V_S= (V+) – (V–) = 5.5 V, V_IN= (V_IN+) – (V_IN–) = 0 V, R_L= 10 kΩ, C_L= 10 pF, V_REF= V_S/ 2, V_CM= [(V_IN+) +

(V_IN–)] / 2 = V_S/ 2, V_OUT= V_S/ 2 and G = 10 (unless otherwise noted)

4

3

2.5

2

V_IN

V_OUT

Shutdown Voltage

Output Voltage

2

1.5

1

0.5

0

-0.5

-1

-2

-3

-4

-1.5

-2

-2.5

-3

Time (500 µs/div)

Time (100 µs/div)

TR12

TR15

V+ = 2.75 V V– = –2.75 V

G = 10

V_IN= 0.6 V_PP

V+ = +2.75 V

V– = –2.75 V

G = 10

Figure 7-49. No Phase Reversal

Figure 7-50. Enable Response

3

2.5

2

3.6

Shutdown Voltage

Output Voltage

3.2

2.8

2.4

2

1.5

1

0.5

0

1.6

1.2

0.8

0.4

0

-0.5

-1

-1.5

-2

-2.5

-3

-0.4

Time (5 µs/div)

-0.4

0

0.4 0.8 1.2 1.6 2

Output Voltage (V)

2.4 2.8 3.2 3.6

TR16

D01_

V+ = +2.75 V

V– = –2.75 V

G = 10

V_S= 3.3 V

G = 10, 20

V_REF= V_S/ 2

Figure 7-51. Disable Response

Figure 7-52. Input Common-Mode Voltage vs Output Voltage

(High CMRR Region)

6

5.4

4.8

4.2

3.6

3

3.6

3.2

2.8

2.4

2

1.6

1.2

0.8

0.4

0

2.4

1.8

1.2

0.6

0

-0.6

-0.4

-0.6

0

0.6 1.2 1.8 2.4

3

Output Voltage (V)

3.6 4.2 4.8 5.4

6

-0.4

0

0.4 0.8 1.2 1.6 2

Output Voltage (V)

2.4 2.8 3.2 3.6

D01_

D09_

V_S= 5.5 V

G = 10, 20

V_REF= V_S/ 2

V_S= 3.3 V

G = 10, 20

V_REF= 0 V

Figure 7-53. Input Common-Mode Voltage vs Output Voltage

(High CMRR Region)

Figure 7-54. Input Common-Mode Voltage vs Output Voltage

(High CMRR Region)

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7.6 Typical Characteristics (continued)

at T_A= 25°C, V_S= (V+) – (V–) = 5.5 V, V_IN= (V_IN+) – (V_IN–) = 0 V, R_L= 10 kΩ, C_L= 10 pF, V_REF= V_S/ 2, V_CM= [(V_IN+) +

(V_IN–)] / 2 = V_S/ 2, V_OUT= V_S/ 2 and G = 10 (unless otherwise noted)

6

5.4

4.8

4.2

3.6

3

3.6

3.2

2.8

2.4

2

1.6

1.2

0.8

0.4

0

2.4

1.8

1.2

0.6

0

-0.4

-0.6

-0.4

0

0.4 0.8 1.2 1.6 2

Output Voltage (V)

2.4 2.8 3.2 3.6

-0.6

0

0.6 1.2 1.8 2.4

3

Output Voltage (V)

3.6 4.2 4.8 5.4

6

D05_

D09_

V_S= 3.3 V

G = 10, 20

V_REF= V_S/ 2

V_S= 5.5 V

G = 10, 20

V_REF= 0 V

Figure 7-56. Input Common-Mode Voltage vs Output Voltage

Figure 7-55. Input Common-Mode Voltage vs Output Voltage

(High CMRR Region)

6

5.4

4.8

4.2

3.6

3

3.6

3.2

2.8

2.4

2

1.6

1.2

0.8

0.4

0

2.4

1.8

1.2

0.6

0

-0.6

-0.4

-0.6

0

0.6 1.2 1.8 2.4

3

Output Voltage (V)

3.6 4.2 4.8 5.4

6

-0.4

0

0.4 0.8 1.2 1.6 2

Output Voltage (V)

2.4 2.8 3.2 3.6

D05_

D13_

V_S= 5.5 V

G = 10, 20

V_REF= V_S/ 2

V_S= 3.3 V

G = 10, 20

V_REF= 0 V

Figure 7-57. Input Common-Mode Voltage vs Output Voltage

Figure 7-58. Input Common-Mode Voltage vs Output Voltage

6

5.4

4.8

4.2

3.6

3

2.4

1.8

1.2

0.6

0

-0.6

0

0.6 1.2 1.8 2.4

3

Output Voltage (V)

3.6 4.2 4.8 5.4

6

D13_

V_S= 5.5 V

G = 10, 20

V_REF= 0 V

Figure 7-59. Input Common-Mode Voltage vs Output Voltage

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8 Detailed Description

8.1 Overview

INA350 is a selectable gain instrumentation amplifier mainly targeted to provide an integrated small size, cost

effective solution for applications employing general purpose INAs or discrete implementation of INAs using

commodity amplifiers and resistors. It incorporates a three op amp INA architecture integrating three operational

amplifiers and seven precision matched integrated resistors. It is mainly targeted for use in 10-bit to 14-bit

systems, but calibrating offset and gain error at a system level can further improve system resolution and

accuracy enabling use in precision applications.

One of the key features of INA350 is that it does not need any external resistors to set the gain. Often these

external resistors warrant tighter tolerance and need to be routed carefully which adds to the system complexity

and cost. INA350 is offered in four gain options across two variants. INA350ABS has two gain options of 10 and

20. INA350CDS has two other gain options of 30 and 50. Gains can be selected by connecting the GS pin to

logic high or logic low. Note that the GS pin can be left floating as well, as it is designed with an internal pull up to

default to the same configuration as GS tied logic high.

The INA350 is developed for industrial applications in factory automation and appliances sector where pressure

sensing and temperature sensing are done using bridge-type sensor networks and load cells. It can also be used

in tight spaces in medical applications such as patient monitoring, sleep diagnostics, electronic hospital beds,

blood glucose monitoring, and so forth for voltage sensing and differential to single-ended conversion. INA350

can enable these applications to reduce their overall size through the use of tiny packages, including a 2-mm ×

1.5-mm X2QFN package and a 2-mm × 2-mm WSON package.

8.2 Functional Block Diagram

V+

IN

60 k

+

–

60 k

–

+

90 k / 145 k

R_G

GS

OUT

REF

–

+

60 k

+IN

_____

SHDN

V

Note: 90 kΩ for INA350ABS and 145 kΩ for INA350CDS

Simplified Internal Schematic

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8.3 Feature Description

8.3.1 Gain-Setting

The gain equation of INA350ABS can be given by Equation 1:

180 kΩ

G = 1+

(1)

R

G

The value of the internal gain resistor R_Gfor INA350ABS can then be derived from the gain equation:

180 kΩ

R =

(2)

(3)

G

G − 1

Similarly The gain equation of INA350CDS can be given by Equation 1:

290 kΩ

G = 1+

R

G

The value of the internal gain resistor R_Gfor INA350CDS can then be derived from the gain equation:

290 kΩ

R =

(4)

G

G − 1

Gain selection table below outlines how to choose different gain options across INA350ABS and INA350CDS.

The 60-kΩ, 90-kΩ, and 145-kΩ resistors mentioned are all typical values of the on-chip resistors.

Table 8-1. Gain Selection Table

DEVICE

GAIN SELECT (GS)

High or No Connect

Low

SELECTED GAIN

20

10

50

30

INA350ABS

High or No Connect

Low

INA350CDS

8.3.1.1 Gain Error and Drift

Gain error in INA350 is limited by the mismatch of the integrated precision resistors and it is specified based

on characterization results. Gain error of maximum 0.5% can be expected for the gains of 10 and 0.6% for the

gains of 20, 30 and 50. Gain drift in INA350 is limited by the slight mismatch of the temperature coefficient of

the integrated resistors. Since these integrated resistors are precision matched with low temperature coefficient

resistors to begin with, the overall gain drift would be much better in comparison to discrete implementation of

the instrumentation amplifiers built using external resistors.

8.3.2 Input Common-Mode Voltage Range

INA350 has two gain stages, the first stage has a common-mode gain of 1 and a differential gain set by the GS

pin. The second stage is configured in a difference-amplifier configuration with differential gain of 1 and ideally

rejects all of the input common mode completely. The second stage also provides a gain of 1 from REF pin to set

the output common-mode voltage.

The linear input voltage range of the INA350, even for a rail-to-rail first stage is dictated by the signal swing at

output of the first stage as well as the input common-mode voltage range output swing of the second stage. It is

imperative that the INA350 stays linear for a particular combination of gain, reference, and input common-mode

voltage for a chosen input differential. Input common-mode voltage (V_CM) vs output voltage graphs (V_OUT) in this

section show a particular reference voltage and gain configuration to outline the linear performance region of

INA350. A good common-mode rejection can be expected when operating with in the limits of the V_CMvs V_OUT

graph. Note, that the INA350 linear input voltage cannot be close to or extend beyond the supply rails as the

output of the first stage will be driven into saturation.

The common-mode range for the most common operating conditions is outlined below. Figure 8-1 shows the

region of operation where a minimum of 85 dB can be achieved. Figure 8-2 has much wider region of operation

20

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with a lower minimum CMRR of 62 dB, because the input signal crosses over the transition region of the input

pairs to achieve rail-to-rail operation. The common-mode range for other operating conditions is best calculated

with the INA V_CMvs V_OUTtool located under the Amplifiers and Comparators section of the Analog Engineer's

Calculator on ti.com. INA350-HCM model can be specifically used for applications requiring high CMRR and

corresponds to performance shown in Figure 8-1. INA350xxS model can be used for applications where the

input common mode can be expected to vary rail-to-rail and it corresponds to performance shown in Figure 8-2

where CMRR drops to 62-dB minimum.

6

5.4

4.8

4.2

3.6

3

6

5.4

4.8

4.2

3.6

3

2.4

1.8

1.2

0.6

0

2.4

1.8

1.2

0.6

0

-0.6

0

0.6 1.2 1.8 2.4

3

Output Voltage (V)

3.6 4.2 4.8 5.4

6

-0.6

0

0.6 1.2 1.8 2.4

3

Output Voltage (V)

3.6 4.2 4.8 5.4

6

D01_

D05_

V_S= 5.5 V

G = 10, 20

V_REF= V_S/ 2

V_S= 5.5 V

G = 10, 20

V_REF= V_S/ 2

Figure 8-1. Input Common-Mode Voltage vs Output Figure 8-2. Input Common-Mode Voltage vs Output

Voltage (High CMRR Region) Voltage

8.3.3 EMI Rejection

The INA350 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from

sources such as wireless communications and densely-populated boards with a mix of analog signal chain and

digital components. EMI immunity can be improved with circuit design techniques; the INA350 benefits from

these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the

immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure

8-3 shows the results of this testing on the INA350. Table 8-2 shows the EMIRR IN+ values for the INA350 at

particular frequencies commonly encountered in real-world applications. The EMI Rejection Ratio of Operational

Amplifiers application report contains detailed information on the topic of EMIRR performance as it relates to op

amps and is available for download from www.ti.com.

150

G = 10

G = 20

130

140

120

110

100

90

80

70

60

50

40

30

1M

10M

100M

Frequency (Hz)

1G

A14_

Figure 8-3. EMIRR Testing

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Table 8-2. INA350 EMIRR IN+ for Frequencies of Interest

FREQUENCY

APPLICATION OR ALLOCATION

EMIRR IN+

Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)

applications

400 MHz

60 dB

Global system for mobile communications (GSM) applications, radio communication, navigation,

GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications

900 MHz

1.8 GHz

2.4 GHz

3.6 GHz

5 GHz

92 dB

90 dB

GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)

802.11b, 802.11g, 802.11n, Bluetooth^®, mobile personal communications, industrial, scientific and

medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)

95 dB

Radiolocation, aero communication and navigation, satellite, mobile, S-band

108 dB

105 dB

802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite

operation, C-band (4 GHz to 8 GHz)

8.3.4 Typical Specifications and Distributions

Designers often have questions about a typical specification of an amplifier in order to design a more robust

circuit. Due to natural variation in process technology and manufacturing procedures, every specification of an

amplifier will exhibit some amount of deviation from the ideal value, like an amplifier's input offset voltage. These

deviations often follow Gaussian ("bell curve"), or normal distributions, and circuit designers can leverage this

information to guard band their system, even when there is not a minimum or maximum specification in the

Electrical Characteristics table.

0.00312% 0.13185%

0.13185% 0.00312%

0.00002%

2.145% 13.59% 34.13% 34.13% 13.59% 2.145%

1

1 1 1 1 1 1 1 1

1

ꢀ-61 ꢀ-51 ꢀ-41 ꢀ-31 ꢀ-21 ꢀ-1

ꢀ+1 ꢀ+21 ꢀ+31 ꢀ+41 ꢀ+51 ꢀ+61

ꢀ

Figure 8-4. Ideal Gaussian Distribution

Figure 8-4 shows an example distribution, where µ, or mu, is the mean of the distribution, and where σ,

or sigma, is the standard deviation of a system. For a specification that exhibits this kind of distribution,

approximately two-thirds (68.26%) of all units can be expected to have a value within one standard deviation, or

one sigma, of the mean (from µ – σ to µ + σ).

Depending on the specification, values listed in the typical column of the Electrical Characteristics table are

represented in different ways. As a general rule, if a specification naturally has a nonzero mean (for example,

like gain bandwidth), then the typical value is equal to the mean (µ). However, if a specification naturally has a

mean near zero (like input offset voltage), then the typical value is equal to the mean plus one standard deviation

(µ + σ) in order to most accurately represent the typical value.

22

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You can use this chart to calculate approximate probability of a specification in a unit; for example, the INA350

typical input voltage offset is 200 µV, so 68.2% of all INA350 devices are expected to have an offset from –200

µV to +200 µV. At 4 σ (±800 µV), 99.9937% of the distribution has an offset voltage less than ±800 µV, which

means 0.0063% of the population is outside of these limits, which corresponds to about 1 in 15,873 units.

Specifications with a value in the minimum or maximum column are assured by TI, and units outside these limits

will be removed from production material. For example, the INA350 family has a maximum offset voltage of 1.2

mV at 25°C, and even though this corresponds to 6 σ (≈1 in 500 million units), which is extremely unlikely, TI

assures that any unit with larger offset than 1.2 mV will be removed from production material.

For specifications with no value in the minimum or maximum column, consider selecting a sigma value of

sufficient guard band for your application, and design worst-case conditions using this value. As stated earlier,

the 6-σ value corresponds to about 1 in 500 million units, which is an extremely unlikely chance, and could be

an option as a wide guard band to design a system around. In this case, the INA350 family does not have a

maximum or minimum for offset voltage drift, but based on Figure 7-2 and the typical value of 0.6 µV/°C in the

Electrical Characteristics table, it can be calculated from that the 6-σ value for offset voltage drift is about 2

µV/°C. When designing for worst-case system conditions, this value can be used to estimate the worst possible

offset drift without having an actual minimum or maximum value.

However, process variation and adjustments over time can shift typical means and standard deviations, and

unless there is a value in the minimum or maximum specification column, TI cannot assure the performance of a

device. This information should be used only to estimate the performance of a device.

8.3.5 Electrical Overstress

Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.

These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output

pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown

characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.

Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from

accidental ESD events both before and during product assembly.

Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event

is helpful. Figure 8-5 shows the ESD circuits contained in the INA350 devices. The ESD protection circuitry

involves several current-steering diodes connected from the input and output pins and routed back to the internal

power supply lines, where they meet at an absorption device internal to the operational amplifier. This protection

circuitry is intended to remain inactive during normal circuit operation.

V+

Power Supply

ESD Cell

+IN

+

–

OUT

– IN

_____

SHDN

GS

REF

V–

Figure 8-5. Equivalent Internal ESD Circuitry

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8.4 Device Functional Modes

The INA350 has a shutdown or disable mode to enable power savings in battery powered applications. The

shutdown mode has a maximum quiescent current of just 1.25 µA, which is 100 times lower from the quiescent

current when the amplifier is powered-on or enabled.

INA350 enters disable mode when the SHDN pin is tied low. INA350 is enabled when the SHDN pin is tied high.

A no connection or a floating SHDN pin enables or powers-on the INA as the pin has an internal pull up current

to default to the same configuration as SHDN pin tied high.

24

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

9.1.1 Reference Pin

The output voltage of the INA350 is developed with respect to the voltage on the reference pin (REF). Often

in dual-supply operation, REF pin connects to the low-impedance system ground. In single-supply operation,

offsetting the output signal to a precise mid-supply level is useful (for example, 2.75-V in a 5.5-V supply

environment). To accomplish this level shift, a voltage source must be connected to the REF pin to level-shift the

output so that the INA350 can drive a single-supply ADC.

The voltage source applied to the reference pin must have a low output impedance. Any resistance at the

reference pin (R_REF) in is in series with the internal 60-kΩ resistor.

The parasitic resistance at the reference pin (R_REF) creates an imbalance in the four resistors of the internal

difference amplifier that results in a degraded common-mode rejection ratio (CMRR). For the best performance,

keep the source impedance to the REF pin (R_REF) less than 5 Ω.

Voltage reference devices are an excellent option for providing a low-impedance voltage source for the reference

pin. However, if a resistor voltage divider generates a reference voltage, buffer the divider by an op amp, as

shown in Figure 9-1, to avoid CMRR degradation.

5 V

+IN

INA350

OUT

–IN

5 V

100 k

+

TLV9041

1

F

–

100 k

Figure 9-1. Use an Op Amp to Buffer Reference Voltages

9.1.2 Input Bias Current Return Path

The input impedance of the INA350 is extremely high, but a path must be provided for the input bias current of

both inputs. This input bias current is typically a few pico amps but at high temperature this can be a few nano

amps. High input impedance means that the input bias current changes little with varying input voltage.

For proper operation, input circuitry must provide a path for this input bias current. Figure 9-2 shows various

provisions for an input bias current path. Without a bias current path, the inputs float to a potential that exceeds

the common-mode range of the INA350, and the input amplifiers saturate. If the differential source resistance

is low, the bias current return path connects to one input (as shown in the thermocouple example in Figure

9-2). With a higher source impedance, use two equal resistors to provide a balanced input, with the possible

advantages of a lower input offset voltage as a result of bias current, and better high-frequency common-mode

rejection.

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Microphone,

Hydrophone,

and So Forth

TI Device

47 kW

Thermocouple

TI Device

10 kW

TI Device

Center tap provides

bias current return.

Figure 9-2. Providing an Input Common-Mode Current Path

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9.2 Typical Applications

9.2.1 Resistive-Bridge Pressure Sensor

The INA350 is an integrated instrumentation amplifier that measures small differential voltages while

simultaneously rejecting larger common-mode voltages. The device offers a low power consumption of 100

µA (typical) and has a smaller form factor.

The device is designed for portable applications where sensors measure physical parameters, such as changes

in fluid, pressure, temperature, or humidity. An example of a pressure sensor used in the medical sector is in

portable infusion pumps or dialysis machines.

The pressure sensor is made of a piezo-resistive element that can be derived as a classical 4-resistor

Wheatstone bridge.

Occlusion (infusion of fluids, medication, or nutrients) happens only in one direction, and therefore can only

cause the resistive element (R) to expand. This expansion causes a change in voltage on one leg of the

Wheatstone bridge, which induces a differential voltage V_DIFF

.

Figure 9-3 showcases an example circuit for an occlusion pressure sensor application, as required in infusion

pumps. When blockage (occlusion) occurs against a set-point value, the tubing depresses, thus causing the

piezo-resistive element to expand (Node AD: R + ΔR). The signal chain connected to the bridge downstream

processes the pressure change and can trigger an alarm.

V_S= 5.5 V

V_EXT= 5 V

1

F

1

F

REF

A

0.1

F

D

Pressure

Occlusion

Sensor

B

–

+

V_OUT

V_DIFF

ADC

µC

INA350

C

VREF

R1

GND

Figure 9-3. Resistive-Bridge Pressure Sensor

Low-tolerance bridge resistors must be used to minimize the offset and gain errors.

Given that there is only a positive differential voltage applied, this circuit is laid out in single-ended supply mode.

The excitation voltage, V_EXT, to the bridge must be precise and stable; otherwise, measurement errors can be

introduced.

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9.2.1.1 Design Requirements

For this application, the design requirements are as shown in Table 9-1.

Table 9-1. Design Requirements

DESCRIPTION

VALUE

Single supply voltage

V_S= 5.5 V

Excitation voltage

V_EXT= 5.0 V

Occlusion pressure range

Occlusion pressure sensitivity

Occlusion pressure impedance (R)

Total pressure sampling rate

Full-scale range of ADC

P = 1 psi to 12 psi, increments of P = 0.5 psi

S = 2 ±0.5 (25%) mV/V/psi

R = 4.99 kΩ ±50 Ω (0.1%)

Sr = 20 Hz

V_ADC(fs)= V_OUT= 3.0 V

9.2.1.2 Detailed Design Procedure

This section provides basic calculations to lay out the instrumentation amplifier with respect to the given design

requirements.

One of the key considerations in resistive-bridge sensors is the common-mode voltage, V_CM. If the bridge

is balanced (no pressure, thus no voltage change), V_CM(zero)is half of the bridge excitation (V_EXT). In this

example V_{CM (zero)}is 2.5 V. For the maximum pressure of 12 psi, the bridge common-mode voltage, V_CM(MAX), is

calculated by:

V

DIFF

2

V

=

+ V

CM(zero)

(5)

(6)

(7)

(8)

CM MAX

where

•

mV

V

= S

× V

× P = 2.5

MAX

× 5 V × 12 psi = 150 mV

V×psi

DIFF

MAX

EXT

Thus, the maximum common-mode voltage applied results in:

150 mV

V

=

+ 2.5 V = 2.575 V

CM MAX

2

Similarly, the minimum common-mode voltage can be calculated as,

−150 mV

V

=

+ 2.5 V = 2.425 V

CM MIN

2

The next step is to calculate the gain required for the given maximum sensor output voltage span, V_DIFF, in

respect to the required V_OUT, which is the full-scale range of the ADC.

The following equation calculates the gain value using the maximum input voltage and the required output

voltage:

V

OUT

3.0 V

G =

=

= 20 V/V

150 mV

(9)

V

DIFF(MAX)

Considering, INA350 is a selectable gain INA with gain options of 10, 20, 30, 50, the INA350ABS with GS tied

high enables G = 20 ensuring the maximum output signal swing for the ADC.

Next, let us make sure that the INA350 can operate within this range checking the Input Common-Mode Voltage

vs Output Voltage curves in the Typical Characteristics section. The relevant figure is also in this section for

convenience. Looking at Figure 9-4, we can confirm that a output signal swing of 3 V is supported for the input

signal swing between 2.425 V and 2.575 V, thus making sure of the linear operation.

28

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6

5.4

4.8

4.2

3.6

3

2.4

1.8

1.2

0.6

0

-0.6

0

0.6 1.2 1.8 2.4

3

Output Voltage (V)

3.6 4.2 4.8 5.4

6

D09_

V_S= 5.5 V

G = 10, 20

V_REF= 0 V

Figure 9-4. Input Common-Mode Voltage vs Output Voltage (High CMRR Region)

Additional series resistor in the Wheatstone bridge string (R1) may or may not be required. This is decided

based on the intended output voltage swing for a particular combination of supply voltage, reference voltage and

the selected gain for an input common mode voltage range. R1 helps adjust the input common-mode voltage

range, and thus can help accommodate the intended output voltage swing. In this particular example, it are not

required and can be shorted out.

9.2.1.3 Application Curves

The following typical characteristic curve is for the circuit in Figure 9-3.

3

2.7

2.4

2.1

1.8

1.5

1.2

0.9

0.6

0.3

0

0.30

0.27

0.24

0.21

0.18

0.15

0.12

0.09

0.06

0.03

0

V_OUT

V_DIFF

5000 5200 5400 5600 5800 6000 6200 6400 6600 6800 7000

Bridge Resistance R + DR (W)

D100

Figure 9-5. Input Differential Voltage, Output Voltage vs Bridge Resistance

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10 Power Supply Recommendations

The nominal performance of the INA350 is specified with a supply voltage of ±2.75 V and midsupply reference

voltage. The device also operates using power supplies from ±0.85 V (1.7 V) to ±2.75 V (5.5 V) and non-

midsupply reference voltages with excellent performance. Parameters can vary significantly with operating

voltage and reference voltage.

11 Layout

11.1 Layout Guidelines

Attention to good layout practices is always recommended. For best operational performance of the device, use

the following PCB layout practices:

•

Make sure that both input paths are well-matched for source impedance and capacitance to avoid converting

common-mode signals into differential signals.

•

Use bypass capacitors to reduce the coupled noise by providing low-impedance power sources local to the

analog circuitry.

– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

•

Route the input traces as far away from the supply or output traces as possible to reduce parasitic coupling. If

these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than crossing

in parallel with the noisy trace.

•

Place the external components as close to the device as possible.

Use short, symmetric, and wide traces to connect the external gain resistor to minimize capacitance

mismatch between the RG pins.

•

Keep the traces as short as possible.

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11.2 Layout Example

+V

C2

R2

+IN

–IN

INA350ABS

OUT

R1

C1

Ground plane

removed at gain

–V

resistor to minimize

parasitic capacitance

Use ground pours for

shielding the input

signal pairs

+V

GND

_____

C2

R1

1

2

3

4

GS

SHDN

V_S+

8

7

6

5

–IN

+IN

–IN

+IN

V_S

Input traces routed

adjacent to each other

OUT

REF

OUT

R2

Low-impedance

connection for

reference terminal

GND

C1

Place bypass

capacitors as close to

IC as possible

–V

Figure 11-1. Example Schematic and Associated PCB Layout

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12 Device and Documentation Support

12.1 Device Support

12.1.1 Development Support

•

SPICE-based analog simulation program — TINA-TI software folder

Analog Engineers Calculator

12.1.1.1 PSpice^®for TI

PSpice^®for TI is a design and simulation environment that helps evaluate performance of analog circuits. Create

subsystem designs and prototype solutions before committing to layout and fabrication, reducing development

cost and time to market.

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation see the following:

Texas Instruments, EMI Rejection Ratio of Operational Amplifiers application report

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

12.4 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

Bluetooth^®is a registered trademark of Bluetooth SIG, Inc.

All trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.7 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

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13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE MATERIALS INFORMATION

www.ti.com

20-Dec-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

INA350ABSIDDFR

INA350ABSIDSGR

SOT-

23-THIN

DDF

DSG

8

3000

180.0

8.4

3.2

1.4

4.0

8.0

Q3

WSON

180.0

8.4

2.3

1.15

4.0

8.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Dec-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

INA350ABSIDDFR

INA350ABSIDSGR

SOT-23-THIN

WSON

DDF

DSG

8

3000

210.0

185.0

35.0

Pack Materials-Page 2

PACKAGE OUTLINE

DDF0008A

SOT-23 - 1.1 mm max height

S

C

A

L

E

4

.

0

PLASTIC SMALL OUTLINE

C

2.95

2.65

SEATING PLANE

TYP

PIN 1 ID

AREA

0.1 C

A

6X 0.65

8

1

2.95

2.85

NOTE 3

2X

1.95

4

5

0.4

0.2

8X

0.1

C A

B

1.65

1.55

B

1.1 MAX

0.20

0.08

TYP

SEE DETAIL A

0.25

GAGE PLANE

0.1

0.0

0 - 8

0.6

0.3

DETAIL A

TYPICAL

4222047/B 11/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

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EXAMPLE BOARD LAYOUT

DDF0008A

SOT-23 - 1.1 mm max height

PLASTIC SMALL OUTLINE

8X (1.05)

SYMM

1

8

8X (0.45)

SYMM

6X (0.65)

5

4

(R0.05)

TYP

(2.6)

LAND PATTERN EXAMPLE

SCALE:15X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4222047/B 11/2015

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN

DDF0008A

SOT-23 - 1.1 mm max height

PLASTIC SMALL OUTLINE

8X (1.05)

SYMM

(R0.05) TYP

8

1

8X (0.45)

SYMM

6X (0.65)

5

4

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

4222047/B 11/2015

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

www.ti.com

GENERIC PACKAGE VIEW

DSG 8

2 x 2, 0.5 mm pitch

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224783/A

www.ti.com

PACKAGE OUTLINE

DSG0008A

WSON - 0.8 mm max height

SCALE 5.500

PLASTIC SMALL OUTLINE - NO LEAD

2.1

1.9

B

A

PIN 1 INDEX AREA

2.1

1.9

0.32

0.18

0.4

0.2

ALTERNATIVE TERMINAL SHAPE

TYPICAL

C

0.8 MAX

SEATING PLANE

0.08 C

0.05

0.00

EXPOSED

THERMAL PAD

(0.2) TYP

0.9 0.1

5

4

6X 0.5

2X

1.5

9

1.6 0.1

8

1

0.32

0.18

8X

0.4

0.2

PIN 1 ID

8X

0.1

C A B

C

0.05

4218900/D 04/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

DSG0008A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(0.9)

(

0.2) VIA

8X (0.5)

TYP

1

8

8X (0.25)

(0.55)

SYMM

9

(1.6)

6X (0.5)

5

4

SYMM

(1.9)

(R0.05) TYP

LAND PATTERN EXAMPLE

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4218900/D 04/2020

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

DSG0008A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

8X (0.5)

METAL

8

SYMM

1

8X (0.25)

(0.45)

SYMM

9

(0.7)

6X (0.5)

5

4

(R0.05) TYP

(0.9)

(1.9)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 9:

87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:25X

4218900/D 04/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	PINA350ABSIDDFR
厂家：	TEXAS INSTRUMENTS
描述：	INA350 Cost and Size Optimized, Low Power, 1.8-V to 5.5-V Selectable Gain Instrumentation Amplifier
文件：	总45页 (文件大小：3947K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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