PCA9554DBRG4 [TI]
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PCA9554
SCPS128C –JULY 2006–REVISED JUNE 2014
PCA9554 Remote 8-Bit I2C AND SMBus I/O Expander With Interrupt Output and
Configuration Registers
1 Features
2 Description
•
I2C to Parallel Port Expander
This 8-bit I/O expander for the two-line bidirectional
bus (I2C) is designed for 2.3-V to 5.5-V VCC
operation. It provides general-purpose remote I/O
expansion for most microcontroller families via the I2C
interface [serial clock (SCL), serial data (SDA)].
1
•
•
Open-Drain Active-Low Interrupt Output
Operating Power-Supply Voltage Range of 2.3 V
to 5.5 V
•
•
•
5-V Tolerant I/Os
The PCA9554 consists of one 8-bit Configuration
(input or output selection), Input, Output, and Polarity
Inversion (active high or active low) registers. At
power on, the I/Os are configured as inputs with a
weak pullup to VCC. However, the system master can
enable the I/Os as either inputs or outputs by writing
to the I/O configuration bits. The data for each input
or output is kept in the corresponding Input or Output
register. The polarity of the Input Port register can be
inverted with the Polarity Inversion register. All
registers can be read by the system master.
400-kHz Fast I2C Bus
Three Hardware Address Pins Allow up to Eight
Devices on the I2C/SMBus
•
•
•
•
•
•
Input/Output Configuration Register
Polarity Inversion Register
Internal Power-On Reset
Power-Up With All Channels Configured as Inputs
No Glitch On Power Up
Latched Outputs With High-Current Drive
Maximum Capability for Directly Driving LEDs
The system master can reset the PCA9554 in the
event of a timeout or other improper operation by
utilizing the power-on reset feature, which puts the
registers in their default state and initializes the
I2C/SMBus state machine.
•
•
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
The PCA9554 open-drain interrupt (INT) output is
activated when any input state differs from its
corresponding Input Port register state and is used to
indicate to the system master that an input state has
changed.
–
–
–
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
6.20 mm × 5.30 mm
4.00 mm × 4.00 mm
3.00 mm × 3.00 mm
SSOP (16)
PCA9554
VQFN (16)
QFN (16)
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
DB, DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
RGV PACKAGE
(TOP VIEW)
RGT PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A0
A1
VCC
SDA
SCL
INT
P7
16 15 14 13
16 15 14 13
1
2
12
11
A2
P0
P1
SCL
INT
P7
1
12
A2
P0
P1
SCL
INT
A2
P0
P1
P2
2
3
4
11
10 P7
3
4
10
9
9
P2
P6
P6
P5
P2
P6
5
6
7
8
P3
5
6
7
8
GND
P4
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PCA9554
SCPS128C –JULY 2006–REVISED JUNE 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
Features.................................................................. 1
Description ............................................................. 1
Revision History..................................................... 2
Description (Continued)........................................ 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 Handling Ratings....................................................... 4
6.3 Recommended Operating Conditions....................... 4
6.4 Electrical Characteristics........................................... 5
6.5 I2C Interface Timing Requirements........................... 6
6.6 Switching Characteristics.......................................... 6
6.7 Typical Characteristics.............................................. 7
Parameter Measurement Information ................ 10
8
Detailed Description ............................................ 13
8.1 Functional Block Diagram ....................................... 13
8.2 Device Functional Modes........................................ 14
8.3 Programming........................................................... 15
Application And Implementation........................ 21
9.1 Typical Application ................................................. 21
9
10 Power Supply Recommendations ..................... 23
10.1 Power-On Reset Errata......................................... 23
11 Device and Documentation Support ................. 24
11.1 Trademarks........................................................... 24
11.2 Electrostatic Discharge Caution............................ 24
11.3 Glossary................................................................ 24
12 Mechanical, Packaging, and Orderable
Information ........................................................... 24
7
3 Revision History
Changes from Revision B (August 2008) to Revision C
Page
•
•
Added Interrupt Errata section.............................................................................................................................................. 15
Added Power-On Reset Errata section. ............................................................................................................................... 23
2
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SCPS128C –JULY 2006–REVISED JUNE 2014
4 Description (Continued)
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the
remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via
the I2C bus. Thus, the PCA9554 can remain a simple slave device.
The device's outputs (latched) have high-current drive capability for directly driving LEDs and low current
consumption.
Three hardware pins (A0, A1, and A2) are used to program and vary the fixed I2C address and allow up to eight
devices to share the same I2C bus or SMBus.
The PCA9554 is pin-to-pin and I2C address compatible with the PCF8574. However, software changes are
required, due to the enhancements in the PCA9554 over the PCF8574.
The PCA9554 and PCA9554A are identical except for their fixed I2C address. This allows for up to 16 of these
devices (eight of each) on the same I2C/SMBus.
5 Pin Configuration and Functions
DB, DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
RGV PACKAGE
(TOP VIEW)
RGT PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A0
A1
VCC
SDA
SCL
INT
P7
16 15 14 13
16 15 14 13
1
12
11
A2
P0
P1
SCL
INT
P7
1
12
A2
P0
P1
SCL
INT
A2
P0
P1
P2
2
3
4
2
3
4
11
10 P7
10
9
9
P2
P6
P6
P5
P2
P6
5
6
7
8
P3
5
6
7
8
GND
P4
Pin Functions
PIN
QSOP (DBQ)
SOIC (DW),
SSOP (DB),
DESCRIPTION
QFN (RGT) AND
QFN (RGV)
NAME
TSSOP (PW), AND
TVSOP (DGV)
A0
A1
1
2
15
16
1
Address input. Connect directly to VCC or ground.
Address input. Connect directly to VCC or ground.
Address input. Connect directly to VCC or ground.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
Ground
A2
3
P0
4
2
P1
5
3
P2
6
4
P3
7
5
GND
P4
8
6
9
7
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P5
10
11
12
13
14
15
16
8
P6
9
P7
10
11
12
13
14
INT
SCL
SDA
VCC
Interrupt output. Connect to VCC through a pullup resistor.
Serial clock bus. Connect to VCC through a pullup resistor.
Serial data bus. Connect to VCC through a pullup resistor.
Supply voltage
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6 Specifications
6.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX UNIT
VCC
VI
Supply voltage range
Input voltage range(2)
Output voltage range(2)
6
6
V
V
VO
IIK
6
V
Input clamp current
VI < 0
–20
–20
±20
50
mA
mA
mA
mA
mA
mA
mA
IOK
IIOK
IOL
IOH
Output clamp current
VO < 0
Input/output clamp current
Continuous output low current
Continuous output high current
Continuous current through GND
Continuous current through VCC
VO < 0 or VO > VCC
VO = 0 to VCC
VO = 0 to VCC
–50
–250
160
82
ICC
DB package
DBQ package
DGV package
DW package
N package
90
120
57
θJA
Package thermal impedance(3)
°C/W
67
PW package
RGT package
RGV package
108
TBD
TBD
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
6.2 Handling Ratings
MIN
–65
MAX
150
UNIT
Tstg
Storage temperature range
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
0
0
2000
1000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
MAX
UNIT
VCC
VIH
Supply voltage
2.3
0.7 × VCC
2
5.5
5.5
V
SCL, SDA
A2–A0, P7–P0
SCL, SDA
A2–A0, P7–P0
P7–P0
High-level input voltage
V
V
5.5
–0.5
0.3 × VCC
0.8
VIL
Low-level input voltage
–0.5
IOH
IOL
TA
High-level output current
Low-level output current
Operating free-air temperature
–10
mA
mA
°C
P7–P0
25
–40
85
4
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SCPS128C –JULY 2006–REVISED JUNE 2014
6.4 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2.3 V to 5.5 V
VPOR
MIN
TYP(1)
MAX UNIT
VIK
Input diode clamp voltage II = –18 mA
–1.2
V
VPOR
Power-on reset voltage
VI = VCC or GND, IO = 0
1.5
1.65
V
2.3 V
1.8
2.6
3.1
4.1
1.7
2.5
3
3 V
IOH = –8 mA
4.5 V
4.75 V
2.3 V
P-port high-level output
voltage(2)
VOH
V
3 V
IOH = –10 mA
VOL = 0.4 V
VOL = 0.5 V
4.5 V
4.75 V
2.3 V to 5.5 V
2.3 V
4
SDA
3
8
10
14
17
35
13
19
24
45
10
8
3 V
8
4.5 V
8
4.75 V
2.3 V
8
IOL
P port(3)
mA
10
10
10
10
3
3 V
VOL = 0.7 V
4.5 V
4.75 V
2.3 V to 5.5 V
INT
VOL = 0.4 V
SCL, SDA
A2–A0
P port
P port
±1
±1
II
VI = VCC or GND
2.3 V to 5.5 V
μA
IIH
IIL
VI = VCC
2.3 V to 5.5 V
2.3 V to 5.5 V
5.5 V
1
μA
μA
VI = GND
–100
175
90
104
50
VI = VCC, IO = 0, I/O = inputs,
fscl = 400 kHz, No load
3.6 V
2.7 V
20
65
Operating mode
5.5 V
60
150
40
VI = VCC, IO = 0, I/O = inputs,
fscl = 100 kHz, No load
3.6 V
15
2.7 V
8
20
ICC
μA
5.5 V
450
300
225
0.25
0.2
0.1
700
600
500
1
VI = GND, IO = 0, I/O = inputs,
fscl = 0 kHz, No load
3.6 V
2.7 V
Standby mode
5.5 V
VI = VCC, IO = 0, I/O = inputs,
fscl = 0 kHz, No load
3.6 V
0.9
0.8
2.7 V
One input at VCC – 0.6 V,
Other inputs at VCC or GND
2.3 V to 5.5 V
1.5
1
Additional current in
standby mode
ΔICC
mA
Every LED I/O at VI = 4.3 V,
fscl = 0 kHz
5.5 V
Ci
SCL
VI = VCC or GND
2.3 V to 5.5 V
4
5.5
8
5
6.5
9.5
pF
pF
SDA
P port
Cio
VIO = VCC or GND
2.3 V to 5.5 V
(1) All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC) and TA = 25°C.
(2) The total current sourced by all I/Os must be limited to 85 mA.
(3) Each I/O must be externally limited to a maximum of 25 mA, and the P port (P0 to P7) must be limited to a maximum current of 200 mA.
Copyright © 2006–2014, Texas Instruments Incorporated
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6.5 I2C Interface Timing Requirements
over operating free-air temperature range (unless otherwise noted) (see Figure 14)
STANDARD MODE
I2C BUS
FAST MODE
I2C BUS
UNIT
MIN
0
MAX
MIN
0
MAX
fscl
tsch
tscl
tsp
I2C clock frequency
I2C clock high time
I2C clock low time
I2C spike time
I2C serial-data setup time
I2C serial-data hold time
I2C input rise time
I2C input fall time
100
400
kHz
μs
μs
ns
ns
ns
ns
ns
ns
μs
μs
μs
μs
4
0.6
1.3
4.7
50
50
tsds
tsdh
ticr
250
0
100
0
(1)
1000
300
20 + 0.1Cb
300
300
300
(1)
(1)
ticf
20 + 0.1Cb
20 + 0.1Cb
tocf
tbuf
tsts
tsth
tsps
I2C output fall time
10-pF to 400-pF bus
300
I2C bus free time between stop and start
I2C start or repeated start condition setup
I2C start or repeated start condition hold
I2C stop condition setup
4.7
4.7
4
1.3
0.6
0.6
0.6
4
SCL low to SDA output
valid
tvd(data)
Valid data time
300
0.3
50
ns
ACK signal from SCL low
to SDA (out) low
tvd(ack)
Cb
Valid data time of ACK condition
I2C bus capacitive load
3.45
400
0.1
0.9
μs
400
ns
(1) Cb = Total capacitive load of one bus in pF
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted) (see Figure 15 and Figure 16)
STANDARD MODE
FAST MODE
I2C BUS
I2C BUS
MIN
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MAX
4
MIN
MAX
tiv
Interrupt valid time
Interrupt reset delay time
Output data valid
P port
SCL
INT
INT
4
4
μs
μs
ns
ns
μs
tir
4
tpv
tps
tph
SCL
P7–P0
SCL
200
200
Input data setup time
Input data hold time
P port
P port
100
1
100
1
SCL
6
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SCPS128C –JULY 2006–REVISED JUNE 2014
6.7 Typical Characteristics
35
30
25
20
15
10
5
55
50
VCC = 5 V
45
40
35
30
VCC = 5 V
fSCL = 400 kHz
I/Os unloaded
VCC = 3.3 V
25
VCC = 3.3 V
20
VCC = 2.5 V
15
VCC = 2.5 V
10
5
SCL = VCC
60
0
0
-40
-15
10
35
60
85
-40
-15
10
35
85
TA – Free-Air Temperature – °C
TA – Free-Air Temperature – °C
Figure 1. Supply Current vs Temperature
Figure 2. Quiescent Supply Current vs Temperature
70
600
fSCL = 400 kHz
I/Os unloaded
VCC = 5 V
550
500
450
400
350
300
250
200
150
100
50
60
50
40
30
20
10
0
TA = –40°C
TA = 25°C
TA = 85°C
0
0
1
2
3
4
5
6
7
8
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
Number of I/Os Held Low
VCC – Supply Voltage – V
Figure 4. Supply Current vs Number Of I/Os Held Low
Figure 3. Supply Current vs Supply Voltage
30
300
VCC = 2.5 V
275
VCC = 2.5 V, ISINK = 10 mA
250
25
TA = –40°C
225
200
175
20
TA = 25°C
VCC = 5 V, ISINK = 10 mA
15
150
125
100
TA = 85°C
10
VCC = 2.5 V, ISINK = 1 mA
VCC = 5 V, ISINK = 1 mA
75
50
25
0
5
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
-40
-15
10
35
60
85
VOL – Output Low Voltage – V
TA – Free-Air Temperature – °C
Figure 6. I/O Sink Current vs Output Low Voltage
Figure 5. I/O Output Low Voltage vs Temperature
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Typical Characteristics (continued)
60
55
50
45
40
35
30
25
20
15
10
5
40
VCC = 5 V
VCC = 3.3 V
35
TA = –40°C
30
TA = –40°C
25
TA = 25°C
TA = 25°C
20
15
TA = 85°C
TA = 85°C
10
5
0
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
VOL – Output Low Voltage – V
VOL – Output Low Voltage – V
Figure 7. I/O Sink Current vs Output Low Voltage
Figure 8. I/O Sink Current vs Output Low Voltage
35
275
VCC = 2.5 V
250
VCC = 2.5 V, IOL = 10 mA
30
225
200
175
150
TA = –40°C
25
TA = 25°C
20
15
10
5
125
100
75
50
25
0
VCC = 5 V, IOL = 10 mA
VCC = 2.5 V, IOL = 1 mA
TA = 85°C
VCC = 5 V, IOL = 1 mA
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
-40
-15
10
35
60
85
(VCC – VOH) – Output High Voltage – V
TA – Free-Air Temperature – °C
Figure 10. I/O Source Current vs Output High Voltage
Figure 9. I/O Output High Voltage vs Temperature
75
50
VCC = 3.3 V
45
VCC = 5 V
70
65
60
55
50
45
40
35
30
25
20
15
10
5
40
TA = –40°C
TA = –40°C
35
TA = 25°C
30
25
20
15
10
5
TA = 25°C
TA = 85°C
TA = 85°C
0
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
(VCC – VOH) – Output High Voltage – V
(VCC – VOH) – Output High Voltage – V
Figure 11. I/O Source Current vs Output High Voltage
Figure 12. I/O Source Current vs Output High Voltage
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Typical Characteristics (continued)
6
TA = 25°C
5
4
3
2
1
0
IOH = –8 mA
IOH = –10 mA
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VCC – Supply Voltage – V
Figure 13. Output High Voltage vs Supply Voltage
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7 Parameter Measurement Information
V
CC
R
L
= 1 kΩ
SDA
DUT
C
L
= 50 pF
(see Note A)
SDA LOAD CONFIGURATION
Three Bytes for Complete
Device Programming
Stop
Condition Condition
(P) (S)
Start
Address
Bit 7
(MSB)
R/W
Bit 0
(LSB)
Data
Bit 07
(MSB)
Data
Bit 10 Condition
(LSB)
Stop
Address
Bit 6
Address
Bit 1
ACK
(A)
(P)
t
scl
t
sch
0.7 × V
0.3 × V
CC
SCL
SDA
CC
t
icr
t
sts
t
PHL
t
icf
t
buf
t
t
sp
PLH
0.7 × V
0.3 × V
CC
CC
t
icf
t
icr
t
sdh
t
sps
t
sth
t
sds
Repeat
Start
Condition
Stop
Condition
Start or
Repeat
Start
Condition
VOLTAGE WAVEFORMS
BYTE
1
DESCRIPTION
2
I C address
2, 3
P-port data
A. CL includes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C. All parameters and waveforms are not applicable to all devices.
Figure 14. I2C Interface Load Circuit And Voltage Waveforms
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Parameter Measurement Information (continued)
V
CC
R
L
= 4.7 kΩ
INT
DUT
C
L
= 100 pF
(see Note A)
INTERRUPT LOAD CONFIGURATION
ACK
From Slave
ACK
From Slave
Start
Condition
8 Bits
(One Data Bytes)
From Port
R/W
Slave Address
Data From Port
Data 2
S
0
1
0
0
A2 A1 A0
1
A
Data 1
A
1
P
1
2
3
4
5
6
7
8
A
A
t
ir
B
B
t
ir
INT
A
t
iv
t
sps
A
Data
Into
Port
Address
Data 1
Data 2
0.7 × V
0.3 × V
CC
0.7 × V
0.3 × V
CC
SCL
R/W
INT
A
CC
CC
t
iv
t
ir
0.7 × V
1.5 V
0.7 × V
0.3 × V
CC
CC
INT
P
n
0.3 × V
CC
CC
View A−A
A. CL includes probe and jig capacitance.
View B−B
B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C. All parameters and waveforms are not applicable to all devices.
Figure 15. Interrupt Load Circuit And Voltage Waveforms
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Parameter Measurement Information (continued)
Pn
500 W
2 × V
DUT
CC
C
= 50 pF
L
500 W
(see Note A)
P-PORT LOAD CONFIGURATION
0.7 × V
CC
SCL
SDA
P0
A
P7
0.3 × V
CC
Slave
ACK
t
pv
(see Note B)
P
n
Last Stable Bit
Unstable
Data
WRITE MODE (R/W = 0)
0.7 × V
0.3 × V
CC
SCL
P0
A
P7
CC
t
ps
t
ph
0.7 × V
1.5 V
CC
P
n
0.3 × V
CC
READ MODE (R/W = 1)
A. CL includes probe and jig capacitance.
B. tpv is measured from 0.7 × VCC on SCL to 50% I/O pin output.
C. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 16. P-Port Load Circuit And Voltage Waveforms
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8 Detailed Description
8.1 Functional Block Diagram
13
Interrupt
Logic
LP Filter
INT
1
A0
2
A1
3
A2
14
P7−P0
SCL
2
Input
Filter
I C Bus
Shift
Register
I/O
Port
15
8 Bits
Control
SDA
Write Pulse
Read Pulse
16
V
Power-On
Reset
CC
8
GND
A. Pin numbers shown are for the DB, DBQ, DGV, DW, N, or PW package.
B. All I/Os are set to inputs at reset.
Figure 17. Logic Diagram
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Functional Block Diagram (continued)
Data From
Shift Register
Configuration
Output Port
Register Data
Register
V
CC
Data From
Shift Register
Q1
D
Q
FF
100 kW
Write Configuration
Pulse
D
C
Q
C
K
Q
FF
P0 to P7
GND
Write Pulse
Q
K
Q2
Output Port
Register
Input Port
Register
Input Port
Register Data
D
Q
FF
Read Pulse
C
K
Q
INT
Data From
Shift Register
Polarity
Register Data
D
C
Q
FF
Write Polarity
Pulse
Q
K
Polarity
Inversion
Register
A. At power-on reset, all registers return to default values.
Figure 18. Simplified Schematic Of P0 To P7
8.2 Device Functional Modes
8.2.1 Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA9554 in a reset condition until
VCC has reached VPOR. At that point, the reset condition is released and the PCA9554 registers and I2C/SMBus
state machine initialize to their default states. After that, VCC must be lowered to below 0.2 V and then back up to
the operating voltage for a power-reset cycle.
Refer to the Power-On Reset Errata section.
8.2.2 I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 (in Figure 18) are off, which creates a high-impedance
input with a weak pullup (100 kΩ typ) to VCC. The input voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In
this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
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Device Functional Modes (continued)
8.2.3 Interrupt Output (INT)
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv, the
signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original
setting, data is read from the port that generated the interrupt. Resetting occurs in the read mode at the
acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal.
Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of
the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
Writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an
interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the pin
does not match the contents of the Input Port register. Because each 8-pin port is read independently, the
interrupt caused by port 0 is not cleared by a read of port 1 or vice versa.
The INT output has an open-drain structure and requires pullup resistor to VCC
.
8.2.3.1 Interrupt Errata
Description
The INT will be improperly de-asserted if the following two conditions occur:
1. The last I2C command byte (register pointer) written to the device was 00h.
NOTE
This generally means the last operation with the device was a Read of the input
register. However, the command byte may have been written with 00h without ever
going on to read the input register. After reading from the device, if no other command
byte written, it will remain 00h.
2. Any other slave device on the I2C bus acknowledges an address byte with the R/W bit set high
System Impact
Can cause improper interrupt handling as the Master will see the interrupt as being cleared.
System Workaround
Minor software change: User must change command byte to something besides 00h after a Read operation to
the PCA9554 device or before reading from another slave device.
NOTE
Software change will be compatible with other versions (competition and TI redesigns) of
this device.
8.3 Programming
8.3.1 I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see Figure 19). After the start condition, the device address
byte is sent, MSB first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. The address inputs (A0–A2) of the slave device must
not be changed between the start and the stop conditions.
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Programming (continued)
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (start or stop) (see Figure 20).
A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 19).
Any number of data bytes can be transferred from the transmitter to the receiver between the start and the stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see
Figure 21). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,
the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold
times must be met to ensure proper operation.
A master receiver will signal an end of data to the slave transmitter by not generating an acknowledge (NACK)
after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line
high. In this event, the transmitter must release the data line to enable the master to generate a Stop condition.
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 19. Definition Of Start And Stop Conditions
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 20. Bit Transfer
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Programming (continued)
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Start
Clock Pulse for
Condition
Acknowledgment
Figure 21. Acknowledgment On The I2C Bus
8.3.2 Register Map
Table 1. Interface Definition
BIT
BYTE
7 (MSB)
6
H
5
L
4
L
3
2
1
0 (LSB)
R/W
I2C slave address
Px I/O data bus
L
A2
P3
A1
P2
A0
P1
P7
P6
P5
P4
P0
8.3.2.1 Device Address
Figure 22 shows the address byte for the PCA9554.
Slave Address
0
0
1
0
A2 A1
R/W
A0
Hardware
Selectable
Fixed
Figure 22. PCA9554 Address
Table 2. Address Reference
INPUTS
I2C BUS SLAVE ADDRESS
A2
L
A1
L
A0
L
32 (decimal), 20 (hexadecimal)
33 (decimal), 21 (hexadecimal)
34 (decimal), 22 (hexadecimal)
35 (decimal), 23 (hexadecimal)
36 (decimal), 24 (hexadecimal)
37 (decimal), 25 (hexadecimal)
38 (decimal), 26 (hexadecimal)
39 (decimal), 27 (hexadecimal)
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
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The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read
is selected, while a low (0) selects a write operation.
8.3.2.2 Control Register And Command Byte
Following the successful acknowledgment of the address byte, the bus master sends a command byte that is
stored in the control register in the PCA9554. Two bits of this command byte state the operation (read or write)
and the internal register (input, output, polarity inversion or configuration) that will be affected. This register can
be written or read through the I2C bus. The command byte is sent only during a write transmission.
Once a command byte has been sent, the register that was addressed continues to be accessed by readsuntil a
new command byte has been sent.
0
0
0
0
0
0
B1 B0
Figure 23. Control Register Bits
Table 3. Command Byte
CONTROL REGISTER BITS
COMMAND BYTE
POWER-UP
DEFAULT
REGISTER
PROTOCOL
(HEX)
B1
0
B0
0
0x00
0x01
0x02
0x03
Input Port Register
Output Port Register
Read byte
XXXX XXXX
1111 1111
0000 0000
1111 1111
0
1
Read/write byte
Read/write byte
Read/write byte
1
0
Polarity Inversion Register
Configuration Register
1
1
8.3.2.3 Register Descriptions
The Input Port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is
defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these
registers have no effect. The default value, X, is determined by the externally applied logic level.
Before a read operation, a write transmission is sent with the command byte to indicate to the I2C device that the
Input Port register will be accessed next.
Table 4. Register 0 (Input Port Register) Table
BIT
I7
X
I6
X
I5
X
I4
X
I3
X
I2
X
I1
X
I0
X
DEFAULT
The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the
Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this
register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.
Table 5. Register 1 (Output Port Register) Table
BIT
O7
1
O6
1
O5
1
O4
1
O3
1
O2
1
O1
1
O0
1
DEFAULT
The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration
register. If a bit in this register is set (written with 1), the corresponding port pin polarity is inverted. If a bit in this
register is cleared (written with a 0), the corresponding port pin's original polarity is retained.
Table 6. Register 2 (Polarity Inversion Register) Table
BIT
N7
0
N6
0
N5
0
N4
0
N3
0
N2
0
N1
0
N0
0
DEFAULT
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The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1,
the corresponding port pin is enabled as an input with high impedance output driver. If a bit in this register is
cleared to 0, the corresponding port pin is enabled as an output.
Table 7. Register 3 (Configuration Register) Table
BIT
C7
1
C6
1
C5
1
C4
1
C3
1
C2
1
C1
1
C0
1
DEFAULT
8.3.2.4 Bus Transactions
Data is exchanged between the master and PCA9554 through write and read commands.
8.3.2.4.1 Writes
Data is transmitted to the PCA9554 by sending the device address and setting the least-significant bit to a logic 0
(see Figure 22 for device address). The command byte is sent after the address and determines which register
receives the data that follows the command byte. There is no limitation on the number of data bytes sent in one
write transmission.
SCL
1
2
3
4
5
6
7
8
9
Slave Address
Command Byte
Data to Port
Data 1
S
0
1
0
0 A2 A1 A0
0
A
0
0
0
0
0
0
0
1
A
A
P
SDA
ACK From Slave
ACK From Slave
R/W ACK From Slave
Start Condition
Write to Port
Data Out
From Port
Data 1 Valid
t
pv
Figure 24. Write To Output Port Register
<br/>
SCL
1
2
3
4
5
6
7
8
0
9
Slave Address
Command Byte
Data to Register
Data
SDA
S
0
1
0
0
A2 A1 A0
A
0
0
0
0
0
0
1
1/0
A
A
P
Start Condition
R/W ACK From Slave
ACK From Slave
ACK From Slave
Data to
Register
Figure 25. Write To Configuration Or Polarity Inversion Registers
8.3.2.4.2 Reads
The bus master first must send the PCA9554 address with the least-significant bit set to a logic 0 (see Figure 22
for device address). The command byte is sent after the address and determines which register is accessed.
After a restart, the device address is sent again but, this time, the least-significant bit is set to a logic 1. Data
from the register defined by the command byte then is sent by the PCA9554 (see Figure 26 and Figure 27). After
a restart, the value of the register defined by the command byte matches the register being accessed when the
restart occurred. Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation
on the number of data bytes received in one read transmission, but when the final byte is received, the bus
master must not acknowledge the data
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ACK From
Master
ACK From
Slave
ACK From
Slave
ACK From
Slave
Data from Register
Data
Slave Address
Slave Address
Command Byte
A
S
A
0
1
0
0
A2 A1 A0
1
A
S
0
1
0
0
A2 A1 A0
0
A
R/W
R/W
NACK From
Master
Data from Register
Data
P
NA
Last Byte
Figure 26. Read From Register
<br/>
1
2
3
4
5
6
7
8
9
SCL
SDA
Data From Port
Data 1
Slave Address
Data From Port
Data 4
S
0
1
0
0
A2 A1 A0
R/W
1
A
P
NA
A
Start
Condition
NACK From
Master
ACK From
Slave
ACK From
Master
Stop
Condition
Read From
Port
Data Into
Port
Data 2
Data 3
Data 4
Data 5
t
ph
t
ps
INT
t
iv
t
ir
A. This figure assumes the command byte has previously been programmed with 00h.
B. Transfer of data can be stopped at any moment by a Stop condition.
C. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from P port. See Figure 26 for these details.
Figure 27. Read From Input Port Register
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9 Application And Implementation
9.1 Typical Application
Figure 28 shows an application in which the PCA9554 can be used.
V
CC
100 kW
(y3)
(5 V)
2 kW
10 kW
10 kW
10 kW
V
CC
V
CC
Subsystem 1
(e.g., temperature sensor)
SDA
SCL
INT
SDA
P0
P1
Master
SCL
INT
Controller
GND
INT
P2
P3
RESET
Subsystem 2
(e.g., counter)
PCA9554
P4
A
P5
P6
P7
Controlled Device
A2
(e.g., CBT device)
ENABLE
A1
A0
B
GND
ALARM
Subsystem 3
(e.g., alarm system)
V
CC
A. Device address is configured as 0100000 for this example.
B. P0, P2, and P3 are configured as outputs.
C. P1, P4, and P5 are configured as inputs.
D. P6 and P7 are not used and and have internal 100-kΩ pullup resistors to protect them from floating.
Figure 28. Typical Application
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Typical Application (continued)
9.1.1 Design Requirements
9.1.1.1 Minimizing ICC When I/Os Control Leds
When the I/Os are used to control LEDs, they are normally connected to VCC through a resistor as shown in
Figure 28. The LED acts as a diode, so when the LED is off, the I/O VIN is about 1.2 V less than VCC. ΔICC in
Electrical Characteristics shows how ICC increases as VIN becomes lower than VCC
.
For battery-powered applications, it is essential that the voltage of I/O pins is greater than or equal to VCC when
the LED is off to minimize current consumption. Figure 29 shows a high-value resistor in parallel with the LED.
Figure 30 shows VCC less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O
VIN at or above VCC and prevent additional supply-current consumption when the LED is off.
V
CC
LED
100 kW
V
CC
LEDx
Figure 29. High-Value Resistor In Parallel With Led
5 V
3.3 V
LED
V
CC
LEDx
Figure 30. Device Supplied By A Lower Voltage
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10 Power Supply Recommendations
10.1 Power-On Reset Errata
A power-on reset condition can be missed if the VCC ramps are outside specification listed below.
System Impact
If ramp conditions are outside timing allowances above, POR condition can be missed, causing the device to lock
up.
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11 Device and Documentation Support
11.1 Trademarks
All trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
17-May-2014
PACKAGING INFORMATION
Orderable Device
PCA9554DB
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SSOP
SSOP
DB
16
16
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PD554
PCA9554DBG4
ACTIVE
DB
TBD
Call TI
Call TI
-40 to 85
PCA9554DBQ
PCA9554DBQR
PCA9554DBR
NRND
NRND
SSOP
SSOP
SSOP
DBQ
DBQ
DB
16
16
16
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 85
-40 to 85
-40 to 85
PD554
PD554
ACTIVE
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9554DBRG4
ACTIVE
SSOP
DB
16
TBD
Call TI
Call TI
-40 to 85
PCA9554DGV
NRND
TVSOP
TVSOP
DGV
DGV
16
16
TBD
Call TI
Call TI
-40 to 85
-40 to 85
PCA9554DGVR
ACTIVE
2000
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PD554
PCA9554DGVRG4
PCA9554DW
ACTIVE
ACTIVE
TVSOP
SOIC
DGV
DW
16
16
TBD
Call TI
Call TI
-40 to 85
-40 to 85
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9554
PCA9554
PCA9554DWG4
PCA9554DWR
ACTIVE
ACTIVE
SOIC
SOIC
DW
DW
16
16
TBD
Call TI
Call TI
-40 to 85
-40 to 85
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9554DWRG4
PCA9554PW
ACTIVE
NRND
SOIC
DW
PW
16
16
TBD
Call TI
Call TI
-40 to 85
-40 to 85
TSSOP
90
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PD554
PD554
PD554
PD554
PCA9554PWG4
PCA9554PWR
NRND
NRND
NRND
TSSOP
TSSOP
TSSOP
PW
PW
PW
16
16
16
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
2000
2000
Green (RoHS
& no Sb/Br)
PCA9554PWRG4
Green (RoHS
& no Sb/Br)
PCA9554RGTR
PCA9554RGVR
NRND
NRND
QFN
RGT
RGV
16
16
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 85
-40 to 85
VQFN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-May-2014
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PCA9554DBR
PCA9554DGVR
PCA9554DWR
PCA9554PWR
SSOP
TVSOP
SOIC
DB
DGV
DW
PW
16
16
16
16
2000
2000
2000
2000
330.0
330.0
330.0
330.0
16.4
12.4
16.4
12.4
8.2
6.8
6.6
4.0
2.5
1.6
2.7
1.6
12.0
8.0
16.0
12.0
16.0
12.0
Q1
Q1
Q1
Q1
10.75 10.7
6.9 5.6
12.0
8.0
TSSOP
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
PCA9554DBR
PCA9554DGVR
PCA9554DWR
PCA9554PWR
SSOP
TVSOP
SOIC
DB
DGV
DW
PW
16
16
16
16
2000
2000
2000
2000
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
38.0
35.0
38.0
35.0
TSSOP
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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