PCA9554DTR2G_技术文档

PCA9554

8-bit I²C and SMBus I/O Port

with Interrupt

Description

The PCA9554 is a CMOS device that provides 8−bit parallel

2

input/output port expansion for I C and SMBus compatible

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applications. This I/O expander provides a simple solution in

applications where additional I/Os are needed: sensors, power

switches, LEDs, pushbuttons, and fans.

The PCA9554 consist of an input port register, an output port

register, a configuration register, a polarity inversion register and an

I C/SMBus−compatible serial interface.

TSSOP−16

Y SUFFIX

CASE 948AN

2

Any of the eight I/Os can be configured as an input or output by

writing to the configuration register. The system master can invert the

PCA9554 input data by writing to the active−high polarity inversion

register.

The PCA9554 features an active low interrupt output which

indicates to the system master that an input state has changed.

The device’s extended addressing capability allows up to 8 devices

to share the same bus.

PIN CONNECTIONS

1

A0

A1

A2

V

CC

SDA

SCL

INT

I/O

0

1

I/O

7

6

5

4

Features

2

• 400 kHz I C Bus Compatible (Note 1)

3

V

SS

• 2.3 V to 5.5 V Operation

• Low Standby Current

TSSOP (Y)

(Top View)

• 5 V Tolerant I/Os

• 8 I/O Pins that Default to Inputs at Power−up

• High Drive Capability

ORDERING INFORMATION

• Individual I/O Configuration

• Polarity Inversion Register

• Active Low Interrupt Output

• Internal Power−on Reset

• No Glitch on Power−up

• Noise Filter on SDA/SCL Inputs

• Cascadable up to 8 Devices

• Industrial Temperature Range

• 16−lead TSSOP Package

†

Device

PCA9554DTR2G

Package

Shipping

TSSOP16

(Pb−Free)

2500 / Tape &

Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

Applications

• White Goods (dishwashers, washing machines)

• Handheld Devices (cell phones, PDAs, digital cameras)

• Data Communications (routers, hubs and servers)

1. All I/Os are set to inputs at RESET.

1

Publication Order Number:

November, 2017 − Rev. 0

PCA9554/D

PCA9554

A0

A1

I/O

0

1

2

3

4

5

6

7

A2

8−BIT

SCL

SDA

INPUT/

OUTPUT

PORTS

2

INPUT

I C/SMBUS

CONTROL

FILTER

WRITE pulse

READ pulse

V

CC

POWER−ON

RESET

V

CC

V

SS

LP FILTER

INT

Note: All I/Os are set to inputs at RESET.

Figure 1. Block Diagram

Table 1. PIN DESCRIPTION

TSSOP

Pin Name

Function

1

2

A0

A1

A2

Address Input 0

Address Input 1

Address Input 2

3

4−7

8

I/O

Input/Output Port 0 to Input/Output Port 3

Ground

0−3

SS

V

9−12

13

14

15

16

I/O

Input/Output Port 4 to Input/Output Port 7

Interrupt Output (open drain)

Serial Clock

4−7

INT

SCL

SDA

Serial Data

V

CC

Power Supply

Table 2. ABSOLUTE MAXIMUM RATINGS

Parameters

Ratings

−0.5 to +6.5

−0.5 to +5.5

50

Units

V

CC

with Respect to Ground

Voltage on Any Pin with Respect to Ground

V

DC Current on I/O to I/O

mA

W

0

7

DC Input Current

20

V

CC

V

SS

Supply Current

85

100

Package Power Dissipation Capability (T = 25°C)

1.0

A

Junction Temperature

Storage Temperature

+150

°C

−65 to +150

°C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

Table 3. RELIABILITY CHARACTERISTICS

Symbol

(Note 2)

Parameter

ESD Susceptibility

Latch−up

Reference Test Method

JEDEC Standard JESD 22

JEDEC Standard 17

Min

2000

100

Units

Volts

mA

V

ZAP

I

(Notes 2, 3)

LTH

2. This parameter is tested initially and after a design or process change that affects the parameter.

3. Latch−up protection is provided for stresses up to 100 mA on address and data pins from −1 V to V +1 V.

CC

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2

PCA9554

Table 4. D.C. OPERATING CHARACTERISTICS (V = 2.3 to 5.5 V; T = −40°C to +85°C, unless otherwise specified.)

CC

A

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

SUPPLIES

V

Supply voltage

2.3

−

5.5

V

CC

I

Supply current

Operating mode; V = 5.5 V;

104

175

mA

CC

no load; f

= 100 kHz

SCL

I

Standby current

Standby mode; V = 5.5 V; no load;

−

550

0.25

1.5

700

1

mA

V

stbl

CC

V = V ; f

= 0 kHz; I/O = inputs

I

SS SCL

I

Standby current

Standby mode; V = 5.5 V; no load;

CC

stbh

V = V ; f

= 0 kHz; I/O = inputs

I

CC SCL

V

POR

Power−on reset voltage

No load; V = V or V

1.65

I

CC

SS

SCL, SDA, INT

V

(Note 4)

Low level input voltage

High level input voltage

Low level output current

Leakage current

−0.5

−

0.3 x V

V

IL

CC

V

IH

0.7 x V

5.5

−

CC

I

OL

V

= 0.4 V

3

−1

−

mA

pF

OL

I

L

V = V or V

I

+1

6

CC

SS

C (Note 5)

Input capacitance

V = V

I

SS

C

(Note 5)

Output capacitance

V

O

= V

SS

−

8

O

A0, A1, A2

V

(Note 4)

Low level input voltage

High level input voltage

Input leakage current

−0.5

2.0

−1

−

0.8

5.5

1

V

IL

V

IH

I

LI

mA

I/Os

V

Low level input voltage

High level input voltage

Low level output current

−0.5

2.0

8

−

0.8

5.5

−

V

IL

V

IH

I

OL

V

= 0.5 V; V = 2.3 V (Note 6)

10

13

17

24

14

19

−

mA

V

OL

OH

CC

= 0.7 V; V = 2.3 V (Note 6)

10

8

−

CC

= 0.5 V; V = 4.5 V (Note 6)

−

CC

= 0.7 V; V = 4.5 V (Note 6)

10

8

−

CC

= 0.5 V; V = 3.0 V (Note 6)

−

CC

= 0.7 V; V = 3.0 V (Note 6)

10

1.8

1.7

2.6

2.5

4.1

4.0

−

CC

V

OH

High level output

voltage

I

= −8 mA; V = 2.3 V (Note 7)

−

CC

= −10 mA; V = 2.3 V (Note 7)

−

V

CC

= −8 mA; V = 3.0 V (Note 7)

−

V

CC

= −10 mA; V = 3.0 V (Note 7)

−

V

CC

= −8 mA; V = 4.75 V (Note 7)

−

V

CC

= −10 mA; V = 4.75 V (Note 7)

−

V

CC

I

IH

Input leakage current

Input capacitance

V

CC

V

CC

= 3.6 V; V = V

−

1

mA

pF

I

CC

SS

I

IL

= 5.5 V; V = V

−

−100

I

C (Note 5)

−

5

8

I

C

(Note 5)

Output capacitance

−

O

4. V

and V

are reference values only and are not tested.

IL min

IH max

5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.

6. The total current sunk by all I/Os must be limited to 100 mA and each I/O limited to 25 mA maximum.

7. The total current sourced by all I/Os must be limited to 85 mA.

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3

PCA9554

Table 5. A.C. CHARACTERISTICS (V = 2.3 V to 5.5 V; T = −40°C to +85°C, unless otherwise specified.) (Note 8)

CC

A

2

Standard I C

Fast I C

Max

Min

Max

Min

Symbol

Parameter

Units

kHz

ms

F

SCL

Clock Frequency

100

400

t

START Condition Hold Time

Low Period of SCL Clock

High Period of SCL Clock

START Condition Setup Time

Data In Hold Time

4

4.7

4

0.6

1.3

0.6

0

HD:STA

t

ms

LOW

t

ms

HIGH

t

4.7

0

ms

SU:STA

HD:DAT

t

ms

t

Data In Setup Time

250

100

ns

SU:DAT

t

(Note 9)

SDA and SCL Rise Time

SDA and SCL Fall Time

STOP Condition Setup Time

Bus Free Time Between STOP and START

SCL Low to Data Out Valid

Data Out Hold Time

1000

300

ns

R

t (Note 9)

ns

F

t

4

0.6

1.3

ms

SU:STO

t

(Note 9)

4.7

ms

BUF

t

3.5

0.9

ms

AA

DH

t

100

50

ns

T (Note 9)

i

Noise Pulse Filtered at SCL and SDA Inputs

100

ns

Symbol

Parameter

Min

Max

Units

PORT TIMING

t

Output Data Valid

200

ns

ms

PV

PS

PH

Input Data Setup Time

Input Data Hold Time

100

1

t

INTERRUPT TIMING

t

Interrupt Valid

Interrupt Reset

4

ms

IV

IR

t

8. Test conditions according to “AC Test Conditions” table.

9. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.

Table 6. A.C. TEST CONDITIONS

Input Rise and Fall time

CMOS Input Voltages

≤ 10 ns

0.2 V to 0.8 V

CC

CMOS Input Reference Voltages

TTL Input Voltages

0.3 V to 0.7 V

CC

0.4 V to 2.4 V

0.8 V, 2.0 V

TTL Input Reference Voltages

Output Reference Voltages

Output Load: SDA, INT

Output Load: I/Os

0.5 V

CC

Current Source I = 3 mA; C = 100 pF

OL

L

Current Source: I /I = 10 mA; C = 50 pF

OL OH

L

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4

PCA9554

t

F

t

R

t

HIGH

t

LOW

SCL

t

HD:DAT

SU:STA

t

SU:STO

SU:DAT

HD:STA

SDA IN

t

BUF

t

AA

DH

SDA OUT

Figure 2. I²C Serial Interface Timing

A0, A1, A2: Device Address Inputs

These inputs are used for extended addressing capability.

The A0, A1, A2 pins should be hardwired to V or V

When hardwired, up to eight PCA9554s may be addressed

on a single bus system. The levels on these inputs are

compared with corresponding bits, A2, A1, A0, from the

slave address byte.

Pin Description

SCL: Serial Clock

The serial clock input clocks all data transferred into or out

of the device. The SCL line requires a pull−up resistor if it

is driven by an open drain output.

.

SS

CC

SDA: Serial Data/Address

The bidirectional serial data/address pin is used to transfer

all data into and out of the device. The SDA pin is an open

drain output and can be wire−ORed with other open drain or

open collector outputs. A pull−up resistor must be connected

I/O₀to I/O₇: Input / Output Ports

Any of these pins may be configured as input or output.

The simplified schematic of I/O to I/O is shown in

Figure 5. When an I/O is configured as an input, the Q1 and

Q2 output transistors are off creating a high impedance input

with a weak pull−up resistor (typical 100 kW). If the I/O pin

is configured as an output, the push−pull output stage is

enabled. Care should be taken if an external voltage is

applied to an I/O pin configured as an output due to the low

0

7

from SDA line to V . The value of the pull−up resistor, R ,

CC

P

can be calculated based on minimum and maximum values

from Figure 3 and Figure 4 (see Note).

impedance paths that exist between the pin and either V

CC

or V .

SS

2.5

8

2

Fast Mode I C Bus /

I

OL

= 3 mA @ V

OLmax

7

6

5

4

3

2

tr max − 300 ns

2.0

1.5

1.0

0.5

0

1

0

2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6

(V)

0

50

100 150 200 250 300 350 400

V

CC

C

(pF)

BUS

Figure 3. Minimum R_PValue vs.

Figure 4. Maximum R_PValue vs.

Bus Capacitance

Supply Voltage

2

NOTE: According to the Fast Mode I C bus specification, for bus capacitance up to 200 pF, the pull up device can be a resistor. For bus

loads between 200 pF and 400 pF, the pull−up device can be a current source (Imax = 3 mA) or a switched resistor circuit.

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5

PCA9554

INT: Interrupt Output

The open−drain interrupt output is activated when one of

the port pins configured as an input changes state (differs

from the corresponding input port register bit state). The

interrupt is deactivated when the input returns to its previous

state or the input port register is read. Changing an I/O from

an output to an input may cause a false interrupt if the state

of the pin does not match the contents of the input port

register.

Data from

Shift Register

Output Port

Register Data

Configuration

Register

Data from

Shift Register

V

CC

Q

D

FF

Q1

Write

Configuration

Pulse

100 kW

C

Q

K

Q

D

C

FF

I/O to I/O

0

7

Write Pulse

K

Output Port

Register

Q2

Input Port

Register

V

SS

Q

D

Input Port

Register Data

LATCH

Read Pulse

C

Q

K

To INT

Data from

Shift Register

Polarity

Register Data

D

Q

FF

Write

Polarity

Register

C

K

Polarity

Inversion Register

Figure 5. Simplified Schematic of I/O₀to I/O₇

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6

PCA9554

START and STOP Conditions

Functional Description

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of SDA

when SCL is HIGH. The PCA9554 monitors the SDA and

SCL lines and will not respond until this condition is met.

A LOW to HIGH transition of SDA when SCL is HIGH

determines the STOP condition. All operations must end

with a STOP condition.

The PCA9554’s general purpose input/output (GPIO)

peripherals provide up to eight I/O ports, controlled through

2

an I C compatible serial interface.

2

The PCA9554 supports the I C Bus data transmission

2

protocol. This I C Bus protocol defines any device that

sends data to the bus to be a transmitter and any device

receiving data to be a receiver. The transfer is controlled by

the Master device which generates the serial clock and all

START and STOP conditions for bus access. The PCA9554

operates as a Slave device. Both the Master device and Slave

device can operate as either transmitter or receiver, but the

Master device controls which mode is activated.

Device Addressing

After the bus Master sends a START condition, a slave

address byte is required to enable the PCA9554 for a read or

write operation. The four most significant bits of the slave

address are fixed as binary 0100 for the PCA9554 (Figure 7).

The PCA9554 uses the next three bits as address bits.

The address bits A2, A1 and A0 are used to select which

device is accessed from maximum eight devices on the same

bus. These bits must compare to their hardwired input pins.

The 8th bit following the 7−bit slave address is the R/W bit

that specifies whether a read or write operation is to be

performed. When this bit is set to “1”, a read operation is

initiated, and when set to “0”, a write operation is selected.

Following the START condition and the slave address

byte, the PCA9554 monitors the bus and responds with an

acknowledge (on the SDA line) when its address matches

the transmitted slave address. The PCA9554 then performs

a read or a write operation depending on the state of the R/W

bit.

I²C Bus Protocol

2

The features of the I C bus protocol are defined as follows:

1. Data transfer may be initiated only when the bus is

not busy.

2. During a data transfer, the data line must remain

stable whenever the clock line is high. Any

changes in the data line while the clock line is high

will be interpreted as a START or STOP condition

(Figure 6).

SCL

SDA

START

STOP

CONDITION

Figure 6. START/STOP Condition

SLAVE ADDRESS

A2

0

1

0

A1

A0 R/W

FIXED

PROGRAMMABLE

HARDWARE

SELECTABLE

Figure 7. PCA9554 Slave Address

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7

PCA9554

Acknowledge

The command byte is the first byte to follow the device

address byte during a write/read bus transaction. The

register command byte acts as a pointer to determine which

register will be written or read.

The input port register is a read only port. It reflects the

incoming logic levels of the I/O pins, regardless of whether

the pin is defined as an input or an output by the

configuration register. Writes to the input port register are

ignored.

After a successful data transfer, each receiving device is

required to generate an acknowledge. The acknowledging

device pulls down the SDA line during the ninth clock cycle,

signaling that it received the 8 bits of data. The SDA line

remains stable LOW during the HIGH period of the

acknowledge related clock pulse (Figure 6).

The PCA9554 responds with an acknowledge after

receiving a START condition and its slave address. If the

device has been selected along with a write operation, it

responds with an acknowledge after receiving each 8−bit

byte.

Table 8. REGISTER 0 – INPUT PORT REGISTER

bit

I

7

I

6

I

5

I

4

I

3

I

2

I

1

I

0

When the PCA9554 begins a READ mode it transmits 8

bits of data, releases the SDA line, and monitors the line for

an acknowledge. Once it receives this acknowledge, the

PCA9554 will continue to transmit data. If no acknowledge

is sent by the Master, the device terminates data transmission

and waits for a STOP condition. The master must then issue

a STOP condition to return the PCA9554 to the standby

power mode and place the device in a known state.

default

1

Table 9. REGISTER 1 – OUTPUT PORT REGISTER

bit

O

0

7

6

5

4

3

2

1

default

1

Table 10. REGISTER 2 –

POLARITY INVERSION REGISTER

Registers and Bus Transactions

The PCA9554 consists of an input port register, an output

bit

N

0

7

6

5

4

3

2

1

default

0

port register,

a polarity inversion register and a

configuration register. Table 7 shows the register address

table. Tables 8 to 11 list Register 0 through Register 3

information.

Table 11. REGISTER 3 – CONFIGURATION REGISTER

bit

C

0

7

6

5

4

3

2

1

default

1

Table 7. REGISTER COMMAND BYTE

Command

(hex)

0x00

0x01

0x02

0x03

Protocol

Function

Read byte

Input port register

Read/write byte

Output port register

Polarity inversion register

Configuration register

BUS RELEASE DELAY (TRANSMITTER)

BUS RELEASE DELAY (RECEIVER)

SCL FROM

MASTER

1

8

9

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

ACK SETUP

START

ACK DELAY

Figure 8. Acknowledge Timing

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8

PCA9554

The output port register sets the outgoing logic levels of

corresponding port pin as an input with a high impedance

output driver. If a bit in this register is cleared, the

corresponding port pin is enabled as an output. At

power−up, the I/Os are configured as inputs with a weak

the I/O ports, defined as outputs by the configuration

register. Bit values in this register have no effect on I/O pins

defined as inputs. Reads from the output port register reflect

the value that is in the flip−flop controlling the output, not

the actual I/O pin value.

The polarity inversion register allows the user to invert the

polarity of the input port register data. If a bit in this register

is set (“1”) the corresponding input port data is inverted. If

a bit in the polarity inversion register is cleared (“0”), the

original input port polarity is retained.

pull−up resistor to V

.

CC

Data is transmitted to the PCA9554’s registers using the

write mode shown in Figure 9 and Figure 10.

The PCA9554’s registers are read according to the timing

diagrams shown in Figure 11 and Figure 12. Once a

command byte has been sent, the register which was

addressed will continue to be accessed by reads until a new

command byte will be sent.

The configuration register sets the directions of the ports.

Set the bit in the configuration register to enable the

SCL

1

2

3

4

5

6

7

8

9

R/W

slave address

A2 A1 A0

command byte

data to port

SDA

S

0

1

0

A

DATA 1

A

P

A

0

1

acknowledge

from slave

acknowledge from slave

start condition

stop

condition

WRITE TO

PORT

DATA 1 VALID

DATA OUT FROM PORT

t

pv

Figure 9. Write to Output Port Register

SCL

1

2

3

4

5

6

7

8

9

R/W

0

slave address

A2 A1 A0

command byte

data to register

DATA 1

SDA

A

P

S

0

1

0

A

0

1 1/0

acknowledge from slave

acknowledge

from slave

acknowledge from slave

stop

condition

start condition

WRITE TO

REGISTER

Figure 10. Write to Configuration or Polarity Inversion Register

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9

PCA9554

Power−On Reset Operation

When the power supply is applied to V pin, an internal

power−on reset pulse holds the PCA9554 in a reset state

condition is released and the internal state machine and the

PCA9554’s registers are initialized to their default state.

CC

until V

reaches V

level. At this point, the reset

CC

POR

acknowledge from master

R/W

slave address

R/W

slave address

data from register

S

0

1

0

0 A2 A1 A0

0

A S

A

COMMAND BYTE

0

1

0

A2 A1 A0 1 A

DATA

A

acknowledge from slave

first byte

At this moment master−transmitter becomes

master−receiver and slave−receiver

becomes slave−transmitter

no acknowledge

from master

data from register

DATA

NA

P

last byte

Figure 11. Read from Register

SCL

SDA

1

2

3

4

5

6

7

8

9

slave address

data from port

R/W

DATA 1

S

0

1

0

A2 A1 A0

1

A

DATA 4

A

NA

P

acknowledge

from slave

acknowledge

from master

no acknowledge

from master

start condition

stop

condition

READ FROM

PORT

DATA INTO

PORT

DATA 1

DATA 2

DATA 3

DATA 4

t

PS

PH

INT

t

IR

t

IV

Figure 12. Read Input Port Register

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10

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

TSSOP16, 4.4x5

CASE 948AN−01

ISSUE O

DATE 19 DEC 2008

b

SYMBOL

MIN

NOM

MAX

A

A1

A2

b

1.10

0.15

0.95

0.30

0.20

5.10

6.50

4.50

0.05

0.85

0.19

0.13

4.90

6.30

4.30

E1

E

c

D

E

E1

e

0.65 BSC

1.00 REF

L

L1

0.45

0.75

0º

8º

θ

e

PIN#1

IDENTIFICATION

TOP VIEW

D

c

A2

A1

A

θ1

L1

L

SIDE VIEW

Notes:

END VIEW

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MO-153.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON34436E

TSSOP16, 4.4X5

PAGE 1 OF 1

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


型号：	PCA9554DTR2G
厂家：	ONSEMI
描述：	具有中断、8 位 I2C 的 SMBus I / O 端口
文件：	总12页 (文件大小：163K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCA9554DTR2G [ONSEMI]

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