PCA9543APWR [TI]
TWO-CHANNEL I2C-BUS SWITCH WITH INTERRUPT LOGIC AND RESET; TWO- CHANNEL I2C总线具有中断逻辑和复位开关
| 型号： | PCA9543APWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TWO-CHANNEL I2C-BUS SWITCH WITH INTERRUPT LOGIC AND RESET |
| 文件： | 总20页 (文件大小：500K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCA9543A
TWO-CHANNEL I2C-BUS SWITCH
WITH INTERRUPT LOGIC AND RESET
www.ti.com
SCPS169–SEPTEMBER 2007
1
FEATURES
•
1-of-2 Bidirectional Translating Switches
I2C Bus and SMBus Compatible
Two Active-Low Interrupt Inputs
Active-Low Interrupt Output
•
•
•
Supports Hot Insertion
Low Standby Current
•
•
•
•
•
Operating Power-Supply Voltage Range of
2.3 V to 5.5 V
•
•
•
5-V Tolerant Inputs
Active-Low Reset Input
0 to 400-kHz Clock Frequency
Two Address Pins Allowing up to Four
Devices on the I2C Bus
Channel Selection Via I2C Bus, in Any
Combination
Latch-Up Performance Exceeds 100 mA Per
JESD78
•
•
•
ESD Protection Exceeds JESD 22
Power Up With All Switch Channels
Deselected
–
–
–
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
•
•
Low ron Switches
1000-V Charged-Device Model (C101)
Allows Voltage-Level Translation Between
1.8-V, 2.5-V, 3.3-V, and 5-V Buses
•
No Glitch on Power Up
D PACKAGE
(TOP VIEW)
PW PACKAGE
(TOP VIEW)
VCC
1
2
3
4
5
6
7
14
13
12
11
10
9
A0
A1
VCC
1
2
3
4
5
6
7
14
13
12
11
10
9
A0
A1
SDA
SCL
INT
SDA
SCL
INT
RESET
INT0
SD0
RESET
INT0
SD0
SC1
SD1
INT1
SC1
SD1
INT1
SC0
SC0
GND
8
GND
8
DESCRIPTION/ORDERING INFORMATION
The PCA9543A is a bidirectional translating switch controlled by the I2C bus. The SCL/SDA upstream pair fans
out to two downstream pairs, or channels. Any individual SCn/SDn channel or combination of channels can be
selected, determined by the contents of the programmable control register. Two interrupt inputs (INT0–INT1),
one for each of the downstream pairs, are provided. One interrupt output (INT) acts as an AND of the two
interrupt inputs.
ORDERING INFORMATION
TA
PACKAGE(1)(2)
ORDERABLE PART NUMBER
PCA9543AD
TOP-SIDE MARKING
PCA9543A
Tube of 50
SOIC – D
Reel of 2500
Tube of 90
PCA9543ADR
PCA9543APW
PCA9543APWR
–40°C to 85°C
TSSOP – PW
PD543A
Reel of 2000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
PCA9543A
TWO-CHANNEL I2C-BUS SWITCH
WITH INTERRUPT LOGIC AND RESET
www.ti.com
SCPS169–SEPTEMBER 2007
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
An active-low reset (RESET) input allows the PCA9543A to recover from a situation where one of the
downstream I2C buses is stuck in a low state. Pulling RESET low resets the I2C state machine and causes all the
channels to be deselected, as does the internal power-on reset function.
The pass gates of the switches are constructed such that the VCC pin can be used to limit the maximum high
voltage, which will be passed by the PCA9543A. This allows the use of different bus voltages on each pair, so
that 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts without any additional protection. External
pullup resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5-V tolerant.
TERMINAL FUNCTIONS
D AND PW
PIN NUMBER
NAME
DESCRIPTION
1
2
A0
A1
Address input 0. Connect directly to VCC or ground.
Address input 1. Connect directly to VCC or ground.
Active-low reset input. Connect to VCC through a pullup resistor, if not used.
Active-low interrupt input 0. Connect to VCC through a pullup resistor.
Serial data 0. Connect to VCC through a pullup resistor.
Serial clock 0. Connect to VCC through a pullup resistor.
Ground
3
RESET
INT0
SD0
SC0
GND
INT1
SD1
SC1
INT
4
5
6
7
8
Active-low interrupt input 1. Connect to VCC through a pullup resistor.
Serial data 1. Connect to VCC through a pullup resistor.
Serial clock 1. Connect to VCC through a pullup resistor.
Active-low interrupt output. Connect to VCC through a pullup resistor.
Serial clock line. Connect to VCC through a pullup resistor.
Serial data line. Connect to VCC through a pullup resistor.
Supply power
9
10
11
12
13
14
SCL
SDA
VCC
2
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PCA9543A
TWO-CHANNEL I2C-BUS SWITCH
WITH INTERRUPT LOGIC AND RESET
www.ti.com
SCPS169–SEPTEMBER 2007
BLOCK DIAGRAM
PCA9543A
6
SC0
10
SC1
5
SD0
9
SD1
7
Switch Control Logic
GND
14
VCC
Power-On
Reset
3
RESET
1
12
13
SCL
SDA
A0
I2C Bus
Control
Input Filter
2
A1
4
8
11
INT0
INT1
INT
Output Filter
Interrupt Logic
Figure 1. Block Diagram
Device Address
Following a start condition, the bus master must output the address of the slave it is accessing. The address of
the PCA9543A is shown in Figure 2. To conserve power, no internal pullup resistors are incorporated on the
hardware-selectable address pins and they must be pulled high or low.
1
1
1
0
0
A1 A0 R/W
Fixed
Hardware
selectable
Figure 2. Slave Address PCA9543A
The last bit of the slave address defines the operation to be performed. When set to a logic 1, a read is selected,
while a logic 0 selects a write operation.
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PCA9543A
TWO-CHANNEL I2C-BUS SWITCH
WITH INTERRUPT LOGIC AND RESET
www.ti.com
SCPS169–SEPTEMBER 2007
Control Register
Following the successful acknowledgement of the slave address, the bus master sends a byte to the PCA9543A,
which is stored in the control register (see Figure 3). If multiple bytes are received by the PCA9543A, it saves the
last byte received. This register can be written and read via the I2C bus.
Channel Selection Bits
(Read/Write)
Interrupt Bits
(Read Only)
7
6
X
5
4
3
X
2
X
1
0
X
INT1 INT0
B1 B0
Channel 0
Channel 1
INT0
INT1
Figure 3. Control Register
Control Register Definition
One or several SCn/SDn downstream pairs, or channels, are selected by the contents of the control register (see
Table 1). After the PCA9543A has been addressed, the control register is written. The two LSBs of the control
byte are used to determine which channel or channels are to be selected. When a channel is selected, the
channel becomes active after a stop condition has been placed on the I2C bus. This ensures that all SCn/SDn
lines are in a high state when the channel is made active, so that no false conditions are generated at the time of
connection. A stop condition must occur always right after the acknowledge cycle.
Table 1. Control Register Write (Channel Selection), Control Register Read (Channel Status)(1)
D7
D6
INT1
INT0
D3
D2
B1
B0
0
COMMAND
Channel 0 disabled
X
X
X
X
X
X
X
1
Channel 0 enabled
0
1
0
Channel 1 disabled
X
0
X
0
X
0
X
0
X
0
X
0
X
0
Channel 1 enabled
No channel selected; power-up/reset default state
(1) Channel 0 and channel 1 can be enabled at the same time. Care should be taken not to exceed the maximum bus capacitance.
Interrupt Handling
The PCA9543A provides two interrupt inputs (one for each channel) and one open-drain interrupt output (see
Table 2). When an interrupt is generated by any device, it is detected by the PCA9543A and the interrupt output
is driven low. The channel does not need to be active for detection of the interrupt. A bit also is set in the control
register.
Bit 4 and Bit 5 of the control register correspond to the INT0 and INT1 inputs of the PCA9543A, respectively.
Therefore, if an interrupt is generated by any device connected to channel 1, the state of the interrupt inputs is
loaded into the control register when a read is accomplished. Likewise, an interrupt on any device connected to
channel 0 would cause bit 4 of the control register to be set on the read. The master then can address the
PCA9543A and read the contents of the control register to determine which channel contains the device
generating the interrupt. The master then can reconfigure the PCA9543A to select this channel, and locate the
device generating the interrupt and clear it.
It should be noted that more than one device can provide an interrupt on a channel, so it is up to the master to
ensure that all devices on a channel are interrogated for an interrupt.
The interrupt inputs may be used as general-purpose inputs if the interrupt function is not required.
If unused, interrupt input(s) must be connected to VCC through a pullup resistor.
4
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PCA9543A
TWO-CHANNEL I2C-BUS SWITCH
WITH INTERRUPT LOGIC AND RESET
www.ti.com
SCPS169–SEPTEMBER 2007
Table 2. Control Register Read (Interrupt)(1)
D7
D6
INT1
INT0
D3
D2
B1
B0
COMMAND
No interrupt on channel 0
0
1
X
X
X
X
X
X
X
Interrupt on channel 0
0
1
0
No interrupt on channel 1
X
0
X
0
X
0
X
0
X
0
X
0
X
0
Interrupt on channel 1
No channel selected; power-up/reset default state
(1) Two interrupts can be active at the same time.
RESET Input
The RESET input can be used to recover the PCA9543A from a bus-fault condition. The registers and the I2C
state machine within this device initialize to their default states if this signal is asserted low for a minimum of tWL
.
All channels also are deselected in this case. RESET must be connected to VCC through a pullup resistor.
Power-On Reset
When power is applied to VCC, an internal power-on reset holds the PCA9543A in a reset condition until VCC has
reached VPOR. At this point, the reset condition is released and the PCA9543A registers and I2C state machine
are initialized to their default states, all zeroes, causing all the channels to be deselected. Thereafter, VCC must
be lowered below 0.2 V to reset the device.
Voltage Translation
The pass-gate transistors of the PCA9543A are constructed such that the VCC voltage can be used to limit the
maximum voltage that is passed from one I2C bus to another.
5.0
4.0
Max
Typ
3.0
Min
2.0
1.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VCC (V)
Figure 4. Vpass Voltage vs VCC
Figure 4 shows the voltage characteristics of the pass gate transistors (note that the graph was generated using
the data specified in Electrical Characteristics section of this data sheet). In order for the PCA9543A to act as a
voltage translator, the Vpass voltage should be equal to or lower than the lowest bus voltage. For example, if the
main bus is running at 5 V and the downstream buses are 3.3 V and 2.7 V, Vpass must be equal to or below 2.7 V
to effectively clamp the downstream bus voltages. As shown in Figure 4, Vpass(max) is at 2.7 V when the
PCA9543A supply voltage is 3.5 V or lower, so the PCA9543A supply voltage could be set to 3.3 V. Pullup
resistors then can be used to bring the bus voltages to their appropriate levels (see Figure 14).
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PCA9543A
TWO-CHANNEL I2C-BUS SWITCH
WITH INTERRUPT LOGIC AND RESET
www.ti.com
SCPS169–SEPTEMBER 2007
I2C Interface
The I2C bus is for two-way, two-line communication between different ICs or modules. The two lines are a serial
data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pullup
resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not
busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high
period of the clock pulse as changes in the data line at this time is interpreted as control signals (see Figure 5).
SDA
SCL
Data Line
Stable;
Data Valid
Change
of data
allowed
Figure 5. Bit Transfer
Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the
clock is high is defined as the start condition (S). A low-to-high transition of the data line while the clock is high is
defined as the stop condition (P) (see Figure 6).
SDA
SDA
SCL
SCL
S
P
STOP Condition
START Condition
Figure 6. Definition of Start and Stop Conditions
A device generating a message is a transmitter; a device receiving a message is the receiver. The device that
controls the message is the master and the devices that are controlled by the master are the slaves (see
Figure 7).
SDA
SCL
Master
Transmitter/
Receiver
Slave
Master
Transmitter/
Receiver
I2C-Bus
Slave
Master
Transmitter/
Receiver
Receiver
Transmitter
Multiplexer
Slave
Figure 7. System Configuration
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not
limited. Each byte of eight bits is followed by one acknowledge (ACK) bit. The transmitter must release the SDA
line before the receiver can send an ACK bit.
6
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PCA9543A
TWO-CHANNEL I2C-BUS SWITCH
WITH INTERRUPT LOGIC AND RESET
www.ti.com
SCPS169–SEPTEMBER 2007
When a slave receiver is addressed, it must generate an ACK after the reception of each byte. Also, a master
must generate an ACK after the reception of each byte that has been clocked out of the slave transmitter. The
device that acknowledges must pull down the SDA line during the ACK clock pulse, so that the SDA line is stable
low during the high pulse of the ACK-related clock period (see Figure 8). Setup and hold times must be taken
into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.
In this event, the transmitter must release the data line to enable the master to generate a stop condition.
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Clock Pulse for
Acknowledgment
Start
Condition
Figure 8. Acknowledgment on I2C Bus
Data is transmitted to the PCA9543A control register using the write mode shown in Figure 9.
Slave Address
Control Register
SDA
S
1
1
1
0
0
A1 A0
0
A
X
X
X
X
X
X
B1 B0
A
P
Start
Condition
R/W Acknowledge
From Slave
Acknowledge
From Slave
Stop
Condition
Figure 9. Write Control Register
Data is read from the PCA9543A control register using the read mode shown in Figure 10.
Last Byte
Slave Address
Control Register
SDA
INT1
S
1
1
1
0
0
A1 A0
1
A
X
X
INT0
X
X
B1 B0 NA
P
Start
Condition
R/W Acknowledge
From Slave
No Acknowledge
From Master
Stop
Condition
Figure 10. Read Control Register
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PCA9543A
TWO-CHANNEL I2C-BUS SWITCH
WITH INTERRUPT LOGIC AND RESET
www.ti.com
SCPS169–SEPTEMBER 2007
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
MAX
UNIT
VCC
VI
Supply voltage range
Input voltage range(2)
Input current
7
V
7
±20
±25
±100
±100
86
V
II
mA
mA
mA
mA
IO
Output current
Continuous current through VCC
Continuous current through GND
D package
θJA
Package thermal impedance(3)
°C/W
PW package
113
400
150
85
Ptot
Tstg
TA
Total power dissipation
mW
°C
Storage temperature range
Operating free-air temperature range
–60
–40
°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
MIN
2.3
MAX
5.5
UNIT
VCC
Supply voltage
V
SCL, SDA
0.7 × VCC
0.7 × VCC
0.7 × VCC
0.7 × VCC
–0.5
6
VCC = 2.3 V to 3.6 V
VCC + 0.5
VCC + 0.5
VCC + 0.5
0.3 × VCC
0.3 × VCC
85
VIH
High-level input voltage
V
A1, A0, INT1, INT0, RESET VCC = 3.6 V to 4.5 V
VCC = 4.5 V to 5.5 V
SCL, SDA
VIL
TA
Low-level input voltage
V
A1, A0, INT1, INT0, RESET
–0.5
Operating free-air temperature
–40
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
8
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PCA9543A
TWO-CHANNEL I2C-BUS SWITCH
WITH INTERRUPT LOGIC AND RESET
www.ti.com
SCPS169–SEPTEMBER 2007
Electrical Characteristics(1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
No load: VI = VCC or GND(2)
VCC
VPOR
MIN
TYP
1.6
MAX
UNIT
VPOR
Power-on reset voltage
2.1
V
5 V
3.6
4.5 V to 5.5 V
3.3 V
2.6
1.6
1.1
4.5
2.8
1.9
1.5
VSWin = VCC
ISWout = –100 μA
,
Vpass
Switch output voltage
V
3 V to 3.6 V
2.5 V
2.3 V to 2.7 V
2.3 V to 5.5 V
2
IOH
INT
VO = VCC
100
μA
VOL = 0.4 V
VOL = 0.6 V
VOL = 0.4 V
VI = VCC or GND
3
6
7
SDA
IOL
2.3 V to 5.5 V
10
mA
INT
3
SCL, SDA
2.3 V to 5.5 V
2.3 V to 3.6 V
4.5 V to 5.5 V
2.3 V to 3.6 V
4.5 V to 5.5 V
2.3 V to 3.6 V
4.5 V to 5.5 V
2.3 V to 3.6 V
4.5 V to 5.5 V
5.5 V
–1
–1
–1
–1
–1
–1
–1
–1
–1
1
1
SC1–SC0, SD1–SD0
A1, A0
VI = VCC or GND
VI = VCC or GND
VI = VCC or GND
VI = VCC or GND
100
1
II
50
1
μA
INT1–INT0
RESET
50
1
50
50
20
16
1
17
6
Operating fSCL = 100
mode
VI = VCC or GND, IO = 0
VI = GND, IO = 0
3.6 V
kHz
2.7 V
3
5.5 V
0.3
0.1
0.1
0.3
0.1
0.1
ICC
Low inputs
3.6 V
1
μA
2.7 V
1
Standby
mode
5.5 V
1
High inputs
INT1–INT0
VI = VCC, IO = 0
3.6 V
1
2.7 V
1
One INT1–INT0 input at 0.6 V,
Other inputs at VCC or GND
8
8
8
8
20
20
20
20
One INT1–INT0 input at VCC – 0.6 V,
Other inputs at VCC or GND
Supply-
current
change
ΔICC
2.3 V to 5.5 V
μA
SCL or SDA input at 0.6 V,
Other inputs at VCC or GND
SCL, SDA
SCL or SDA input at VCC – 0.6 V,
Other inputs at VCC or GND
2.3 V to 3.6 V
4.5 V to 5.5 V
2.3 V to 3.6 V
4.5 V to 5.5 V
2.3 V to 3.6 V
4.5 V to 5.5 V
2.3 V to 5.5 V
4
4
4
4
4
4
9
5
5
A1, A0
VI = VCC or GND
VI = VCC or GND
6
INT1–INT0
Ci
6
pF
5
RESET
SCL
VI = VCC or GND
VI = VCC or GND
5
12
(1) For operation between published voltage ranges, refer to the worst-case parameter in both ranges.
(2) To reset the part, either RESET must be low or VCC must be lowered to 0.2 V.
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TWO-CHANNEL I2C-BUS SWITCH
WITH INTERRUPT LOGIC AND RESET
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SCPS169–SEPTEMBER 2007
Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
SDA
TEST CONDITIONS
VCC
MIN
TYP
11
6
MAX
UNIT
13
8
(3)
Cio(OFF)
VI = VCC or GND, Switch OFF
2.3 V to 5.5 V
pF
SC1–SC0, SD1–SD0
4.5 V to 5.5 V
3 V to 3.6 V
4
5
7
9
20
25
50
VO = 0.4 V, IO = 15 mA
VO = 0.4 V, IO = 10 mA
ron
Switch on-state resistance
11
16
Ω
2.3 V to 2.7 V
(3) Cio(ON) depends on the device capacitance and load that is downstream from the device.
I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 11)
STANDARD MODE
I2C BUS
FAST MODE
I2C BUS
UNIT
MIN
0
MAX
MIN
0
MAX
fscl
tsch
tscl
tsp
I2C clock frequency
I2C clock high time
I2C clock low time
I2C spike time
I2C serial-data setup time
I2C serial-data hold time
I2C input rise time
I2C input fall time
100
400 kHz
4
0.6
1.3
μs
μs
4.7
50
50 ns
ns
tsds
tsdh
ticr
250
0(1)
100
0(1)
μs
(2)
1000 20 + 0.1Cb
300 20 + 0.1Cb
300 20 + 0.1Cb
300 ns
300 ns
300 ns
μs
(2)
(2)
ticf
tocf
tbuf
tsts
tsth
tsps
I2C output fall time
10-pF to 400-pF bus
I2C bus free time between stop and start
I2C start or repeated start condition setup
I2C start or repeated start condition hold
I2C stop condition setup
4.7
4.7
4
1.3
0.6
0.6
0.6
μs
μs
4
μs
tvdL(Data) Valid-data time (high to low)(3)
tvdH(Data) Valid-data time (low to high)(3)
SCL low to SDA output low valid
SCL low to SDA output high valid
1
1
μs
0.6
0.6 μs
ACK signal from SCL low
to SDA output low
tvd(ack)
Cb
Valid-data time of ACK condition
I2C bus capacitive load
1
1
μs
400
400 pF
(1) A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to as the VIH min of the SCL signal), in order
to bridge the undefined region of the falling edge of SCL.
(2) Cb = total bus capacitance of one bus line in pF
(3) Data taken using a 1-kΩ pullup resistor and 50-pF load (see Figure 11)
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TWO-CHANNEL I2C-BUS SWITCH
WITH INTERRUPT LOGIC AND RESET
www.ti.com
SCPS169–SEPTEMBER 2007
Switching Characteristics
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 13)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
RON = 20 Ω, CL = 15 pF
RON = 20 Ω, CL = 50 pF
0.3
1
(1)
tpd
Propagation delay time
SDA or SCL
SDn or SCn
ns
tiv
tir
Interrupt valid time(2)
Interrupt reset delay time(2)
INTn
INTn
INT
INT
4
μs
μs
2
(1) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
(2) Data taken using a 4.7-kΩ pullup resistor and 100-pF load (see Figure 13)
Interrupt and Reset Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 13)
PARAMETER
Required low-level pulse duration of INTn inputs(1)
Required high-level pulse duration of INTn inputs(1)
Pulse duration, RESET low
MIN
1
MAX UNIT
tPWRL
tPWRH
tWL
μs
μs
ns
0.5
4
(2)
trst
RESET time (SDA clear)
500
ns
ns
tREC
Recovery time from RESET to start
0
(1) The device has interrupt input rejection circuitry for pulses less than the listed minimum.
(2) trst is the propagation delay measured from the time the RESET pin is first asserted low to the time the SDA pin is asserted high,
signaling a stop condition. It must be a minimum of tWL
.
Copyright © 2007, Texas Instruments Incorporated
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Product Folder Link(s): PCA9543A
PCA9543A
TWO-CHANNEL I2C-BUS SWITCH
WITH INTERRUPT LOGIC AND RESET
www.ti.com
SCPS169–SEPTEMBER 2007
PARAMETER MEASUREMENT INFORMATION
V
CC
R
L
= 1 kΩ
SDn, SCn
DUT
C
= 50 pF
L
(See Note A)
2
I C PORT LOAD CONFIGURATION
Two Bytes for Complete
Device Programming
Stop
Condition Condition
(P) (S)
Start
Address
Bit 7
(MSB)
R/W
Data
Bit 7
(MSB)
Data
Bit 0
(LSB)
Stop
Condition
(P)
ACK
(A)
Address
Bit 6
Address
Bit 1
ACK
(A)
Bit 0
(LSB)
BYTE
DESCRIPTION
2
1
I C address + R/W
2
Control register data
t
scl
t
sch
0.7 × VCC
0.3 × VCC
SCL
SDA
t
vd(ACK)
t
t
icr
sts
or t
vdL
t
icf
t
buf
t
t
sp
vdH
0.7 × VCC
0.3 × VCC
t
t
icr
icf
t
sdh
t
sps
t
sth
t
Repeat
sds
Stop
Condition
Start
Condition
Start or Repeat
Start Condition
VOLTAGE WAVEFORMS
A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω,
tr/tf = 30 ns.
C. The outputs are measured one at a time, with one transition per measurement.
Figure 11. I2C Interface Load Circuit, Byte Descriptions, and Voltage Waveforms
12
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Product Folder Link(s): PCA9543A
PCA9543A
TWO-CHANNEL I2C-BUS SWITCH
WITH INTERRUPT LOGIC AND RESET
www.ti.com
SCPS169–SEPTEMBER 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 12. Reset Timing
VCC
RL = 4.7 kΩ
INT
DUT
CL = 100 pF
(See Note A)
INTERRUPT LOAD CONFIGURATION
INTn
INTn
0.5 × VCC
0.5 × VCC
0.5 × VCC
(input)
(input)
t
ir
t
iv
INT
INT
0.5 × VCC
(output)
(output)
VOLTAGE WAVEFORMS (t )
iv
VOLTAGE WAVEFORMS (t )
ir
A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω,
tr/tf = 30 ns.
Figure 13. Interrupt Load Circuit and Voltage Waveforms
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Product Folder Link(s): PCA9543A
PCA9543A
TWO-CHANNEL I2C-BUS SWITCH
WITH INTERRUPT LOGIC AND RESET
www.ti.com
SCPS169–SEPTEMBER 2007
APPLICATION INFORMATION
Figure 14 shows an application in which the PCA9543A can be used.
VCC = 2.7 V to 5.5 V
VCC = 3.3 V
VCC
VCC = 2.7 V to 5.5 V
See Note A
12
5
6
SCL
SDA
SCL
SDA
INT
SD0
SC0
INT0
Channel 0
13
11
4
I2C/SMBus
Master
3
RESET
PCA9543A
VCC = 2.7 V to 5.5 V
See Note A
2
1
7
9
A1
SD1
SC1
Channel 1
10
8
A0
GND
INT1
NOTE: A. If the device generating the interrupt has an open-drain output structure or can be 3-stated, a
pullup resistor is required.
If the device generating the interrupt has a totem-pole output structure and cannot be 3-stated,
a pullup resistor is not required.
The interrupt inputs should not be left floating.
B. Pin numbers shown are for the D and PW packages.
Figure 14. Typical Application
14
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Product Folder Link(s): PCA9543A
PACKAGE OPTION ADDENDUM
www.ti.com
22-Oct-2007
PACKAGING INFORMATION
Orderable Device
PCA9543AD
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
14
14
14
14
14
14
14
14
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9543ADG4
PCA9543ADR
SOIC
SOIC
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9543ADRG4
PCA9543APW
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9543APWG4
PCA9543APWR
PCA9543APWRG4
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
(mm)
16
PCA9543ADR
D
14
14
SITE 41
SITE 41
6.5
7.0
9.0
5.6
2.1
1.6
8
8
16
12
Q1
Q1
PCA9543APWR
PW
330
12
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Oct-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
PCA9543ADR
D
14
14
SITE 41
SITE 41
346.0
346.0
346.0
346.0
33.0
29.0
PCA9543APWR
PW
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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