PCA9543B [NXP]
2-channel I2C-bus switch with interrupt logic and reset; 与中断逻辑和复位2通道I2C总线开关
| 型号： | PCA9543B |
| 厂家： | 
NXP |
| 描述： | 2-channel I2C-bus switch with interrupt logic and reset |
| 文件： | 总23页 (文件大小：131K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCA9543A/43B/43C
2-channel I2C-bus switch with interrupt logic and reset
Rev. 05 — 17 November 2008
Product data sheet
1. General description
The PCA9543A/43B/43C is a bidirectional translating switch, controlled by the I2C-bus.
The SCL/SDA upstream pair fans out to two downstream pairs, or channels. Any
individual SCx/SDx channels or combination of channels can be selected, determined by
the contents of the programmable control register. Two interrupt inputs, INT0 and INT1,
one for each of the downstream pairs, are provided. One interrupt output, INT, which acts
as an AND of the two interrupt inputs, is provided.
An active LOW reset input allows the PCA9543X to recover from a situation where one of
the downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets the
I2C-bus state machine and causes all the channels to be deselected, as does the internal
power-on reset function.
The pass gates of the switches are constructed such that the VDD pin can be used to limit
the maximum high voltage which will be passed by the PCA9543X. This allows the use of
different bus voltages on each SCx/SDx pair, so that 1.8 V, 2.5 V, or 3.3 V parts can
communicate with 5 V parts without any additional protection. External pull-up resistors
pull the bus up to the desired voltage level for each channel. All I/O pins are 5 V tolerant.
The PCA9543A, PCA9543B and PCA9543C are identical except for the fixed portion of
the slave address.
2. Features
I 1-of-2 bidirectional translating switches
I I2C-bus interface logic; compatible with SMBus standards
I 2 active LOW interrupt inputs
I Active LOW interrupt output
I Active LOW reset input
I 2 address pins allowing up to 4 devices on the I2C-bus
I Alternate address versions A, B and C allow up to a total of 12 devices on the bus for
larger systems or to resolve address conflicts
I Channel selection via I2C-bus, in any combination
I Power-up with all switch channels deselected
I Low Ron switches
I Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses
I No glitch on power-up
I Supports hot insertion
I Low standby current
I Operating power supply voltage range of 2.3 V to 5.5 V
PCA9543A/43B/43C
NXP Semiconductors
2-channel I2C-bus switch with interrupt logic and reset
I 5 V tolerant inputs
I 0 Hz to 400 kHz clock frequency
I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I Packages offered: SO14, TSSOP14
3. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
PCA9543AD
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
PCA9543APW
PCA9543BPW
PCA9543CPW
TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
3.1 Ordering options
Table 2.
Ordering options
Type number
PCA9543AD
PCA9543APW
PCA9543BPW
PCA9543CPW
Topside mark
PCA9543AD
PA9543A
Temperature range (Tamb
Tamb = −40 °C to +85 °C
Tamb = −40 °C to +85 °C
Tamb = −40 °C to +85 °C
Tamb = −40 °C to +85 °C
)
PA9543B
PA9543C
PCA9543A_43B_43C_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 17 November 2008
2 of 23
PCA9543A/43B/43C
NXP Semiconductors
2-channel I2C-bus switch with interrupt logic and reset
4. Block diagram
PCA9543A/43B/43C
SC0
SC1
SD0
SD1
V
SS
SWITCH CONTROL LOGIC
V
DD
POWER-ON
RESET
RESET
SCL
SDA
A0
2
INPUT
FILTER
I C-BUS
CONTROL
A1
INT0
to
INT
INTERRUPT LOGIC
INT1
002aab180
Fig 1. Block diagram of PCA9543A/43B/43C
PCA9543A_43B_43C_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 17 November 2008
3 of 23
PCA9543A/43B/43C
NXP Semiconductors
2-channel I2C-bus switch with interrupt logic and reset
5. Pinning information
5.1 Pinning
1
2
3
4
5
6
7
14
V
A0
A1
DD
13
12
11
10
9
SDA
SCL
INT
1
2
3
4
5
6
7
14
13
12
11
10
9
A0
A1
V
DD
RESET
INT0
SD0
SDA
SCL
INT
PCA9543AD
RESET
INT0
SD0
PCA9543APW
PCA9543BPW
PCA9543CPW
SC1
SD1
INT1
SC1
SD1
INT1
SC0
SC0
8
V
SS
V
SS
8
002aab178
002aab179
Fig 2. Pin configuration for SO14
Fig 3. Pin configuration for TSSOP14
5.2 Pin description
Table 3.
Pin description
Symbol
A0
Pin
1
Description
address input 0
address input 1
A1
2
RESET
INT0
SD0
SC0
VSS
3
active LOW reset input
active LOW interrupt input 0
serial data 0
4
5
6
serial clock 0
7
supply ground
INT1
SD1
SC1
INT
8
active LOW interrupt input 1
serial data 1
9
10
11
12
13
14
serial clock 1
active LOW interrupt output
serial clock line
SCL
SDA
VDD
serial data line
supply voltage
PCA9543A_43B_43C_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 17 November 2008
4 of 23
PCA9543A/43B/43C
NXP Semiconductors
2-channel I2C-bus switch with interrupt logic and reset
6. Functional description
Refer to Figure 1 “Block diagram of PCA9543A/43B/43C”.
6.1 Device address
Following a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA9543A is shown in Figure 4. To conserve power, no
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW.
1
1
1
0
0
A1 A0 R/W
fixed
hardware
selectable
002aab169
Fig 4. Slave address PCA9543A
The last bit of the slave address defines the operation to be performed. When set to
logic 1 a read is selected, while a logic 0 selects a write operation.
The PCA9543B and PCA9543C are alternate address versions if needed for larger
systems or to resolve address conflicts. The data sheet will reference the PCA9543A, but
the PCA9543B and PCA9543C function identically except for the slave address.
1
1
1
1
0
A1 A0 R/W
0
1
1
0
0
A1 A0 R/W
fixed
hardware
selectable
fixed
hardware
selectable
002aab799
002aab800
Fig 5. Slave address PCA9543B
Fig 6. Slave address PCA9543C
6.2 Control register
Following the successful acknowledgement of the slave address, the bus master will send
a byte to the PCA9543A, which will be stored in the control register. If multiple bytes are
received by the PCA9543A, it will save the last byte received. This register can be written
and read via the I2C-bus.
interrupt bits
(read only)
channel selection bits
(read/write)
7
6
5
4
3
2
1
0
INT INT
X
X
X
X
B1 B0
1
0
channel 0
channel 1
INT0
INT1
002aab181
Fig 7. Control register
PCA9543A_43B_43C_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 17 November 2008
5 of 23
PCA9543A/43B/43C
NXP Semiconductors
2-channel I2C-bus switch with interrupt logic and reset
6.2.1 Control register definition
One or several SCx/SDx downstream pair, or channel, is selected by the contents of the
control register. This register is written after the PCA9543A has been addressed. The
2 LSBs of the control byte are used to determine which channel is to be selected. When a
channel is selected, the channel will become active after a STOP condition has been
placed on the I2C-bus. This ensures that all SCx/SDx lines will be in a HIGH state when
the channel is made active, so that no false conditions are generated at the time of
connection.
Table 4.
D7
Control register: Write—channel selection; Read—channel status
D6
INT1
INT0
D3
D2
B1
B0
0
Command
channel 0 disabled
channel 0 enabled
channel 1 disabled
channel 1 enabled
X
X
X
X
X
X
X
1
0
1
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
no channel selected;
power-up/reset default state
Remark: Channel 0 and channel 1 can be enabled at the same time. Care should be
taken not to exceed the maximum bus capacitance.
6.2.2 Interrupt handling
The PCA9543A provides 2 interrupt inputs, one for each channel, and one open-drain
interrupt output. When an interrupt is generated by any device, it will be detected by the
PCA9543A and the interrupt output will be driven LOW. The channel need not be active
for detection of the interrupt. A bit is also set in the control register.
Bit 4 and bit 5 of the control register corresponds to the INT0 and INT1 inputs of the
PCA9543A, respectively. Therefore, if an interrupt is generated by any device connected
to channel 1, the state of the interrupt inputs is loaded into the control register when a
read is accomplished. Likewise, an interrupt on any device connected to channel 0 would
cause bit 4 of the control register to be set on the read. The master can then address the
PCA9543A and read the contents of the control register to determine which channel
contains the device generating the interrupt. The master can then reconfigure the
PCA9543A to select this channel, and locate the device generating the interrupt and
clear it.
It should be noted that more than one device can provide an interrupt on a channel, so it is
up to the master to ensure that all devices on a channel are interrogated for an interrupt.
The interrupt inputs may be used as general purpose inputs if the interrupt function is not
required.
If unused, interrupt input(s) must be connected to VDD through a pull-up resistor.
Table 5.
7
Control register: Read—interrupt
6
INT1
INT0
3
2
B1
B0
Command
0
1
no interrupt on channel 0
interrupt on channel 0
no interrupt on channel 1
interrupt on channel 1
X
X
X
X
X
X
X
X
0
1
X
X
X
X
X
X
PCA9543A_43B_43C_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 17 November 2008
6 of 23
PCA9543A/43B/43C
NXP Semiconductors
2-channel I2C-bus switch with interrupt logic and reset
Remark: Two interrupts can be active at the same time.
6.3 RESET input
The RESET input is an active LOW signal which may be used to recover from a bus fault
condition. By asserting this signal LOW for a minimum of tw(rst)L, the PCA9543A will reset
its registers and I2C-bus state machine and will deselect all channels. The RESET input
must be connected to VDD through a pull-up resistor.
6.4 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9543A in
a reset condition until VDD has reached VPOR. At this point, the reset condition is released
and the PCA9543A registers and I2C-bus state machine are initialized to their default
states (all zeroes) causing all the channels to be deselected. Thereafter, VDD must be
lowered below 0.2 V to reset the device.
6.5 Voltage translation
The pass gate transistors of the PCA9543A are constructed such that the VDD voltage can
be used to limit the maximum voltage that will be passed from one I2C-bus to another.
002aaa964
5.0
V
o(sw)
(V)
4.0
(1)
(2)
(3)
3.0
2.0
1.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
DD
5.5
(V)
V
(1) maximum
(2) typical
(3) minimum
Fig 8. Pass gate voltage versus supply voltage
Figure 8 shows the voltage characteristics of the pass gate transistors (note that the graph
was generated using the data specified in Section 10 “Static characteristics” of this data
sheet). In order for the PCA9543A to act as a voltage translator, the Vo(sw) voltage should
be equal to, or lower than the lowest bus voltage. For example, if the main bus was
running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then Vo(sw) should be
equal to or below 2.7 V to effectively clamp the downstream bus voltages. Looking at
PCA9543A_43B_43C_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 17 November 2008
7 of 23
PCA9543A/43B/43C
NXP Semiconductors
2-channel I2C-bus switch with interrupt logic and reset
Figure 8, we see that Vo(sw)(max) will be at 2.7 V when the PCA9543A supply voltage is
3.5 V or lower, so the PCA9543A supply voltage could be set to 3.3 V. Pull-up resistors
can then be used to bring the bus voltages to their appropriate levels (see Figure 15).
More Information can be found in Application Note AN262: PCA954X family of I2C/SMBus
multiplexers and switches.
7. Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 9).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mba607
Fig 9. Bit transfer
7.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 10).
SDA
SCL
SDA
SCL
S
P
STOP condition
START condition
mba608
Fig 10. Definition of START and STOP conditions
PCA9543A_43B_43C_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 17 November 2008
8 of 23
PCA9543A/43B/43C
NXP Semiconductors
2-channel I2C-bus switch with interrupt logic and reset
7.3 System configuration
A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 11).
SDA
SCL
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
2
SLAVE
RECEIVER
MASTER
TRANSMITTER
I C-BUS
MULTIPLEXER
SLAVE
002aaa966
Fig 11. System configuration
7.4 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also, a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; setup and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from master
1
2
8
9
S
clock pulse for
START
condition
acknowledgement
002aaa987
Fig 12. Acknowledgement on the I2C-bus
PCA9543A_43B_43C_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 17 November 2008
9 of 23
PCA9543A/43B/43C
NXP Semiconductors
2-channel I2C-bus switch with interrupt logic and reset
7.5 Bus transactions
Data is transmitted to the PCA9543A control register using the Write mode as shown in
Figure 13.
slave address
control register
SDA
S
1
1
1
0
0
A1 A0
0
A
X
X
X
X
X
X
B1 B0
A
P
START condition
R/W acknowledge
from slave
acknowledge
from slave
STOP condition
002aab182
Fig 13. Write control register
Data is read from PCA9543A using the Read mode as shown in Figure 14.
last byte
slave address
control register
SDA
S
1
1
1
0
0
A1 A0
1
A
X
X
INT1 INT0
X
X
B1 B0 NA
P
START condition
R/W acknowledge
from slave
no acknowledge
from master
STOP condition
002aab183
Fig 14. Read control register
PCA9543A_43B_43C_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 17 November 2008
10 of 23
PCA9543A/43B/43C
NXP Semiconductors
2-channel I2C-bus switch with interrupt logic and reset
8. Application design-in information
V
= 2.7 V to 5.5 V
DD
V
= 3.3 V
DD
V = 2.7 V to 5.5 V
(1)
see note
SDA
SCL
SDA
SCL
INT
SD0
SC0
INT0
channel 0
V = 2.7 V to 5.5 V
(1)
RESET
see note
PCA9543A
2
I C/SMBus master
A1
A0
V
SD1
channel 1
SC1
INT1
SS
002aab184
(1) If the device generating the interrupt has an open-drain output structure or can be 3-stated, a
pull-up resistor is required.
If the device generating the interrupt has a totem pole output structure and cannot be 3-stated, a
pull-up resistor is not required.
The interrupt inputs should not be left floating.
Fig 15. Typical application
9. Limiting values
Table 6.
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
SS (ground = 0 V).[1]
Limiting values
V
Symbol
VDD
VI
Parameter
Conditions
Min
Max
+7.0
+7.0
±20
Unit
V
supply voltage
−0.5
input voltage
−0.5
V
II
input current
-
mA
mA
mA
mA
mW
°C
IO
output current
-
±25
IDD
supply current
-
±100
±100
400
ISS
ground supply current
total power dissipation
storage temperature
ambient temperature
-
Ptot
Tstg
Tamb
-
−60
−40
+150
+85
operating
°C
[1] The performance capability of a high-performance integrated circuit in conjunction with its thermal
environment can create junction temperatures which are detrimental to reliability. The maximum junction
temperature of this integrated circuit should not exceed 125 °C.
PCA9543A_43B_43C_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 17 November 2008
11 of 23
PCA9543A/43B/43C
NXP Semiconductors
2-channel I2C-bus switch with interrupt logic and reset
10. Static characteristics
Table 7.
Static characteristics
VDD = 2.3 V to 3.6 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
See Table 8 on page 13 for VDD = 4.5 V to 5.5 V.[1]
Symbol
Supply
VDD
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage
supply current
2.3
-
-
3.6
V
IDD
operating mode; VDD = 3.6 V; no load;
VI = VDD or VSS; fSCL = 100 kHz
40
100
µA
Istb
standby current
Standby mode; VDD = 3.6 V; no load;
VI = VDD or VSS; fSCL = 0 kHz
-
-
0.2
1.6
1
µA
[2]
VPOR
power-on reset voltage
no load; VI = VDD or VSS
2.1
V
Input SCL; input/output SDA
VIL
VIH
IOL
LOW-level input voltage
HIGH-level input voltage
LOW-level output current
−0.5
-
+0.3VDD
V
0.7VDD
-
6
V
VOL = 0.4 V
VOL = 0.6 V
VI = VDD or VSS
VI = VSS
3
-
-
mA
mA
µA
pF
6
-
-
IL
leakage current
−1
-
-
+1
10
Ci
input capacitance
9
Select inputs A0, A1, INT0, INT1, RESET
VIL
LOW-level input voltage
HIGH-level input voltage
input leakage current
input capacitance
−0.5
0.7VDD
−1
-
+0.3VDD
V
VIH
-
VDD + 0.5
V
ILI
VI = VDD or VSS
VI = VSS
-
+1
3
µA
pF
Ci
-
1.6
Pass gate
Ron
ON-state resistance
VDD = 3.0 to 3.6 V; VO = 0.4 V;
IO = 15 mA
5
7
11
16
30
55
Ω
Ω
VDD = 2.3 V to 2.7 V; VO = 0.4 V;
IO = 10 mA
Vo(sw)
switch output voltage
Vi(sw) = VDD = 3.3 V; Io(sw) = −100 µA
-
1.9
-
-
V
V
Vi(sw) = VDD = 3.0 V to 3.6 V;
1.6
2.8
Io(sw) = −100 µA
Vi(sw) = VDD = 2.5 V; Io(sw) = −100 µA
-
1.5
-
-
V
V
Vi(sw) = VDD = 2.5 V to 2.7 V;
1.1
2.0
Io(sw) = −100 µA
IL
leakage current
VI = VDD or VSS
VI = VSS
−1
-
+1
5
µA
Cio
input/output capacitance
-
3
pF
INT output
IOL
IOH
LOW-level output current
HIGH-level output current
VOL = 0.4 V
3
-
-
-
-
mA
+100
µA
[1] For operation between published voltage ranges, refer to the worst-case parameter in both ranges.
[2] VDD must be lowered to 0.2 V in order to reset part.
PCA9543A_43B_43C_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 17 November 2008
12 of 23
PCA9543A/43B/43C
NXP Semiconductors
2-channel I2C-bus switch with interrupt logic and reset
Table 8.
Static characteristics
VDD = 4.5 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
See Table 7 on page 12 for VDD = 2.3 V to 3.6 V.[1]
Symbol
Supply
VDD
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage
supply current
4.5
-
-
5.5
V
IDD
Operating mode; VDD = 5.5 V;
25
100
µA
no load; VI = VDD or VSS
;
fSCL = 100 kHz
Istb
standby current
Standby mode; VDD = 5.5 V;
no load; VI = VDD or VSS
SCL = 0 kHz
-
-
0.2
1.7
1
µA
;
f
[2]
VPOR
power-on reset voltage
no load; VI = VDD or VSS
2.1
V
Input SCL; input/output SDA
VIL
VIH
IOL
LOW-level input voltage
HIGH-level input voltage
−0.5
-
+0.3VDD
V
0.7VDD
-
6
V
LOW-level output current VOL = 0.4 V
VOL = 0.6 V
3
-
-
mA
mA
µA
pF
6
-
-
IL
leakage current
VI = VDD or VSS
VI = VSS
−1
-
-
+1
10
Ci
input capacitance
9
Select inputs A0, A1, INT0 to INT3, RESET
VIL
LOW-level input voltage
HIGH-level input voltage
input leakage current
input capacitance
−0.5
0.7VDD
−1
-
+0.3VDD
VDD + 0.5
+50
V
VIH
-
V
ILI
VI = VDD or VSS
VI = VSS
-
µA
pF
Ci
-
2
5
Pass gate
Ron
on-state resistance
switch output voltage
VDD = 4.5 V to 5.5 V; VO = 0.4 V;
IO = 15 mA
4
9
24
-
Ω
V
V
Vo(sw)
Vi(sw) = VDD = 5.0 V;
-
3.6
-
I
o(sw) = −100 µA
Vi(sw) = VDD = 4.5 V to 5.5 V;
o(sw) = −100 µA
VI = VDD or VSS
2.6
4.5
I
IL
leakage current
−1
-
+100
5
µA
Cio
input/output capacitance VI = VSS
-
3
pF
INT output
IOL
IOH
LOW-level output current VOL = 0.4 V
HIGH-level output current
3
-
-
-
-
mA
+100
µA
[1] For operation between published voltage ranges, refer to the worst-case parameter in both ranges.
[2] VDD must be lowered to 0.2 V in order to reset part.
PCA9543A_43B_43C_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 17 November 2008
13 of 23
PCA9543A/43B/43C
NXP Semiconductors
2-channel I2C-bus switch with interrupt logic and reset
11. Dynamic characteristics
Table 9.
Symbol
Dynamic characteristics
Parameter
Conditions
Standard-mode Fast-mode I2C-bus Unit
I2C-bus
Min
Max
Min
Max
tPD
propagation delay
from SDA to SDn,
or SCL to SCn
-
0.3[1]
-
0.3[1] ns
fSCL
tBUF
SCL clock frequency
0
100
-
0
400 kHz
bus free time between a STOP and
START condition
4.7
1.3
-
µs
[2]
tHD;STA
tLOW
hold time (repeated) START condition
LOW period of the SCL clock
4.0
4.7
4.0
4.7
-
-
-
-
0.6
1.3
0.6
0.6
-
-
-
-
µs
µs
µs
µs
tHIGH
HIGH period of the SCL clock
tSU;STA
set-up time for a repeated START
condition
tSU;STO
tHD;DAT
tSU;DAT
tr
set-up time for STOP condition
data hold time
4.0
0[3]
250
-
-
3.45
-
0.6
0[3]
-
µs
0.9 µs
ns
data set-up time
100
-
[4]
[4]
rise time of both SDA and SCL
signals
1000 20 + 0.1Cb
300 ns
tf
fall time of both SDA and SCL signals
capacitive load for each bus line
-
-
-
300
400
50
20 + 0.1Cb
300 µs
400 µs
50 ns
Cb
tSP
-
-
pulse width of spikes that must be
suppressed by the input filter
[5]
[5]
tVD;DAT
data valid time
HIGH-to-LOW
LOW-to-HIGH
-
-
-
1
0.6
1
-
-
-
1
µs
0.6 µs
tVD;ACK
data valid acknowledge time
1
µs
INT
tv(INTnN-INTN) valid time from INTn to INT signal
td(INTnN-INTN) delay time from INTn to INT inactive
-
-
4
2
-
-
-
4
2
-
µs
µs
µs
µs
tw(rej)L
tw(rej)H
RESET
tw(rst)L
trst
LOW-level rejection time
HIGH-level rejection time
INTn inputs
INTn inputs
1
1
0.5
-
0.5
-
LOW-level reset time
reset time
4
500
0
-
-
-
4
500
0
-
-
-
ns
ns
ns
SDA clear
tREC;STA
recovery time to START condition
[1] Pass gate propagation delay is calculated from the 20 Ω typical Ron and the 15 pF load capacitance.
[2] Hold time (repeated) START condition. After this period, the first clock pulse is generated.
[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to
bridge the undefined region of the falling edge of SCL.
[4] Cb = total capacitance of one bus line in pF.
[5] Measurements taken with 1 kΩ pull-up resistor and 50 pF load.
PCA9543A_43B_43C_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 17 November 2008
14 of 23
PCA9543A/43B/43C
NXP Semiconductors
2-channel I2C-bus switch with interrupt logic and reset
SDA
t
t
t
t
SP
t
r
f
HD;STA
BUF
t
LOW
SCL
t
t
t
SU;STO
HD;STA
SU;STA
t
t
t
SU;DAT
HD;DAT
HIGH
P
S
Sr
P
002aaa986
Fig 16. Definition of timing on the I2C-bus
ACK or read cycle
START
SCL
SDA
30 %
t
rst
RESET
50 %
50 %
50 %
t
REC;STA
t
w(rst)L
002aac549
Fig 17. Definition of RESET timing
START
condition
(S)
bit 7
MSB
(A7)
STOP
condition
(P)
bit 6
(A6)
bit 0 acknowledge
(R/W) (A)
protocol
t
t
t
HIGH
SU;STA
LOW
1
/f
SCL
SCL
SDA
t
t
BUF
f
t
r
t
t
t
t
t
t
HD;DAT
VD;DAT
VD;ACK
SU;STO
002aab175
HD;STA
SU;DAT
Rise and fall times refer to VIL and VIH
.
Fig 18. I2C-bus timing diagram
PCA9543A_43B_43C_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 17 November 2008
15 of 23
PCA9543A/43B/43C
NXP Semiconductors
2-channel I2C-bus switch with interrupt logic and reset
12. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
v
c
y
H
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
Fig 19. Package outline SOT108-1 (SO14)
PCA9543A_43B_43C_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 17 November 2008
16 of 23
PCA9543A/43B/43C
NXP Semiconductors
2-channel I2C-bus switch with interrupt logic and reset
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
Fig 20. Package outline SOT402-1 (TSSOP14)
PCA9543A_43B_43C_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 17 November 2008
17 of 23
PCA9543A/43B/43C
NXP Semiconductors
2-channel I2C-bus switch with interrupt logic and reset
13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
PCA9543A_43B_43C_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 17 November 2008
18 of 23
PCA9543A/43B/43C
NXP Semiconductors
2-channel I2C-bus switch with interrupt logic and reset
13.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 21) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 10 and 11
Table 10. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
235
≥ 350
220
< 2.5
≥ 2.5
220
220
Table 11. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 21.
PCA9543A_43B_43C_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 17 November 2008
19 of 23
PCA9543A/43B/43C
NXP Semiconductors
2-channel I2C-bus switch with interrupt logic and reset
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 21. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
14. Abbreviations
Table 12. Abbreviations
Acronym
CDM
ESD
Description
Charged-Device Model
ElectroStatic Discharge
Human Body Model
Integrated Circuit
HBM
IC
I2C-bus
LSB
Inter-Integrated Circuit bus
Least Significant Bit
Machine Model
MM
MSB
PCB
Most Significant Bit
Printed-Circuit Board
System Management Bus
SMBus
PCA9543A_43B_43C_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 17 November 2008
20 of 23
PCA9543A/43B/43C
NXP Semiconductors
2-channel I2C-bus switch with interrupt logic and reset
15. Revision history
Table 13. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA9543A_43B_43C_5 20081117
Product data sheet
-
PCA9543A_43B_43C_4
”
Modifications:
• Section 6.3 “RESET input”: changed symbol from “tWL” to “tw(rst)L
• Table 9 “Dynamic characteristics”, sub-section “INT”:
–
symbol tw(rej)L: changed Unit from “ns” to “µs”
–
symbol tw(rej)H: Min value (for both Standard-mode I2C-bus and Fast-mode I2C-bus)
changed from “500 ns” to “0.5 µs”
PCA9543A_43B_43C_4 20061020
Product data sheet
Product data sheet
-
-
PCA9543A_3
PCA9543A_2
PCA9543A_3
20050321
20040929
20040728
(9397 750 14316)
PCA9543A_2
Objective data sheet
Objective data sheet
-
-
PCA9543A_1
-
(9397 750 13988)
PCA9543A_1
(9397 750 13299)
PCA9543A_43B_43C_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 17 November 2008
21 of 23
PCA9543A/43B/43C
NXP Semiconductors
2-channel I2C-bus switch with interrupt logic and reset
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
to result in personal injury, death or severe property or environmental
16.2 Definitions
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
I2C-bus — logo is a trademark of NXP B.V.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA9543A_43B_43C_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 17 November 2008
22 of 23
PCA9543A/43B/43C
NXP Semiconductors
2-channel I2C-bus switch with interrupt logic and reset
18. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3
3.1
4
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
Functional description . . . . . . . . . . . . . . . . . . . 5
Device address. . . . . . . . . . . . . . . . . . . . . . . . . 5
Control register . . . . . . . . . . . . . . . . . . . . . . . . . 5
Control register definition . . . . . . . . . . . . . . . . . 6
Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . 6
RESET input. . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 7
Voltage translation . . . . . . . . . . . . . . . . . . . . . . 7
6.1
6.2
6.2.1
6.2.2
6.3
6.4
6.5
7
Characteristics of the I2C-bus. . . . . . . . . . . . . . 8
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
START and STOP conditions . . . . . . . . . . . . . . 8
System configuration . . . . . . . . . . . . . . . . . . . . 9
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 10
7.1
7.2
7.3
7.4
7.5
8
Application design-in information . . . . . . . . . 11
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11
Static characteristics. . . . . . . . . . . . . . . . . . . . 12
Dynamic characteristics . . . . . . . . . . . . . . . . . 14
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
9
10
11
12
13
Soldering of SMD packages . . . . . . . . . . . . . . 18
Introduction to soldering . . . . . . . . . . . . . . . . . 18
Wave and reflow soldering . . . . . . . . . . . . . . . 18
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 18
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 19
13.1
13.2
13.3
13.4
14
15
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 21
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 22
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 22
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 17 November 2008
Document identifier: PCA9543A_43B_43C_5
相关型号：
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