OPA693IDBVT [TI]
具有禁用功能的超高宽带、固定增益缓冲器 | DBV | 6 | -40 to 85;
| 型号： | OPA693IDBVT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有禁用功能的超高宽带、固定增益缓冲器 | DBV | 6 | -40 to 85 放大器 PC 光电二极管 |
| 文件： | 总33页 (文件大小：967K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
O
P
OPA693
A
6
9
3
O
P
A
6
9
3
www.ti.com
SBOS285A – OCTOBER 2003 – REVISED JULY 2008
Ultra-Wideband, Fixed Gain
Video BUFFER AMPLIFIER with Disable
DESCRIPTION
FEATURES
The OPA693 provides an easy to use, broadband, fixed gain
buffer amplifier. Depending on the external connections, the
internal resistor network may be used to provide either a
fixed gain of +2 video buffer or a gain of ±1 voltage buffer.
Operating on a low 13mA supply current, the OPA693 offers
a slew rate (2500V/µs) and bandwidth (> 700MHz) normally
associated with a much higher supply current. A new output
stage architecture delivers high output current with a minimal
headroom and crossover distortion. This gives exceptional
single-supply operation. Using a single +5V supply, the
OPA693 can deliver a 2.5VPP swing with over 90mA drive
current and 500MHz bandwidth at a gain of +2. This combi-
nation of features makes the OPA693 an ideal RGB line
driver or single-supply undersampling Analog-to-Digital Con-
verter (ADC) input driver.
● VERY HIGH BANDWIDTH (G = +2): 700MHz
● FLEXIBLE SUPPLY RANGE:
+5V to +12V Single Supply
±2.5V to ±6V Dual Supplies
● INTERNALLY FIXED GAIN: +2 or ±1
● LOW SUPPLY CURRENT: 13mA
● LOW DISABLED CURRENT: 120µA
● HIGH OUTPUT CURRENT: ±120mA
● OUTPUT VOLTAGE SWING: ±4.1V
● SOT23-6 AVAILABLE
APPLICATIONS
The OPA693’s low 13mA supply current is precisely trimmed
at 25°C. This trim, along with low drift over temperature,
ensures lower maximum supply current than competing
products that report only a room temperature nominal supply
current. System power may be further reduced by using the
optional disable control pin. Leaving this disable pin open, or
holding it HIGH, gives normal operation. This optional dis-
able allows the OPA693 to fit into existing video buffer
layouts where the disable pin is unconnected to get improved
performance with no board changes. If pulled LOW, the
OPA693 supply current drops to less than 170µA while the
output goes into a high impedance state. This feature may be
used for power savings.
● BROADBAND VIDEO LINE DRIVERS
● MULTIPLE LINE VIDEO DA
● PORTABLE INSTRUMENTS
● ADC BUFFERS
● HIGH FREQUENCY ACTIVE FILTERS
● HFA1112 IMPROVED DROP-IN
OPA693 RELATED PRODUCTS
SINGLES
DUALS
TRIPLES
Voltage Feedback
Current Feedback
Fixed Gain
OPA690
OPA691
OPA692
OPA695
OPA2690
OPA2691
—
OPA3690
OPA3691
OPA3692
—
The low gain stable current-feedback architecture used in the
OPA693 is particularly suitable for high full-power bandwidth
cable driving requirements. Where the additional flexibility of
an op amp is required, consider the OPA695 ultra-wideband
current feedback op amp. Where a unity gain stable voltage
feedback op amp with very high slew rate is required,
consider the OPA690.
> 900MHz
—
OPA693
1
2
3
300Ω
8
7
6
5
DIS
75Ω
75Ω
300Ω
Video
+5V
Out
Video
In
RG-59
75Ω
−5V
75Ω
Video
4
Out
RG-59
75Ω
SO-8
G = +2
700MHz, 2-Output Component Video DA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2002-2008, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
Power Supply ............................................................................... ±6.5VDC
Internal Power Dissipation(2) ............................ See Thermal Information
Differential Input Voltage .................................................................. ±1.2V
Input Voltage Range............................................................................ ±VS
Storage Temperature Range: D, DVB ...........................–65°C to +125°C
Lead Temperature (soldering, 10s).............................................. +300°C
Junction Temperature (TJ ) ........................................................... +150°C
ESD Rating (Human Body Model) .................................................. 2000V
(Charge Device Model) ............................................... 1000V
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
(Machine Model) ............................................................ 100V
NOTES:: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those specified is not implied.
(2) Packages must be derated based on specified θJA. Maximum TJ must be
observed.
(1)
PACKAGE/ORDERING INFORMATION
SPECIFIED
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
OPA693
SO-8
D
"
–40°C to +85°C
OPA693D
OPA693ID
OPA693IDR
Rails, 100
"
OPA693
"
"
"
"
C59
"
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 3000
SOT23-6
DBV
–40°C to +85°C
OPA693IDBVT
OPA693IDBVR
"
"
"
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
PIN CONFIGURATION
Top View
SO
Top View
SOT23
Output
−VS
1
2
3
6
5
4
+VS
RF
300Ω
DIS
NC
−IN
+IN
−VS
1
2
3
4
8
7
6
5
DIS
RG
300Ω
R
F
R
G
+IN
−IN
+VS
300Ω
300Ω
Output
NC
6
5
4
NC = No Connection
C59
1
2
3
Pin Orientation/Package Marking
OPA693
2
SBOS285A
www.ti.com
ELECTRICAL CHARACTERISTICS: VS = ±5V
Boldface limits are tested at 25°C.
G = +2 (–IN grounded) and RL = 100Ω (see Figure 1 for AC performance only), unless otherwise noted.
OPA693ID, IDBV
TYP
MIN/MAX OVER TEMPERATURE(1)
0
°
C to
–40
+85°C
°
C to
MIN/
TEST
MAX LEVEL(2 )
PARAMETER
CONDITIONS
+25°C
+25°C
70°C
UNITS
AC PERFORMANCE (see Figure 1)
Small-Signal Bandwidth (VO < 1.0VPP
)
G = +1
G = +2
1400
700
700
400
2.5
MHz
MHz
MHz
MHz
dB
typ
min
typ
C
B
C
B
B
C
B
B
B
C
C
510
510
122
3.8
490
490
112
4.8
480
480
108
5.2
G = –1
Bandwidth for 0.2dB Gain Flatness
Peaking at a Gain of +1
Large-Signal Bandwidth
Slew Rate
G = +2, VO < 1.0VPP, RL = 150Ω
VO < 1.0VPP
min
max
typ
G = +2, VO = 4VPP
G = +2, 4V Step
G = +2, VO = 0.5V Step
G = +2, VO = 5V Step
G = +2, VO = 2V Step
G = +2, VO = 2V Step
G = +2, f = 10MHz, VO = 2VPP
RL = 100Ω
400
2500
0.6
MHz
V/µs
ns
2200
0.8
2100
0.8
2000
0.8
min
max
max
typ
Rise-and-Fall Time
1.2
1.3
1.3
1.4
ns
Settling Time to 0.02%
Settling Time to 0.1%
Harmonic Distortion
2nd-Harmonic
16
ns
12
ns
typ
–69
–82
–83
–96
1.8
–66
–80
–80
–86
2
–65
–79
–70
–85
2.7
21
–64
–78
–69
–82
2.9
22
dBc
dBc
max
max
max
max
max
max
max
typ
B
B
B
B
B
B
B
C
C
C
C
RL ≥ 500Ω
3rd-Harmonic
RL = 100Ω
dBc
RL ≥ 500Ω
dBc
Input Voltage Noise
f > 1MHz
nV/√Hz
pA/√Hz
pA/√Hz
%
Noninverting Input Current Noise
Inverting Input Current Noise (internal)
Differential Gain
f > 1MHz
18
19
f > 1MHz
22
24
26
27
NTSC, RL = 150Ω
NTSC, RL = 37.5Ω
NTSC, RL = 150Ω
NTSC, RL = 37.5Ω
0.03
0.03
0.01
0.1
%
typ
Differential Phase
deg
typ
deg
typ
DC PERFORMANCE(3)
Gain Error
G = +1
G = +2
±0.2
±0.3
%
%
%
%
typ
max
max
typ
C
A
B
C
±0.9
±0.8
±1.0
±0.9
±1.1
±1.0
G = –1, RS = 0Ω
VO = ±2, RL = 100Ω, G = +2
±0.2
DC Linearity
0.0016
Internal RF and RG
Maximum
300
300
341
264
345
260
0.03
±2.3
±5
346
259
0.03
±2.5
±8
Ω
Ω
max
min
A
A
B
A
B
A
B
A
B
Minimum
Average Drift
%/C°
mV
max
max
max
max
max
max
max
Input Offset Voltage
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
±0.3
+15
±20
±2.0
±35
±50
Average Offset Voltage Drift
Noninverting Input Bias Current
Average Noninverting Input Bias Current Drift
Inverting Input Bias Current (internal)
Average Inverting Input Bias Current Drift
µV/°C
µA
±43
170
±52
50
±45
170
±54
60
nA/°C
µA
nA°C
INPUT
Common-Mode Input Range
Noninverting Input Impedance
±3.4
±3.3
±3.2
±3.2
V
min
typ
B
C
300 || 1.2
kΩ || pF
OUTPUT
Voltage Output Swing
No Load
±4.1
±3.8
+120
–120
0.18
±3.9
±3.7
+90
–90
±3.9
±3.7
+80
–80
±3.8
±3.6
+70
–70
V
V
min
min
min
min
typ
A
A
A
A
C
100Ω Load
Current Output, Sourcing
Current Output, Sinking
mA
mA
Ω
Closed-Loop Output Impedance
G = +2, f = 100kHz
(1) Junction temperature = ambient temperature for low temperature limit and +25°C specifications. Junction temperature = ambient temperature +20°C at high
temperature limit specifications.
(2) Test Levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation.
(B) Limits set by characterization and simulation.
(C) Typical value only for information.
(3) Current is considered positive out-of-node. VCM is the input common-mode voltage.
OPA693
SBOS285A
3
www.ti.com
ELECTRICAL CHARACTERISTICS: VS = ±5V (Cont.)
Boldface limits are tested at 25°C.
G = +2 (–IN grounded) and RL = 100Ω (see Figure 1 for AC performance only), unless otherwise noted.
OPA693ID, IDBV
MIN/MAX OVER TEMPERATURE(1)
TYP
0
°
C to
–40
+85°C
°
C to
MIN/
TEST
MAX LEVEL(2 )
PARAMETER
CONDITIONS
+25°C
+25°C
–170
70°C
UNITS
DISABLE/POWER DOWN (DIS Pin)
Power-Down Supply Current (+VS)
Disable Time
VDIS = 0V
VIN = +1VDC
VIN = +1VDC
G = +2, 5MHz
–70
3
–186
–192
µA
µs
ns
dB
pF
mV
mV
V
max
typ
A
C
C
C
C
C
C
A
A
A
Enable Time
25
typ
Off Isolation
70
typ
Output Capacitance in Disable
Turn-On Glitch
4
typ
G = +2, RL = 150Ω, VIN = 0VDC
G = +2, RL = 150Ω, VIN = 0VDC
+VS = +5V
±100
±20
3.3
1.8
75
typ
Turn-Off Glitch
typ
Enable Voltage
3.5
1.7
130
3.6
1.6
143
3.7
1.5
149
min
max
max
Disable Voltage
+VS = +5V
V
Control Pin Input Bias Current
VDIS = 0V
µA
POWER SUPPLY
Specified Operating Voltage
Maximum Operating Voltage Range
Max Quiescent Current
±5
V
typ
max
max
min
min
C
A
A
A
A
±6
13.3
12.5
54
±6
13.7
11.6
52
±6
14.1
11.0
51
V
VS = ±5V
VS = ±5V
13
13
58
mA
mA
dB
Min Quiescent Current
Power-Supply Rejection Ratio (+PSRR)
Input Referred
TEMPERATURE RANGE
Specification: D, DBV
–40 to +85
°C
typ
C
Thermal Resistance, θJA
D
SO-8
125
150
°C/W
°C/W
typ
typ
C
C
DBV SOT23-6
(1) Junction temperature = ambient temperature for low temperature limit and +25°C specifications. Junction temperature = ambient temperature +20°C at high
temperature limit specifications.
(2) Test Levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation.
(B) Limits set by characterization and simulation.
(C) Typical value only for information.
(3) Current is considered positive out-of-node. VCM is the input common-mode voltage.
OPA693
4
SBOS285A
www.ti.com
ELECTRICAL CHARACTERISTICS: VS = +5V
Boldface limits are tested at +25°C.
G = +2 (–IN grounded though 0.001µF) and RL = 100Ω to VS/2 (see Figure 4 for AC performance only), unless otherwise noted.
OPA693ID, IDBV
TYP
MIN/MAX OVER TEMPERATURE
0
°
C to –40 C to
°
MIN/
TEST
MAX LEVEL(2 )
PARAMETER
CONDITIONS
+25°C
+25°C(1)
70°C
+85°C
UNITS
AC PERFORMANCE (see Figure 4)
Small-Signal Bandwidth (VO < 1.0VPP
)
G = +1
G = +2
634
526
512
210
1.9
MHz
MHz
MHz
MHz
dB
typ
min
typ
C
B
C
B
B
C
B
C
C
C
C
400
390
380
G = –1
Bandwidth for 0.2dB Gain Flatness
Peaking at a Gain of +1
Large-Signal Bandwidth
Slew Rate
G = +2, VO < 1.0VPP
VO < 1.0VPP
110
2.6
100
3.6
96
min
max
typ
3.9
G = +2, VO = 2VPP
G = +2, 2V Step
G = +2, VO = 0.5V Step
G = +2, VO = 2V Step
G = +2, VO = 2V Step
G = +2, VO = 2V Step
G = +2, f = 10MHz, VO = 2VPP
RL = 100Ω to VS/2
RL ≥ 500Ω to VS/2
RL = 100Ω to VS/2
RL ≥ 500Ω to VS /2
f > 1MHz
400
1500
0.8
MHz
V/µs
ns
1200
1100
1000
min
typ
Rise-and-Fall Time
1.0
ns
typ
Settling Time to 0.02%
Settling Time to 0.1%
Harmonic Distortion
2nd-Harmonic
16
ns
typ
12
ns
typ
–66
–75
–70
–69
1.8
18
–62
–69
–64
–63
2
–62
–68
–63
–62
2.7
21
–61
–68
–62
–61
2.9
22
dBc
dBc
max
max
max
max
max
max
max
B
B
B
B
B
B
B
3rd-Harmonic
dBc
dBc
Input Voltage Noise
nV/√Hz
pA/√Hz
pA/√Hz
Noninverting Input Current Noise
Inverting Input Current Noise
f > 1MHz
19
f > 1MHz
22
24
26
27
DC PERFORMANCE(3)
Gain Error
G = +1
G = +2
G = –1
±0.2
±0.5
±0.4
%
%
%
typ
C
A
B
±1.2
±1.1
±1.3
±1.2
±1.4
±1.3
max
max
Internal RF and RG
Maximum
300
300
341
264
345
260
0.03
±2.8
±5
346
259
0.03
±3.0
±8
Ω
Ω
max
min
B
B
B
A
B
A
B
A
B
Minimum
Average Drift
0.03
±2.5
%/C°
mV
max
max
max
max
max
max
max
Input Offset Voltage
Average Offset Voltage Drift
Noninverting Input Bias Current
VCM = 2.5V
VCM = 2.5V
VCM = 2.5V
VCM = 2.5V
VCM = 2.5V
VCM = 2.5V
±0.3
+5
µV/°C
µA
±25
±50
±33
±170
±52
±50
±35
±170
±54
±60
Average Noninverting Input Bias Current Drift
Inverting Input Bias Current
nA/°C
µA
±20
Average Inverting Input Bias Current Drift
nA°C
INPUT
Least Positive Input Voltage
Most Positive Input Voltage
Noninverting Input Impedance
1.6
3.4
1.7
3.3
1.8
3.2
1.8
3.2
V
V
max
min
typ
B
B
C
300||1.2
kΩ || pF
OUTPUT
Most Positive Output Voltage
No Load
RL = 100Ω
No Load
4.1
3.9
3.9
3.8
1.1
1.2
+90
–90
3.9
3.8
1.1
1.2
+80
–80
3.8
3.7
1.2
1.3
+70
–70
V
V
min
min
max
max
min
min
typ
A
A
A
A
A
A
C
Least Positive Output Voltage
0.9
V
RL = 100Ω
1.1
V
Current Output, Sourcing
Current Output, Sinking
Output Impedance
+120
–120
0.18
mA
mA
Ω
G = +2, f = 100kHz
(1) Junction temperature = ambient temperature for low temperature limit and +25°C specifications. Junction temperature = ambient temperature +10°C at high
temperature limit specifications.
(2) Test Levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation.
(B) Limits set by characterization and simulation.
(C) Typical value only for information.
(3) Current is considered positive out-of-node. VCM is the input common-mode voltage.
OPA693
SBOS285A
5
www.ti.com
ELECTRICAL CHARACTERISTICS: VS = +5V (Cont.)
Boldface limits are tested at +25°C.
G = +2 (–IN grounded though 0.001µF) and RL = 100Ω to VS/2 (see Figure 4 for AC performance only), unless otherwise noted.
OPA693ID, IDBV
TYP
MIN/MAX OVER TEMPERATURE
0
°
C to –40 C to
°
MIN/
TEST
MAX LEVEL(2 )
PARAMETER
CONDITIONS
+25°C(1)
+25°C
–155
70°C
+85°C
UNITS
DISABLE/POWER DOWN (DIS Pin)
Power-Down Supply Current (+VS)
Off Isolation
VDIS = 0
–95
65
–172
–180
µA
dB
pF
mV
mV
V
typ
typ
A
C
C
B
B
B
B
A
G = +2, 5MHz
Output Capacitance in Disable
Turn-On Glitch
4
typ
G = +2, RL = 150Ω, VIN = 2.5V
G = +2, RL = 150Ω, VIN = 2.5V
±20
±20
3.3
1.8
80
typ
Turn-Off Glitch
typ
Enable Voltage
3.5
1.7
137
3.6
1.6
153
3.7
1.5
160
min
max
typ
Disable Voltage
V
Control Pin Input Bias Current (DIS
)
VDIS = 0
µA
POWER SUPPLY
Specified Single-Supply Operating Voltage
Maximum Single-Supply Operating Voltage
Maximum Quiescent Current
5
V
V
typ
max
max
min
typ
C
A
A
A
C
+12
12.0
11.0
+12
12.5
9.5
+12
12.9
9.2
VS = +5V
VS = +5V
11.5
11.5
57
mA
mA
dB
Minimum Quiescent Current
Power-Supply Rejection Ratio (+PSRR)
Input Referred
TEMPERATURE RANGE
Specification: D, DBV
–40 to +85
°C
typ
C
Thermal Resistance, θJA
D
SO-8
125
150
°C/W
°C/W
typ
typ
C
C
DBV SOT23-6
(1) Junction temperature = ambient temperature for low temperature limit and +25°C specifications. Junction temperature = ambient temperature +10°C at high
temperature limit specifications.
(2) Test Levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation.
(B) Limits set by characterization and simulation.
(C) Typical value only for information.
(3) Current is considered positive out-of-node. VCM is the input common-mode voltage.
OPA693
6
SBOS285A
www.ti.com
TYPICAL CHARACTERISTICS: VS = ±5V
At TA = +25°C, G = +2, and RL = 100Ω, unless otherwise specified.
SMALL-SIGNAL FREQUENCY RESPONSE
LARGE-SIGNAL FREQUENCY RESPONSE
3
2
8
7
VO = 1VPP
G = +1
G = +2
RL = 100Ω
1
6
VO = 1VPP
G = +2
0
5
−1
−2
−3
−4
−5
−6
4
VO = 2VPP
G = −1
3
2
VO = 7VPP
1
VO = 4VPP
0
See Figure 1
200
−1
10
100
Frequency (MHz)
1000
2000
0
400
600
800
1000
Frequency (MHz)
FREQUENCY RESPONSE FLATNESS vs LOAD
G = +2
DEVIATION FROM LINEAR PHASE
RL = 100Ω
0.2
0.1
1.00
0.75
0.50
0.25
0
RL = 200Ω
VO = 1VPP
G = +1
RL = 150Ω
G = −1
0
−0.1
−0.2
−0.3
−0.4
RL = 75Ω
−0.25
−0.50
−0.75
−1.00
G = +2
RL = 100Ω
See Figure 1
100
0
200
Frequency (MHz)
300
400
0
50
100
Frequency (MHz)
150
200
GAIN OF +2 PULSE RESPONSE
Large Signal
GAIN OF +1 PULSE RESPONSE
Large Signal
3
2
3
2
RL = 100Ω
RL = 100Ω
1
1
Small Signal
Small Signal
0
0
−1
−2
−3
−1
−2
−3
See Figure 1
See Figure 2
Time (2ns/div)
Time (2ns/div)
OPA693
SBOS285A
7
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TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
At TA = +25°C, G = +2, and RL = 100Ω, unless otherwise specified.
10MHz HARMONIC DISTORTION
vs LOAD RESISTANCE
10MHz HARMONIC DISTORTION
vs SUPPLY VOLTAGE
−60
−65
−70
−75
−80
−85
−90
−95
−100
−60
−65
−70
−75
−80
−85
−90
−95
−100
2nd Harmonic
2nd Harmonic
3rd Harmonic
3rd Harmonic
G = +2
RL = 100Ω
G = +2
f = 10MHz
VO = 2VPP
VO = 2VPP
See Figure 1
See Figure 1
50
0.5
0.5
100
Load Resistance (Ω)
500
2.5
0.5
0.5
3.0
3.5
4.0
4.5
5.0
5.5 6.0
Supply Voltage (±V)
10MHz HARMONIC DISTORTION
vs OUTPUT VOLTAGE
G = +2 HARMONIC DISTORTION vs FREQUENCY
−60
−65
−70
−75
−80
−85
−90
−95
−100
−60
−65
−70
−75
−80
−85
−90
−95
−100
G = +2
RL = 100Ω
f = 10MHz
See Figure 1
RL = 100Ω
V
O = 2VPP
2nd Harmonic
2nd Harmonic
3rd Harmonic
3rd Harmonic
See Figure 1
1
5
1
10
Frequency (MHz)
50
Output Voltage (VPP
)
G = +1 HARMONIC DISTORTION vs FREQUENCY
G = –1 HARMONIC DISTORTION vs FREQUENCY
RL = 100Ω
O = 2VPP
See Figure 3
−60
−65
−70
−75
−80
−85
−90
−95
−100
−50
−55
−60
−65
−70
−75
−80
−85
−90
−95
−100
RL = 100Ω
O = 2VPP
See Figure 2
2nd Harmonic
V
V
2nd Harmonic
3rd Harmonic
3rd Harmonic
1
10
Frequency (MHz)
50
1
10
Frequency (MHz)
50
OPA693
8
SBOS285A
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TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
At TA = +25°C, G = +2, and RL = 100Ω, unless otherwise specified.
2-TONE, 3RD-ORDER
INTERMODULATION INTERCEPT
INPUT VOLTAGE vs CURRENT NOISE DENSITY
60
50
40
30
20
100
10
1
+5V
PI
PO
OPA693
RF
50Ω
Inverting Current Noise (internal)
22pA/√Hz
500Ω
300Ω
RG
300Ω
Noninverting Current Noise
17.8pA/√Hz
−5V
+5V
PI
50Ω
PO
OPA693
50Ω
RF
300Ω
50Ω
Voltage Noise
1.8nV/√Hz
RG
300Ω
−5V
0
25
50
75
100
125
150
175
200
100
1k
10k
100k
1M
10M
Frequency (MHz)
Frequency (MHz)
INPUT RETURN LOSS vs FREQUENCY (S11
)
OUTPUT RETURN LOSS vs FREQUENCY (S22)
0
−10
−20
−30
−40
−50
−60
−70
0
−10
−20
−30
−40
−50
−60
G = +2
See Figure 1
No Output
Trim Capacitor
VSWR < 1.2:1
G = −1
See Figure 3
VSWR < 1.2:1
50Ω
OPA693
G = +2
S
With
22
See Figure 1
Trim Capacitor
1.8pF
10
100
Frequency (MHz)
1000
10
100
Frequency (MHz)
1000
SMALL-SIGNAL FREQUENCY RESPONSE
vs CAPACITIVE LOAD
RECOMMENDED RS vs CAPACITIVE LOAD
G = +2
60
50
40
30
20
10
0
9
6
G = +2
Optimized RS
< 0.1dB Peaking
3
CL = 100pF
CL = 50pF
CL = 10pF
CL = 20pF
0
VIN
RS
VO
OPA693
−3
−6
−9
50Ω
300Ω
CL
1kΩ
300Ω
1kΩ is optional
1
10
100
10
100
Frequency (MHz)
1000
Capacitive Load (pF)
OPA693
SBOS285A
9
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TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
At TA = +25°C, G = +2, and RL = 100Ω, unless otherwise specified.
CLOSED-LOOP OUTPUT IMPEDANCE
PSRR vs FREQUENCY
–PSRR
10
65
60
55
50
45
40
35
30
25
20
+5V
+PSRR
OPA693
50Ω
ZO
–5V
300Ω
1
300Ω
0.1
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
1W Internal
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
5
4
150
140
130
120
110
100
15
14
13
12
11
10
Power
3
Boundary
Supply Current
100Ω Load Line
2
50Ω Load Line
20Ω Load Line
Right Scale
1
Sourcing Output Current
0
Left Scale
−1
−2
−3
−4
−5
Sinking Output Current
1W Internal
Power
Boundary
–50
–25
0
25
50
75
100
125
−250 −200 −150 −100 −50
0
50 100 150 200 250
Ambient Temperature (°C)
I
O (mA)
NONINVERTING OVERDRIVE RECOVERY
INVERTING OVERDRIVE RECOVERY
6
4
6
4
G = +2
L = 100Ω
G = −1
L = 100Ω
R
R
Output
2
2
Input
Output
Input
0
0
−2
−4
−6
−2
−4
−6
See Figure 1
See Figure 3
Time (50ns/div)
Time (50ns/div)
OPA693
10
SBOS285A
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TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
At TA = +25°C, G = +2, and RL = 100Ω, unless otherwise specified.
SETTLING TIME
DISABLED FEEDTHRU vs FREQUENCY
−20
−30
−40
−50
−60
−70
−80
−90
−100
20
15
G = +2
RL = 100Ω
DIS = 0V
G = +2
RL = 100Ω
2V → 0V
Output Step
V
10
Forward and Reverse
5
Input
0
−5
Output
−10
−15
−20
See Figure 1
See Figure 1
0
2
4
6
8
10 12 14 16 18 20
10
100
1000
Time (2ns/div)
Frequency (MHz)
COMMON-MODE INPUT AND OUTPUT SWING
vs SUPPLY VOLTAGE
TYPICAL DC DRIFT OVER TEMPERATURE
6
5
4
3
2
1
0
1.0
0.5
16
8
+
IB
Output
Input
0
0
VIO
−0.5
−1.0
−8
−16
IB− (internal)
–50
–25
0
25
50
75
100
125
2.0
2.5
3.0 3.5
4.0 4.5
5.0
5.5
6.0
6.5
Ambient Temperature (°C)
Supply Voltages (±V)
LARGE-SIGNAL DISABLE/ENABLE RESPONSE
COMPOSITE VIDEO dG/dP
7
6
0.12
0.10
0.08
0.06
0.04
0.02
0
+5V
DIS
No Pull-Down
With 1.0kΩ Pull-Down
Video In
Video Loads
5
OPA693
VDIS
dP
dP
4
75Ω
Optional
1.0kΩ
Pull-Down
3
−5V
2
VOUT
1
0
dG
dG
G = +2
IN = 1VDC
RL = 100Ω
−1
−2
−3
V
See Figure 1
1
2
3
4
Time (500ns/div)
Number of 150Ω Loads
OPA693
SBOS285A
11
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TYPICAL CHARACTERISTICS: VS = +5V
At TA = +25°C, G = +2, and RL = 100Ω to VS/2, unless otherwise specified.
SMALL-SIGNAL FREQUENCY RESPONSE
LARGE-SIGNAL FREQUENCY RESPONSE
3
2
8
7
VO = 1VPP
G = +2
L = 100Ω
R
G = +1
1
6
G = +2
0
5
VO = 1VPP
−1
−2
−3
−4
−5
−6
4
VO = 3VPP
G = −1
3
2
VO = 2VPP
1
0
See Figure 4
200
−1
1
10
Frequency (MHz)
100
1000
0
400
600
800
1000
Frequency (MHz)
SMALL-SIGNAL BANDWIDTH
vs SINGLE-SUPPLY VOLTAGE
FREQUENCY RESPONSE FLATNESS vs LOAD
G = +2
0.2
0.1
800
750
700
650
600
550
500
450
400
G = +2
VO = 0.5VPP
RL = 100Ω
VO = 1VPP
RL = 200Ω
0
RL = 150Ω
−0.1
−0.2
−0.3
−0.4
RL = 75Ω
RL = 100Ω
See Figure 4
See Figure 4
5
0
50
100
Frequency (MHz)
150
200
4
6
7
8
9
10
11
12
Single-Supply Voltage (V)
GAIN OF +2 PULSE RESPONSE
GAIN OF +1 PULSE RESPONSE
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
RL = 100Ω
RL = 100Ω
Large Signal
Small Signal
Large Signal
Small Signal
See Figure 4
See Figure 5
Time (2ns/div)
Time (2ns/div)
OPA693
12
SBOS285A
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TYPICAL CHARACTERISTICS: VS = +5V (Cont.)
At TA = +25°C, G = +2, and RL = 100Ω to VS/2, unless otherwise specified.
HARMONIC DISTORTION vs FREQUENCY
2nd Harmonic
HARMONIC DISTORTION vs OUTPUT VOLTAGE
−55
−60
−65
−70
−75
−80
−85
−90
−95
−55
−60
−65
−70
−75
−80
−85
−90
−95
G = +2
L = 100Ω
O = 2VPP
G = +2
RL = 100Ω
f = 10MHz
R
V
3rd Harmonic
2nd Harmonic
3rd Harmonic
See Figure 4
1
See Figure 4
0.5
10
Frequency (MHz)
50
0.1
1
3
Output Voltage (VPP
)
2-TONE, 3RD-ORDER
INTERMODULATION INTERCEPT
HARMONIC DISTORTION
vs LOAD RESISTANCE
−55
−60
−65
−70
−75
−80
−85
−90
−95
50
45
40
35
30
25
20
15
10
+5V
G = +2
f = 10MHz
1kΩ
PI
2nd Harmonic
PO
OPA693
50Ω
1kΩ
RF
300Ω
500Ω
RG
300Ω
3rd Harmonic
+5V
1kΩ
PI
50Ω
50Ω
PO
OPA693
1kΩ
RF
300Ω
50Ω
RG
300Ω
See Figure 4
0
25
50
75
100
125
150
175
200
50
100
Load Resistance (Ω)
500
Frequency (MHz)
OPA693
SBOS285A
13
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Figure 2 shows the DC-coupled, gain of +1V/V buffer con-
figuration used as a starting point for the gain of +1V/V
Typical Characteristic curves. In this case, the inverting input
resistor, RG, is left open giving a very broadband gain of +1
performance. While the test circuit shows a 50Ω input resis-
tor, a buffer application is typically transforming from a
source that cannot drive a heavy load to a 100Ω load, such
as shown in Figure 2. The noninverting input impedance of
the OPA693 is typically 100kΩ || 2pF. Driving directly into
the noninverting input will provide this very light load to the
source. However, the source must still provide the noninverting
input bias current required by the input stage to operate. An
alternative approach to a gain of +1 buffer is described in the
Wideband Unity Gain Buffers section of this data sheet.
APPLICATION INFORMATION
WIDEBAND BUFFER OPERATION
The OPA693 gives the exceptional AC performance of a
wideband current-feedback op amp with a highly linear
output stage. It features internal RF and RG resistors, making
it a simple matter to select a gain of +2, +1 or –1 with no
external resistors. Requiring only 13mA supply current, the
OPA693’s output swings to within 1V of either supply with
> 700MHz small signal bandwidth and > 300MHz delivering
7VPP into a 100Ω load. This low output headroom in a very
high-speed amplifier gives remarkable single +5V operation.
The OPA693 delivers 2VPP swing with > 500MHz bandwidth
operating on a single +5V supply. The primary advantage of
a current-feedback fixed gain video buffer, as opposed to a
slew-enhanced low-gain stable voltage-feedback implemen-
tation, is a higher slew rate with lower quiescent power and
output noise.
+5V
+
6.8µF
0.1µF
Figure 1 shows the DC-coupled, gain of +2V/V, dual power-
supply circuit configuration used as the basis for the ±5V
Electrical Characteristics table and Typical Characteristics
curves. For test purposes, the input impedance is set to 50Ω
with a resistor to ground and the output impedance is set to
50Ω with a series output resistor. Voltage swings reported in
the specifications are taken directly at the input and output
pins while load powers (dBm) are defined at a matched 50Ω
load. For the circuit of Figure 1, the total effective load will be
100Ω || 600Ω = 85.7Ω. The disable control line (DIS) is
typically left open to ensure normal amplifier operation. In
addition to the usual power supply decoupling capacitors to
ground, a 0.01µF capacitor can be included between the two
power-supply pins. This optional added capacitor will typi-
cally improve the 2nd harmonic distortion performance by
3dB to 6dB.
50Ω Source
DIS
50Ω
VI
50Ω
OPA693
VO
50Ω Load
RF
300Ω
RG
300Ω
0.1µF
6.8µF
+
Open
−5V
Figure 2. DC-Coupled, G = +1V/V, Bipolar-Supply, Specifica-
tion and Test Circuit.
Figure 3 shows the DC-coupled, gain of –1V/V buffer con-
figuration used as a starting point for the gain of –1V/V
Typical Characteristic curves. The input impedance is set to
50Ω using the parallel combination of an external 60.4Ω
resistor and the internal 300Ω RG resistor. The noninverting
input is tied directly to ground. Since the internal design for
the OPA693 is current-feedback, trying to get improved DC
accuracy by including a resistor on the noninverting input to
ground is ineffective. Using a direct short to ground on the
noninverting input reduces both the contribution of the DC
bias current and noise current to the output error. While the
external 60.4Ω is used here to match to the 50Ω source from
the test equipment, the maximum input impedance in this
configuration is limited to the 300Ω RG resistor even with the
RM resistor removed. Unlike the noninverting unity gain
buffer application, removing RM does not strongly impact the
DC operating point because the short on the noninverting
input of Figure 3 provides the DC operating voltage. This
application of the OPA693 provides a very broadband, high-
output, signal inverter.
+5V
+
6.8µF
0.1µF
50Ω Source
DIS
VI
50Ω
50Ω
OPA693
VO
50Ω Load
RF
300Ω
RG
300Ω
0.1µF
6.8µF
+
−5V
Figure 1. DC-Coupled, G = +2, Bipolar-Supply, Specification
and Test Circuit.
OPA693
14
SBOS285A
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+5V
+VS
+5V
+
0.1µF
6.8µF
+
0.1µF
6.8µF
50Ω Source
1000pF
604Ω
604Ω
DIS
50Ω
DIS
VO 100Ω
VI
VO
60.4Ω
OPA693
VS/2
OPA693
50Ω Load
RF
300Ω
50Ω Source
RG
300Ω
RF
300Ω
VI
RG
300Ω
RM
60.4Ω
0.1µF
6.8µF
1000pF
+
−5V
Figure 3. DC-Coupled, G = –1V/V, Bipolar-Supply Specifica-
Figure 4. AC-Coupled, G = +2V/V, Single-Supply Specifica-
tion and Test Circuit.
tion and Test Circuit.
While the circuit of Figure 4 shows +5V single-supply opera-
tion, this same circuit may be used for single supplies
ranging as high as +12V nominal. The noninverting input bias
resistors are relatively low in Figure 4 to minimize output DC
offset due to noninverting input bias current. At higher signal-
supply voltage, these should be increased to limit the added
supply current drawn through this path.
SINGLE-SUPPLY OPERATION
The OPA693 may be used over a single-supply range of +5V
to +12V. Though not a rail-to-rail output design, the OPA693
requires minimal input and output voltage headroom com-
pared to other very-wideband video buffer amplifiers. As
shown in the single +5V Typical Characteristic curves, the
OPA693 provides > 300MHz bandwidth driving a 3VPP swing
into a 100Ω load. The key requirement of broadband single-
supply operation is to maintain input and output signal
swings within the useable voltage ranges at both the input
and the output.
Figure 5 shows the AC-coupled, G = +1V/V, single-supply
specification and test circuit. In this case, the gain setting
resistor, RG, is simply left open to get a gain of +1V for AC
signals. Once again, the noninverting input is DC biased at
mid-supply, putting that same VS/2 at the output pin. The
signal is AC-coupled into this midpoint with an added termi-
nation resistor on the source side of the blocking capacitor.
The circuit of Figure 4 shows the AC-coupled, gain of
+2V/V, video buffer circuit used as the basis for the Electrical
Characteristics table and Typical Characteristics curves. The
circuit of Figure 4 establishes an input midpoint bias using a
simple resistive divider from the +5V supply (two 604Ω
resistors). The input signal is then AC-coupled into this
midpoint voltage bias. The input voltage can swing to within
1.7V of either supply pin, giving a 1.6VPP input signal range
centered between the supply pins. The input impedance
matching resistor (60.4Ω) used for testing is adjusted to give
a 50Ω input match when the parallel combination of the
biasing divider network is included. The gain resistor (RG) is
AC-coupled, giving the circuit a DC gain of +1, which puts the
input DC bias voltage (2.5V) on the output as well. Again, on
a single +5V supply, the output voltage can swing to within
1V of either supply pin while delivering more than 90mA
output current. A demanding 100Ω load to a midpoint bias is
used in this characterization circuit. The new output stage
used in the OPA693 can deliver large bipolar output current
into this midpoint load with minimal crossover distortion, as
shown by the +5V supply, 3rd-harmonic distortion plots.
VS
+5V
+
0.1µF
6.8µF
604Ω
604Ω
50Ω Source
1000pF
DIS
100Ω
VI
VO
60.4Ω
OPA693
VS/2
RF
300Ω
RG
300Ω
Open
Figure 5. AC-Coupled, G = +1V/V, Single-Supply Specifica-
tion and Test Circuit.
OPA693
SBOS285A
15
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SINGLE-SUPPLY ADC INTERFACE
This circuit creates an additional input offset voltage as the
difference in the two input bias currents times the impedance
to ground at VI. Figure 8 shows a comparison of small-signal
frequency response for the unity gain buffer of Figure 2
compared to the improved approach shown in Figure 7.
Most modern, high-performance ADCs (such as the Texas
Instruments ADS8xx series) operate on a single +5V (or
lower) power supply. It has been a considerable challenge
for single-supply op amps to deliver a low distortion input
signal at the ADC input for signal frequencies exceeding
5MHz. The high slew rate, exceptional output swing, and
high linearity of the OPA693 make it an ideal single-supply
ADC driver. Figure 6 shows an example input interface to a
very high-performance, 10-bit, 75MSPS CMOS converter.
+5V
DIS
RO
50Ω
VO
The OPA693 in the circuit of Figure 6 provides > 500MHz
bandwidth at an operating gain of +2V/V delivering 1VPP at the
output for a 0.5VPP input. This broad bandwidth provides
adequate margin to deliver low distortion to the maximum
20Mhz analog input frequency intended for the circuit of Figure
6. A 40MHz low-pass filter is provided as part of the converter
interface to both limit broadband noise and reduce harmonics
as the signal frequency exceeds 15MHz. The noninverting input
bias voltage is referenced to the midpoint of the ADC signal
range by dividing off the top and bottom of the internal ADC
reference ladder.
OPA693
RG
300Ω
RF
300Ω
VI
RM
50Ω
−5V
Figure 7. Improved Unity Gain Buffer.
2
G = +1, Figure 2
WIDEBAND UNITY GAIN BUFFER WITH IMPROVED
FLATNESS
1
0
As shown in the Typical Characteristic curves, the unity gain
buffer configuration of Figure 2 shows a peaking in the fre-
quency response exceeding 2dB. This gives the slight amount
of overshoot and ringing apparent in the gain of +1V/V pulse
response curves. A similar circuit that holds a flatter frequency
response, giving improved pulse fidelity, is shown in Figure 7.
−1
G = +1, Figure 7
−2
−3
−4
−5
−6
This circuit removes the peaking by bootstrapping out any
parasitic effects on RG. The input impedance is still set by RM
as the apparent impedance looking into RG is very high. RM
may be increased to show a higher input impedance, but
larger values will start to impact DC output offset voltage.
10
100
Frequency (MHz)
1000
Figure 8. Buffer Frequency Response Comparison.
+5V
+5V
RF
300Ω
RG
ADS828
10-Bit
75MSPS
1000pF
Clock
300Ω
50Ω
Input
OPA693
1VPP
100pF
Input
0.5VPP
1000pF
CM
2kΩ
DIS
+3.5V
REFT
0.1µF
+2.5V DC Bias
2kΩ
+1.5V
REFB
0.1µF
Figure 6. Wideband, AC-Coupled, Single-Supply ADC Driver.
OPA693
16
SBOS285A
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WIDEBAND, DC-COUPLED,
SINGLE-TO-DIFFERENTIAL CONVERSION
shows an example gain of +2 line driver using the OPA693
that incorporates a 40MHz low-pass Butterworth response
with just a few external components. The filter resistor values
have been adjusted slightly here from an ideal filter analysis
to account for parasitic effects.
The frequency response shown in Figure 7 for the improved
gain of +1V/V buffer closely matches the inverting gain of
–1V/V frequency response. Combining two OPA693s to give
a +1 and –1 response will give a very broadband, DC-
coupled, single-ended input to differential output conversion.
Figure 9 shows this implementation where the input match is
now set by RM in parallel with the RG resistor of the inverting
stage. This circuit is essentially providing a DC to 700MHz
1:1 transformer operation. A 50Ω input match is shown, but
this may be increased by increasing RM. For instance,
targeting a 200Ω input impedance requires an RM = 600Ω to
get the parallel combination of RM and RG = 200Ω.
+5V
22pF
100Ω
226Ω
VI
50Ω
22pF
VO
50Ω
OPA693
0Ω
Source
RF
300Ω
RG
+5V
300Ω
−5V
DIS
OPA693
+VI
Figure 10. Line Driver with 40 MHz Low-Pass Active Filter.
RG
300Ω
RF
300Ω
This type of filter depends on a low output impedance from
the amplifier through very high frequencies to continue to
provide an increasing attenuation with frequency. As the
amplifier output impedance rises with frequency, any input
signal or noise starts to feed directly through to the output via
the feedback capacitor. Since the OPA693 used in Figure 10
has a 700MHz bandwidth, the active filter will continue to roll
off through frequencies exceeding 200MHz. Figure 11 shows
the frequency response for the filter of Figure 10, where the
desired 40MHz cutoff is achieved and a 40dB/dec rolloff is
held through very high frequencies.
VI
RM
60.4Ω
−5V
2VI
RG
300Ω
RF
300Ω
+5V
OPA693
−VI
DIS
−5V
3
0
−3
−6
Figure 9. DC → 700MHz, Single-to-Differential Conversion.
−9
−12
−15
−18
−21
−24
−27
−30
HIGH-FREQUENCY ACTIVE FILTERS
The extremely wide bandwidth of the OPA693 allows a wide
range of active filter topologies to be implemented with
minimal amplifier bandwidth interaction in the filter shape.
Sallen-Key filters, using either a gain of 1 or gain of 2
amplifier, may be easily implemented with no external gain
setting elements. In general, given a desired filter WO, the
amplifier should have at least 20X that WO to minimize filter
interaction with the amplifier frequency response. Figure 10
1
10
Frequency (MHz)
100
1000
Figure 11. 40MHz Low-Pass Active Filter Response.
OPA693
SBOS285A
17
www.ti.com
either the output capabilities or the 1W dissipation limit. A
100Ω load line (the standard test-circuit load) shows full
±3.8V output swing capability, as shown in the Typical
Characteristics.
DESIGN-IN TOOLS
DEMONSTRATION BOARDS
Two printed circuit (PC) boards are available to assist in the
initial evaluation of the circuit performance using the OPA693 in
its two package styles. Both are available free as unpopulated
PC boards delivered with descriptive documentation. The sum-
mary information for these boards is shown in Table I.
The minimum specified output voltage and current specifica-
tions over temperature are set by worst-case simulations at
the cold temperature extreme. Only at cold startup will the
output current and voltage decrease to the numbers shown
in the over-temperature min/max specifications. As the out-
put transistors deliver power, their junction temperatures
increase, which decreases their VBE’s (increasing the avail-
able output voltage swing) and increases their current gains
(increasing the available output current). In steady state
operation, the available output voltage and current will al-
ways be greater than that shown in the over-temperature
characteristics since the output stage junction temperatures
will be higher than the minimum specified operating ambient.
DEMO BOARD
PART
LITERATURE
REQUEST
NUMBER
PRODUCT
PACKAGE
NUMBER
OPA693ID
SO-8
DEM-OPA68xU
DEM-OPA6xxN
SBOU009
SBOU010
OPA693IDBV
SOT23-6
TABLE I. Demo Board Ordering Information.
To request either of these boards, check the Texas Instru-
ments web site at www.ti.com.
To maintain maximum output stage linearity, no output short-
circuit protection is provided. This will not normally be a
problem, since most applications include a series matching
resistor at the output that limits the internal power dissipation
if the output side of this resistor is shorted to ground.
However, shorting the output pin directly to an adjacent
positive power supply pin will, in most cases, destroy the
amplifier. If additional protection to a power-supply short is
required, consider a small series resistor in the power supply
leads. Under heavy output loads, this will reduce the avail-
able output voltage swing. A 5Ω series resistor in each
supply lead will limit the internal power dissipation to < 1W for
an output short while decreasing the available output voltage
swing only 0.5V, for up to 100mA desired load currents.
Always place the 0.1µF power supply decoupling capacitors
after these supply current limiting resistors directly on the
device supply pins.
OPERATING SUGGESTIONS
GAIN SETTING
Setting the gain for the OPA693 is very easy. For a gain of +2,
ground the –IN pin and drive the +IN pin with the signal. For
a gain of +1, either leave the –IN pin open and drive the +IN
pin or drive both the +IN and –IN pins as shown in Figure 7.
For a gain of –1, ground the +IN pin and drive the –IN pin with
the input signal. An external resistor may be used in series
with the –IN pin to reduce the gain. However, since the internal
resistors (RF and RG) have a tolerance and temperature drift
different than the external resistor, the absolute gain accuracy
and gain drift over temperature will be relatively poor com-
pared to the previously described standard gain connections
using no external resistor.
DRIVING CAPACITIVE LOADS
OUTPUT CURRENT AND VOLTAGE
One of the most demanding, and yet very common, load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an ADC, including additional
external capacitance, which may be recommended to improve
ADC linearity. A high-speed, high open-loop gain, amplifier like
the OPA693 can be very susceptible to decreased stability
and may give closed-loop response peaking when a capaci-
tive load is placed directly on the output pin. When the
amplifier’s open loop output resistance is considered, this
capacitive load introduces an additional pole in the signal path
that can decrease the phase margin. Several external solu-
tions to this problem have been suggested. When the primary
considerations are frequency response flatness, pulse re-
sponse fidelity and/or distortion, the simplest and most effec-
tive solution is to isolate the capacitive load from the feedback
loop by inserting a series isolation resistor between the ampli-
fier output and the capacitive load. This does not eliminate the
pole from the loop response, but rather shifts it and adds a
zero at a higher frequency. The additional zero acts to cancel
the phase lag from the capacitive load pole, thus increasing
the phase margin and improving stability.
The OPA693 provides output voltage and current capabilities
that can easily support multiple video loads and/or 100Ω
loads with very low distortion. Under no-load conditions at
25°C, the output voltage typically swings to 1V of either
supply rail; the tested swing limit is within 1.2V of either rail.
Into a 15Ω load (the minimum tested load), it is tested to
deliver more than ±90mA.
The specifications described above, though familiar in the
industry, consider voltage and current limits separately. In
many applications, it is the voltage × current, or V-I product,
which is more relevant to circuit operation. Refer to the
Output Voltage and Current Limitations plot in the Typical
Characteristics. The X and Y axes of this graph show the
zero-voltage output current limit and the zero-current output
voltage limit, respectively. The four quadrants give a more
detailed view of the OPA693’s output drive capabilities,
noting that the graph is bounded by a “Safe Operating Area”
of 1W maximum internal power dissipation. Superimposing
resistor load lines onto the plot shows that the OPA693 can
drive ±3.4V into 20Ω or ±3.7V into 50Ω without exceeding
OPA693
18
SBOS285A
www.ti.com
The Typical Characteristics show a Recommended RS vs
Capacitive Load curve to help the designer pick a value to
give < 0.1dB peaking to the load. The resulting frequency
response curves show a 0.1dB peaked response for several
selected capacitive loads and recommended RS combina-
tions. Parasitic capacitive loads greater than 2pF can begin
to degrade the performance of the OPA693. Long PC board
traces, unmatched cables, and connections to other amplifier
inputs can easily exceed this value. Always consider this
effect carefully, and add the recommended series resistor as
close as possible to the OPA693 output pin (see the Board
Layout Guidelines section).
intermodulation spurious power levels is given by
∆dBc = 2 × (IM3 – PO), where IM3 is the intercept taken from
the Typical Characteristics and PO is the power level in dBm at
the 50Ω load for one of the two closely-spaced test frequencies.
For instance, at 50MHz, the OPA693 at a gain of +2 has an
intercept of 44dBm at a matched 50Ω load. If the full envelope
of the two frequencies needs to be 2VPP at this load, this
requires each tone to be 4dBm (1VPP). The 3rd-order inter-
modulation spurious tones will then be 2 × (44 – 4) = 80dBc
below the test tone power level (–76dBm). If this same 2VPP
2-tone envelope were delivered directly into a lighter 500Ω load,
the intercept would increase to the 52dBm shown in the Typical
Characteristics. With the same output signal and gain condi-
tions, but now driving directly into a light load with no matching
loss, the 3rd-order spurious tones will then be at least
2 × (52 – 4) = 96dBc below the 4dBm test tone power levels
centered on 50MHz (–92dBm). We are still using a 4dBm for the
1VPP output swing into this 500Ω load. While not strictly correct
from a power standpoint, this does give the correct prediction for
spurious level. The class AB output stage for the OPA693 is
much more voltage swing dependent on output distortion than
strictly power dependent. To use the 500Ω intercept curve, use
the single-tone voltage swing as if it were driving a 50Ω load to
compute the PO used in the intercept equation.
The criterion for setting this RS resistor is a maximum
bandwidth, flat frequency response at the load (< 0.1dB
peaking). For the OPA693 operating in a gain of +2, the
frequency response at the output pin is very flat to begin with,
allowing relatively small values of RS to be used for low
capacitive loads.
DISTORTION PERFORMANCE
The OPA693 provides good distortion performance into a
100Ω load on ±5V supplies. Relative to alternative solutions,
the OPA693 holds much lower distortion at higher frequencies
(> 20Mhz) than alternative solutions. Generally, until the
fundamental signal reaches very high frequency or power
levels, the 2nd harmonic will dominate the distortion with a
negligible 3rd harmonic component. Focusing then on the 2nd
harmonic, increasing the load impedance improves distortion
directly. Remember that the total load includes the feedback
network—in the noninverting configuration (see Figure 1) this
is the sum of RF + RG, while in the inverting configuration it is
just RF (see Figure 3). Also, providing an additional supply de-
coupling capacitor (0.01µF) between the supply pins (for
bipolar operation) improves the 2nd-order distortion slightly
(3dB to 6dB).
GAIN ACCURACY AND LINEARITY
The OPA693 provides improved absolute gain accuracy and
DC linearity over earlier fixed gain of two line drivers. Oper-
ating at a gain of +2V/V by tying the –IN pin to ground, the
OPA693 shows a maximum gain error of ±0.9% at 25°C. The
DC gain will therefore lie between 1.982V/V and 2.018V/V at
room temperature. Over the specified temperature ranges,
this gain tolerance expands only slightly due to the matched
temperature drift for RF and RG. Achieving this gain accuracy
requires a very low impedance ground at –IN. Typical pro-
duction lots show a much tighter distribution in gain than this
±0.9% specification. Figure 12 shows a typical distribution in
measured gain at the gain of +2V/V configuration, in this
case showing a slight drop in the mean (0.25%) from the
nominal but with a very tight distribution.
The OPA693 has an extremely low 3rd-order harmonic
distortion. This also produces a high 2-tone, 3rd-order inter-
modulation intercept. Two graphs for this intercept are given
in the in the Typical Characteristics; one for ±5V and one for
+5V. The lower curve shown in each graph is defined at the
50Ω load when driven through a 50Ω matching resistor, to
allow direct comparisons to RF MMIC devices. The higher
curve in each graph shows the intercept if the output is taken
directly at the output pin with a 500Ω load, to allow prediction
of the 3rd-order spurious level when driving a lighter load,
such as an ADC input. The output matching resistor attenu-
ates the voltage swing from the output pin to the load by 6dB.
If the OPA693 drives directly into the input of a high-
impedance device, such as an ADC, this 6dB attenuation is
not taken and the intercept will increase a minimum of 6dB,
as shown in the 500Ω load typical characteristic.
600
Mean = 1.995
σ = 0.005
500
400
300
200
100
0
The intercept is used to predict the intermodulation spurious
levels for two closely-spaced frequencies. If the two test fre-
quencies (f1 and f2) are specified in terms of average and delta
frequency, fO = (f1 + f2)/2 and ∆f = |f2 – f1|/2, then the two, 3rd-
order, close-in spurious tones will appear at fO ±3 × ∆f. The
difference between two equal test tone power levels and these
Gain(V/V)
Figure 12. Typical +2V/V Gain Distribution.
OPA693
SBOS285A
19
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The exceptionally linear output stage (as illustrated by the
high 3rd-order intermodulation intercept) and low thermal
gradient induced errors for the OPA693 give an extremely
linear output over large voltage swings and heavy loads.
Figure 13 shows the tested deviation (in % of peak to peak)
from linearity for a range of symmetrical output swings and
loads. Below 4VPP, for either a 100Ω or a 500Ω load, the
OPA693 delivers > 14-bit linear output response.
The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 1 shows the general form for the
output noise voltage using the terms shown in Figure 14.
(1)
2
2
2
EO
=
ENI + IBNRS + 4kTRS NG2 + I R
+ 4kTRFNG
(
)
(
)
BI
F
Dividing this expression through by noise gain (NG = 1 + RF/RG)
will give the equivalent input-referred spot noise voltage at the
non-inverting input, as shown in Equation 2.
0.0200
Figure 1 Test Circuit
0.0175
0.0150
(2)
2
0.0125
IBIRF
NG
4kTRF
NG
2
2
EN
=
ENI + IBNRS + 4kTRS
+
+
RL = 100Ω
(
)
0.0100
0.0075
Evaluating the output noise and input noise expressions for
the two noninverting gain configurations, and with two differ-
ent values for the noninverting source impedance, gives
output and input referred spot noise voltages of Table II.
0.0050
RL = 500Ω
0.0025
0
2
3
4
5
6
7
8
OUTPUT
SPOT NOISE
EO
TOTAL INPUT
SPOT NOISE
EN
V
O (peak to peak)
RS
(Ω)
Figure 13. DC Linearity vs Output Swing and Loads.
√Hz
√Hz
)
CONFIGURATION
(nV/
)
(nV/
G = +2 (Figure 1)
G = +2 (Figure 1)
G = +1 (Figure 2)
G = +1 (Figure 2)
25
300
25
8.3
4.15
NOISE PERFORMANCE
14
7.3
9.2
7
The OPA693 offers an excellent balance between voltage and
current noise terms to achieve a low output noise under a
variety of operating conditions. The inverting node noise
current (internal) will appear at the output multiplied by the
relatively low 300Ω feedback resistor. The input noise voltage
(1.8nV/√Hz) is extremely low for a unity gain stable amplifier.
This low input voltage noise was achieved at the price of
higher noninverting input current noise (17.8pA/√Hz). As long
as the AC source impedance looking out of the noninverting
input is less than 100Ω, this current noise will not contribute
significantly to the total output noise. The op amp input voltage
noise and the two input current noise terms combine to give
low output noise for the each of the three gain settings
available using the OPA693. Figure 14 shows the op amp
noise analysis model with all of the noise terms included. In
this model, all noise terms are taken to be noise voltage or
7.3
9.2
300
TABLE II. Total Output and Input Referred Noise.
The output noise is being dominated by the inverting current
noise times the internal feedback resistor. This gives a total
input referred noise voltage that exceeds the 1.8nV voltage
term for the amplifier itself.
DC ACCURACY AND OFFSET CONTROL
A current-feedback op amp like the OPA693 provides excep-
tional bandwidth and slew rate giving fast pulse settling but
only moderate DC accuracy. The Electrical Characteristics
show an input offset voltage comparable to high-speed volt-
age-feedback amplifiers. However, the two input bias currents
are somewhat higher and are unmatched. Whereas bias
current cancellation techniques are very effective with most
voltage-feedback op amps, they do not generally reduce the
output DC offset for wideband current-feedback op amps.
Since the two input bias currents are unrelated in both mag-
nitude and polarity, matching the source impedance looking
out of each input to reduce their error contribution to the output
is ineffective. Evaluating the configuration of Figure 1, using
worst case +25°C input offset voltage and the two input bias
currents, gives a worst-case output offset range equal to:
current density terms in either nV/√Hz or pA/√Hz
.
ENI
EO
OPA693
RS
IBN
ERS
RF
√4kTRS
±(NG × VOS) + (IBN × RS/2 × NG) ± (IBI × RF)
= ±(2 × 2.0mV) ± (35µA × 25Ω × 2) ± (50µA × 300Ω)
= ±4mV ± 1.75mV ± 15mV
√4kTRF
IBI
RG
4kT
RG
4kT = 1.6E –20J
at 290°K
= ±30.75mV
where NG = noninverting signal gain.
Figure 14. Op Amp Noise Model.
20
OPA693
SBOS285A
www.ti.com
Minimizing the resistance seen by the noninverting input will
minimize the output DC error. For improved DC precision in
a wideband low-gain amplifier, consider the OPA842 where
a bipolar input is acceptable (low source resistance) or the
OPA656 where a JFET input is required.
The shutdown feature for the OPA693 is a positive supply
referenced, current-controlled, interface. Open collector (or
drain) interfaces are most effective, as long as the controlling
logic can sustain the resulting voltage (in the open mode)
that will appear at the VDIS pin. That voltage will be one diode
below the positive supply voltage applied to the OPA693. For
voltage output logic interfaces, the on/off voltage levels
described in the Electrical Characteristics apply only for a
+5V positive supply on the OPA693. An open-drain interface
is recommended for shutdown operation using a higher
positive supply for the OPA693 and/or logic families with
inadequate high-level voltage swings.
DISABLE OPERATION
The OPA693 provides an optional disable feature that can be
used to reduce system power. If the VDIS control pin is left
unconnected, the OPA693 will operate normally. This shut-
down is intended only as a power-savings feature. Forward
path isolation when disabled is very good for small signals for
gains of +1 or +2. Large-signal isolation is not ensured. Using
this feature to multiplex two or more outputs together is not
recommended. Large signals applied to the disabled output
stages can turn on parasitic devices degrading signal linear-
ity for the desired channel.
THERMAL ANALYSIS
The OPA693 does not require heatsinking or airflow in most
applications. Maximum desired junction temperature sets the
maximum allowed internal power dissipation as described
here. In no case should the maximum junction temperature
be allowed to exceed 150°C.
Turn-on time is very quick from the shutdown condition,
typically < 60ns. Turn-off time is strongly dependent on the
selected gain configuration and load, but is typically 3µs for
the circuit of Figure 1.
Operating junction temperature (TJ) is given by TA + PD × θJA.
The total internal power dissipation (PD) is the sum of
quiescent power (PDQ) and additional power dissipated in the
output stage (PDL) to deliver load power. Quiescent power is
simply the specified no-load supply current times the total
supply voltage across the part. PDL will depend on the
required output signal and load but would, for a grounded
resistive load, be at a maximum when the output is fixed at
a voltage equal to 1/2 either supply voltage (for equal bipolar
To shutdown, the control pin must be asserted low. This logic
control is referenced to the positive supply, as shown in the
simplified circuit of Figure 15.
+VS
2
supplies). Under this worst-case condition, PDL = VS /(4 × RL)
where RL includes feedback network loading. This is the
absolute highest power that can be dissipated for a given RL.
All actual applications will dissipate less power in the output
stage.
15kΩ
Q1
Note that it is the power in the output stage and not into the
load that determines internal power dissipation.
As a worst-case example, compute the maximum TJ using an
OPA693IDBV (SOT23-6 package) in the circuit of Figure 1
operating at the maximum specified ambient temperature of
+85°C and driving a grounded 100Ω load. Maximum internal
power is:
110kΩ
25kΩ
–VS
IS
VDIS
Control
PD = 10V × 14.1mA + 52 /(4 × (100Ω+|| 600Ω)) = 214mW
Figure 15. Simplified Disable Control Circuit.
Maximum TJ = +85°C + (0.21W × 150°C/W) = 117°C.
In normal operation, base current to Q1 is provided through
the 110kΩ resistor while the emitter current through the 15kΩ
resistor sets up a voltage drop that is inadequate to turn on
the two diodes in Q1’s emitter. As VDIS is pulled LOW,
additional current is pulled through the 15kΩ, eventually
turning on these two diodes (≈80µA). At this point, any further
current pulled out of VDIS goes through those diodes holding
the emitter-base voltage of Q1 at approximately 0V. This
shuts off the collector current out of Q1, turning the amplifier
off. The supply current in the shutdown mode is only that
required to operate the circuit of Figure 15.
All actual applications will operate at a lower junction tem-
perature than the 117°C computed above. Compute your
actual output stage power to get an accurate estimate of
maximum junction temperature, or use the results shown
here as an absolute maximum.
OPA693
SBOS285A
21
www.ti.com
BOARD LAYOUT GUIDELINES
matched impedance transmission line using microstrip or stripline
techniques (consult an ECL design handbook for microstrip and
stripline layout techniques). A 50Ω environment is normally not
necessary on board, and in fact, a higher impedance environ-
ment will improve distortion, as shown in the distortion versus
load plots. With a characteristic board trace impedance defined
based on board material and trace dimensions, a matching
series resistor into the trace from the output of the OPA693 is
used, as well as a terminating shunt resistor at the input of the
destination device. Remember also that the terminating imped-
ance will be the parallel combination of the shunt resistor and
the input impedance of the destination device; this total effective
impedance should be set to match the trace impedance. If the
6dB attenuation of a doubly-terminated transmission line is
unacceptable, a long trace can be series-terminated at the
source end only. Treat the trace as a capacitive load in this case
and set the series resistor value as shown in the plot of
Recommended RS vs Capacitive Load. This will not preserve
signal integrity as well as a doubly-terminated line. If the input
impedance of the destination device is low, there will be some
signal attenuation due to the voltage divider formed by the
series output into the terminating impedance.
Achieving optimum performance with a high-frequency amplifier
like the OPA693 requires careful attention to PC board layout
parasitics and external component types. Recommendations
that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for all
of the signal I/O pins. Parasitic capacitance on the output can
cause instability; on the noninverting input, it can react with the
source impedance to cause unintentional bandlimiting. To
reduce unwanted capacitance, create a window around the
signal I/O pins in all of the ground and power planes around
those pins. Otherwise, ground and power planes should be
unbroken elsewhere on the board.
b) Minimize the distance (< 0.25”) from the power supply pins
to high frequency 0.1µF decoupling capacitors. At the device
pins, the ground and power plane layout should not be in close
proximity to the signal I/O pins. Avoid narrow power and ground
traces to minimize inductance between the pins and the decou-
pling capacitors. The power supply connections should always
be decoupled with these capacitors. Larger (2.2µF to 6.8µF)
decoupling capacitors, effective at lower frequency, should also
be used on the supply pins. These may be placed somewhat
farther from the device and may be shared among several
devices in the same area of the PC board.
e) Socketing a high-speed part like the OPA693 is not
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket can create an extremely
troublesome parasitic network, which can make it almost
impossible to achieve a smooth, stable frequency response.
Best results are obtained by soldering the OPA693 directly
onto the board.
c) Careful selection and placement of external compo-
nents will preserve the high frequency performance of the
OPA693. Use resistors that have low reactance at high
frequencies. Surface-mount resistors work best and allow a
tighter overall layout. Metal film and carbon composition axi-
ally-leaded resistors can also provide good high-frequency
performance. Again, keep their leads and PC board trace
length as short as possible. Never use wirewound type resis-
tors in a high-frequency application. Since the output pin and
inverting input pin are the most sensitive to parasitic capaci-
tance, always position the series output resistor, if any, as
close as possible to the output pin. Since the inverting input
node is internal for the OPA693, it is more robust to layout
issues than amplifiers with similar speed but external feedback
and gain resistors. Other network components, such as
noninverting input termination resistors, should also be placed
close to the package. Good axial metal film or surface mount
resistors have approximately 0.2pF in shunt with the resistor.
For resistor values > 2.0kΩ, this parasitic capacitance can add
a pole and/or zero below 400MHz that can effect circuit
operation. Keep resistor values as low as possible consistent
with load driving considerations.
INPUT AND ESD PROTECTION
The OPA693 is built using a very high-speed complementary
bipolar process. The internal junction breakdown voltages are
relatively low for these very small geometry devices. These
breakdowns are reflected in the Absolute Maximum Ratings
table. All device pins are protected with internal ESD protec-
tion diodes to the power supplies, as shown in Figure 16.
+VCC
External
Pin
Internal
Circuitry
–VCC
Figure 16. Internal ESD Protection.
d) Connections to other wideband devices on the PC board
may be made with short direct traces or through onboard
transmission lines. For short connections, consider the trace
and the input to the next device as a lumped capacitive load.
Relatively wide traces (50 to 100mils) should be used, prefer-
ably with ground and power planes opened up around them.
Estimate the total capacitive load and set RS from the plot of
Recommended RS vs Capacitive Load. Low parasitic capacitive
loads (< 4pF) may not need an RS since the OPA693 is
nominally compensated to operate with a 2pF parasitic load. If
a long trace is required, and the 6dB signal loss intrinsic to a
doubly-terminated transmission line is acceptable, implement a
These diodes provide moderate protection to input overdrive
voltages above the supplies as well. The protection diodes can
typically support 30mA continuous current. Where higher
currents are possible (for example, in systems with ±15V
supply parts driving into the OPA693), current limiting series
resistors may be added on the noninverting input. Keep this
resistor value as low as possible since high values degrade
both noise performance and frequency response. The invert-
ing input already has a 300Ω resistor from the external pin to
the internal summing junction for the op amp. This provides
considerable protection for that node.
OPA693
22
SBOS285A
www.ti.com
Revision History
DATE
REVISION PAGE
SECTION
DESCRIPTION
Changed Storage Temperature Range from −40°C to +125C to
−65°C to +125C.
7/08
A
2
Abs Max Ratings
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
OPA693
SBOS285A
23
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA693ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
693
Samples
OPA693IDBVR
OPA693IDBVT
OPA693IDG4
ACTIVE
ACTIVE
LIFEBUY
SOT-23
SOT-23
SOIC
DBV
DBV
D
6
6
8
3000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
C59
Samples
Samples
250
75
RoHS & Green
RoHS & Green
C59
OPA
693
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2023
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
OPA693ID
D
D
SOIC
SOIC
8
8
75
75
506.6
506.6
8
8
3940
3940
4.32
4.32
OPA693IDG4
Pack Materials-Page 1
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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