OPA694ID [TI]
宽带、低功耗、电流反馈放大器 | D | 8 | -40 to 85;
| 型号： | OPA694ID |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 宽带、低功耗、电流反馈放大器 | D | 8 | -40 to 85 放大器 |
| 文件： | 总31页 (文件大小：1062K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA694
www.ti.com
SBOS319G –SEPTEMBER 2004–REVISED JANUARY 2010
Wideband, Low-Power, Current Feedback
Operational Amplifier
Check for Samples: OPA694
1
FEATURES
DESCRIPTION
2
•
•
•
•
•
•
UNITY GAIN STABLE BANDWIDTH: 1.5GHz
HIGH GAIN OF 2V/V BANDWIDTH: 690MHz
LOW SUPPLY CURRENT: 5.8mA
The OPA694 is an ultra-wideband, low-power, current
feedback operational amplifier featuring high slew
rate and low differential gain/phase errors. An
improved output stage provides ±80mA output drive
with < 1.5V output voltage headroom. Low supply
HIGH SLEW RATE: 1700V/msec
HIGH FULL-POWER BANDWIDTH: 675MHz
current with
>
500MHz bandwidth meets the
LOW DIFFERENTIAL GAIN/PHASE:
0.03%/0.015°
requirements of high-density video routers. Being a
current feedback design, the OPA694 holds its
bandwidth to very high gains—at a gain of 10, the
OPA694 will still provide 200MHz bandwidth.
•
Pb-FREE AND GREEN SOT23-5 PACKAGE
APPLICATIONS
RF applications can use the OPA694 as a low-power
SAW pre-amplifier. Extremely high 3rd-order intercept
is provided through 70MHz at much lower quiescent
power than many typical RF amplifiers.
•
•
•
•
•
WIDEBAND VIDEO LINE DRIVER
MATRIX SWITCH BUFFER
DIFFERENTIAL RECEIVER
ADC DRIVER
The OPA694 is available in an industry-standard
pinout in both SO-8 and SOT23-5 packages.
IMPROVED REPLACEMENT FOR OPA658
+5V
OPA694 RELATED PRODUCTS
SINGLES
—
DUALS
TRIPLES
QUADS
FEATURES
OPA2694
—
—
Dual Version
VIN
75W
VLOAD
RG-59
OPA694
Low-Power,
CFBPlus
75W
OPA683 OPA2683
—
—
75W
Low-Power,
CFBPlus
402W
OPA684 OPA2684 OPA3684 OPA4684
OPA691 OPA2691 OPA3691
OPA695 OPA2695 OPA3695
—
—
High Output
402W
-5V
High Intercept
Gain 2V/V Video Line Driver
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2010, Texas Instruments Incorporated
OPA694
SBOS319G –SEPTEMBER 2004–REVISED JANUARY 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
SPECIFIED
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
OPA694ID
OPA694IDR
Rails, 100
OPA694
SO-8
D
-40°C to +85°C
-40°C to +85°C
OPA694
BIA
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 3000
OPA694IDBVT
OPA694IDBVR
OPA694
SOT23-5
DBV
(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see
the TI web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted.
OPA694
UNIT
Power Supply
±6.5
VDC
Internal Power Dissipation
Differential Input Voltage
Input Voltage Range
See Thermal Characteristics
±1.2
±VS
V
V
Storage Temperature Range: D, DBV
Junction Temperature (TJ)
–65 to +125
+150
°C
°C
V
Human Body Model (HBM)
1500
ESD Ratings:
Charge Device Model (CDM)
Machine Model (MM)
1000
V
100
V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
D PACKAGE
DRB PACKAGE
SO-8
SOT23-5
(TOP VIEW)
(TOP VIEW)
NC
Inverting Input
Noninverting Input
-VS
1
2
3
4
8
7
6
5
NC
Output
-VS
1
2
3
5
+VS
+VS
Output
NC
Noninverting Input
4
Inverting Input
BIA
Pin Orientation/Package Marking
2
Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA694
OPA694
www.ti.com
SBOS319G –SEPTEMBER 2004–REVISED JANUARY 2010
ELECTRICAL CHARACTERISTICS: VS = ±5V
Boldface limits are tested at +25°C. At RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted.
OPA694ID, IDBV
MIN/MAX OVER
TYP
TEMPERATURE
0°C to
+70°C( -40°C to
MIN/
MAX
TEST
3)
PARAMETER
AC Performance (see Figure 31)
Small-Signal Bandwidth
TEST CONDITIONS
+25°C
+25°C(2)
+85°C(3)
UNIT
LEVELS(1)
G = +1, VO = 0.5VPP, RF = 430Ω
G = +2, VO = 0.5VPP, RF = 402Ω
G = +5, VO = 0.5VPP, RF = 318Ω
G = +10, VO = 0.5VPP, RF = 178Ω
G = +1, VO = 0.5VPP, RF = 430Ω
1500
690
250
200
90
MHz
MHz
MHz
MHz
MHz
dB
typ
min
min
min
typ
C
B
B
B
C
C
C
B
C
C
C
—
B
B
B
B
B
B
350
200
150
340
180
130
330
160
120
Bandwidth for 0.1dB Gain Flatness
Peaking at a Gain of +1
Large-Signal Bandwidth
Slew Rate
V
O ≤ 0.1VPP, RF = 430Ω
G = +2, VO = 2VPP
G = +2, 2V Step
2
typ
675
1700
0.8
20
MHz
V/ms
ns
typ
1300
1275
1250
min
typ
Rise Time and Fall Time
Settling Time to 0.01%
Settling Time to 0.1%
Harmonic Distortion
G = +2, VO = 0.2V Step
G = +2, VO = 2V Step
G = +2, VO = 2V Step
G = +2, f = 5MHz, VO = 2VPP
RL = 100Ω
ns
typ
13
ns
typ
—
—
xx x 2nd-Harmonic
–68
–92
–72
–93
2.1
22
–63
–87
–69
–88
2.4
24
–62
–85
–67
–86
2.8
26
–61
–83
–66
–84
3.0
28
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
max
max
max
max
max
max
R
L ≥ 500Ω
RL = 100Ω
L ≥ 500Ω
xx x 3rd-Harmonic
R
Input Voltage Noise Density
f > 1MHz
f > 1MHz
Inverting Input Current Noise Density
Noninverting Input Current Noise
Density
f > 1MHz
24
26
28
30
pA/√Hz
max
B
NTSC Differential Gain
VO - 1.4VPP, RL = 150Ω
VO - 1.4VPP, RL = 37.5Ω
0.03
0.05
%
%
°
max
max
typ
C
C
C
C
NTSC Differential Phase
G = +2, VO - 1.4VPP, RL = 150Ω
VO - 1.4VPP, RL = 37.5Ω
0.015
0.16
°
typ
DC PERFORMANCE(4)
Open-Loop Transimpedance
Input Offset Voltage
VO = 0V, RL = 100Ω
VCM = 0V
145
90
65
±3.7
12
60
±4.1
15
kΩ
mV
min
max
max
max
max
max
max
A
A
B
A
B
A
B
±0.5
±3.0
Average Input Offset Voltage Drift
Noninverting Input Bias Current
Average Input Bias Current Drift
Inverting Input Bias Current
Average Input Bias Current Drift
INPUT
VCM = 0V
mV/°C
mA
VCM = 0V
±5
±2
±20
±18
±26
±100
±26
±150
±31
±150
±38
±200
VCM = 0V
nA/°C
mA
VCM = 0V
VCM = 0V
nA/°C
Common-mode Input Voltage(5)
(CMIR)
±2.5
60
±2.3
55
±2.2
53
±2.1
51
V
min
min
A
A
Common-Mode Rejection Ratio
(CMRR)
VCM = 0V
dB
Noninverting Input Impedance
Inverting Input Resistance
280 | | 1.2
30
kΩ | | pF
typ
typ
C
C
Open-Loop
Ω
(1) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
(2) Junction temperature = ambient for +25°C specifications.
(3) Junction temperature = ambient at low temperature limits; junction temperature = ambient +9°C at high temperature limit for over
temperature specifications.
(4) Current is considered positive out of node. VCM is the input common-mode voltage.
(5) Tested < 3dB below minimum specified CMRR at ±CMIR limits.
Copyright © 2004–2010, Texas Instruments Incorporated
3
Product Folder Link(s): OPA694
OPA694
SBOS319G –SEPTEMBER 2004–REVISED JANUARY 2010
www.ti.com
ELECTRICAL CHARACTERISTICS: VS = ±5V (continued)
Boldface limits are tested at +25°C. At RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted.
OPA694ID, IDBV
MIN/MAX OVER
TYP
TEMPERATURE
0°C to
+70°C( -40°C to
MIN/
MAX
TEST
3)
PARAMETER
TEST CONDITIONS
+25°C
+25°C(2)
+85°C(3)
UNIT
LEVELS(1)
OUTPUT
Voltage Output Voltage
No Load
RL = 100Ω
±4
±3.8
±3.1
±60
±3.7
±3.1
±58
±3.6
±3.0
±50
V
V
min
min
min
min
typ
A
A
A
C
C
±3.4
±80
Output Current
VO = 0V
mA
mA
Ω
Short-Circuit Output Current
Closed-Loop Output Impedance
POWER SUPPLY
VO = 0V
±200
0.02
G = +2, f =100kHz
Specified Operating Voltage
Maximum Operating Voltage Range
Minimum Operating Voltage Range
Maximum Quiescent Current
Minimum Quiescent Current
±5
V
V
typ
max
max
max
min
min
C
A
B
A
A
±6.3
±3.5
6.0
±6.3
±3.5
6.2
±6.3
±3.5
6.3
V
VS = ±5V
VS = ±5V
5.8
5.8
mA
mA
5.6
5.3
5.0
Power-Supply Rejection Ratio
(PSRR)
Input-Referred
58
54
52
50
dB
A
THERMAL CHARACTERISTICS
Specification: ID, IDBV
Thermal Resistance, q JA
xx x D xxxx x SO-8
-40 to +85
—
°C
—
typ
—
C
—
C
Junction-to-Ambient
125
°C/W
°C/W
typ
typ
xx x DBV xxx SOT23
150
C
4
Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA694
OPA694
www.ti.com
SBOS319G –SEPTEMBER 2004–REVISED JANUARY 2010
TYPICAL CHARACTERISTICS: VS = ±5V
At RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted.
NONINVERTING SMALL−SIGNAL FREQUENCY RESPONSE
INVERTING SMALL−SIGNAL FREQUENCY RESPONSE
3
3
G = -5V/V
RF = 318W
VO = 0.5VPP
VO = 0.5VPP
RL = 100W
G = +2V/V
0
RL = 100W
0
RF = 402W
G = -1V/V
RF = 430W
-3
-3
-6
-9
-12
-6
G = -10V/V
RF = 500W
-9
G = +10V/V
G = +5V/V
-12
-15
-18
RF = 178W
RF = 318W
G = -2V/V
RF = 402W
See Figure 31
200
See Figure 32
200
0
400
600
800
1000
0
400
600
800
1000
Frequency (MHz)
Frequency (MHz)
Figure 1.
Figure 2.
NONINVERTING LARGE−SIGNAL FREQUENCY RESPONSE
INVERTING LARGE−SIGNAL FREQUENCY RESPONSE
9
9
VO = 1VPP
G = +2V/V
6
3
RF = 402W
6
VO = 4VPP
VO = 2VPP
3
0
0
VO = 1VPP
VO = 2VPP
-3
-6
-9
-12
-3
VO = 7VPP
-6
VO = 7VPP
G = -2V/V
VO = 4VPP
-9
RF = 402W
See Figure 31
200
See Figure 32
-12
0
400
600
800
1000
0
200
400
600
800
1000
Frequency (MHz)
Frequency (MHz)
Figure 3.
Figure 4.
NONINVERTING PULSE RESPONSE
INVERTING PULSE RESPONSE
0.6
0.4
0.2
0
3
2
0.6
0.4
0.2
0
3
2
G = +2V/V
See Figure 31
G = -2V/V
See Figure 32
Large Signal, 5VPP
Left Scale
Large Signal, 5VPP
Left Scale
1
1
Small Signal, 0.5VPP
Right Scale
Small Signal, 0.5VPP
Right Scale
0
0
-0.2
-0.4
-0.6
-1
-2
-3
-1
-2
-3
-0.2
-0.4
-0.6
Time (5ns/div)
Time (5ns/div)
Figure 5.
Figure 6.
Copyright © 2004–2010, Texas Instruments Incorporated
5
Product Folder Link(s): OPA694
OPA694
SBOS319G –SEPTEMBER 2004–REVISED JANUARY 2010
www.ti.com
TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted.
HARMONIC DISTORTION vs
LOAD RESISTANCE
HARMONIC DISTORTION vs
SUPPLY VOLTAGE
-65
-60
-65
-70
-75
-80
G = +2V/V
G = +2V/V
f = 5MHz
RL = 100W
f = 5MHz
-70
VO = 2VPP
VO = 2VPP
-75
2nd Harmonic
3rd Harmonic
2nd Harmonic
-80
-85
3rd Harmonic
-90
-95
See Figure 31
-100
See Figure 31
3.5 4.0
100
1000
4.5
5.0
5.5
6.0
Load Resistance (W)
Supply Voltage (±VS)
Figure 7.
Figure 8.
HARMONIC DISTORTION vs
FREQUENCY
HARMONIC DISTORTION vs
OUTPUT VOLTAGE
-50
-60
-65
-70
-75
-80
-85
G = +2V/V
2nd Harmonic
G = +2V/V
RL = 100W
RL = 100W
f = 5MHz
VO = 2VPP
2nd Harmonic
3rd Harmonic
-70
-80
3rd Harmonic
-90
See Figure 31
0.1
See Figure 31
-100
1
10
20
0.1
1
10
Frequency (MHz)
Output Voltage Swing (VPP
)
Figure 9.
Figure 10.
HARMONIC DISTORTION vs
NONINVERTING GAIN
HARMONIC DISTORTION vs
INVERTING GAIN
-60
-65
-70
-75
-60
-65
-70
-75
RL = 100W
RL = 100W
f = 5MHz
f = 5MHz
VO = 2VPP
VO = 2VPP
2nd Harmonic
3rd Harmonic
2nd Harmonic
3rd Harmonic
See Figure 31
See Figure 32
1
10
1
10
Gain (V/V)
Gain (|V/V|)
Figure 11.
Figure 12.
6
Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA694
OPA694
www.ti.com
SBOS319G –SEPTEMBER 2004–REVISED JANUARY 2010
TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted.
TWO−TONE, THIRD−ORDER
INPUT VOLTAGE AND CURRENT NOISE
INTERMODULATION INTERCEPT
1k
55
50
45
40
35
30
25
20
50W
PI
OPA694
PO
50W
50W
402W
Noninverting Current Noise (24pA/ÖHz)
100
402W
Inverting Current Noise (22pA/ÖHz)
10
Voltage Noise (2.1nV/ÖHz)
1
10
100
1k
10k
100k
1M
10M 100M
0
10
20
30
40
50
60
70
80
90 100
Frequency (Hz)
Frequency (MHz)
Figure 13.
RECOMMENDED RS vs CAPACITIVE LOAD
Figure 14.
FREQUENCY RESPONSE vs CAPACITIVE LOAD
60
50
40
30
20
10
0
3
CL = 10pF
CL = 22pF
0dB Peaking Targeted
0
CL = 100pF
CL = 47pF
-3
-6
RS
VI
OPA694
VO
-9
50W
(1)
CL
1kW
402W
-12
-15
-18
402W
NOTE: (1) 1kW load is optional
10
100
1M
10M
100M
1G
Capacitive Load (pF)
Frequency (Hz)
Figure 15.
Figure 16.
COMMON−MODE REJECTION RATIO AND
POWER−SUPPLY REJECTION RATIO vs FREQUENCY
OPEN−LOOP ZOL GAIN AND PHASE
120
30
70
CMRR
110
100
90
0
60
+PSRR
-30
-60
-90
-120
-150
-180
-210
50
< ZOL
40
80
-PSRR
30
70
20 log |ZOL
|
20
10
0
60
50
40
100
1k
10k
100k
1M
10M
100M
1G
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
Figure 17.
Figure 18.
Copyright © 2004–2010, Texas Instruments Incorporated
7
Product Folder Link(s): OPA694
OPA694
SBOS319G –SEPTEMBER 2004–REVISED JANUARY 2010
www.ti.com
TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted.
VIDEO DIFFERENTIAL GAIN/DIFFERENTIAL PHASE
(No Pulldown)
TYPICAL DC DRIFT OVER TEMPERATURE
1.0
0.5
10
5
0.08
0.06
0.04
0.02
0
0.16
0.12
0.08
0.04
0
dP Positive Video
dG Positive Video
Input Offset Voltage (VOS
)
Left Scale
Inverting Input Bias Current (IBI
)
Right Scale
0
0
Noninverting Input Bias Current (IBN
)
dG Negative Video
Right Scale
-0.5
-5
dP Negative Video
3
-1.0
-10
-50
-25
0
+25
+50
+75
+100 +125
1
2
4
Ambient Temperature (°C)
Video Loads
Figure 19.
Figure 20.
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
4
100
10
1W Internal Power Limit
Sourcing Output Current
Left Scale
3
90
80
70
60
50
40
9
8
7
6
5
4
RL = 100W
2
RL = 50W
Output
1
0
Sinking Output Current
Left Scale
Current
Limit
RL = 25W
Output
Current
Limit
Supply Current
Right Scale
-1
-2
-3
-4
1W Internal Power Limit
100 200
-200
-100
0
-50
-25
0
+25
+50
+75
+100 +125
Output Current (mA)
Ambient Temperature (°C)
Figure 21.
Figure 22.
NONINVERTING OVERDRIVE RECOVERY
INVERTING OVERDRIVE RECOVERY
8
4
4
4
2
4
Input
RL = 100W
G = -1V/V
RL = 100W
Right Scale
G = +2V/V
2
2
Input
Output
Right Scale
Left Scale
0
0
0
0
Output
Left Scale
-4
-8
-2
-4
-2
-4
-2
-4
See Figure 32
See Figure 31
Time (10ns/div)
Time (10ns/div)
Figure 23.
Figure 24.
8
Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA694
OPA694
www.ti.com
SBOS319G –SEPTEMBER 2004–REVISED JANUARY 2010
TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted.
DIFFERENTIAL PERFORMANCE TEST CIRCUIT
DIFFERENTIAL SMALL−SIGNAL FREQUENCY RESPONSE
3
VO = 2VPP
+5V
RL = 400W
0
GD = 1
GD = 2
RF = 430W
OPA694
RF = 402W
-3
-6
RG
RF
RF
VI
RL
GD = 5
VO
RT
RG
400W
RF = 330W
-9
GD = 10
RF = 250W
-12
OPA694
VO
VI
RF
=
RG
0
50 100 150 200 250 300 350 400 450 500
Frequency (MHz)
GD
=
-5V
Figure 25.
Figure 26.
DIFFERENTIAL LARGE−SIGNAL FREQUENCY RESPONSE
DIFFERENTIAL DISTORTION vs LOAD RESISTANCE
-60
9
VO = 4VPP
GD = 2
f = 5MHz
RL = 400W
-65
GD = 2
6
3rd Harmonic
VO = 12VPP
-70
3
-75
-80
0
VO = 5VPP
VO = 16VPP
-3
-85
VO = 8VPP
2nd Harmonic
-90
-6
10
100
1000
0
50 100 150 200 250 300 350 400 450 500
Frequency (MHz)
Resistance (W)
Figure 27.
Figure 28.
DIFFERENTIAL DISTORTION vs FREQUENCY
DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE
-55
-65
GD = 2
GD = 2
VO = 4VPP
RL = 400W
3rd Harmonic
2nd Harmonic
f = 5MHz
-70
RL = 400W
-65
-75
-75
3rd Harmonic
-80
-85
-85
-95
-90
2nd Harmonic
-105
-95
1
10
20
0.1
1
10
100
Frequency (MHz)
Output Voltage Swing (VPP
)
Figure 29.
Figure 30.
Copyright © 2004–2010, Texas Instruments Incorporated
9
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OPA694
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APPLICATION INFORMATION
rate for inverting operation is higher and the distortion
performance is slightly improved. An additional input
resistor, RT, is included in Figure 32 to set the input
impedance equal to 50Ω. The parallel combination of
RT and RG sets the input impedance. Both the
noninverting and inverting applications of Figure 31
and Figure 32 will benefit from optimizing the
feedback resistor (RF) value for bandwidth (see the
discussion in the Setting Resistor Values to Optimize
Bandwidth section). The typical design sequence is to
select the RF value for best bandwidth, set RG for the
gain, then set RT for the desired input impedance. As
the gain increases for the inverting configuration, a
point will be reached where RG will equal 50Ω, where
RT is removed and the input match is set by RG only.
With RG fixed to achieve an input match to 50Ω, RF is
simply increased, to increase gain. This will, however,
quickly reduce the achievable bandwidth, as shown
by the inverting gain of –10 frequency response in the
Typical Characteristic curves. For gains > 10V/V
(14dB at the matched load), noninverting operation is
recommended to maintain broader bandwidth.
WIDEBAND CURRENT FEEDBACK
OPERATION
The OPA694 provides exceptional AC performance
for
a
wideband, low-power, current-feedback
operational amplifier. Requiring only 5.8mA quiescent
current, the OPA694 offers a 690MHz bandwidth at a
gain of +2, along with a 1700V/ms slew rate. An
improved output stage provides ±80mA output drive,
along with < 1.5V output voltage headroom. This
combination of low power and high bandwidth can
benefit high-resolution video applications.
Figure 31 shows the DC-coupled, gain of +2, dual
power-supply circuit configuration used as the basis
of the ±5V Electrical Characteristics table and Typical
Characteristic curves. For test purposes, the input
impedance is set to 50Ω with a resistor to ground and
the output impedance is set to 50Ω with a series
output resistor. Voltage swings reported in the
Electrical Characteristics are taken directly at the
input and output pins, while load powers (dBm) are
defined at a matched 50Ω load. For the circuit of
Figure 31, the total effective load will be 100Ω || 804Ω
= 89Ω. One optional component is included in
Figure 31. In addition to the usual power-supply
decoupling capacitors to ground, a 0.1mF capacitor is
included between the two power-supply pins. In
practical printed circuit board (PCB) layouts, this
optional added capacitor will typically improve the
2nd-harmonic distortion performance by 3dB to 6dB.
+5V
+VS
+
0.1mF
6.8mF
20W
50W Load
50W
VO
OPA694
+5V
+VS
Optional
0.01mF
0.1mF
6.8mF
+
RF
RG
200W
50W Source
50W Source
402W
VI
50W Load
VO 50W
VI
50W
OPA694
RT
66.5W
0.1mF
6.8mF
+
-VS
-5V
0.1mF
RF
402W
Figure 32. DC-Coupled, G = −2V/V,
Bipolar-Supply Specification and Test Circuit
RG
402W
6.8mF
+
0.1mF
-VS
-5V
ADC DRIVER
Figure 31. DC-Coupled, G = +2, Bipolar-Supply
Specification and Test Circuit
Most modern, high-performance analog-to-digital
converters (ADCs) require a low-noise, low-distortion
driver. The OPA694 combines low-voltage noise
(2.1nV/√Hz) with low harmonic distortion. See
Figure 33 for an example of a wideband, AC-coupled,
12-bit ADC driver.
Figure 32 shows the DC-coupled, gain of −2V/V, dual
power-supply circuit used as the basis of the inverting
Typical Characteristic curves. Inverting operation
offers several performance benefits. Since there is no
common-mode signal across the input stage, the slew
10
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SBOS319G –SEPTEMBER 2004–REVISED JANUARY 2010
Two OPA694s are used in the circuit of Figure 33 to
form a differential driver for a 12-bit ADC. The two
OPA694s offer > 250MHz bandwidth at a differential
gain of 5V/V, with a 2VPP output swing. A 2nd-order
RLC filter is used in order to limit the noise from the
amplifier and provide some attenuation for
higher-frequency harmonic distortion.
have been adjusted to maintain both maximum
bandwidth and input impedance matching. If each RF
signal is assumed to be driven from a 50Ω source,
the NG for this circuit will be [1 + 100Ω/(100Ω/5)] = 6.
The total feedback impedance (from VO to the
inverting error current) is the sum of RF + (RI • NG),
where RI is the impedance looking into the inverting
input from the summing junction (see the Setting
Resistor Values to Optimize Performance section).
Using 100Ω feedback (to get a signal gain of –2 from
each input to the output pin) requires an additional
30Ω in series with the inverting input to increase the
feedback impedance. With this resistor added to the
WIDEBAND INVERTING SUMMING
AMPLIFIER
Since the signal bandwidth for a current-feedback op
amp can be controlled independently of the noise
gain (NG, which is normally the same as the
noninverting signal gain), wideband inverting
summing stages may be implemented using the
OPA694. The circuit in Figure 34 shows an example
inverting summing amplifier, where the resistor values
typical internal RI
= 30Ω, the total feedback
impedance is 100Ω + (60Ω • 6) = 460Ω, which is
equal to the required value to get a maximum
bandwidth flat frequency response for NG = 6.
+5V
Power-supply decoupling not shown.
C1
R1
L
25W
OPA694
V+
100W
100W
500W
1:2
C
R2
VI
50W
12-Bit
ADC
VCM
500W
0.1mF
R2
C1
Single-to-Differential
Gain of 10
R1
L
V-
OPA694
25W
-5V
Figure 33. Wideband, AC-Coupled, Low-Power ADC Driver
+5V
50W
V1
V2
50W
VO = -(V1 + V2 + V3 + V4 + V5)
50W
50W
50W
50W
OPA694
RG-58
50W
30W
V3
V4
V5
100W
100MHz, -1dB Compression = 15dBm
-5V
Figure 34. 200MHz RF Summing Amplifier
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SAW FILTER BUFFER
small-signal frequency response for the unity gain
buffer of Figure 31 compared to the improved
approach shown in Figure 36. Either approach gives
One common requirement in an IF strip is to buffer
the output of a mixer with enough gain to recover the
insertion loss of a narrowband SAW filter. Figure 35
shows one possible configuration driving a SAW filter.
The Two-Tone, Third-Order Intermodulation Intercept
plot (Figure 14) is shown in the Typical
Characteristics curves. Operating in the inverting
mode at a voltage gain of –8V/V, this circuit provides
a 50Ω input match using the gain set resistor, has the
feedback optimized for maximum bandwidth (250MHz
in this case), and drives through a 50Ω output resistor
into the matching network at the input of the SAW
filter. If the SAW filter gives a 12dB insertion loss, a
net gain of 0dB to the 50Ω load at the output of the
SAW (which could be the input impedance of the next
IF amplifier or mixer) will be delivered in the
passband of the SAW filter. Using the OPA694 in this
application will isolate the first mixer from the
impedance of the SAW filter and provide very low
two-tone, 3rd-order spurious levels in the SAW filter
bandwidth.
a
low-power unity-gain buffer with
>
1.56GHz
bandwidth.
+5V
RO
50W
VO
OPA694
RG
RF
430W
430W
VI
RM
50W
-5V
Figure 36. Improve Unity Gain Buffer
3
0
G = +1, Figure 1
+12V
G = +1, Figure 6
5kW
-3
-6
-9
-12
50W
Matching
Network
PO
50W
OPA694
1000pF
0.1mF
5kW
SAW
Filter
50W
Source
1000pF 50W
400W
PO
PI
= 12dB - (SAW Loss)
PI
10M
100M
1G
3G
Figure 35. IF Amplifier Driving SAW Filter
Frequency (Hz)
Figure 37. Gain of +1 Frequency Response
WIDEBAND UNITY GAIN BUFFER WITH
IMPROVED FLATNESS
DESIGN-IN TOOLS
The unity gain buffer configuration of Figure 31
shows peaking in the frequency response
exceeding 2dB. This gives the slight amount of
overshoot and ringing apparent in the gain of +1V/V
pulse response curves. A similar circuit that holds a
flatter frequency response, giving improved pulse
fidelity, is shown in Figure 36.
a
DEMONSTRATION FIXTURES
Two printed circuit boards (PCBs) are available to
assist in the initial evaluation of circuit performance
using the OPA694 in its two package options. Both of
these are offered free of charge as unpopulated
PCBs, delivered with a user’s guide. The summary
information for these fixtures is shown in Table 1.
This circuit removes the peaking by bootstrapping out
any parasitic effects on RG. The input impedance is
still set by RM as the apparent impedance looking into
RG is very high. RM may be increased to show a
higher input impedance, but larger values will start to
impact DC output offset voltage. This circuit creates
an additional input offset voltage as the difference in
the two input bias currents times the impedance to
ground at VI. Figure 37 shows a comparison of
Table 1. Demonstration Fixtures by Package
ORDERING
NUMBER
LITERATURE
NUMBER
PRODUCT
PACKAGE
DEM-OPA-
SO-1B
OPA694ID
SO-8
SBOU026
SBOU027
DEM-OPA-
SOT-1B
OPA694IDBV
SOT23-5
12
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The demonstration fixtures can be requested at the
Texas Instruments web site (www.ti.com) through the
OPA694 product folder.
The key elements of this current-feedback op amp
model are:
a → Buffer gain from the noninverting input to the
inverting input
RI → Buffer output impedance
MACROMODELS AND APPLICATIONS SUPPORT
Computer simulation of circuit performance using
SPICE is often useful when analyzing the
performance of analog circuits and systems. This is
particularly true for video and RF amplifier circuits
where parasitic capacitance and inductance can have
a major effect on circuit performance. A SPICE model
for the OPA694 is available through the TI web site
(www.ti.com). These models do a good job of
predicting small-signal AC and transient performance
under a wide variety of operating conditions. They do
not do as well in predicting the harmonic distortion or
dG/df characteristics. These models do not attempt
to distinguish between package types in their
small-signal AC performance.
i
ERR → Feedback error current signal
Z(s) Frequency-dependent,
transimpedance gain from iERR to VO
→
open-loop
The buffer gain is typically very close to 1.00 and is
normally neglected from signal gain considerations. It
will, however, set the CMRR for a single op amp
differential amplifier configuration.
For a buffer gain a < 1.0, the CMRR = –20 × log (1–
a) dB.
RI, the buffer output impedance, is a critical portion of
the bandwidth control equation. RI for the OPA694 is
typically about 30Ω.
A current-feedback op amp senses an error current in
the inverting node (as opposed to a differential input
error voltage for a voltage-feedback op amp) and
passes this on to the output through an internal
frequency dependent transimpedance gain. The
Typical Characteristics show this open-loop
transimpedance response. This is analogous to the
open-loop voltage gain curve for a voltage-feedback
op amp. Developing the transfer function for the
circuit of Figure 38 gives Equation 1:
OPERATING SUGGESTIONS
space
SETTING RESISTOR VALUES TO OPTIMIZE
BANDWIDTH
A current-feedback op amp like the OPA694 can hold
an almost constant bandwidth over signal gain
settings with the proper adjustment of the external
resistor values. This is shown in the Typical
Characteristic curves; the small-signal bandwidth
decreases only slightly with increasing gain. Those
curves also show that the feedback resistor has been
changed for each gain setting. The resistor values on
the inverting side of the circuit for a current-feedback
op amp can be treated as frequency response
compensation elements while their ratios set the
signal gain. Figure 38 shows the small-signal
frequency response analysis circuit for the OPA694.
RF
a 1 +
(
(
RG
VO
VI
aNG
=
=
RF + RI·NG
RF
1 +
RF + RI
(
Z(s)
(
RG
Z(s)
1 +
(1)
where:
NG = 1 +
RF
(
(
RG
This is written in a loop-gain analysis format, where
the errors arising from a noninfinite open-loop gain
are shown in the denominator. If Z(s) were infinite
over all frequencies, the denominator of Equation 1
would reduce to 1 and the ideal desired signal gain
shown in the numerator would be achieved. The
fraction in the denominator of Equation 1 determines
the frequency response. Equation 2 shows this as the
loop-gain equation:
VI
a
VO
RI
Z(S) iERR
iERR
RF
Z(s)
= Loop Gain
RG
RF + RI·NG
(2)
If 20 × log(RF + NG × RI) were drawn on top of the
open-loop transimpedance plot, the difference
between the two would be the loop gain at a given
frequency. Eventually, Z(s) rolls off to equal the
denominator of Equation 2, at which point the loop
Figure 38. Recommended Feedback Resistor
Versus Noise Gain
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gain reduces to 1 (and the curves intersect). This
point of equality is where the amplifier closed-loop
frequency response given by Equation 1 starts to roll
off, and is exactly analogous to the frequency at
which the noise gain equals the open-loop voltage
gain for a voltage-feedback op amp. The difference
here is that the total impedance in the denominator of
Equation 2 may be controlled somewhat separately
from the desired signal gain (or NG).
bandwidth. Inserting a series resistor between the
inverting input and the summing junction will increase
the feedback impedance (denominator of Equation 1),
decreasing the bandwidth. This approach to
bandwidth control is used for the inverting summing
circuit on the front page. The internal buffer output
impedance for the OPA694 is slightly influenced by
the source impedance looking out of the noninverting
input terminal. High source resistors will have the
effect of increasing RI, decreasing the bandwidth.
The OPA694 is internally compensated to give a
maximally flat frequency response for RF = 402Ω at
NG = 2 on ±5V supplies. Evaluating the denominator
of Equation 2 (which is the feedback transimpedance)
gives an optimal target of 462Ω. As the signal gain
changes, the contribution of the NG × RI term in the
feedback transimpedance will change, but the total
can be held constant by adjusting RF. Equation 3
gives an approximate equation for optimum RF over
signal gain:
OUTPUT CURRENT AND VOLTAGE
The OPA694 provides output voltage and current
capabilities that are not usually found in wideband
amplifiers. Under no-load conditions at +25°C, the
output voltage typically swings closer than 1.2V to
either supply rail; the +25°C swing limit is within 1.2V
of either rail. Into a 15Ω load (the minimum tested
load), it is tested to deliver more than ±60mA.
RF = 462W - NG · RI
(3)
The specifications described above, though familiar in
the industry, consider voltage and current limits
separately. In many applications, it is the (voltage ×
current), or V-I product, which is more relevant to
circuit operation. Refer to the Output Voltage and
Current Limitations plot (Figure 21) in the Typical
Characteristics. The X and Y axes of this graph show
the zero-voltage output current limit and the
zero-current output voltage limit, respectively. The
four quadrants give a more detailed view of the
OPA694 output drive capabilities, noting that the
graph is bounded by a Safe Operating Area of 1W
maximum internal power dissipation. Superimposing
resistor load lines onto the plot shows that the
OPA694 can drive ±2.5V into 25Ω or ±3.5V into 50Ω
without exceeding the output capabilities or the 1W
dissipation limit. A 100Ω load line (the standard test
circuit load) shows the full ±3.4V output swing
capability, as shown in the Electrical Characteristics.
As the desired signal gain increases, this equation
will eventually predict a negative RF. A somewhat
subjective limit to this adjustment can also be set by
holding RG to a minimum value of 20Ω. Lower values
will load both the buffer stage at the input and the
output stage, if RF gets too low, actually decreasing
the bandwidth. Figure 39 shows the recommended
RF versus NG for ±5V operation. The values for RF
versus gain shown here are approximately equal to
the values used to generate the Typical
Characteristics. They differ in that the optimized
values used in the Typical Characteristics are also
correcting for board parasitics not considered in the
simplified analysis leading to Equation 2. The values
shown in Figure 39 give a good starting point for
design where bandwidth optimization is desired.
450
400
350
300
250
200
150
The minimum specified output voltage and current
over-temperature are set by worst-case simulations at
the cold temperature extreme. Only at cold startup
will the output current and voltage decrease to the
numbers shown in the Electrical Characteristic tables.
As the output transistors deliver power, the junction
temperatures will increase, decreasing both VBE
(increasing the available output voltage swing) and
increasing the current gains (increasing the available
output current). In steady-state operation, the
available output voltage and current will always be
greater than that shown in the over-temperature
specifications, since the output stage junction
temperatures will be higher than the minimum
specified operating ambient.
0
5
10
15
20
Noise Gain
Figure 39. Feedback Resistor vs Noise Gain
The total impedance going into the inverting input
may be used to adjust the closed-loop signal
14
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DRIVING CAPACITIVE LOADS
a little less than the expected 2x rate, while the
3rd-harmonic increases at a little less than the
expected 3x rate. Where the test power doubles, the
2nd-harmonic increases by less than the expected
6dB, while the 3rd-harmonic increases by less than
the expected 12dB. This also shows up in the
two-tone, third-order intermodulation spurious (IM3)
response curves. The 3rd-order spurious levels are
extremely low at low output power levels. The output
stage continues to hold them low even as the
fundamental power reaches very high levels. As the
One of the most demanding and yet very common
load conditions for an op amp is capacitive loading.
Often, the capacitive load is the input of an
ADC—including additional external capacitance that
may be recommended to improve ADC linearity. A
high-speed, high open-loop gain amplifier like the
OPA694 can be very susceptible to decreased
stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin.
When the amplifier open−loop output resistance is
considered, this capacitive load introduces an
additional pole in the signal path that can decrease
the phase margin. Several external solutions to this
problem have been suggested. When the primary
considerations are frequency response flatness,
pulse response fidelity, and/or distortion, the simplest
and most effective solution is to isolate the capacitive
load from the feedback loop by inserting a series
isolation resistor between the amplifier output and the
capacitive load. This does not eliminate the pole from
the loop response, but rather shifts it and adds a zero
at a higher frequency. The additional zero acts to
cancel the phase lag from the capacitive load pole,
thus increasing the phase margin and improving
stability.
Typical
Characteristics
show,
the
spurious
intermodulation powers do not increase as predicted
by a traditional intercept model. As the fundamental
power level increases, the dynamic range does not
decrease significantly.
NOISE PERFORMANCE
Wideband, current-feedback op amps generally have
a
higher
output
noise
than
comparable
voltage-feedback op amps. The OPA694 offers an
excellent balance between voltage and current noise
terms to achieve low output noise. The inverting
current noise (24pA/√Hz) is significantly lower than
earlier solutions, while the input voltage noise
(2.1nV/√Hz) is lower than most unity-gain stable,
wideband, voltage-feedback op amps. This low input
voltage noise was achieved at the price of higher
noninverting input current noise (22pA/√Hz). As long
as the AC source impedance looking out of the
noninverting node is less than 100Ω, this current
noise will not contribute significantly to the total
output noise. The op amp input voltage noise and the
two input current noise terms combine to give low
output noise under a wide variety of operating
conditions. Figure 40 shows the op amp noise
analysis model with all the noise terms included. In
this model, all noise terms are taken to be noise
voltage or current density terms in either nV/√Hz or
pA/√Hz.
The Typical Characteristics show the recommended
RS vs Capacitive Load (Figure 15) and the resulting
frequency response at the load. Parasitic capacitive
loads greater than 2pF can begin to degrade the
performance of the OPA694. Long PCB traces,
unmatched cables, and connections to multiple
devices can easily cause this value to be exceeded.
Always consider this effect carefully, and add the
recommended series resistor as close as possible to
the OPA694 output pin (see the Board Layout
Guidelines section).
DISTORTION PERFORMANCE
The OPA694 provides good distortion performance
into a 100Ω load on ±5V supplies. Generally, until the
fundamental signal reaches very high frequency or
power levels, the 2nd-harmonic will dominate the
distortion with a negligible 3rd-harmonic component.
Focusing then on the 2nd-harmonic, increasing the
load impedance improves distortion directly.
Remember that the total load includes the feedback
network—in the noninverting configuration (see
Figure 31), this is the sum of RF + RG, while in the
inverting configuration it is just RF. Also, providing an
additional supply decoupling capacitor (0.1mF)
between the supply pins (for bipolar operation)
improves the 2nd-order distortion slightly (3dB to
6dB).
ENI
EO
OPA694
RS
IBN
ERS
RF
Ö
4kTRS
Ö
4kTRF
IBI
RG
4kT
RG
-20
4kT = 1.6 ´ 10
J
at 290K
In most op amps, increasing the output voltage swing
increases harmonic distortion directly. The Typical
Characteristics show the 2nd-harmonic increasing at
Figure 40. Op Amp Noise Analysis Model
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The total output spot noise voltage can be computed
as the square root of the sum of all squared output
noise voltage contributors. Equation 4 shows the
general form for the output noise voltage using the
terms shown in Figure 40.
xx = ±(2 × 3mV) ± (20mA × 25Ω × 2) ± (402Ω × 18mA)
xx = ±6mV + 1mV ±7.24mV = ±14.24mV
A fine-scale, output offset null, or DC operating point
adjustment, is sometimes required. Numerous
techniques are available for introducing DC offset
control into an op amp circuit. Most simple
adjustment techniques do not correct for temperature
drift. It is possible to combine a lower speed,
precision op amp with the OPA694 to get the DC
accuracy of the precision op amp along with the
signal bandwidth of the OPA694. Figure 41 shows a
noninverting G = +10 circuit that holds an output
offset voltage less than ±7.5mV over-temperature
with > 150MHz signal bandwidth.
EO = ENI2 + (IBNRS)2 + 4kTRS NG2 + (IBIRF)2 + 4kTRFNG
(
(
(4)
Dividing this expression by the noise gain [NG = (1 +
RF/RG)] will give the equivalent input-referred spot
noise voltage at the noninverting input, as shown in
Equation 5.
2
4kTRF
NG
IBIRF
NG
EN = ENI2 + (IBNRS)2 + 4kTRS +
+
(
(
(5)
+5V
Power-supply
decoupling not shown.
VI
Evaluating these two equations for the OPA694
circuit and component values (see Figure 31) gives a
total output spot noise voltage of 11.2nV/√Hz and a
total equivalent input spot noise voltage of 5.6nV/√Hz.
This total input-referred spot noise voltage is higher
than the 2.1nV/√Hz specification for the op amp
voltage noise alone. This reflects the noise added to
the output by the inverting current noise times the
feedback resistor. If the feedback resistor is reduced
in high-gain configurations (as suggested previously),
the total input-referred voltage noise given by
Equation 5 will approach just the 2.1nV/√Hz of the op
amp itself. For example, going to a gain of +10 using
RF = 178Ω will give a total input-referred noise of
2.36nV/√Hz.
VO
OPA694
1.8kW
+5V
-5V
180W
2.86kW
18kW
OPA237
20W
-5V
2kW
Figure 41. Wideband, DC-Connected Composite
Circuit
DC ACCURACY AND OFFSET CONTROL
A current-feedback op amp like the OPA694 provides
exceptional bandwidth in high gains, giving fast pulse
settling, but only moderate DC accuracy. The
Electrical Characteristics show an input offset voltage
This DC-coupled circuit provides very high signal
bandwidth using the OPA694. At lower frequencies,
the output voltage is attenuated by the signal gain
and compared to the original input voltage at the
inputs of the OPA237 (this is a low-cost, precision
voltage-feedback op amp with 1.5MHz gain
bandwidth product). If these two do not agree (due to
DC offsets introduced by the OPA694), the OPA237
sums in a correction current through the 2.86kΩ
comparable
to
high-speed,
voltage-feedback
amplifiers. However, the two input bias currents are
somewhat higher and are unmatched. Whereas bias
current cancellation techniques are very effective with
most voltage-feedback op amps, they do not
generally reduce the output DC offset for wideband,
current-feedback op amps. Since the two input bias
currents are unrelated in both magnitude and polarity,
matching the source impedance looking out of each
input to reduce their error contribution to the output is
ineffective. Evaluating the configuration of Figure 31,
using worst-case +25°C input offset voltage and the
two input bias currents, gives a worst-case output
offset range equal to:
inverting
summing
path.
Several
design
considerations will allow this circuit to be optimized.
First, the feedback to the OPA237 noninverting input
must be precisely matched to the high-speed signal
gain. Making the 2kΩ resistor to ground an adjustable
resistor would allow the low- and high-frequency
gains to be precisely matched. Second, the crossover
frequency region where the OPA237 passes control
to the OPA694 must occur with exceptional phase
linearity. These two issues reduce to designing for
pole/zero cancellation in the overall transfer function.
Using the 2.86kΩ resistor will nominally satisfy this
±(NG × VOS) ± (IBN × RS/2 × NG) ± (IBI × RF)
where NG = noninverting signal gain
space
space
16
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requirement for the circuit in Figure 41. Perfect
cancellation over process and temperature is not
possible. However, this initial resistor setting and
precise gain matching will minimize long-term pulse
settling tails.
BOARD LAYOUT GUIDELINES
Achieving
optimum
performance
with
a
high-frequency amplifier like the OPA694 requires
careful attention to board layout parasitics and
external component types. Recommendations that
will optimize performance include:
THERMAL ANALYSIS
a) Minimize parasitic capacitance to any AC ground
for all of the signal I/O pins. Parasitic capacitance on
the output and inverting input pins can cause
instability: on the noninverting input, it can react with
the source impedance to cause unintentional
bandlimiting. To reduce unwanted capacitance, a
window around the signal I/O pins should be opened
in all of the ground and power planes around those
pins. Otherwise, ground and power planes should be
unbroken elsewhere on the board.
Due to the high output power capability of the
OPA694, heatsinking or forced airflow may be
required under extreme operating conditions.
Maximum desired junction temperature will set the
maximum allowed internal power dissipation, as
described below. In no case should the maximum
junction temperature be allowed to exceed +150°C.
Operating junction temperature (TJ) is given by TA +
PD × qJA. The total internal power dissipation (PD) is
the sum of quiescent power (PDQ) and additional
power dissipated in the output stage (PDL) to deliver
load power. Quiescent power is simply the specified
no-load supply current times the total supply voltage
across the part. PDL will depend on the required
output signal and load but would, for a grounded
resistive load, be at a maximum when the output is
fixed at a voltage equal to 1/2 either supply voltage
(for equal bipolar supplies). Under this condition PDL
= VS 2/(4 × RL) where RL includes feedback network
loading.
b) Minimize the distance (< 0.25in, or 0.635cm)
from the power-supply pins to high-frequency 0.1mF
decoupling capacitors. At the device pins, the ground
and power plane layout should not be in close
proximity to the signal I/O pins. Avoid narrow power
and ground traces to minimize inductance between
the pins and the decoupling capacitors. The
power-supply connections (on pins 4 and 7) should
always be decoupled with these capacitors. An
optional supply decoupling capacitor across the two
power supplies (for bipolar operation) will improve
2nd-harmonic distortion performance. Larger (2.2mF
to 6.8mF) decoupling capacitors, effective at lower
frequencies, should also be used on the main supply
pins. These may be placed somewhat farther from
the device and may be shared among several
devices in the same area of the PCB.
Note that it is the power in the output stage and not in
the load that determines internal power dissipation.
As a worst-case example, compute the maximum TJ
using an OPA694IDBV (SOT23-5 package) in the
circuit of Figure 31 operating at the maximum
specified ambient temperature of +85°C and driving a
grounded 20Ω load to +2.5V DC:
c) Careful selection and placement of external
components will preserve the high-frequency
performance of the OPA694. Resistors should be a
very low reactance type. Surface-mount resistors
work best and allow a tighter overall layout. Metal-film
and carbon composition, axially-leaded resistors can
also provide good high-frequency performance.
Again, keep their leads and PCB trace length as short
as possible. Never use wirewound type resistors in a
high-frequency application. Since the output pin and
inverting input pin are the most sensitive to parasitic
capacitance, always position the feedback and series
output resistor, if any, as close as possible to the
output pin. Other network components, such as
noninverting input termination resistors, should also
be placed close to the package. Where double-side
component mounting is allowed, place the feedback
resistor directly under the package on the other side
of the board between the output and inverting input
pins. The frequency response is primarily determined
by the feedback resistor value, as described
previously. Increasing its value will reduce the
bandwidth, while decreasing it will give a more
peaked frequency response. The 402Ω feedback
PD = 10V × 6.0mA + 52/[4 × (20Ω || 804Ω)] = 380mΩ
Maximum TJ = +85°C + (0.38W × (150°C/W) = 142°C
Although this is still below the specified maximum
junction temperature, system reliability considerations
may require lower junction temperatures. Remember,
this is a worst-case internal power dissipation—use
your actual signal and load to compute PDL. The
highest possible internal dissipation will occur if the
load requires current to be forced into the output for
positive output voltages or sourced from the output
for negative output voltages. This puts a high current
through a large internal voltage drop in the output
transistors. The Output Voltage and Current
Limitations plot (Figure 21) shown in the Typical
Characteristics includes a boundary for 1W maximum
internal power dissipation under these conditions.
space
space
space
Copyright © 2004–2010, Texas Instruments Incorporated
17
Product Folder Link(s): OPA694
OPA694
SBOS319G –SEPTEMBER 2004–REVISED JANUARY 2010
www.ti.com
resistor used in the Electrical Characteristic tables at
a gain of +2 on ±5V supplies is a good starting point
for design. Note that a 430Ω feedback resistor, rather
than a direct short, is recommended for the unity-gain
follower application. A current-feedback op amp
requires a feedback resistor even in the unity-gain
follower configuration to control stability.
trace as a capacitive load in this case and set the
series resistor value as shown in the plot of
Recommended RS vs Capacitive Load. This will not
preserve
signal
integrity
as
well
as
a
doubly-terminated line. If the input impedance of the
destination device is low, there will be some signal
attenuation due to the voltage divider formed by the
series output into the terminating impedance.
d) Connections to other wideband devices on the
board may be made with short, direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to the
next device as a lumped capacitive load. Relatively
wide traces (50mils to 100mils, or 1,270mm to
2,540mm) should be used, preferably with ground
and power planes opened up around them. Estimate
the total capacitive load and set RS from the plot of
Recommended RS vs Capacitive Load (Figure 15).
Low parasitic capacitive loads (< 5pF) may not need
an RS, since the OPA694 is nominally compensated
to operate with a 2pF parasitic load. If a long trace is
required, and the 6dB signal loss intrinsic to a
doubly-terminated transmission line is acceptable,
implement a matched impedance transmission line
using microstrip or stripline techniques (consult an
ECL design handbook for microstrip and stripline
layout techniques). A 50Ω environment is normally
e) Socketing a high-speed part like the OPA694 is
not recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket can
create an extremely troublesome parasitic network
which can make it almost impossible to achieve a
smooth, stable frequency response. Best results are
obtained by soldering the OPA694 onto the board..
The additional lead length and pin-to-pin capacitance
introduced by the socket can create an extremely
troublesome parasitic network which can make it
almost impossible to achieve a smooth, stable
frequency response. Best results are obtained by
soldering the OPA694 onto the board.
INPUT AND ESD PROTECTION
The OPA694 is built using a very high speed
complementary bipolar process. The internal junction
breakdown voltages are relatively low for these very
small geometry devices. These breakdowns are
reflected in the Absolute Maximum Ratings table. All
device pins have limited ESD protection using internal
diodes to the power supplies, as shown in Figure 42.
not necessary onboard, and in fact,
a higher
impedance environment will improve distortion, as
shown in the Distortion versus Load plots. With a
characteristic board trace impedance defined based
on board material and trace dimensions, a matching
series resistor into the trace from the output of the
OPA694 is used as well as a terminating shunt
resistor at the input of the destination device.
Remember also that the terminating impedance will
be the parallel combination of the shunt resistor and
the input impedance of the destination device: this
total effective impedance should be set to match the
trace impedance. The high output voltage and current
capability of the OPA694 allows multiple destination
devices to be handled as separate transmission lines,
each with their own series and shunt terminations. If
These diodes provide moderate protection to input
overdrive voltages above the supplies as well. The
protection diodes can typically support 30mA
continuous current. Where higher currents are
possible (for example, in systems with ±15V supply
parts driving into the OPA694), current-limiting series
resistors should be added into the two inputs. Keep
these resistor values as low as possible, since high
values degrade both noise performance and
frequency response.
the 6dB attenuation of
a
doubly-terminated
transmission line is unacceptable, a long trace can be
series-terminated at the source end only. Treat the
+VCC
Internal
Circuitry
External
Pin
-VCC
Figure 42. Internal ESD Protection
18
Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA694
OPA694
www.ti.com
SBOS319G –SEPTEMBER 2004–REVISED JANUARY 2010
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (August, 2008) to Revision G
Page
•
•
•
•
•
•
•
Updated document format to current standards ................................................................................................................... 1
Deleted lead temperature specifications from Absolute Maximum Ratings table ................................................................ 2
Revised ADC Driver section to remove references to TI ADS522x devices ...................................................................... 10
Changed Figure 33 ............................................................................................................................................................. 11
Updated Figure 34 .............................................................................................................................................................. 11
Changed Figure 36 ............................................................................................................................................................. 12
Updated Figure 41 .............................................................................................................................................................. 16
REVISION HISTORY
Changes from Revision E (March, 2006) to Revision F
Page
•
Changed Storage Temperature minimum value from −40°C to −65°C ................................................................................ 2
Copyright © 2004–2010, Texas Instruments Incorporated
19
Product Folder Link(s): OPA694
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA694ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
694
Samples
OPA694IDBVR
OPA694IDBVT
OPA694IDG4
ACTIVE
ACTIVE
LIFEBUY
SOT-23
SOT-23
SOIC
DBV
DBV
D
5
5
8
3000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
BIA
Samples
Samples
250
75
RoHS & Green
RoHS & Green
BIA
OPA
694
OPA694IDR
ACTIVE
SOIC
SOIC
D
D
8
8
2500 RoHS & Green
2500 RoHS & Green
NIPDAU
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
OPA
694
Samples
OPA694IDRG4
LIFEBUY
OPA
694
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2023
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA694IDBVR
OPA694IDBVT
OPA694IDR
SOT-23
SOT-23
SOIC
DBV
DBV
D
5
5
8
3000
250
180.0
180.0
330.0
8.4
8.4
3.15
3.15
6.4
3.1
3.1
5.2
1.55
1.55
2.1
4.0
4.0
8.0
8.0
8.0
Q3
Q3
Q1
2500
12.4
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA694IDBVR
OPA694IDBVT
OPA694IDR
SOT-23
SOT-23
SOIC
DBV
DBV
D
5
5
8
3000
250
210.0
210.0
356.0
185.0
185.0
356.0
35.0
35.0
35.0
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
OPA694ID
D
D
SOIC
SOIC
8
8
75
75
506.6
506.6
8
8
3940
3940
4.32
4.32
OPA694IDG4
Pack Materials-Page 3
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated
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