OMAPL137DZKB3 [TI]
OMAP-L137 Low-Power Applications Processor;
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SPRS563F –SEPTEMBER 2008–REVISED FEBRUARY 2013
OMAP-L137 Low-Power Applications Processor
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1 OMAP-L137 Low-Power Applications Processor
1.1 Features
1234
– 8K-Byte RAM (Vector Table)
• Highlights
– 64K-Byte ROM
– Dual Core SoC
• C674x Instruction Set Features
•
•
375/456-MHz ARM926EJ-S™ RISC MPU
375/456-MHz C674x VLIW DSP
– Superset of the C67x+™ and C64x+™ ISAs
– Up to 3648/2736 C674x MIPS/MFLOPS
– Byte-Addressable (8-/16-/32-/64-Bit Data)
– 8-Bit Overflow Protection
– TMS320C674x Fixed/Floating-Point VLIW
DSP Core
– Enhanced Direct-Memory-Access Controller
3 (EDMA3)
– Bit-Field Extract, Set, Clear
– 128K-Byte RAM Shared Memory
– Two External Memory Interfaces
– Normalization, Saturation, Bit-Counting
– Compact 16-Bit Instructions
– Three Configurable 16550 type UART
Modules
– LCD Controller
• C674x Two Level Cache Memory Architecture
– 32K-Byte L1P Program RAM/Cache
– 32K-Byte L1D Data RAM/Cache
– Two Serial Peripheral Interfaces (SPI)
– Multimedia Card (MMC)/Secure Digital (SD)
– Two Master/Slave Inter-Integrated Circuit
– One Host-Port Interface (HPI)
– 256K-Byte L2 Unified Mapped RAM/Cache
– Flexible RAM/Cache Partition (L1 and L2)
• Enhanced Direct-Memory-Access Controller 3
(EDMA3):
– USB 1.1 OHCI (Host) With Integrated PHY
(USB1)
• Applications
– 2 Transfer Controllers
– 32 Independent DMA Channels
– 8 Quick DMA Channels
– Industrial Diagnostics
– Test and measurement
– Military Sonar/ Radar
– Programmable Transfer Burst Size
• TMS320C674x Fixed/Floating-Point VLIW DSP
Core
– Medical measurement
– Professional Audio
– Load-Store Architecture With Non-Aligned
Support
• Software Support
– 64 General-Purpose Registers (32 Bit)
– Six ALU (32-/40-Bit) Functional Units
– TI DSP/BIOS™
– Chip Support Library and DSP Library
• Dual Core SoC
– 375/456-MHz ARM926EJ-S™ RISC MPU
– 375/456-MHz C674x VLIW DSP
• ARM926EJ-S Core
•
Supports 32-Bit Integer, SP (IEEE Single
Precision/32-Bit) and DP (IEEE Double
Precision/64-Bit) Floating Point
Supports up to Four SP Additions Per
Clock, Four DP Additions Every 2 Clocks
Supports up to Two Floating Point (SP or
DP) Reciprocal Approximation (RCPxP)
and Square-Root Reciprocal
Approximation (RSQRxP) Operations Per
Cycle
•
•
– 32-Bit and 16-Bit (Thumb®) Instructions
– DSP Instruction Extensions
– Single Cycle MAC
– ARM™ Jazelle® Technology
– EmbeddedICE-RT™ for Real-Time Debug
• ARM9 Memory Architecture
– 16K-Byte Instruction Cache
– 16K-Byte Data Cache
– Two Multiply Functional Units
•
Mixed-Precision IEEE Floating Point
Multiply Supported up to:
–
–
2 SP x SP -> SP Per Clock
2 SP x SP -> DP Every Two Clocks
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DSP/BIOS, TMS320C6000, C6000 are trademarks of Texas Instruments.
ARM926EJ-S, ETM9, CoreSight are trademarks of ARM Limited.
All other trademarks are the property of their respective owners.
2
3
4
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated
OMAP-L137
SPRS563F –SEPTEMBER 2008–REVISED FEBRUARY 2013
www.ti.com
–
–
2 SP x DP -> DP Every Three Clocks
2 DP x DP -> DP Every Four Clocks
•
Entire subsystem under a single PSC
clock gating domain
– Dedicated interrupt controller
– Dedicated switched central resource
•
Fixed Point Multiply Supports Two 32 x
32-Bit Multiplies, Four 16 x 16-Bit
Multiplies, or Eight 8 x 8-Bit Multiplies per
Clock Cycle, and Complex Multiples
• USB 1.1 OHCI (Host) With Integrated PHY
(USB1)
– Instruction Packing Reduces Code Size
– All Instructions Conditional
– Hardware Support for Modulo Loop
Operation
– Protected Mode Operation
– Exceptions Support for Error Detection and
Program Redirection
• USB 2.0 OTG Port With Integrated PHY (USB0)
– USB 2.0 High-/Full-Speed Client
– USB 2.0 High-/Full-/Low-Speed Host
– End Point 0 (Control)
– End Points 1,2,3,4 (Control, Bulk, Interrupt or
ISOC) Rx and Tx
• Three Multichannel Audio Serial Ports:
– Six Clock Zones and 28 Serial Data Pins
– Supports TDM, I2S, and Similar Formats
– DIT-Capable (McASP2)
– FIFO buffers for Transmit and Receive
• 10/100 Mb/s Ethernet MAC (EMAC):
– IEEE 802.3 Compliant (3.3-V I/O Only)
– RMII Media Independent Interface
– Management Data I/O (MDIO) Module
• Real-Time Clock With 32 KHz Oscillator and
Separate Power Rail
• One 64-Bit General-Purpose Timer
(Configurable as Two 32-Bit Timers)
• 128K-Byte RAM Shared Memory
• 3.3V LVCMOS IOs (except for USB interfaces)
• Two External Memory Interfaces:
– EMIFA
•
•
•
NOR (8-/16-Bit-Wide Data)
NAND (8-/16-Bit-Wide Data)
16-Bit SDRAM With 128MB Address
Space
– EMIFB
32-Bit or 16-Bit SDRAM With 256MB
Address Space
•
• Three Configurable 16550 type UART Modules:
– UART0 With Modem Control Signals
• One 64-bit General-Purpose/Watchdog Timer
(Configurable as Two 32-bit General-Purpose
Timers)
– Autoflow control signals (CTS, RTS) on
UART0 only
– 16-byte FIFO
– 16x or 13x Oversampling Option
• LCD Controller
• Two Serial Peripheral Interfaces (SPI) Each
With One Chip-Select
• Multimedia Card (MMC)/Secure Digital (SD)
Card Interface with Secure Data I/O (SDIO)
• Two Master/Slave Inter-Integrated Circuit (I2C
Bus™)
• Three Enhanced Pulse Width Modulators
(eHRPWM):
– Dedicated 16-Bit Time-Base Counter With
Period And Frequency Control
– 6 Single Edge, 6 Dual Edge Symmetric or 3
Dual Edge Asymmetric Outputs
– Dead-Band Generation
– PWM Chopping by High-Frequency Carrier
– Trip Zone Input
• One Host-Port Interface (HPI) With 16-Bit-Wide
Muxed Address/Data Bus For High Bandwidth
• Three 32-Bit Enhanced Capture Modules
(eCAP):
• Programmable Real-Time Unit Subsystem
(PRUSS)
– Configurable as 3 Capture Inputs or 3
Auxiliary Pulse Width Modulator (APWM)
outputs
– Single Shot Capture of up to Four Event
Time-Stamps
– Two Independent Programmable Realtime
Unit (PRU) Cores
•
•
•
•
32-Bit Load/Store RISC architecture
4K Byte instruction RAM per core
512 Bytes data RAM per core
PRU Subsystem (PRUSS) can be disabled
via software to save power
• Two 32-Bit Enhanced Quadrature Encoder
Pulse Modules (eQEP)
• 256-Ball Pb-Free Plastic Ball Grid Array (PBGA)
[ZKB Suffix], 1.0-mm Ball Pitch
• Commercial, Industrial, Extended, or
Automotive Temperature
– Standard power management mechanism
•
Clock gating
2
OMAP-L137 Low-Power Applications Processor
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1.2 Description
The OMAP-L137 is a low-power applications processor based on an ARM926EJ-S™ and a C674x DSP
core. It consumes significantly lower power than other members of the TMS320C6000™ platform of
DSPs.
The OMAP-L137 enables OEMs and ODMs to quickly bring to market devices featuring robust operating
systems support, rich user interfaces, and high processing performance life through the maximum
flexibility of a fully integrated mixed processor solution.
The dual-core architecture of the OMAP-L137 provides benefits of both DSP and Reduced Instruction Set
Computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an
ARM926EJ-S core.
The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and
processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and
memory system can operate continuously.
The ARM core has a coprocessor 15 (CP15), protection module, and Data and program Memory
Management Units (MMUs) with table look-aside buffers. It has separate 16K-byte instruction and 16K-
byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also
has a 8KB RAM (Vector Table) and 64KB ROM.
The OMAP-L137 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P)
is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache.
The Level 2 program cache (L2P) consists of a 256KB memory space that is shared between program
and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.
Although the DSP L2 is accessible by ARM and other hosts in the system, an additional 128KB RAM
shared memory is available for use by other hosts without affecting DSP performance.
The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output
(MDIO) module; two inter-integrated circuit (I2C) bus interfaces; 3 multichannel audio serial ports (McASP)
with 16/12/4 serializers and FIFO buffers; 2 64-bit general-purpose timers each configurable (one
configurable as watchdog); a configurable 16-bit host port interface (HPI) ; up to 8 banks of 16 pins of
general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed
with other peripherals; 3 UART interfaces (one with RTS and CTS); 3 enhanced high-resolution pulse
width modulator (eHRPWM) peripherals; 3 32-bit enhanced capture (eCAP) module peripherals which can
be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; 2 32-bit enhanced
quadrature pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM
external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory
interface (EMIFB) for SDRAM.
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the OMAP-L137
and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and
100 Mbps in either half- or full-duplex mode. Additionally an Management Data Input/Output (MDIO)
interface is available for PHY configuration.
The HPI, I2C, SPI, USB1.1 and USB2.0 ports allow the OMAP-L137 to easily control peripheral devices
and/or communicate with host processors.
The rich peripheral set provides the ability to control external peripheral devices and communicate with
external processors. For details on each of the peripherals, see the related sections later in this document
and the associated peripheral reference guides.
The OMAP-L137 has a complete set of development tools for both the ARM and DSP. These include C
compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™
debugger interface for visibility into source code execution.
Copyright © 2008–2013, Texas Instruments Incorporated
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1.3 Functional Block Diagram
ARM Subsystem
DSP Subsystem
JTAG Interface
System Control
ARM926EJ-S CPU
With MMU
C674x™
DSP CPU
PLL/Clock
Generator
w/OSC
Input
Clock(s)
Memory
Protection
4 KB ETB
AET
General-
Purpose
Timer
16 KB
I-Cache
32 KB
L1 Pgm
16 KB
D-Cache
32 KB
L1 RAM
Power/Sleep
Controller
General-
Purpose
Timer
8 KB RAM
(Vector Table)
256 KB L2 RAM
BOOT ROM
RTC/
32-KHz
OSC
Pin
Multiplexing
64 KB ROM
(Watchdog)
Switched Central Resource (SCR)
Peripherals
Display
Internal Memory
DMA
Audio Ports
Serial Interfaces
McASP
w/FIFO
(3)
2
SPI
(2)
UART
(3)
I C
(2)
LCD
Ctlr
PRU
Subsystem
128 KB
RAM
GPIO
EDMA3
Connectivity
External Memory Interfaces
Control Timers
(10/100)
EMAC
(RMII)
EMIFB
SDRAM Only
(16b/32b)
USB2.0
OTG Ctlr OHCI Ctlr
PHY PHY
USB1.1
EMIFA(8b/16B)
NAND/Flash
16b SDRAM
eHRPWM
(3)
eCAP
(3)
eQEP
(2)
MMC/SD
(8b)
MDIO
HPI
Note: Not all peripherals are available at the same time due to multiplexing.
Figure 1-1. OMAP-L137 Functional Block Diagram
4
OMAP-L137 Low-Power Applications Processor
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SPRS563F –SEPTEMBER 2008–REVISED FEBRUARY 2013
1
OMAP-L137 Low-Power Applications Processor . 1
5.9 General-Purpose Input/Output (GPIO) ............. 78
5.10 EDMA ............................................... 81
5.11 External Memory Interface A (EMIFA) ............. 86
5.12 External Memory Interface B (EMIFB) ............. 97
5.13 Memory Protection Units .......................... 104
5.14 MMC / SD / SDIO (MMCSD) ...................... 107
5.15 Ethernet Media Access Controller (EMAC) ....... 110
1.1 Features ............................................. 1
1.2 Description ........................................... 3
1.3 Functional Block Diagram ........................... 4
Revision History .............................................. 6
2
Device Overview ........................................ 9
2.1 Device Characteristics ............................... 9
2.2 Device Compatibility ................................ 10
2.3 ARM Subsystem .................................... 10
2.4 DSP Subsystem .................................... 13
2.5 Memory Map Summary ............................ 24
2.6 Pin Assignments .................................... 27
2.7 Terminal Functions ................................. 28
Device Configuration ................................. 49
3.1 Boot Modes ......................................... 49
3.2 SYSCFG Module ................................... 50
3.3 Pullup/Pulldown Resistors .......................... 52
Device Operating Conditions ....................... 53
5.16 Management Data Input/Output (MDIO) .......... 115
5.17 Multichannel Audio Serial Ports (McASP0, McASP1,
and McASP2) ..................................... 117
5.18 Serial Peripheral Interface Ports (SPI0, SPI1) .... 130
5.19 Enhanced Capture (eCAP) Peripheral ............ 149
5.20 Enhanced Quadrature Encoder (eQEP) Peripheral
..................................................... 152
5.21 Enhanced High-Resolution Pulse-Width Modulator
(eHRPWM) ........................................ 154
3
4
5.22 LCD Controller .................................... 158
5.23 Timers ............................................. 173
5.24 Inter-Integrated Circuit Serial Ports (I2C0, I2C1) . 175
5.25 Universal Asynchronous Receiver/Transmitter
(UART) ............................................ 180
5.26 USB1 Host Controller Registers (USB1.1 OHCI) . 182
5.27 USB0 OTG (USB2.0 OTG) ........................ 183
5.28 Host-Port Interface (UHPI) ........................ 191
5.29 Power and Sleep Controller (PSC) ................ 198
5.30 Programmable Real-Time Unit Subsystem (PRUSS)
..................................................... 201
4.1
Absolute Maximum Ratings Over Operating Case
Temperature Range
(Unless Otherwise Noted) ................................. 53
4.2 Recommended Operating Conditions .............. 54
4.3
Notes on Recommended Power-On Hours (POH) . 55
4.4
Electrical Characteristics Over Recommended
Ranges of Supply Voltage and Operating Case
Temperature (Unless Otherwise Noted) ........... 56
5
Peripheral Information and Electrical
5.31 Emulation Logic ................................... 204
5.32 IEEE 1149.1 JTAG ................................ 211
5.33 Real Time Clock (RTC) ........................... 213
Device and Documentation Support ............. 216
6.1 Device Support .................................... 216
6.2 Documentation Support ........................... 217
6.3 Community Resources ............................ 218
Specifications .......................................... 57
5.1 Parameter Information .............................. 57
5.2
Recommended Clock and Control Signal Transition
Behavior ............................................ 58
6
7
5.3 Power Supplies ..................................... 58
5.4
Unused USB0 (USB2.0) and USB1 (USB1.1) Pin
Configurations ...................................... 59
5.5 Reset ............................................... 60
Mechanical Packaging and Orderable
5.6
Crystal Oscillator or External Clock Input .......... 63
Information ............................................ 219
7.1 Thermal Data for ZKB ............................. 219
7.2 Packaging Information ............................ 219
5.7 Clock PLLs ......................................... 65
5.8 Interrupts ............................................ 69
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This data manual revision history highlights the changes made to the SPRS563E device-specific data
manual to make it an SPRS563F revision.
Scope: Applicable updates to the OMAP-L137 Low-Power Applications Processor device family,
specifically relating to the OMAP-L137 device, which are all now in the production data (PD) stage of
development have been incorporated.
•
•
•
Silicon Revision 3.0
Digital I/O Buffers Premature Aging
456 MHz Version now PD
Revision History
SEE
ADDITIONS/MODIFICATIONS/DELETIONS
Updated/Changed Product Status on the 456-MHz Version device from “Advanced Information (AI)” to
“Production Data (PD)”
Global
Added DSP/BIOS as a Texas Instruments trademark
Section 1.3
Functional Block
Diagram
Figure 1-1, OMAP-L137 Functional Block Diagram:
•
Added “Memory Protection” in the System Control Block
Table 2-1, Characteristics of the OMAP-L137 Processor:
Section 2.1
Device
Characteristics
•
•
Updated/Changed EMIFB "16/32bit, up to 512 Mb SDRAM” to "16/32bit, up to 256 MB SDRAM”
Added Silicon Revisions "3.0" and "2.1" to the JTAG BSDL_ID row
Section 2.3.7
ARM Memory
Mapping
Added “To improve security …” paragraph
Section 2.5
Memory Map
Summary
Added “Note: Read/Write accesses …” sentence
Section 2.7.5
External Memory
Interface B (only
SDRAM):
Table 2-9, External Memory Interface B (EMIFB) Terminal Functions:
•
•
Updated/Changed EMIFB SDRAM data bus upper byte (EMB_D[31:16]) TYPE from “O” to “I/O”
Updated/Changed EMB_SDCKE, C13, EMIFB SDRAM clock TYPE from “I/O” to “O”
Table 2-13, Enhanced Quadrature Encoder Pulse Module (eQEP) Terminal Functions:
Section 2.7.9
Enhanced
Quadrature Encoder
Pulse Module
(eQEP):
•
•
•
•
Updated/Changed eQEP0 MUXED column from “SPIO” and “SPI1” to “SPI0”
Updated/Changed eQEP1 DESCRIPTION column for eQEP1 to “eQEP1A” and “eQEP1B”
Split eQEP1 MUXED column for ZKB Pin No. T5 and T6
Added "SIP0, GPIO, BOOT" to MUXED column for ZKB Pin No. T5
Table 2-14, Boot Mode Selection Terminal Functions:
Updated/Changed SPI0_CLK/EQEP1I/GP5[2]/BOOT[2], T5, MUXED column from “SPIO” to “SPI0”
Section 2.7.10
Boot
•
Section 2.7.15
Multichannel Audio
Serial Ports
(McASP0, McASP1,
McASP2)
Table 2-19, Multichannel Audio Serial Ports (McASPs) Terminal Functions:
Split McASP2 MUXED column for pin AXR2[0] (A5) and added “McASP2, GPIO”
•
Section 2.7.16
Universal Serial Bus
Modules (USB0,
USB1)
Table 2-20, Universal Serial Bus (USB) Terminal Functions:
Updated/Changed the USB0_VDDA12 pin DESCRIPTION column and associated footnote
•
Table 2-24, Reserved and No Connect Terminal Functions:
Section 2.7.20
Reserved and No
Connect
•
•
Updated/Changed the RSV1 TYPE column from “PWR” to “-“
Updated/Changed RSV2 DESCRIPTION to “… be tied either directly to CVDD or left unconnected [do
not connect to ground (VSS)]”
Section 3.1
Boot Modes
Added “16-bit NAND” sub-bullet to NAND Flash boot
6
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Revision History (continued)
SEE
Section 3.2
ADDITIONS/MODIFICATIONS/DELETIONS
Table 3-1, System Configuration (SYSCFG) Module Register Access:
•
Updated/Changed 0x01C1 4018, DEVIDR0 REGISTER DESCRIPTION from “Device Identification
Register 0” to “JTAG Identification Register”
SYSCFG Module
•
Added 0x01C1 4024, CHIPREVID, Silicon Revision Identification Register row
Section 4.1, Absolute Maximum Ratings Over Operating Case Temperature Range:
Section 4
Device Operating
Conditions
•
•
Updated/Changed Input voltage ranges, “VI I/O, CVDD" to "VI I/O, 1.2V"
Updated/Changed Input voltage ranges, VI I/O, 3.3V (Steady State) from “-0.3V to DVDD + 0.3V” to “-
0.3V to DVDD + 0.35V”
Section 4.2, Recommended Operating Conditions:
•
Updated/Change DVDD, Supply voltage, I/O, 3.3V (DVDD, USB0_VDDA33, USB1_VDDA33) MIN value
from “3.15” to “3.0” V
Section 5.3.1, Power-on Sequence:
Updated/Changed, for clarity, the order the device should be powered-on
Section 5.5.1, Power-On Reset (POR):
Section 5.3
Power Supplies
•
Section 5.5
Reset
•
Updated/Changed "RTCK is maintained active through a POR." to "RTCK/GP7[14] is maintained active
through a POR."
Section 5.5.2, Warm Reset:
•
Updated/Changed "RTCK is maintained active through a warm reset." to "RTCK/GP7[14] is maintained
active through a warm reset."
Table 5-7, AINTC System Interrupt Assignments:
Table 5-7
AINTC System
Interrupt
•
Updated/Changed SYSTEM INTERRUPT 27 INTERRUPT NAME from “PROTERR” to
“MPU_BOOTCFG_ERR”
Assignments on
OMAP-L137
•
Updated/Changed SYSTEM INTERRUPT 27 SOURCE from “SYSCFG Protection Shared Interrupt” to
“Shared MPU and SYSCFG Address/Protection Error Interrupt"
Table 5-8, AINTC Memory Map:
•
•
•
Updated/Changed SRSR[0], SECR[0], ESR[0], and ECR[0] REGISTER NAME to [1] registers
Updated/Changed "HIPIR[0] - HIPIR[1]" REGISTER NAME to "HIPIR[1] - HIPIR[2]"
Updated/Changed BYTE ADDRESS 0xFFFE EF00 - 0xFFFE EF04 from "DSR[0] - DSR[1]" REGISTER
NAME and "Debug Select Registers" DESCRIPTION to "-" REGISTER NAME and "Reserved"
DESCRIPTION
Section 5.8.1.5
AINTC Memory Map
•
•
•
Updated/Changed "HINLR[0] - HINLR[1]" REGISTER NAME to "HINLR[1] - HINLR[2]"
Deleted "[0]" to 0xFFFE F500 "HIER" REGISTER NAME
Updated/Changed "HIPVR[0] - HIPVR[1]" REGISTER NAME to "HIPVR[1] - HIPVR[2]"
Table 5-9, OMAP-L137 DSP Interrupts:
Section 5.8.2
DSP Interrupts
•
•
Updated/Changed EVT# 74 INTERRUPT NAME from “PROTERR” to “MPU_BOOTCFG_ERR”
Updated/Changed EVT# 74 SOURCE from “SYSCFG Protection Shared Interrupt” to “Shared MPU and
SYSCFG Address/Protection Error Interrupt"
Section 5.11
External Memory
Interface A (EMIFA)
Section 5.11.4, EMIFA Connection Examples:
Added new Subsection
•
Section 5.12
External Memory
Interface B (EMIFB)
Figure 5-20, EMIFB Functional Block Diagram:
Added MPU2 block to figure
•
Section 5.12.1, EMIFB SDRAM Loading Limitations:
•
Updated/Changed “EMIFB supports SDRAM up to 133MHz …” to “EMIFB supports SDRAM up to
152MHz …”
Table 5-30, EMIFB SDRAM Interface Switching Characteristics:
Section 5.12.3
EMIFB Electrical
Data/Timing
•
Updated/Changed PARAMETER No. 1, tc(CLK) Cycle time, EMIF clock EMB_CLK MIN value from “7.5”
to “6.579” ns
•
Updated/Changed PARAMETER No. 2, tw(CLK) Pulse width, EMIF clock EMB_CLK high or low MIN
value from “3” to “2.63” ns
Table 5-35, Switching Characteristics Over Recommended Operating Conditions for MMC/SD Module:
Section 5.14.3
MMC/SD Electrical
Data/Timing
•
Updated/Changed the MAX value of PARAMETER No. 14, td(CLKL-DAT), Delay time, MMCSD_CLK low to
MMCSD_DATx transition from “2” to “2.5” ns
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Revision History (continued)
SEE
ADDITIONS/MODIFICATIONS/DELETIONS
Section 5.16.2
Management Data
Input/Output (MDIO)
Electrical
Table 5-8, Timing Requirements for MDIO Input:
•
Updated/Changed the MIN value of No. 5, th(MDIO_CLKH-MDIO), Hold time, MDIO_D data input valid after
MDIO_CLK high from “10” to “0” ns
Data/Timing
Table 5-57, General Timing Requirements for SPI0 Slave Modes:
Section 5.18.2
SPI Electrical
Data/Timing
•
Updated/Changed MIN value of PARAMETER No. 9, tc(SPC)S, Cycle Time, SPI0_CLK, All Slave Modes
from “greater of 3P or 20” to “greater of 3P or 40” ns
Section 5.22.1
LCD Interface
Display Driver (LIDD
Mode):
Table 5-84, LCD LIDD Mode Timing Requirements:
Table 5-85, LCD LIDD Mode Timing Characteristics:
•
Updated/Changed LCD_CLK (SYSCLK2) all references to "LCD_MCLK"
Table 5-86, LCD Raster Mode Timing:
•
Updated/Changed PARAMETER NO. 9, td(LCD_VSYNC_I) description from "Delay time, LCD_PCLK low to
LCD_VSYNC high" to "Delay time, LCD_PCLK low to LCD_VSYNC low"
•
•
•
Changed parameter descriptions, replacing arrows with text.
Added "The activation edge of the control signals ..." footnote
Section 5.22.2
LCD Raster Mode
Added associated footnote cross-references to PARAMETER No. 8, 9, 10, and 11
Figure 5-56, LCD Raster-Mode Active:
•
•
•
Updated/Changed LCD_AC_ENB_CS signal in figure
Added LCD_AC_ENB_CS in expanded view
Added "x" in "16 (1 to 1024)"
Table 5-102, Switching Characteristics for Host-Port Interface Cycles:
•
Added "UHPI_" to the all signal names and descriptions to match associated figures and Terminal
Functions signal names
Section 5.28.3
HPI Electrical
Data/Timing
Figure 5-67 through Figure 5-70:
Added "UHPI_" to the all signal names in footnotes to match figures
•
Section 5.29.1
Power Domain and
Module Topology
Section 5.29.1.1, Power Domain States:
Added new subsection
•
Section 5.32.1, JTAG Peripheral Register Description(s) – JTAG ID Register (DEVIDR0):
Added Silicon Revisions "3.0" and "2.1" to the "0x9B7D F02F for silicon revision 2.0" bullet
Section 5.32
IEEE 1149.1 JTAG
•
Section 6.1.2
Device and
Development-
Support Tool
Nomenclature
Updated/Changed subsection title from “Device Nomenclature” to “Device and Development-Support Tool
Nomenclature”
Figure 6-1, Device Nomenclature:
•
Updated/Changed Silicon Revision to include Revision 3.0
Deleted the following document(s):
•
•
SPRUG84, OMAP-L137 Applications Processor System Reference Guide
Section 6.2
Documentation
Support
SPRUGA6, OMAP-L137 Applications Processor Peripherals Overview Reference Guide
Added the following document(s):
•
SPRUH92, OMAP-L137 DSP_ARM Processor Technical Reference Manual
•
Deleted “Mechanical Drawings” section and moved paragraph under Section 7, Mechanical Packaging
and Orderable Information
Section 7
Mechanical
Packaging and
Orderable
•
•
Deleted Packaging Materials Information subsection (was Section 7.1 in the previous revision), duplicate
information
Information
Added Section 7.2, Packaging Information
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2 Device Overview
2.1 Device Characteristics
Table 2-1 provides an overview of the OMAP-L137 low power applications processor. The table shows
significant features of the device, including the capacity of on-chip RAM, peripherals, and the package
type with pin count.
Table 2-1. Characteristics of the OMAP-L137 Processor
HARDWARE FEATURES
OMAP-L137
EMIFB
16/32bit, up to 256MB SDRAM
Asynchronous (8/16-bit bus width) RAM, Flash, 16bit up to 128MB SDRAM, NOR,
NAND
EMIFA
Flash Card Interface
MMC and SD cards supported.
EDMA3
32 independent channels, 8 QDMA channels, 2 Transfer controllers
2 64-Bit General Purpose (each configurable as 2 separate 32-bit timers, 1 configurable
as Watch Dog)
Timers
UART
SPI
I2C
3 (one with RTS and CTS flow control)
2 (each with one hardware chip select)
2 (both Master/Slave)
Multichannel Audio
Serial Port [McASP]
Peripherals
3 (each with transmit/receive, FIFO buffer, 16/12/4 serializers)
Not all peripherals pins
are available at the
same time (for more
detail, see the Device
Configurations section).
10/100 Ethernet MAC
with Management Data
I/O
1 (RMII Interface)
eHRPWM
eCAP
6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
3 32-bit capture inputs or 3 32-bit auxiliary PWM outputs
2 32-bit QEP channels with 4 inputs/channel
eQEP
UHPI
1 (16-bit multiplexed address/data)
USB 2.0 (USB0)
USB 1.1 (USB1)
High-Speed OTG Controller with on-chip OTG PHY
Full-Speed OHCI (as host) with on-chip PHY
General-Purpose
Input/Output Port
8 banks of 16-bit
1
LCD Controller
PRU Subsystem
(PRUSS)
2 Programmable PRU Cores
Size (Bytes)
488KB RAM
DSP
32KB L1 Program (L1P)/Cache (up to 32KB)
32KB L1 Data (L1D)/Cache (up to 32KB)
256KB Unified Mapped RAM/Cache (L2)
DSP Memories can be made accessible to ARM, EDMA3, and other peripherals.
On-Chip Memory
ARM
16KB I-Cache
Organization
16KB D-Cache
8KB RAM (Vector Table)
64KB ROM
ADDITIONAL SHARED MEMORY
128KB RAM
C674x CPU ID + CPU Control Status Register
0x1400
0x0000
Rev ID
(CSR.[31:16])
C674x Megamodule
Revision
Revision ID Register
(MM_REVID[15:0])
0x0B7D F02F (Silicon Revision 1.0)
0x8B7D F02F (Silicon Revision 1.1)
JTAG BSDL_ID
DEVIDR0 register
0x9B7D F02F (Silicon Revisions 3.0, 2.1, and 2.0)
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Table 2-1. Characteristics of the OMAP-L137 Processor (continued)
HARDWARE FEATURES
OMAP-L137
674x DSP at 375 MHz(1.2V) or 456 MHz (1.3V)
ARM926 at 375 MHz(1.2V) or 456 MHz (1.3V)
1.2V / 1.3V
CPU Frequency
MHz
Core (V)
I/O (V)
Voltage
3.3 V / 1.8 V (1.8 V for USB only)
Package
17 mm x 17 mm, 256-Ball 1 mm pitch, PBGA (ZKB)
Product Preview (PP),
Advance Information
(AI),
or Production Data
(PD)
375 MHz Versions -PD
456 MHz Version - PD
Product Status(1)
(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
2.2 Device Compatibility
The ARM926EJ-S RISC CPU is compatible with other ARM9 CPUs from ARM Holdings plc.
The C674x DSP core is code-compatible with the C6000™ DSP platform and supports features of both
the C64x+ and C67x+ DSP families.
2.3 ARM Subsystem
The ARM Subsystem includes the following features:
•
•
•
•
•
•
•
•
•
•
ARM926EJ-S RISC processor
ARMv5TEJ (32/16-bit) instruction set
Little endian
System Control Co-Processor 15 (CP15)
MMU
16KB Instruction cache
16KB Data cache
Write Buffer
Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)
ARM Interrupt controller
2.3.1 ARM926EJ-S RISC CPU
The ARM Subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of
ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications
where full memory management, high performance, low die size, and low power are all important. The
ARM926EJ-S processor supports the 32-bit ARM and 16 bit THUMB instruction sets, enabling the user to
trade off between high performance and high code density. Specifically, the ARM926EJ-S processor
supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes,
providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code
overhead.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both
hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a
complete high performance subsystem, including:
•
•
•
•
ARM926EJ -S integer core
CP15 system control coprocessor
Memory Management Unit (MMU)
Separate instruction and data caches
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•
•
•
•
Write buffer
Separate instruction and data (internal RAM) interfaces
Separate instruction and data AHB bus interfaces
Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)
For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available
at http://www.arm.com
2.3.2 CP15
The ARM926EJ-S system control coprocessor (CP15) is used to configure and control instruction and
data caches, Memory Management Unit (MMU), and other ARM subsystem functions. The CP15 registers
are programmed using the MRC and MCR ARM instructions, when the ARM in a privileged mode such as
supervisor or system mode.
2.3.3 MMU
A single set of two level page tables stored in main memory is used to control the address translation,
permission checks and memory region attributes for both data and instruction accesses. The MMU uses a
single unified Translation Lookaside Buffer (TLB) to cache the information held in the page tables. The
MMU features are:
•
•
Standard ARM architecture v4 and v5 MMU mapping sizes, domains and access protection scheme.
Mapping sizes are:
–
–
–
–
1MB (sections)
64KB (large pages)
4KB (small pages)
1KB (tiny pages)
•
Access permissions for large pages and small pages can be specified separately for each quarter of
the page (subpage permissions)
•
•
•
•
Hardware page table walks
Invalidate entire TLB, using CP15 register 8
Invalidate TLB entry, selected by MVA, using CP15 register 8
Lockdown of TLB entries, using CP15 register 10
2.3.4 Caches and Write Buffer
The size of the Instruction cache is 16KB, Data cache is 16KB. Additionally, the caches have the following
features:
•
•
Virtual index, virtual tag, and addressed using the Modified Virtual Address (MVA)
Four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with
two dirty bits in the Dcache
•
Dcache supports write-through and write-back (or copy back) cache operation, selected by memory
region using the C and B bits in the MMU translation tables
•
•
Critical-word first cache refilling
Cache lockdown registers enable control over which cache ways are used for allocation on a line fill,
providing a mechanism for both lockdown, and controlling cache corruption
•
Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the TAG
RAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the
TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the
possibility of TLB misses related to the write-back address.
•
Cache maintenance operations provide efficient invalidation of, the entire Dcache or Icache, regions of
the Dcache or Icache, and regions of virtual memory.
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The write buffer is used for all writes to a noncachable bufferable region, write-through region and write
misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for
cache line evictions or cleaning of dirty cache lines. The main write buffer has 16-word data buffer and a
four-address buffer. The Dcache write-back has eight data word entries and a single address entry.
2.3.5 Advanced High-Performance Bus (AHB)
The ARM Subsystem uses the AHB port of the ARM926EJ-S to connect the ARM to the Config bus and
the external memories. Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB by the
Config Bus and the external memories bus.
2.3.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an
Embedded Trace Macrocell (ETM). The ARM926EJ-S Subsystem in the OMAP-L137 also includes the
Embedded Trace Buffer (ETB). The ETM consists of two parts:
•
•
Trace Port provides real-time trace capability for the ARM9.
Triggering facilities provide trigger resources, which include address and data comparators, counter,
and sequencers.
The OMAP-L137 trace port is not pinned out and is instead only connected to the Embedded Trace Buffer.
The ETB has a 4KB buffer memory. ETB enabled debug tools are required to read/interpret the captured
trace data.
This device uses ETM9™ version r2p2 and ETB version r0p1. Documentation on the ETM and ETB is
available from ARM Ltd. Reference the ' CoreSight™ ETM9™ Technical Reference Manual, revision r0p1'
and the 'ETM9 Technical Reference Manual, revision r2p2'.
2.3.7 ARM Memory Mapping
By default the ARM has access to most on and off chip memory areas, including the DSP Internal
memories, EMIFA, EMIFB, and the additional 128K byte on chip shared SRAM. Likewise almost all of the
on chip peripherals are accessible to the ARM by default.
To improve security and/or robustness, the device has extensive memory and peripheral protection units
which can be configured to limit access rights to the various on/off chip resources to specific hosts;
including the ARM as well as other master peripherals. This allows the system tasks to be partitioned
between the ARM and DSP as best suites the particular application; while enhancing the overall
robustness of the solution.
See Table 2-4 for a detailed top level OMAP-L137 memory map that includes the ARM memory space.
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2.4 DSP Subsystem
The DSP Subsystem includes the following features:
C674x DSP CPU
32KB L1 Program (L1P)/Cache (up to 32KB)
•
•
•
•
•
•
32KB L1 Data (L1D)/Cache (up to 32KB)
256KB Unified Mapped RAM/Cache (L2)
Boot ROM (cannot be used for application code)
Little endian
32K Bytes
L1P RAM/
Cache
256K Bytes
L2 RAM
Boot ROM
256
256
256
256
Cache Control
Memory Protect
Bandwidth Mgmt
Cache Control
Memory Protect
Bandwidth Mgmt
L1P
L2
256
256
Power Down
256
256
Instruction Fetch
C674x
Fixed/Floating Point CPU
Interrupt
Controller
IDMA
256
Register
File A
Register
File B
64
64
CFG
Bandwidth Mgmt
Memory Protect
Cache Control
EMC
Configuration
Peripherals
Bus
32
L1D
MDMA
SDMA
8 x 32
64
64
64
64
32K Bytes
L1D RAM/
Cache
High
Performance
Switch Fabric
Figure 2-1. C674x Megamodule Block Diagram
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2.4.1 C674x DSP CPU Description
The C674x Central Processing Unit (CPU) consists of eight functional units, two register files, and two
data paths as shown in Figure 2-2. The two general-purpose register files (A and B) each contain 32 32-
bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be data
address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-
bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in
register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the
next upper register (which is always an odd-numbered register).
The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one
instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units
perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from
memory to the register file and store results from the register file into memory.
The C674x CPU combines the performance of the C64x+ core with the floating-point capabilities of the
C67x+ core.
Each C674x .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x
32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with
add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four
16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for
Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and
modems require complex multiplication. The complex multiply (CMPY) instruction takes four 16-bit inputs
and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding
capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The
32 x 32 bit multiply instructions provide the extended precision necessary for high-precision algorithms on
a variety of signed and unsigned 32-bit data types.
The .L Unit (or Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on
a pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data
performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.
The C674x core enhances the .S unit in several ways. On the previous cores, dual 16-bit MIN2 and MAX2
comparisons were only available on the .L units. On the C674x core they are also available on the .S unit
which increases the performance of algorithms that do searching and sorting. Finally, to increase data
packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit
and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack
instructions return parallel results to output precision including saturation support.
Other new features include:
•
SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where
multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size
associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.
•
Compact Instructions - The native instruction size for the C6000™ devices is 32 bits. Many common
instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C674x
compiler can restrict the code to use certain registers in the register file. This compression is
performed by the code generation tools.
•
•
•
Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit
multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field
multiplication.
Exceptions Handling - Intended to aid the programmer in isolating bugs. The C674x CPU is able to
detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and
from system events (such as a watchdog time expiration).
Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a
basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with
read, write, and execute permissions.
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•
Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a free-
running time-stamp counter is implemented in the CPU which is not sensitive to system stalls.
For more details on the C674x CPU and its enhancements over the C64x architecture, see the following
documents:
•
•
TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number: SPRU732)
TMS320C64x Technical Overview (literature number: SPRU395)
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Even
register
file A
(A0, A2,
A4...A30)
src1
src2
Odd
register
file A
(A1, A3,
A5...A31)
.L1
odd dst
even dst
long src
(D)
8
32 MSB
ST1b
ST1a
32 LSB
8
long src
even dst
odd dst
src1
(D)
Data path A
.S1
src2
32
32
(A)
(B)
dst2
dst1
src1
.M1
src2
(C)
32 MSB
32 LSB
LD1b
LD1a
dst
src1
src2
.D1
.D2
DA1
2x
1x
Even
register
file B
(B0, B2,
B4...B30)
Odd
register
file B
(B1, B3,
B5...B31)
src2
DA2
src1
dst
32 LSB
LD2a
LD2b
32 MSB
src2
(C)
.M2
src1
dst2
32
32
(B)
(A)
dst1
src2
src1
.S2
odd dst
even dst
long src
(D)
Data path B
8
8
32 MSB
32 LSB
ST2a
ST2b
long src
even dst
(D)
odd dst
.L2
src2
src1
Control Register
A. On .M unit, dst2 is 32 MSB.
B. On .M unit, dst1 is 32 LSB.
C. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits.
D. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files.
Figure 2-2. TMS320C674x CPU (DSP Core) Data Paths
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2.4.2 DSP Memory Mapping
The DSP memory map is shown in Section 2.5.
By default the DSP also has access to most on and off chip memory areas, with the exception of the ARM
RAM, ROM, and AINTC interrupt controller. The DSP also boots first, and must release the ARM from
reset before the ARM can execute any code.
Additionally, the DSP megamodule includes the capability to limit access to its internal memories through
its SDMA port; without needing an external MPU unit.
2.4.2.1 ARM Internal Memories
The DSP does not have access to the ARM internal memory.
2.4.2.2 External Memories
The DSP has access to the following External memories:
•
•
Asynchronous EMIF / SDRAM / NAND / NOR Flash (EMIFA)
SDRAM (EMIFB)
2.4.2.3 DSP Internal Memories
The DSP has access to the following DSP memories:
•
•
•
L2 RAM
L1P RAM
L1D RAM
2.4.2.4 C674x CPU
The C674x core uses a two-level cache-based architecture. The Level 1 Program cache (L1P) is 32 KB
direct mapped cache and the Level 1 Data cache (L1D) is 32 KB 2-way set associated cache. The Level 2
memory/cache (L2) consists of a 256 KB memory space that is shared between program and data space.
L2 memory can be configured as mapped memory, cache, or a combination of both.
Table 2-2 shows a memory map of the C674x CPU cache registers for the device.
Table 2-2. C674x Cache Registers
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
L2 Cache configuration register (See the System reference Guide for the
reset configuration)
0x0184 0000
L2CFG
L1P Size Cache configuration register (See the System reference Guide for
the reset configuration)
0x0184 0020
0x0184 0024
0x0184 0040
L1PCFG
L1PCC
L1P Freeze Mode Cache configuration register
L1D Size Cache configuration register (See the System reference Guide for
the reset configuration)
L1DCFG
0x0184 0044
0x0184 0048 - 0x0184 0FFC
0x0184 1000
L1DCC
-
L1D Freeze Mode Cache configuration register
Reserved
EDMAWEIGHT
-
L2 EDMA access control register
Reserved
0x0184 1004 - 0x0184 1FFC
0x0184 2000
L2ALLOC0
L2ALLOC1
L2ALLOC2
L2ALLOC3
-
L2 allocation register 0
L2 allocation register 1
L2 allocation register 2
L2 allocation register 3
Reserved
0x0184 2004
0x0184 2008
0x0184 200C
0x0184 2010 - 0x0184 3FFF
0x0184 4000
L2WBAR
L2WWC
L2 writeback base address register
L2 writeback word count register
0x0184 4004
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Table 2-2. C674x Cache Registers (continued)
BYTE ADDRESS
0x0184 4010
ACRONYM
L2WIBAR
REGISTER DESCRIPTION
L2 writeback invalidate base address register
0x0184 4014
L2WIWC
L2IBAR
L2IWC
L2 writeback invalidate word count register
L2 invalidate base address register
L2 invalidate word count register
L1P invalidate base address register
L1P invalidate word count register
L1D writeback invalidate base address register
L1D writeback invalidate word count register
Reserved
0x0184 4018
0x0184 401C
0x0184 4020
L1PIBAR
L1PIWC
L1DWIBAR
L1DWIWC
-
0x0184 4024
0x0184 4030
0x0184 4034
0x0184 4038
0x0184 4040
L1DWBAR
L1DWWC
L1DIBAR
L1DIWC
-
L1D writeback base address register
L1D writeback word count register
L1D invalidate base address register
L1D invalidate word count register
Reserved
0x0184 4044
0x0184 4048
0x0184 404C
0x0184 4050 - 0x0184 4FFF
0x0184 5000
L2WB
L2 writeback all register
0x0184 5004
L2WBINV
L2INV
L2 writeback invalidate all register
L2 Global Invalidate without writeback
Reserved
0x0184 5008
0x0184 500C - 0x0184 5027
0x0184 5028
-
L1PINV
-
L1P Global Invalidate
0x0184 502C - 0x0184 5039
0x0184 5040
Reserved
L1DWB
L1DWBINV
L1DINV
MAR0 - MAR63
L1D Global Writeback
0x0184 5044
L1D Global Writeback with Invalidate
L1D Global Invalidate without writeback
Reserved 0x0000 0000 – 0x3FFF FFFF
0x0184 5048
0x0184 8000 – 0x0184 80FF
Memory Attribute Registers for EMIFA SDRAM Data (CS0)
0x4000 0000 – 0x5FFF FFFF
0x0184 8100 – 0x0184 817F
0x0184 8180 – 0x0184 8187
0x0184 8188 – 0x0184 818F
0x0184 8190 – 0x0184 8197
MAR64 – MAR95
MAR96 - MAR97
MAR98 – MAR99
MAR100 – MAR101
Memory Attribute Registers for EMIFA Async Data (CS2)
0x6000 0000 – 0x61FF FFFF
Memory Attribute Registers for EMIFA Async Data (CS3)
0x6200 0000 – 0x63FF FFFF
Memory Attribute Registers for EMIFA Async Data (CS4)
0x6400 0000 – 0x65FF FFFF
Memory Attribute Registers for EMIFA Async Data (CS5)
0x6600 0000 – 0x67FF FFFF
0x0184 8198 – 0x0184 819F
0x0184 81A0 – 0x0184 81FF
MAR102 – MAR103
MAR104 – MAR127
Reserved 0x6800 0000 – 0x7FFF FFFF
Memory Attribute Register for Shared RAM 0x8000 0000 – 0x8001 FFFF
Reserved 0x8002 0000 – 0x81FF FFFF
0x0184 8200
MAR128
0x0184 8204 – 0x0184 82FF
0x0184 8300 – 0x0184 837F
0x0184 8380 – 0x0184 83FF
MAR129 – MAR191
MAR192 – MAR223
MAR224 – MAR255
Reserved 0x8200 0000 – 0xBFFF FFFF
Memory Attribute Registers for EMIFB SDRAM Data (CS0)
0xC000 0000 – 0xDFFF FFFF
Reserved 0xE000 0000 – 0xFFFF FFFF
Table 2-3. C674x L1/L2 Memory Protection Registers
BYTE ADDRESS
0x0184 A000
ACRONYM
L2MPFAR
L2MPFSR
L2MPFCR
-
REGISTER DESCRIPTION
L2 memory protection fault address register
L2 memory protection fault status register
L2 memory protection fault command register
Reserved
0x0184 A004
0x0184 A008
0x0184 A00C - 0x0184 A0FF
0x0184 A100
L2MPLK0
L2 memory protection lock key bits [31:0]
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SPRS563F –SEPTEMBER 2008–REVISED FEBRUARY 2013
Table 2-3. C674x L1/L2 Memory Protection Registers (continued)
BYTE ADDRESS
ACRONYM
L2MPLK1
L2MPLK2
L2MPLK3
L2MPLKCMD
L2MPLKSTAT
-
REGISTER DESCRIPTION
L2 memory protection lock key bits [63:32]
0x0184 A104
0x0184 A108
L2 memory protection lock key bits [95:64]
L2 memory protection lock key bits [127:96]
L2 memory protection lock key command register
L2 memory protection lock key status register
Reserved
0x0184 A10C
0x0184 A110
0x0184 A114
0x0184 A118 - 0x0184 A1FF
L2 memory protection page attribute register 0
(controls memory address 0x0080 0000 - 0x0080 1FFF)
0x0184 A200
0x0184 A204
0x0184 A208
0x0184 A20C
0x0184 A210
0x0184 A214
0x0184 A218
0x0184 A21C
0x0184 A220
0x0184 A224
0x0184 A228
0x0184 A22C
0x0184 A230
0x0184 A234
0x0184 A238
0x0184 A23C
0x0184 A240
0x0184 A244
0x0184 A248
0x0184 A24C
0x0184 A250
0x0184 A254
0x0184 A258
0x0184 A25C
L2MPPA0
L2MPPA1
L2MPPA2
L2MPPA3
L2MPPA4
L2MPPA5
L2MPPA6
L2MPPA7
L2MPPA8
L2MPPA9
L2MPPA10
L2MPPA11
L2MPPA12
L2MPPA13
L2MPPA14
L2MPPA15
L2MPPA16
L2MPPA17
L2MPPA18
L2MPPA19
L2MPPA20
L2MPPA21
L2MPPA22
L2MPPA23
L2 memory protection page attribute register 1
(controls memory address 0x0080 2000 - 0x0080 3FFF)
L2 memory protection page attribute register 2
(controls memory address 0x0080 4000 - 0x0080 5FFF)
L2 memory protection page attribute register 3
(controls memory address 0x0080 6000 - 0x0080 7FFF)
L2 memory protection page attribute register 4
(controls memory address 0x0080 8000 - 0x0080 9FFF)
L2 memory protection page attribute register 5
(controls memory address 0x0080 A000 - 0x0080 BFFF)
L2 memory protection page attribute register 6
(controls memory address 0x0080 C000 - 0x0080 DFFF)
L2 memory protection page attribute register 7
(controls memory address 0x0080 E000 - 0x0080 FFFF)
L2 memory protection page attribute register 8
(controls memory address 0x0081 0000 - 0x0081 1FFF)
L2 memory protection page attribute register 9
(controls memory address 0x0081 2000 - 0x0081 3FFF)
L2 memory protection page attribute register 10
(controls memory address 0x0081 4000 - 0x0081 5FFF)
L2 memory protection page attribute register 11
(controls memory address 0x0081 6000 - 0x0081 7FFF)
L2 memory protection page attribute register 12
(controls memory address 0x0081 8000 - 0x0081 9FFF)
L2 memory protection page attribute register 13
(controls memory address 0x0081 A000 - 0x0081 BFFF)
L2 memory protection page attribute register 14
(controls memory address 0x0081 C000 - 0x0081 DFFF)
L2 memory protection page attribute register 15
(controls memory address 0x0081 E000 - 0x0081 FFFF)
L2 memory protection page attribute register 16
(controls memory address 0x0082 0000 - 0x0082 1FFF)
L2 memory protection page attribute register 17
(controls memory address 0x0082 2000 - 0x0082 3FFF)
L2 memory protection page attribute register 18
(controls memory address 0x0082 4000 - 0x0082 5FFF)
L2 memory protection page attribute register 19
(controls memory address 0x0082 6000 - 0x0082 7FFF)
L2 memory protection page attribute register 20
(controls memory address 0x0082 8000 - 0x0082 9FFF)
L2 memory protection page attribute register 21
(controls memory address 0x0082 A000 - 0x0082 BFFF)
L2 memory protection page attribute register 22
(controls memory address 0x0082 C000 - 0x0082 DFFF)
L2 memory protection page attribute register 23
(controls memory address 0x0082 E000 - 0x0082 FFFF)
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Table 2-3. C674x L1/L2 Memory Protection Registers (continued)
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
L2 memory protection page attribute register 24
(controls memory address 0x0083 0000 - 0x0083 1FFF)
0x0184 A260
L2MPPA24
L2 memory protection page attribute register 25
(controls memory address 0x0083 2000 - 0x0083 3FFF)
0x0184 A264
0x0184 A268
0x0184 A26C
0x0184 A270
0x0184 A274
0x0184 A278
0x0184 A27C
0x0184 A280
0x0184 A284
0x0184 A288
0x0184 A28C
0x0184 A290
0x0184 A294
0x0184 A298
0x0184 A29C
0x0184 A2A0
0x0184 A2A4
0x0184 A2A8
0x0184 A2AC
0x0184 A2B0
0x0184 A2B4
0x0184 A2B8
0x0184 A2BC
0x0184 A2C0
0x0184 A2C4
0x0184 A2C8
0x0184 A2CC
L2MPPA25
L2MPPA26
L2MPPA27
L2MPPA28
L2MPPA29
L2MPPA30
L2MPPA31
L2MPPA32
L2MPPA33
L2MPPA34
L2MPPA35
L2MPPA36
L2MPPA37
L2MPPA38
L2MPPA39
L2MPPA40
L2MPPA41
L2MPPA42
L2MPPA43
L2MPPA44
L2MPPA45
L2MPPA46
L2MPPA47
L2MPPA48
L2MPPA49
L2MPPA50
L2MPPA51
L2 memory protection page attribute register 26
(controls memory address 0x0083 4000 - 0x0083 5FFF)
L2 memory protection page attribute register 27
(controls memory address 0x0083 6000 - 0x0083 7FFF)
L2 memory protection page attribute register 28
(controls memory address 0x0083 8000 - 0x0083 9FFF)
L2 memory protection page attribute register 29
(controls memory address 0x0083 A000 - 0x0083 BFFF)
L2 memory protection page attribute register 30
(controls memory address 0x0083 C000 - 0x0083 DFFF)
L2 memory protection page attribute register 31
(controls memory address 0x0083 E000 - 0x0083 FFFF)
L2 memory protection page attribute register 32
(controls memory address 0x0070 0000 - 0x0070 7FFF)
L2 memory protection page attribute register 33
(controls memory address 0x0070 8000 - 0x0070 FFFF)
L2 memory protection page attribute register 34
(controls memory address 0x0071 0000 - 0x0071 7FFF)
L2 memory protection page attribute register 35
(controls memory address 0x0071 8000 - 0x0071 FFFF)
L2 memory protection page attribute register 36
(controls memory address 0x0072 0000 - 0x0072 7FFF)
L2 memory protection page attribute register 37
(controls memory address 0x0072 8000 - 0x0072 FFFF)
L2 memory protection page attribute register 38
(controls memory address 0x0073 0000 - 0x0073 7FFF)
L2 memory protection page attribute register 39
(controls memory address 0x0073 8000 - 0x0073 FFFF)
L2 memory protection page attribute register 40
(controls memory address 0x0074 0000 - 0x0074 7FFF)
L2 memory protection page attribute register 41
(controls memory address 0x0074 8000 - 0x0074 FFFF)
L2 memory protection page attribute register 42
(controls memory address 0x0075 0000 - 0x0075 7FFF)
L2 memory protection page attribute register 43
(controls memory address 0x0075 8000 - 0x0075 FFFF)
L2 memory protection page attribute register 44
(controls memory address 0x0076 0000 - 0x0076 7FFF)
L2 memory protection page attribute register 45
(controls memory address 0x0076 8000 - 0x0076 FFFF)
L2 memory protection page attribute register 46
(controls memory address 0x0077 0000 - 0x0077 7FFF)
L2 memory protection page attribute register 47
(controls memory address 0x0077 8000 - 0x0077 FFFF)
L2 memory protection page attribute register 48
(controls memory address 0x0078 0000 - 0x0078 7FFF)
L2 memory protection page attribute register 49
(controls memory address 0x0078 8000 - 0x0078 FFFF)
L2 memory protection page attribute register 50
(controls memory address 0x0079 0000 - 0x0079 7FFF)
L2 memory protection page attribute register 51
(controls memory address 0x0079 8000 - 0x0079 FFFF)
20
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SPRS563F –SEPTEMBER 2008–REVISED FEBRUARY 2013
Table 2-3. C674x L1/L2 Memory Protection Registers (continued)
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
L2 memory protection page attribute register 52
(controls memory address 0x007A 0000 - 0x007A 7FFF)
0x0184 A2D0
0x0184 A2D4
0x0184 A2D8
0x0184 A2DC
0x0184 A2E0
0x0184 A2E4
0x0184 A2E8
0x0184 A2EC
0x0184 A2F0
0x0184 A2F4
0x0184 A2F8
0x0184 A2FC
L2MPPA52
L2 memory protection page attribute register 53
(controls memory address 0x007A 8000 - 0x007A FFFF)
L2MPPA53
L2MPPA54
L2MPPA55
L2MPPA56
L2MPPA57
L2MPPA58
L2MPPA59
L2MPPA60
L2MPPA61
L2MPPA62
L2MPPA63
L2 memory protection page attribute register 54
(controls memory address 0x007B 0000 - 0x007B 7FFF)
L2 memory protection page attribute register 55
(controls memory address 0x007B 8000 - 0x007B FFFF)
L2 memory protection page attribute register 56
(controls memory address 0x007C 0000 - 0x007C 7FFF)
L2 memory protection page attribute register 57
(controls memory address 0x007C 8000 - 0x007C FFFF)
L2 memory protection page attribute register 58
(controls memory address 0x007D 0000 - 0x007D 7FFF)
L2 memory protection page attribute register 59
(controls memory address 0x007D 8000 - 0x007D FFFF)
L2 memory protection page attribute register 60
(controls memory address 0x007E 0000 - 0x007E 7FFF)
L2 memory protection page attribute register 61
(controls memory address 0x007E 8000 - 0x007E FFFF)
L2 memory protection page attribute register 62
(controls memory address 0x007F 0000 - 0x007F 7FFF)
L2 memory protection page attribute register 63
(controls memory address 0x007F 8000 - 0x007F FFFF)
0x0184 A300 - 0x0184 A3FF
0x0184 A400
-
Reserved
L1PMPFAR
L1PMPFSR
L1PMPFCR
-
L1P memory protection fault address register
L1P memory protection fault status register
L1P memory protection fault command register
Reserved
0x0184 A404
0x0184 A408
0x0184 A40C - 0x0184 A4FF
0x0184 A500
L1PMPLK0
L1PMPLK1
L1PMPLK2
L1PMPLK3
L1PMPLKCMD
L1PMPLKSTAT
-
L1P memory protection lock key bits [31:0]
L1P memory protection lock key bits [63:32]
L1P memory protection lock key bits [95:64]
L1P memory protection lock key bits [127:96]
L1P memory protection lock key command register
L1P memory protection lock key status register
Reserved
0x0184 A504
0x0184 A508
0x0184 A50C
0x0184 A510
0x0184 A514
0x0184 A518 - 0x0184 A5FF
0x0184 A600 - 0x0184 A63F
(1)
-
Reserved
L1P memory protection page attribute register 16
(controls memory address 0x00E0 0000 - 0x00E0 07FF)
0x0184 A640
0x0184 A644
0x0184 A648
0x0184 A64C
0x0184 A650
0x0184 A654
0x0184 A658
L1PMPPA16
L1PMPPA17
L1PMPPA18
L1PMPPA19
L1PMPPA20
L1PMPPA21
L1PMPPA22
L1P memory protection page attribute register 17
(controls memory address 0x00E0 0800 - 0x00E0 0FFF)
L1P memory protection page attribute register 18
(controls memory address 0x00E0 1000 - 0x00E0 17FF)
L1P memory protection page attribute register 19
(controls memory address 0x00E0 1800 - 0x00E0 1FFF)
L1P memory protection page attribute register 20
(controls memory address 0x00E0 2000 - 0x00E0 27FF)
L1P memory protection page attribute register 21
(controls memory address 0x00E0 2800 - 0x00E0 2FFF)
L1P memory protection page attribute register 22
(controls memory address 0x00E0 3000 - 0x00E0 37FF)
(1) These addresses correspond to the L1P memory protection page attribute registers 0-15 (L1PMPPA0-L1PMPPA15) of the C674x
megamaodule. These registers are not supported for this device.
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Table 2-3. C674x L1/L2 Memory Protection Registers (continued)
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
L1P memory protection page attribute register 23
(controls memory address 0x00E0 3800 - 0x00E0 3FFF)
0x0184 A65C
L1PMPPA23
L1P memory protection page attribute register 24
(controls memory address 0x00E0 4000 - 0x00E0 47FF)
0x0184 A660
0x0184 A664
0x0184 A668
0x0184 A66C
0x0184 A670
0x0184 A674
0x0184 A678
0x0184 A67C
L1PMPPA24
L1PMPPA25
L1PMPPA26
L1PMPPA27
L1PMPPA28
L1PMPPA29
L1PMPPA30
L1PMPPA31
L1P memory protection page attribute register 25
(controls memory address 0x00E0 4800 - 0x00E0 4FFF)
L1P memory protection page attribute register 26
(controls memory address 0x00E0 5000 - 0x00E0 57FF)
L1P memory protection page attribute register 27
(controls memory address 0x00E0 5800 - 0x00E0 5FFF)
L1P memory protection page attribute register 28
(controls memory address 0x00E0 6000 - 0x00E0 67FF)
L1P memory protection page attribute register 29
(controls memory address 0x00E0 6800 - 0x00E0 6FFF)
L1P memory protection page attribute register 30
(controls memory address 0x00E0 7000 - 0x00E0 77FF)
L1P memory protection page attribute register 31
(controls memory address 0x00E0 7800 - 0x00E0 7FFF)
0x0184 A67F – 0x0184 ABFF
0x0184 AC00
-
Reserved
L1DMPFAR
L1DMPFSR
L1DMPFCR
-
L1D memory protection fault address register
L1D memory protection fault status register
L1D memory protection fault command register
Reserved
0x0184 AC04
0x0184 AC08
0x0184 AC0C - 0x0184 ACFF
0x0184 AD00
L1DMPLK0
L1DMPLK1
L1DMPLK2
L1DMPLK3
L1DMPLKCMD
L1DMPLKSTAT
-
L1D memory protection lock key bits [31:0]
L1D memory protection lock key bits [63:32]
L1D memory protection lock key bits [95:64]
L1D memory protection lock key bits [127:96]
L1D memory protection lock key command register
L1D memory protection lock key status register
Reserved
0x0184 AD04
0x0184 AD08
0x0184 AD0C
0x0184 AD10
0x0184 AD14
0x0184 AD18 - 0x0184 ADFF
0x0184 AE00 - 0x0184 AE3F
(2)
-
Reserved
L1D memory protection page attribute register 16
(controls memory address 0x00F0 0000 - 0x00F0 07FF)
0x0184 AE40
0x0184 AE44
0x0184 AE48
0x0184 AE4C
0x0184 AE50
0x0184 AE54
0x0184 AE58
0x0184 AE5C
0x0184 AE60
0x0184 AE64
L1DMPPA16
L1DMPPA17
L1DMPPA18
L1DMPPA19
L1DMPPA20
L1DMPPA21
L1DMPPA22
L1DMPPA23
L1DMPPA24
L1DMPPA25
L1D memory protection page attribute register 17
(controls memory address 0x00F0 0800 - 0x00F0 0FFF)
L1D memory protection page attribute register 18
(controls memory address 0x00F0 1000 - 0x00F0 17FF)
L1D memory protection page attribute register 19
(controls memory address 0x00F0 1800 - 0x00F0 1FFF)
L1D memory protection page attribute register 20
(controls memory address 0x00F0 2000 - 0x00F0 27FF)
L1D memory protection page attribute register 21
(controls memory address 0x00F0 2800 - 0x00F0 2FFF)
L1D memory protection page attribute register 22
(controls memory address 0x00F0 3000 - 0x00F0 37FF)
L1D memory protection page attribute register 23
(controls memory address 0x00F0 3800 - 0x00F0 3FFF)
L1D memory protection page attribute register 24
(controls memory address 0x00F0 4000 - 0x00F0 47FF)
L1D memory protection page attribute register 25
(controls memory address 0x00F0 4800 - 0x00F0 4FFF)
(2) These addresses correspond to the L1D memory protection page attribute registers 0-15 (L1DMPPA0-L1DMPPA15) of the C674x
megamaodule. These registers are not supported for this device.
22
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SPRS563F –SEPTEMBER 2008–REVISED FEBRUARY 2013
Table 2-3. C674x L1/L2 Memory Protection Registers (continued)
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
L1D memory protection page attribute register 26
(controls memory address 0x00F0 5000 - 0x00F0 57FF)
0x0184 AE68
0x0184 AE6C
0x0184 AE70
0x0184 AE74
0x0184 AE78
L1DMPPA26
L1D memory protection page attribute register 27
(controls memory address 0x00F0 5800 - 0x00F0 5FFF)
L1DMPPA27
L1DMPPA28
L1DMPPA29
L1DMPPA30
L1D memory protection page attribute register 28
(controls memory address 0x00F0 6000 - 0x00F0 67FF)
L1D memory protection page attribute register 29
(controls memory address 0x00F0 6800 - 0x00F0 6FFF)
L1D memory protection page attribute register 30
(controls memory address 0x00F0 7000 - 0x00F0 77FF)
L1D memory protection page attribute register 31
(controls memory address 0x00F0 7800 - 0x00F0 7FFF)
0x0184 AE7C
L1DMPPA31
-
0x0184 AE80 – 0x0185 FFFF
Reserved
See Table 2-4 for a detailed top level OMAP-L137 memory map that includes the DSP memory space.
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2.5 Memory Map Summary
Note: Read/Write accesses to illegal or reserved addresses in the memory map may cause undefined
behavior.
Table 2-4. OMAP-L137 Top Level Memory Map
Start Address
End Address
Size
ARM Mem
Map
DSP Mem Map
EDMA Mem PRUSS Mem
Master
Peripheral
Mem Map
LCDC
Mem
Map
Map
Map
0x0000 0000
0x0000 0FFF
4K
-
PRUSS Local
Address
Space
0x0000 1000
0x0070 0000
0x0080 0000
0x0084 0000
0x00E0 0000
0x00E0 8000
0x00F0 0000
0x00F0 8000
0x0180 0000
0x006F FFFF
0x007F FFFF
0x0083 FFFF
0x00DF FFFF
0x00E0 7FFF
0x00EF FFFF
0x00F0 7FFF
0x017F FFFF
0x0180 FFFF
-
(1)
1024K
256K
-
-
DSP L2 ROM
-
-
DSP L2 RAM
DSP L1P RAM
DSP L1D RAM
-
32K
32K
-
-
-
-
-
-
64K
4K
-
-
DSP Interrupt
Controller
-
-
0x0181 0000
0x0181 0FFF
DSP Powerdown
Controller
0x0181 1000
0x0181 2000
0x0181 3000
0x0182 0000
0x0183 0000
0x0181 1FFF
0x0181 2FFF
0x0181 FFFF
0x0182 FFFF
0x0183 FFFF
4K
4K
-
-
-
-
-
DSP Security ID
DSP Revision ID
-
-
-
-
-
-
52K
64K
64K
DSP EMC
DSP Internal
Reserved
0x0184 0000
0x0184 FFFF
64K
4K
-
DSP Memory
System
-
0x0185 0000
0x01BC 0000
0x01BB FFFF
0x01BC 0FFF
-
-
ARM ETB
memory
-
0x01BC 1000
0x01BC 1800
0x01BC 17FF
0x01BC 18FF
2K
ARM ETB reg
-
-
256
ARM Ice
Crusher
0x01BC 1900
0x01C0 0000
0x01C0 8000
0x01C0 8400
0x01C0 8800
0x01C1 0000
0x01C1 1000
0x01C1 2000
0x01C1 4000
0x01C1 5000
0x01C1 6000
0x01C1 7000
0x01C1 8000
0x01C2 0000
0x01C2 1000
0x01BF FFFF
0x01C0 7FFF
0x01C0 83FF
0x01C0 87FF
0x01C0 FFFF
0x01C1 0FFF
0x01C1 1FFF
0x01C1 3FFF
0x01C1 4FFF
0x01C1 5FFF
0x01C1 6FFF
0x01C1 7FFF
0x01C1 FFFF
0x01C2 0FFF
0x01C2 1FFF
32K
1024
1024
EDMA3 Channel Controller
-
-
-
EDMA3 Transfer Controller 0
EDMA3 Transfer Controller 1
-
4K
4K
PSC 0
-
-
PLL Controller
-
4K
SYSCFG
-
-
-
-
-
4K
4K
Timer64P 0
Timer64P 1
-
-
(1) The DSP L2 ROM is used for boot purposes and cannot be programmed with application code
24 Device Overview
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SPRS563F –SEPTEMBER 2008–REVISED FEBRUARY 2013
Table 2-4. OMAP-L137 Top Level Memory Map (continued)
Start Address
End Address
Size
ARM Mem
Map
DSP Mem Map
EDMA Mem PRUSS Mem
Map Map
Master
Peripheral
Mem Map
LCDC
Mem
Map
0x01C2 2000
0x01C2 3000
0x01C2 4000
0x01C2 5000
0x01C4 0000
0x01C4 1000
0x01C4 2000
0x01C4 3000
0x01D0 0000
0x01D0 1000
0x01D0 2000
0x01D0 3000
0x01D0 4000
0x01D0 5000
0x01D0 6000
0x01D0 7000
0x01D0 8000
0x01D0 9000
0x01D0 A000
0x01D0 B000
0x01D0 C000
0x01D0 D000
0x01D0 E000
0x01E0 0000
0x01E1 0000
0x01E1 1000
0x01E1 2000
0x01E1 3000
0x01E1 4000
0x01E1 5000
0x01E1 6000
0x01E2 0000
0x01E2 2000
0x01E2 3000
0x01E2 4000
0x01E2 5000
0x01E2 6000
0x01E2 7000
0x01E2 8000
0x01E2 9000
0x01F0 0000
0x01F0 1000
0x01F0 2000
0x01F0 3000
0x01F0 4000
0x01F0 5000
0x01C2 2FFF
0x01C2 3FFF
0x01C2 4FFF
0x01C3 FFFF
0x01C4 0FFF
0x01C4 1FFF
0x01C4 2FFF
0x01CF FFFF
0x01D0 0FFF
0x01D0 1FFF
0x01D0 2FFF
0x01D0 3FFF
0x01D0 4FFF
0x01D0 5FFF
0x01D0 6FFF
0x01D0 7FFF
0x01D0 8FFF
0x01D0 9FFF
0x01D0 AFFF
0x01D0 BFFF
0x01D0 CFFF
0x01D0 DFFF
0x01DF FFFF
0x01E0 FFFF
0x01E1 0FFF
0x01E1 1FFF
0x01E1 2FFF
0x01E1 3FFF
0x01E1 4FFF
0x01E1 5FFF
0x01E1 FFFF
0x01E2 1FFF
0x01E2 2FFF
0x01E2 3FFF
0x01E2 4FFF
0x01E2 5FFF
0x01E2 6FFF
0x01E2 7FFF
0x01E2 8FFF
0x01EF FFFF
0x01F0 0FFF
0x01F0 1FFF
0x01F0 2FFF
0x01F0 3FFF
0x01F0 4FFF
0x01F0 5FFF
4K
4K
I2C 0
-
-
-
RTC
-
-
4K
4K
4K
MMC/SD 0
SPI 0
-
-
-
UART 0
-
4K
4K
4K
McASP 0 Control
-
-
-
McASP 0 AFIFO Control
McASP 0 Data
-
4K
4K
4K
McASP 1 Control
-
-
-
McASP 1 AFIFO Control
McASP 1 Data
-
4K
4K
4K
McASP 2 Control
-
-
-
McASP 2 AFIFO Control
McASP 2 Data
-
4K
4K
UART 1
-
-
UART 2
-
USB0
64K
4K
-
-
UHPI
-
4K
4K
4K
4K
SPI 1
-
-
-
-
LCD Controller
Memory Protection Unit 1 (MPU 1)
Memory Protection Unit 2 (MPU 2)
-
EMAC Control Module RAM
EMAC Control Module Registers
EMAC Control Registers
EMAC MDIO port
USB1
8K
4K
4K
4K
4K
4K
4K
4K
-
-
-
-
-
-
-
-
GPIO
PSC 1
I2C 1
-
4K
4K
4K
4K
4K
4K
eHRPWM 0
-
-
-
-
-
-
HRPWM 0
eHRPWM 1
HRPWM 1
eHRPWM 2
HRPWM 2
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Table 2-4. OMAP-L137 Top Level Memory Map (continued)
Start Address
End Address
Size
ARM Mem
Map
DSP Mem Map
EDMA Mem PRUSS Mem
Master
Peripheral
Mem Map
LCDC
Mem
Map
Map
Map
0x01F0 6000
0x01F0 7000
0x01F0 8000
0x01F0 9000
0x01F0 A000
0x01F0 B000
0x1170 0000
0x1180 0000
0x1184 0000
0x11E0 0000
0x11E0 8000
0x11F0 0000
0x11F0 8000
0x4000 0000
0x4800 0000
0x6000 0000
0x6200 0000
0x6400 0000
0x6600 0000
0x6800 0000
0x6800 8000
0x8000 0000
0x8002 0000
0xB000 0000
0xB000 8000
0xC000 0000
0xD000 0000
0xFFFD 0000
0x01F0 6FFF
0x01F0 7FFF
0x01F0 8FFF
0x01F0 9FFF
0x01F0 AFFF
0x116F FFFF
0x117F FFFF
0x1183 FFFF
0x11DF FFFF
0x11E0 7FFF
0x11EF FFFF
0x11F0 7FFF
0x3FFF FFFF
0x47FF FFFF
0x5FFF FFFF
0x61FF FFFF
0x63FF FFFF
0x65FF FFFF
0x67FF FFFF
0x6800 7FFF
0x7FFF FFFF
0x8001 FFFF
0xAFFF FFFF
0xB000 7FFF
0xBFFF FFFF
0xCFFF FFFF
0xFFFC FFFF
0xFFFD FFFF
4K
4K
4K
4K
4K
ECAP 0
ECAP 1
ECAP 2
EQEP 0
EQEP 1
-
-
-
-
-
-
(2)
1024K
256K
DSP L2 ROM
-
-
DSP L2 RAM
-
32K
32K
DSP L1P RAM
-
-
-
-
DSP L1D RAM
-
128M
EMIFA SDRAM data (CS0)
32M
32M
32M
32M
32K
EMIFA async data (CS2)
EMIFA async data (CS3)
EMIFA async data (CS4)
EMIFA async data (CS5)
EMIFA Control Registers
-
-
-
-
-
-
128K
32K
Shared RAM
-
-
EMIFB Control Registers
-
256M
64K
EMIFB SDRAM Data
-
ARM local
ROM
-
0xFFFE 0000
0xFFFE E000
0xFFFE DFFF
0xFFFE FFFF
-
8K
8K
ARM Interrupt
Controller
-
ARM Local
RAM (PRU0
only)
0xFFFF 0000
0xFFFF 1FFF
ARM local
RAM
-
0xFFFF 2000
0xFFFF FFFF
-
(2) The DSP L2 ROM is used for boot purposes and cannot be programmed with application code
26
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SPRS563F –SEPTEMBER 2008–REVISED FEBRUARY 2013
2.6 Pin Assignments
Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in
the smallest possible package. Pin multiplexing is controlled using a combination of hardware
configuration at device reset and software programmable register settings.
2.6.1 Pin Map (Bottom View)
Figure 2-3 shows the pin assignments for the ZKB package.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
EMA_D[0]/
MMCSD_DAT[0]/
UHPI_HD[0]/
GP0[0]/
SPI0_CLK/
EQEP1I/
GP5[2]/
SPI1_CLK/
EQEP1S/
GP5[7]/
EMA_D[9]/
UHPI_HD[9]/
LCD_D[9]/
GP0[9]
EMA_CS[3]/ EMA_CS[0]/
AMUTE2/
GP2[6]
EMA_A[0]/
LCD_D[7]/
GP1[0]
EMA_A[4]/
LCD_D[3]/
GP1[4]
EMA_A[8]/
LCD_PCLK/
GP1[8]
AXR1[0]/
GP4[0]
AXR1[11]/
GP5[11]
EMA_SDCKE/
GP2[0]
T
R
P
N
M
L
T
R
P
N
M
L
VSS
VSS
UHPI_HAS/
GP2[4]
VSS
VSS
BOOT[2]
BOOT[7]
BOOT[12]
UART0_RXD/
I2C0_SDA/
TM64P0_IN12/ UART2_RXD/
GP5[8]/
BOOT[8]
SPI0_ENA/
UART0_CTS/
EQEP0A/
GP5[3]/
EMA_A[1]/
MMCSD_CLK/
UHPI_HCNTL0/
GP1[1]
EMA_CLK/
OBSCLK/
AHCLKR2/
GP1[15]
EMA_D[2]/
EMA_D[10]/
EMA_D[1]/
SPI0_SOMI[0]/
EQEP0I/
GP5[0]/
EMA_OE/
UHPI_HDS1/
AXR0[13]/
GP2[7]
SPI1_ENA/
EMA_BA[0]/
LCD_D[4]/
GP1[14]
EMA_A[5]/ EMA_A[9]/
LCD_D[2]/ LCD_HSYNC/
GP1[5]
AXR1[1]/
GP4[1]
MMCSD_DAT[2]/ UHPI_HD[10]/ MMCSD_DAT[1]/
UHPI_HD[2]/
GP0[2]
DVDD
DVDD
LCD_D[10]/
GP0[10]
UHPI_HD[1]/
GP0[1]
GP5[12]
GP1[9]
BOOT[0]
BOOT[3]
UART0_TXD/
I2C0_SCL/
TM64P0_OUT12/ UART2_TXD/
GP5[9]/
BOOT[9]
EMA_WE_
DQM[1]/
UHPI_HDS2/
AXR0[14]/
GP2[8]
SPI1_SOMI[0]/ SPI0_SIMO[0]/
I2C1_SCL/
GP5[5]/
EMA_BA[1]/
LCD_D[5]/ MMCSD_CMD/
UHPI_HHWIL/ UHPI_HCNTL1/
EMA_A[2]/
EMA_A[11]/
LCD_AC_
ENB_CS/
GP1[11]
EMA_D[4]/
EMA_D[12]/
EMA_D[3]/
EMA_D[11]/
EMA_CS[2]/
UHPI_HCS/
GP2[5]/
AXR1[3]/
EQEP1A/
GP4[3]
SPI1_SCS[0]/
EMA_A[6]/
LCD_D[1]/
GP1[6]
AXR1[2]/
GP4[2]
EQEP0S/
GP5[1]/
BOOT[1]
MMCSD_DAT[4]/ UHPI_HD[12]/ MMCSD_DAT[3]/ UHPI_HD[11]/
UHPI_HD[4]/
GP0[4]
LCD_D[12]/
GP0[12]
UHPI_HD[3]/
GP0[3]
LCD_D[11]
GP0[11]
GP5[13]
BOOT[5]
GP1[13]
GP1[2]
BOOT[15]
SPI0_SCS[0]/
UART0_RTS/
SPI1_SIMO[0]/
I2C1_SDA/
GP5[6]/
EMA_D[8]/
EMA_D[6]/
EMA_D[14]/
EMA_D[5]/
EMA_D[13]/
AXR1[5]/
EPWM2B/
GP4[5]
AXR1[4]/
EQEP1B/
GP4[4]
EMA_WAIT[0]/ EMA_RAS/ EMA_A[10]/ EMA_A[3]/
UHPI_HRDY/ EMA_CS[5]/ LCD_VSYNC/ LCD_D[6]/
GP2[10]
EMA_A[7]/
LCD_D[0]/
GP1[7]
EMA_A[12]/
LCD_MCLK/
GP1[12]
AXR1[10]/
UHPI_HD[8]/ MMCSD_DAT[6]/ UHPI_HD[14]/ MMCSD_DAT[5]/ UHPI_HD[13]/
EQEP0B/
GP5[10]
LCD_D[8]/
GP0[8]
UHPI_HD[6]/
GP0[6]
LCD_D[14]/
GP0[14]
UHPI_HD[5]/
GP0[5]
LCD_D[13]/
GP0[13]
GP5[4]/
BOOT[4]
GP2[2]
GP1[10]
GP1[3]
BOOT[6]
EMA_D[7]/
MMCSD_DAT[7]/
UHPI_HD[7]/
GP0[7]/
EMA_WE/
UHPI_HRW/
AXR0[12]/
GP2[3]/
EMA_WE_
DQM[0]/
UHPI_HINT/
AXR0[15]/
GP2[9]
EMA_D[15]/
UHPI_HD[15]/
LCD_D[15]/
GP0[15]
AXR1[8]/
EPWM1A/
GP4[8]
AXR1[7]/
EPWM1B/
GP4[7]
AXR1[6]/
EPWM2A/
GP4[6]
AXR1[9]/
GP4[9]
DVDD
VSS
VSS
DVDD
DVDD
VSS
VSS
DVDD
DVDD
DVDD
CVDD
RVDD
DVDD
DVDD
BOOT[14]]
BOOT[13]
ACLKR1/
ECAP2/
APWM2/
GP4[12]
EMA_CAS/
EMB_D[23] EMA_CS[4]/
GP2[1]
AHCLKR1/
GP4[11]
AFSR1/
GP4[13]
AMUTE0/
RESETOUT
DVDD
CVDD
CVDD
CVDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DVDD
CVDD
CVDD
CVDD
CVDD
DVDD
VSS
EMB_CAS
EMB_D[20]
EMB_D[22]
AFSX1/
EPWMSYNCI/
EPWMSYNCO/
GP4[10]
AHCLKX1/
EPWM0B/
GP3[14]
ACLKX1/
EPWM0A/
GP3[15]
EMB_WE_
DQM[0]/
GP5[15]
K
J
K
J
DVDD
CVDD
CVDD
CVDD
CVDD
RSV1
CVDD
CVDD
CVDD
CVDD
VSS
EMB_WE
EMB_D[21]
RTCK/GP7[14]
EMB_D[5]/
GP6[5]
EMB_D[6]/
GP6[6]
EMB_D[7]/
GP6[7]
TMS
TDI
TDO
TCK
TRST
EMB_D[19]
EMB_D[17]
EMB_D[31]
EMB_D[29]
EMB_D[27]
EMU0/GP7[15]
EMB_D[3]/
GP6[3]
EMB_D[4]/
GP6[4]
USB0_
VDDA33
H
G
F
H
G
F
RTC_XI
RTC_XO
RTC_VSS
OSCIN
RV
DD
CV
DD
CV
DD
EMB_D[18]
EMB_D[16]
EMB_D[30]
EMB_D[28]
NC
EMB_D[1]/
GP6[1]
EMB_D[2]/
GP6[2]
RTC_CVDD
OSCOUT
RESET
USB0_DM
DV
DD
DV
DD
DV
DD
EMB_D[15]/
GP6[15]
EMB_D[0]/
GP6[0]
NC
USB0_DP
USB0_
DRVVBUS/
GP4[15]
EMB_D[13]/
GP6[13]
EMB_D[14]/
GP6[14]
USB0_
VDDA18
E
D
C
B
A
E
D
C
B
A
PLL0_VSSA
PLL0_VDDA
OSCVSS
USB0_ID
VSS
VSS
DV
DD
DV
DD
VSS
DV
DD
AXR0[6]/ AXR0[2]/
RMII_RXER/ RMII_TXEN/
AMUTE1/
USB0_VBUS EPWMTZ/
GP4[14]
AFSX0/
GP2[13]/
BOOT[10]
UART1_TXD/
AXR0[10]/
GP3[10]
EMB_A[0]/
GP7[2]
EMB_A[4]/
GP7[6]
EMB_A[8]/
GP7[10]
EMB_D[9]/
GP6[9]
EMB_D[10]/ EMB_D[11]/ EMB_D[12]/
GP6[11]
EMB_CS[0]
ACLKR2/
GP3[6]
AXR2[3]/
GP3[2]
GP6[10]
GP6[12]
ACLKX0/
ECAP0/
APWM0/
GP2[12]
AXR0[5]/ AXR0[1]/
RMII_RXD[1]/ RMII_TXD[1]/ EMB_BA[0]/
UART1_RXD/
AXR0[9]/
GP3[9]
EMB_WE_
DQM[1]/
GP5[14]
EMB_A[1]/
GP7[3]
EMB_A[5]/
GP7[7]
EMB_A[9]/
GP7[11]
EMB_D[8]/
GP6[8]
USB1_
VDDA33
USB1_
VDDA18
USB0_
VDDA12
AFSR0/
GP3[12]
EMB_SDCKE EMB_CLK
AFSX2/
GP3[5]
ACLKX2/
GP3[1]
GP7[1]
AHCLKX0/
AHCLKX2/
USB_
REFCLKIN/
GP2[11]
ACLKR0/
ECAP1/
APWM1/
GP2[15]
AXR0[4]/ AXR0[0]/
RMII_RXD[0]/ RMII_TXD[0]/ EMB_BA[1]/
AXR0[8]/
MDIO_D/
GP3[8]
EMB_A[2]/
GP7[4]
EMB_A[6]/
GP7[8]
EMB_A[11]/
GP7[13]
EMB_A[12]/
GP3[13]
EMB_WE_
EMB_D[25]
DQM[2]
RSV2
VSS
USB1_DM
DVDD
AXR2[1]/
GP3[4]
AFSR2/
GP3[0]
GP7[0]
AHCLKR0/
RMII_MHZ_ AXR0[11]/
AXR0[3]/
RMII_CRS_DV/
AXR2[2]/
AXR0[7]/
MDIO_CLK/
GP3[7]
EMB_A[10]/
GP7[12]
EMB_A[3]/
GP7[5]
EMB_A[7]/
GP7[9]
EMB_WE_
DQM[3]
VSS
VSS
USB1_DP
3
50_CLK/
GP2[14]/
BOOT[11]
AXR2[0]/
GP3[11]
EMB_RAS
8
EMB_D[24]
13
EMB_D[26]
14
VSS
VSS
GP3[3]
1
2
4
5
6
7
9
10
11
12
15
16
Figure 2-3. Pin Map (ZKB)
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2.7 Terminal Functions
Table 2-5 to Table 2-25 identify the external signal names, the associated pin/ball numbers along with the
mechanical package designator, the pin type (I, O, IO, OZ, or PWR), whether the pin/ball has any internal
pullup/pulldown resistors, whether the pin/ball is configurable as an IO in GPIO mode, and a functional pin
description.
2.7.1 Device Reset and JTAG
Table 2-5. Reset and JTAG Terminal Functions
PIN NO
SIGNAL NAME
TYPE(1)
PULL(2)
DESCRIPTION
ZKB
RESET
Device reset input
Reset output. Multiplexed with McASP0 mute output.
JTAG
RESET
G3
L4
I
AMUTE0/ RESETOUT
O(3)
IPD
TMS
J1
J2
J3
H3
J4
J5
K1
I
I
IPU
IPU
IPD
IPU
IPD
IPU
IPD
JTAG test mode select
JTAG test data input
JTAG test data output
JTAG test clock
TDI
TDO
O
I
TCK
TRST
I
JTAG test reset
EMU[0]/GP7[15]
RTCK/GP7[14]
I/O
I/O
Emulation Signal
JTAG Test Clock Return Clock Output
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
(3) Open drain mode for RESETOUT function.
2.7.2 High-Frequency Oscillator and PLL
Table 2-6. High-Frequency Oscillator and PLL Terminal Functions
PIN NO
SIGNAL NAME
TYPE(1)
PULL(2)
DESCRIPTION
ZKB
EMA_CLK/OBSCLK/AHCLKR2/
GP1[15]
R12
O
IPU
PLL Observation Clock
1.2-V OSCILLATOR
Oscillator input
Oscillator output
Oscillator ground (for filter only)
1.2-V PLL
OSCIN
F2
F1
E2
I
OSCOUT
OSCVSS
O
GND
PLL0_VDDA
PLL0_VSSA
D1
E1
PWR
GND
PLL analog VDD (1.2-V filtered supply)
PLL analog VSS (for filter)
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
28
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2.7.3 Real-Time Clock and 32-kHz Oscillator
Table 2-7. Real-Time Clock (RTC) and 1.2-V, 32-kHz Oscillator Terminal Functions
PIN NO
SIGNAL NAME
RTC_CVDD
TYPE(1)
PULL(2)
DESCRIPTION
ZKB
G1
H1
PWR
I
RTC module core power (isolated from rest of chip CVDD)
RTC_XI
RTC_XO
RTC_Vss
Low-frequency (32-kHz) oscillator receiver for real-time clock
Low-frequency (32-kHz) oscillator driver for real-time clock
Oscillator ground (for filter)
H2
O
G2
GND
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
2.7.4 External Memory Interface A (ASYNC, SDRAM)
Table 2-8. External Memory Interface A (EMIFA) Terminal Functions
PIN
NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
ZKB
M16
N14
N16
P14
P16
R14
T14
N12
EMA_D[15]/UHPI_HD[15]/LCD_D[15]/GP0[15]
EMA_D[14]/UHPI_HD[14]/LCD_D[14]/GP0[14]
EMA_D[13]/UHPI_HD[13]/LCD_D[13]/GP0[13]
EMA_D[12]/UHPI_HD[12]/LCD_D[12]/GP0[12]
EMA_D[11]/UHPI_HD[11]/LCD_D[11]/GP0[11]
EMA_D[10]/UHPI_HD[10]/LCD_D[10]/GP0[10]
EMA_D[9]/UHPI_HD[9]/LCD_D[9]/GP0[9]
EMA_D[8]/UHPI_HD[8]/LCD_D[8]/GP0[8]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
UHPI, LCD,
GPIO
MMC/SD, UHPI,
GPIO, BOOT
EMIFA data bus
EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/BOOT[13]
M15
I/O
IPU
EMA_D[6]/MMCSD_DAT[6]/UHPI_HD[6]/GP0[6]
EMA_D[5]/MMCSD_DAT[5]/UHPI_HD[5]/GP0[5]
EMA_D[4]/MMCSD_DAT[4]/UHPI_HD[4]/GP0[4]
EMA_D[3]/MMCSD_DAT[3]/UHPI_HD[3]/GP0[3]
EMA_D[2]/MMCSD_DAT[2]/UHPI_HD[2]/GP0[2]
EMA_D[1]/MMCSD_DAT[1]/UHPI_HD[1]/GP0[1]
N13
N15
P13
P15
R13
R15
I/O
I/O
I/O
I/O
I/O
I/O
IPU
IPU
IPU
IPU
IPU
IPU
MMC/SD, UHPI,
GPIO
MMC/SD, UHPI,
GPIO, BOOT
EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/BOOT[12]
T13
I/O
IPU
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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Table 2-8. External Memory Interface A (EMIFA) Terminal Functions (continued)
PIN
NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
ZKB
N11
P11
N8
EMA_A[12]/LCD_MCLK/GP1[12]
O
O
O
O
O
O
O
O
O
O
O
O
O
IPU
IPU
IPU
IPU
IPU
IPD
IPD
IPD
IPD
IPD
IPU
IPU
IPD
EMA_A[11]/LCD_AC_ENB_CS/GP1[11]
EMA_A[10]/LCD_VSYNC/GP1[10]
EMA_A[9]/LCD_HSYNC/GP1[9]
EMA_A[8]/LCD_PCLK/GP1[8]
R11
T11
N10
P10
R10
T10
N9
LCD, GPIO
EMIFA address bus
EMA_A[7]/LCD_D[0]/GP1[7]
EMA_A[6]/LCD_D[1]/GP1[6]
EMA_A[5]/LCD_D[2]/GP1[5]
EMA_A[4]/LCD_D[3]/GP1[4]
EMA_A[3]/LCD_D[6]/GP1[3]
EMA_A[2]/MMCSD_CMD/UHPI_HCNTL1/GP1[2]
EMA_A[1]/MMCSD_CLK/UHPI_HCNTL0/GP1[1]
EMA_A[0]/LCD_D[7]/GP1[0]
P9
MMCSD, UHPI,
GPIO
R9
EMIFA address bus
T9
LCD, GPIO
LCD, UHPI,
GPIO
EMA_BA[1]/LCD_D[5]/UHPI_HHWIL/GP1[13]
EMA_BA[0]/LCD_D[4]/GP1[14]
P8
R8
O
O
O
IPU
IPU
IPU
EMIFA bank address
EMIFA clock
LCD, GPIO
McASP2, GPIO,
OBSCLK
EMA_CLK/OBSCLK/AHCLKR2/GP1[15]
R12
EMIFA SDRAM clock
enable
EMA_SDCKE/GP2[0]
T12
N7
O
O
O
IPU
IPU
IPU
GPIO
EMIFA SDRAM row
address strobe
EMA_RAS/EMA_CS[5]/GP2[2]
EMA_CAS/EMA_CS[4]/GP2[1]
EMIF A chip
select, GPIO
EMIFA SDRAM column
address strobe
L16
EMA_RAS/EMA_CS[5] /GP2[2]
EMA_CAS/EMA_CS[4] /GP2[1]
EMA_CS[3]/AMUTE2/GP2[6]
N7
L16
T7
O
O
O
IPU
IPU
IPU
EMIF A
SDRAM, GPIO
EMIFA Async Chip
Select
McASP2, GPIO
UHPI, GPIO,
BOOT
EMA_CS[2]/UHPI_HCS/GP2[5]/BOOT[15]
EMA_CS[0]/UHPI_HAS/GP2[4]
P7
T8
O
O
O
IPU
IPU
IPU
EMIFA SDRAM chip
select
UHPI, GPIO
UHPI, MCASP0, EMIFA SDRAM write
GPIO, BOOT
EMA_WE/UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14]
M13
enable
EMIFA write
EMA_WE_DQM[1]/UHPI_HDS2/AXR0[14]/GP2[8]
EMA_WE_DQM[0]/UHPI_HINT/AXR0[15]/GP2[9]
P12
M14
O
O
IPU
IPU
enable/data mask for
EMA_D[15:8]
UHPI, McASP,
GPIO
EMIFA write
enable/data mask for
EMA_D[7:0]
UHPI, McASP0,
GPIO
EMA_OE/UHPI_HDS1/AXR0[13]/GP2[7]
EMA_WAIT[0]/UHPI_HRDY/GP2[10]
R7
N6
O
I
IPU
IPU
EMIFA output enable
EMIFA wait
input/interrupt
UHPI, GPIO
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2.7.5 External Memory Interface B (only SDRAM)
Table 2-9. External Memory Interface B (EMIFB) Terminal Functions
PIN NO
ZKB
G14
F15
F14
E15
E14
A14
B14
A13
L15
L14
K16
K13
J14
SIGNAL NAME
TYPE(1)
PULL(2)
MUXED
DESCRIPTION
EMB_D[31]
EMB_D[30]
EMB_D[29]
EMB_D[28]
EMB_D[27]
EMB_D[26]
EMB_D[25]
EMB_D[24]
EMB_D[23]
EMB_D[22]
EMB_D[21]
EMB_D[20]
EMB_D[19]
EMB_D[18]
EMB_D[17]
EMB_D[16]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
H15
H14
G15
F13
E16
E13
D16
D15
D14
D13
C16
J16
EMIFB SDRAM data bus
EMB_D[15]/GP6[15]
EMB_D[14]/GP6[14]
EMB_D[13]/GP6[13]
EMB_D[12]/GP6[12]
EMB_D[11]/GP6[11]
EMB_D[10]/GP6[10]
EMB_D[9]/GP6[9]
EMB_D[8]/GP6[8]
EMB_D[7]/GP6[7]
EMB_D[6]/GP6[6]
EMB_D[5]/GP6[5]
EMB_D[4]/GP6[4]
EMB_D[3]/GP6[3]
EMB_D[2]/GP6[2]
EMB_D[1]/GP6[1]
EMB_D[0]/GP6[0]
EMB_A[12]/GP3[13]
EMB_A[11]/GP7[13]
EMB_A[10]/GP7[12]
EMB_A[9]/GP7[11]
EMB_A[8]/GP7[10]
EMB_A[7]/GP7[9]
EMB_A[6]/GP7[8]
EMB_A[5]/GP7[7]
GPIO
J15
J13
H16
H13
G16
G13
F16
B15
B12
A9
O
O
C12
D12
A11
B11
C11
O
EMIFB SDRAM row/column
address bus
GPIO
O
O
O
O
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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Table 2-9. External Memory Interface B (EMIFB) Terminal Functions (continued)
PIN NO
ZKB
D11
A10
B10
C10
D10
B9
SIGNAL NAME
TYPE(1)
PULL(2)
MUXED
DESCRIPTION
EMB_A[4]/GP7[6]
EMB_A[3]/GP7[5]
EMB_A[2]/GP7[4]
EMB_A[1]/GP7[3]
EMB_A[0]/GP7[2]
EMB_BA[1]/GP7[0]
EMB_BA[0]/GP7[1]
EMB_CLK
O
O
O
O
O
O
O
O
O
O
IPD
IPD
IPD
IPD
IPD
IPU
IPU
IPU
IPU
IPU
EMIFB SDRAM row/column
address
GPIO
EMIFB SDRAM bank address
C9
C14
C13
K15
EMIF SDRAM clock
EMB_SDCKE
EMIFB SDRAM clock enable
EMIFB write enable
EMB_WE
EMIFB SDRAM row address
strobe
EMB_RAS
A8
O
IPU
EMB_CAS
L13
D9
O
O
O
O
O
O
IPU
IPU
IPU
IPU
IPU
IPU
EMIFB column address strobe
EMIFB SDRAM chip select 0
EMB_CS[0]
EMB_WE_DQM[3]
EMB_WE_DQM[2]
A12
B13
C15
K14
EMIFB write enable/data mask
for EMB_D
EMB_WE_DQM[1] /GP5[14]
EMB_WE_DQM[0] /GP5[15]
GPIO
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SPRS563F –SEPTEMBER 2008–REVISED FEBRUARY 2013
2.7.6 Serial Peripheral Interface Modules (SPI0, SPI1)
Table 2-10. Serial Peripheral Interface (SPI) Terminal Functions
PIN
NO
SIGNAL NAME
TYPE(1)
SPI0
PULL(2)
MUXED
DESCRIPTION
ZKB
UART0, EQEP0B,
GPIO, BOOT
SPI0_SCS[0] /UART0_RTS/EQEP0B/GP5[4]/BOOT[4]
N4
I/O
IPU
SPI0 chip select
SPI0 enable
UART0, EQEP0A,
GPIO, BOOT
SPI0_ENA /UART0_CTS/EQEP0A/GP5[3]/BOOT[3]
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2]
R5
T5
P6
I/O
I/O
I/O
IPU
IPD
IPD
eQEP1, GPIO, BOOT SPI0 clock
SPI0 data slave-in-
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1]
master-out
eQEP0, GPIO, BOOT
SPI0 data slave-out-
master-in
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0]
R6
I/O
IPD
SPI1
SPI1_SCS[0] /UART2_TXD/GP5[13]
SPI1_ENA /UART2_RXD/GP5[12]
SPI1_CLK/EQEP1S/GP5[7]/BOOT[7]
P4
R4
T6
I/O
I/O
I/O
IPU
IPU
IPD
SPI1 chip select
SPI1 enable
UART2, GPIO
eQEP1, GPIO, BOOT SPI1 clock
SPI1 data slave-in-
SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6]
SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5]
N5
P5
I/O
I/O
IPU
IPU
master-out
I2C1, GPIO, BOOT
SPI1 data slave-out-
master-in
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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2.7.7 Enhanced Capture/Auxiliary PWM Modules (eCAP0, eCAP1, eCAP2)
The eCAP Module pins function as either input captures or auxilary PWM 32-bit outputs, depending upon
how the eCAP module is programmed.
Table 2-11. Enhanced Capture Module (eCAP) Terminal Functions
PIN
NO
SIGNAL NAME
TYPE(1)
PULL(2)
MUXED
DESCRIPTION
ZKB
eCAP0
enhanced capture 0
input or auxiliary
PWM 0 output
ACLKX0/ECAP0/APWM0/GP2[12]
C5
I/O
I/O
I/O
IPD
IPD
IPD
McASP0, GPIO
McASP0, GPIO
McASP1, GPIO
eCAP1
enhanced capture 1
input or auxiliary
PWM 1 output
ACLKR0/ECAP1/APWM1/GP2[15]
ACLKR1/ECAP2/APWM2/GP4[12]
B4
eCAP2
L2
enhanced capture 2
input or auxiliary
PWM 2 output
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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2.7.8 Enhanced Pulse Width Modulators (eHRPWM0, eHRPWM1, eHRPWM2)
Table 2-12. Enhanced Pulse Width Modulator (eHRPWM) Terminal Functions
PIN NO
SIGNAL NAME
TYPE(1)
PULL(2)
MUXED
DESCRIPTION
ZKB
eHRPWM0
eHRPWM0 A output
(with high-resolution)
ACLKX1/EPWM0A/GP3[15]
K3
K2
D4
I/O
I/O
I/O
IPD
IPD
IPD
McASP1, GPIO
AHCLKX1/EPWM0B/GP3[14]
AMUTE1/EPWMTZ/GP4[14]
eHRPWM0 B output
McASP1, eHRPWM1, eHRPWM0 trip zone
GPIO, eHRPWM2
input
Sync input to
McASP1, eHRPWM0, eHRPWM0 module or
AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10]
K4
I/O
IPD
GPIO
sync output to external
PWM
eHRPWM1
eHRPWM1 A output
(with high-resolution)
AXR1[8]/EPWM1A/GP4[8]
AXR1[7]/EPWM1B/GP4[7]
AMUTE1/EPWMTZ/GP4[14]
M2
M3
D4
I/O
I/O
IPD
IPD
IPD
McASP1, GPIO
eHRPWM1 B output
McASP1, eHRPWM1, eHRPWM1 trip zone
I/O
GPIO, eHRPWM2
input
eHRPWM2
I/O
eHRPWM2 A output
(with high-resolution)
AXR1[6]/EPWM2A/GP4[6]
AXR1[5]/EPWM2B/GP4[5]
AMUTE1/EPWMTZ/GP4[14]
M4
N1
D4
IPD
IPD
IPD
McASP1, GPIO
I/O
eHRPWM2 B output
McASP1, eHRPWM1, eHRPWM2 trip zone
GPIO, eHRPWM2 input
I/O
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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2.7.9 Enhanced Quadrature Encoder Pulse Module (eQEP)
Table 2-13. Enhanced Quadrature Encoder Pulse Module (eQEP) Terminal Functions
PIN
NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
ZKB
eQEP0
eQEP0A quadrature
input
SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3]
SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4]
R5
N4
I
I
IPU
IPU
SPI0, UART0, GPIO,
BOOT
eQEP0B quadrature
input
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0]
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1]
R6
P6
I
I
IPD
IPD
eQEP0 index
eQEP0 strobe
SPI0, GPIO, BOOT
McASP1, GPIO
eQEP1
eQEP1A quadrature
input
AXR1[3]/EQEP1A/GP4[3]
AXR1[4]/EQEP1B/GP4[4]
P1
N2
I
I
IPD
IPD
eQEP1B quadrature
input
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2]
SPI1_CLK/EQEP1S/GP5[7]/BOOT[7]
T5
T6
I
I
IPD
IPD
SPI0, GPIO, BOOT
SPI1, GPIO, BOOT
eQEP1 index
eQEP1 strobe
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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SPRS563F –SEPTEMBER 2008–REVISED FEBRUARY 2013
2.7.10 Boot
Table 2-14. Boot Mode Selection Terminal Functions(1)
PIN NO
ZKB
P7
SIGNAL NAME
TYPE(2)
PULL(3)
MUXED
DESCRIPTION
EMA_CS[2]/UHPI_HCS/GP2[5]/BOOT[15]
I
I
IPU
IPU
EMIFA, UHPI, GPIO
EMIFA, UHPI,
McASP0, GPIO
EMA_WE/UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14]
M13
EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/BOOT[13]
EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/BOOT[12]
M15
T13
I
I
IPU
IPU
EMIFA, MMC/SD,
UHPI, GPIO
McASP0, EMAC,
GPIO
AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11]
AFSX0/GP2[13]/BOOT[10]
A4
D5
P3
I
I
I
IPD
IPD
IPU
McASP0, GPIO
UART0, I2C0, Timer0,
GPIO
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]
UART0, I2C0, Timer0,
GPIO
Boot Mode
Selection Pins
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8]
R3
I
IPU
SPI1_CLK/EQEP1S/GP5[7]/BOOT[7]
SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6]
SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5]
T6
N5
P5
I
I
I
IPD
IPU
IPU
SPI1, eQEP1, GPIO
SPI1, I2C1, GPIO
SPI0, UART0,
eQEP0, GPIO
SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4]
SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3]
N4
R5
I
I
IPU
IPU
SPI0, UART0,
eQEP0, GPIO
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2]
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1]
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0]
T5
P6
R6
I
I
I
IPD
IPD
IPD
SPI0, eQEP1, GPIO
SPI0, eQEP0, GPIO
(1) Boot decoding will be defined in the ROM datasheet.
(2) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(3) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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2.7.11 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)
Table 2-15. Universal Asynchronous Receiver/Transmitter (UART) Terminal Functions
PIN
NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
ZKB
UART0
I2C0, BOOT,
Timer0, GPIO,
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8]
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]
SPI0_SCS[0]/ UART0_RTS /EQEP0B/GP5[4]/BOOT[4]
SPI0_ENA/ UART0_CTS /EQEP0A/GP5[3]/BOOT[3]
R3
P3
N4
R5
I
IPU
IPU
IPU
IPU
UART0 receive data
I2C0, Timer0, GPIO, UART0 transmit
BOOT
O
O
I
data
UART0 ready-to-
send output
SPI0, eQEP0, GPIO,
BOOT
UART0 clear-to-
send input
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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Table 2-15. Universal Asynchronous Receiver/Transmitter (UART) Terminal Functions (continued)
PIN
NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
McASP0, GPIO
SPI1, GPIO
DESCRIPTION
ZKB
UART1
C6
UART1_RXD/AXR0[9]/GP3[9](1)
I
IPD
IPD
UART1 receive data
UART1 transmit
data
UART1_TXD/AXR0[10]/GP3[10](1)
D6
O
UART2
SPI1_ENA/UART2_RXD/GP5[12]
SPI1_SCS[0]/UART2_TXD/GP5[13]
R4
I
IPU
IPU
UART2 receive data
UART2 transmit
data
P4
O
(1) As these signals are internally pulled down while the device is in reset, it is necessary to externally pull them high with resistors if
UART1 boot mode is used. Please see the OMAP-L137 Applications Processor System Reference Guide - Literature Number
SPRUG84 for more for details on entering UART1 boot mode.
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2.7.12 Inter-Integrated Circuit Modules(I2C0, I2C1)
Table 2-16. Inter-Integrated Circuit (I2C) Terminal Functions
PIN
NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
ZKB
I2C0
UART0, Timer0,
GPIO, BOOT
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8]
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]
R3
P3
I/O
I/O
IPU
IPU
I2C0 serial data
I2C0 serial clock
UART0, Timer0,
GPIO, BOOT
I2C1
N5
SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6]
SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5]
I/O
I/O
IPU
IPU
I2C1 serial data
I2C1 serial clock
SPI1, GPIO, BOOT
P5
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
2.7.13 Timers
Table 2-17. Timers Terminal Functions
PIN
NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
ZKB
TIMER0
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8]
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]
R3
I
IPU
IPU
Timer0 lower input
UART0, I2C0,
GPIO, BOOT
Timer0 lower
output
P3
O
TIMER1 (Watchdog )
No external pins. The Timer1 peripheral signals are not pinned out as external pins.
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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2.7.14 Universal Host-Port Interface (UHPI)
Table 2-18. Universal Host-Port Interface (UHPI) Terminal Functions
PIN
NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
ZKB
M16
N14
N16
P14
P16
R14
T14
N12
EMA_D[15]/UHPI_HD[15]/LCD_D[15]/GP0[15]
EMA_D[14]/UHPI_HD[14]/LCD_D[14]/GP0[14]
EMA_D[13]/UHPI_HD[13]/LCD_D[13]/GP0[13]
EMA_D[12]/UHPI_HD[12]/LCD_D[12]/GP0[12]
EMA_D[11]/UHPI_HD[11]/LCD_D[11]/GP0[11]
EMA_D[10]/UHPI_HD[10]/LCD_D[10]/GP0[10]
EMA_D[9]/UHPI_HD[9]/LCD_D[9]/GP0[9]
EMA_D[8]/UHPI_HD[8]/LCD_D[8]/GP0[8]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
EMIFA, LCD, GPIO
EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/
BOOT[13]
EMIFA, MMC/SD,
GPIO, BOOT
UHPI data bus
M15
I/O
IPU
EMA_D[6]/MMCSD_DAT[6]/UHPI_HD[6]/GP0[6]
EMA_D[5]/MMCSD_DAT[5]/UHPI_HD[5]/GP0[5]
EMA_D[4]/MMCSD_DAT[4]/UHPI_HD[4]/GP0[4]
EMA_D[3]/MMCSD_DAT[3]/UHPI_HD[3]/GP0[3]
EMA_D[2]/MMCSD_DAT[2]/UHPI_HD[2]/GP0[2]
EMA_D[1]/MMCSD_DAT[1]/UHPI_HD[1]/GP0[1]
N13
N15
P13
P15
R13
R15
I/O
I/O
I/O
I/O
I/O
I/O
IPU
IPU
IPU
IPU
IPU
IPU
EMIFA, MMC/SD,
GPIO
EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/
BOOT[12]
EMIFA, MMC/SD,
GPIO, BOOT
T13
I/O
IPU
EMA_A[2]/MMCSD_CMD/UHPI_HCNTL1/GP1[2]
EMA_A[1]/MMCSD_CLK/UHPI_HCNTL0/GP1[1]
P9
R9
I/O
I/O
IPU
IPU
EMIFA,
MMCSD_CMD,
GPIO
UHPI access control
UHPI half-word
identification control
EMA_BA[1]/LCD_D[5]/UHPI_HHWIL/GP1[13]
EMA_WE/UHPI_HRW /AXR0[12]/GP2[3]/BOOT[14]
EMA_CS[2]/ UHPI_HCS /GP2[5]/BOOT[15]
P8
M13
P7
I/O
I/O
I/O
IPU
IPU
IPU
EMIFA, LCD, GPIO
EMIFA, McASP,
GPIO, BOOT
UHPI read/write
UHPI chip select
EMIFA, GPIO,
BOOT
EMA_WE_DQM[1]/ UHPI_HDS2 /AXR0[14]/GP2[8]
EMA_OE/ UHPI_HDS1 /AXR0[13]/GP2[7]
EMA_WE_DQM[0]/ UHPI_HINT /AXR0[15]/GP2[9]
EMA_WAIT[0]/ UHPI_HRDY /GP2[10]
P12
R7
I/O
I/O
I/O
I/O
I/O
IPU
IPU
IPU
IPU
IPU
UHPI data strobe
EMIFA, McASP0,
GPIO
M14
N6
UHPI host interrupt
UHPI ready
EMIFA, GPIO
EMA_CS[0]/ UHPI_HAS /GP2[4]
T8
UHPI address strobe
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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2.7.15 Multichannel Audio Serial Ports (McASP0, McASP1, McASP2)
Table 2-19. Multichannel Audio Serial Ports (McASPs) Terminal Functions
PIN
NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
ZKB
McASP0
EMA_WE_DQM[0]/UHPI_HINT/AXR0[15]/GP2[9]
EMA_WE_DQM[1]/UHPI_HDS2/AXR0[14]/GP2[8]
EMA_OE/UHPI_HDS1/AXR0[13]/GP2[7]
M14
P12
R7
I/O
I/O
I/O
IPU
IPU
IPU
EMIFA, UHPI,
GPIO
EMIFA, UHPI,
GPIO, BOOT
EMA_WE/UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14]
M13
I/O
IPU
AXR0[11]/AXR2[0]/GP3[11]
A5
D6
C6
B6
A6
D7
C7
B7
A7
D8
C8
B8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IPD
IPD
IPD
IPU
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
McASP2, GPIO
GPIO
UART1_TXD/AXR0[10]/GP3[10]
UART1_RXD/AXR0[9]/GP3[9]
GPIO
McASP0 serial
data
AXR0[8]/MDIO_D/GP3[8]
MDIO, GPIO
AXR0[7]/MDIO_CLK/GP3[7]
AXR0[6]/RMII_RXER/ACLKR2/GP3[6]
AXR0[5]/RMII_RXD[1]/AFSX2/GP3[5]
AXR0[4]/RMII_RXD[0]/AXR2[1]/GP3[4]
AXR0[3]/RMII_CRS_DV/AXR2[2]/GP3[3]
AXR0[2]/RMII_TXEN/AXR2[3]/GP3[2]
AXR0[1]/RMII_TXD[1]/ACLKX2/GP3[1]
AXR0[0]/RMII_TXD[0]/AFSR2/GP3[0]
EMAC,
McASP2, GPIO
McASP2, USB, McASP1 transmit
AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11]
ACLKX0/ECAP0/APWM0/GP2[12]
AFSX0/GP2[13]/BOOT[10]
B5
C5
D5
A4
B4
C4
L4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IPD
IPD
IPD
IPD
IPD
IPD
IPD
GPIO
master clock
McASP0 transmit
bit clock
eCAP0, GPIO
McASP0 transmit
frame sync
GPIO, BOOT
EMAC, GPIO,
BOOT
McASP0 receive
master clock
AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11]
ACLKR0/ECAP1/APWM1/GP2[15]
AFSR0/GP3[12]
McASP0 receive
bit clock
eCAP1, GPIO
GPIO
McASP0 receive
frame sync
McASP0 mute
output
AMUTE0/RESETOUT
RESETOUT
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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Table 2-19. Multichannel Audio Serial Ports (McASPs) Terminal Functions (continued)
PIN
NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
ZKB
McASP1
AXR1[11]/GP5[11]
AXR1[10]/GP5[10]
AXR1[9]/GP4[9]
T4
N3
M1
I/O
I/O
I/O
IPU
IPU
IPD
GPIO
eHRPWM1 A,
GPIO
AXR1[8]/EPWM1A/GP4[8]
AXR1[7]/EPWM1B/GP4[7]
AXR1[6]/EPWM2A/GP4[6]
AXR1[5]/EPWM2B/GP4[5]
M2
M3
M4
N1
I/O
I/O
I/O
I/O
IPD
IPD
IPD
IPD
eHRPWM1 B,
GPIO
eHRPWM2 A,
GPIO
McASP1 serial
data
eHRPWM2 B,
GPIO
AXR1[4]/EQEP1B/GP4[4]
AXR1[3]/EQEP1A/GP4[3]
AXR1[2]/GP4[2]
N2
P1
P2
R2
T3
I/O
I/O
I/O
I/O
I/O
IPD
IPD
IPD
IPD
IPD
eQEP1, GPIO
AXR1[1]/GP4[1]
GPIO
AXR1[0]/GP4[0]
eHRPWM0,
GPIO
McASP1 transmit
master clock
AHCLKX1/EPWM0B/GP3[14]
ACLKX1/EPWM0A/GP3[15]
AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10]
AHCLKR1/GP4[11]
K2
K3
K4
L1
L2
L3
I/O
I/O
I/O
I/O
I/O
I/O
IPD
IPD
IPD
IPD
IPD
IPD
eHRPWM0,
GPIO
McASP1 transmit
bit clock
eHRPWM0,
GPIO
McASP1 transmit
frame sync
McASP1 receive
master clock
GPIO
McASP1 receive
bit clock
ACLKR1/ECAP2/APWM2/GP4[12]
AFSR1/GP4[13]
eCAP2, GPIO
GPIO
McASP1 receive
frame sync
eHRPWM0,
eHRPWM1,
eHRPWM2,
GPIO
McASP1 mute
output
AMUTE1/EPWMTZ/GP4[14]
D4
I/O
IPD
McASP2
AXR0[0]/RMII_TXD[0]/AFSR2/GP3[0]
AXR0[2]/RMII_TXEN/AXR2[3]/GP3[2]
AXR0[3]/RMII_CRS_DV/AXR2[2]/GP3[3]
AXR0[4]/RMII_RXD[0]/AXR2[1]/GP3[4]
AXR0[11]/AXR2[0]/GP3[11]
B8
D8
A7
B7
A5
I/O
I/O
I/O
I/O
I/O
IPD
IPD
IPD
IPD
IPD
McASP0,
EMAC, GPIO
McASP2 serial
data
McASP0, GPIO
McASP2 transmit
master clock
AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11]
AXR0[1]/RMII_TXD[1]/ACLKX2/GP3[1]
AXR0[5]/RMII_RXD[1]/AFSX2/GP3[5]
EMA_CLK/OBSCLK/AHCLKR2/GP1[15]
AXR0[6]/RMII_RXER/ACLKR2/GP3[6]
EMA_CS[3]/AMUTE2/GP2[6]
B5
C8
C7
R12
D7
T7
I/O
I/O
I/O
I/O
I/O
I/O
IPD
IPD
IPD
IPU
IPD
IPU
McASP0, USB,
GPIO
McASP2 transmit
bit clock
McASP0,
EMAC, GPIO
McASP2 transmit
frame sync
EMIFA, GPIO,
OBSCLK
McASP2 receive
master clock
McASP0,
EMAC, GPIO
McASP2 receive
bit clock
McASP2 mute
output
EMIFA, GPIO
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2.7.16 Universal Serial Bus Modules (USB0, USB1)
Table 2-20. Universal Serial Bus (USB) Terminal Functions
PIN
NO
SIGNAL NAME
TYPE(1) PULL(2) MUXED
DESCRIPTION
ZKB
USB0 2.0 OTG (USB0)
USB0_DM
G4
F4
H5
E3
A
NA
NA
NA
NA
USB0 PHY data minus
USB0_DP
A
USB0 PHY data plus
USB0_VDDA33
USB0_VDDA18
PWR
PWR
USB0 PHY 3.3-V supply
USB0 PHY 1.8-V supply input
USB0 PHY 1.2-V LDO output for bypass cap
USB0_VDDA12(3)
C3
PWR
NA
For proper device operation, this pin must always
be connected via a 1 uF capacitor to VSS (GND),
even if USB0 is not being used.
USB0_ID
D2
D3
E4
A
A
0
NA
USB0 PHY identification (mini-A or mini-B plug)
USB0 bus voltage
USB0_VBUS
NA
USB0_DRVVBUS/GP4[15]
IPD
IPD
GPIO
USB0 controller VBUS control output
AHCLKX0/AHCLKX2/USB_REFCLKIN/
GP2[11]
B5
I
USB_REFCLKIN. Optional clock input
USB1 1.1 OHCI (USB1)
USB1_DM
B3
A3
C1
C2
A
NA
USB1 PHY data minus
USB1 PHY data plus
USB1_DP
A
NA
NA
NA
USB1_VDDA33
USB1_VDDA18
PWR
PWR
USB1 PHY 3.3-V supply
USB1 PHY 1.8-V supply
AHCLKX0/AHCLKX2/USB_REFCLKIN/
GP2[11]
B5
I
IPD
NA
USB_REFCLKIN. Optional clock input
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
(3) Core power supply LDO output for USB PHY.
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2.7.17 Ethernet Media Access Controller (EMAC)
Table 2-21. Ethernet Media Access Controller (EMAC) Terminal Functions
PIN
NO
SIGNAL NAME
TYPE(1) PULL(2)
RMII
MUXED
DESCRIPTION
ZKB
EMAC 50-MHz
clock input or output
AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11]
AXR0[6]/RMII_RXER/ACLKR2/GP3[6]
A4
D7
I/O
I
IPD
IPD
McASP0, GPIO, BOOT
EMAC RMII receiver
error
AXR0[5]/RMII_RXD[1]/AFSX2/GP3[5]
AXR0[4]/RMII_RXD[0]/AXR2[1]/GP3[4]
C7
B7
I
I
IPD
IPD
EMAC RMII receive
data
EMAC RMII carrier
sense data valid
AXR0[3]/RMII_CRS_DV/AXR2[2]/GP3[3]
AXR0[2]/RMII_TXEN/AXR2[3]/GP3[2]
A7
D8
I
IPD
IPD
McASP0, McASP2, GPIO
EMAC RMII transmit
enable
O
AXR0[1]/RMII_TXD[1]/ACLKX2/GP3[1]
AXR0[0]/RMII_TXD[0]/AFSR2/GP3[0]
C8
B8
O
O
IPD
IPD
EMAC RMII trasmit
data
MDIO
I/O
AXR0[8]/MDIO_D/GP3[8]
B6
A6
IPU
IPD
MDIO serial data
MDIO clock
McASP0, GPIO
AXR0[7]/MDIO_CLK/GP3[7]
O
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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2.7.18 Multimedia Card/Secure Digital (MMC/SD)
Table 2-22. Multimedia Card/Secure Digital (MMC/SD) Terminal Functions
PIN
NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
ZKB
R9
EMA_A[1]/MMCSD_CLK/UHPI_HCNTL0/GP1[1]
EMA_A[2]/MMCSD_CMD/UHPI_HCNTL1/GP1[2]
O
IPU
IPU
MMCSD Clock
EMIFA, UHPI, GPIO
P9
I/O
MMCSD Command
EMIFA, UHPI, GPIO,
BOOT
EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/BOOT[13]
M15
I/O
IPU
EMA_D[6]/MMCSD_DAT[6]/UHPI_HD[6]/GP0[6]
EMA_D[5]/MMCSD_DAT[5]/UHPI_HD[5]/GP0[5]
EMA_D[4]/MMCSD_DAT[4]/UHPI_HD[4]/GP0[4]
EMA_D[3]/MMCSD_DAT[3]/UHPI_HD[3]/GP0[3]
EMA_D[2]/MMCSD_DAT[2]/UHPI_HD[2]/GP0[2]
EMA_D[1]/MMCSD_DAT[1]/UHPI_HD[1]/GP0[1]
N13
N15
P13
P15
R13
R15
I/O
I/O
I/O
I/O
I/O
I/O
IPU
IPU
IPU
IPU
IPU
IPU
EMIFA, UHPI, GPIO
MMC/SD data
EMIFA, UHPI, GPIO,
BOOT
EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/BOOT[12]
T13
I/O
IPU
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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2.7.19 Liquid Crystal Display Controller (LCD)
Table 2-23. Liquid Crystal Display Controller (LCD) Terminal Functions
PIN NO
ZKB
M16
N14
N16
P14
P16
R14
T14
N12
T9
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
EMA_D[15]/UHPI_HD[15]/LCD_D [15]/GP0[15]
EMA_D[14]/UHPI_HD[14]/LCD_D[14]/GP0[14]
EMA_D[13]/UHPI_HD[13]/LCD_D[13]/GP0[13]
EMA_D[12]/UHPI_HD[12]/LCD_D[12]/GP0[12]
EMA_D[11]/UHPI_HD[11]/LCD_D[11 ]/GP0[11]
EMA_D[10]/UHPI_HD[10]/LCD_D[10]/GP0[10]
EMA_D[9]/UHPI_HD[9]/LCD_D[9]/GP0[9]
EMA_D[8]/UHPI_HD[8]/LCD_D[8]/GP0[8]
EMA_A[0]/LCD_D[7]/GP1[0]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
EMIFA, UHPI,
GPIO
LCD data bus
EMIFA, GPIO
EMA_A[3]/LCD_D[6]/GP1[3]
N9
EMIFA, UHPI,
GPIO
EMA_BA[1]/LCD_D[5]/UHPI_HHWIL/GP1[13]
P8
I/O
IPU
EMA_BA[0]/LCD_D[4]/GP1[14]
EMA_A[4]/LCD_D[3]/GP1[4]
EMA_A[5]/LCD_D[2]/GP1[5]
EMA_A[6]/LCD_D[1]/GP1[6]
EMA_A[7]/LCD_D[0]/GP1[7]
EMA_A[8]/LCD_PCLK/GP1[8]
EMA_A[9]/LCD_HSYNC/GP1[9]
EMA_A[10]/LCD_VSYNC/GP1[10]
R8
T10
R10
P10
N10
T11
R11
N8
I/O
I/O
I/O
I/O
I/O
O
IPU
IPD
IPD
IPD
IPD
IPU
IPU
IPU
LCD data bus
EMIFA, GPIO
LCD pixel clock
O
LCD horizontal sync
LCD vertical sync
O
LCD AC bias enable
chip select
EMA_A[11]/ LCD_AC_ENB_CS /GP1[11]
EMA_A[12]/LCD_MCLK/GP1[12]
P11
N11
O
O
IPU
IPU
LCD memory clock
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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2.7.20 Reserved and No Connect
Table 2-24. Reserved and No Connect Terminal Functions
PIN NO
ZKB
F7
SIGNAL NAME
TYPE(1)
DESCRIPTION
RSV1
RSV2
-
Reserved. (Leave unconnected, do not connect to power or ground.)
Reserved. For proper device operation, this pin must be tied either directly
to CVDD or left unconnected [do not connect to ground (VSS)].
B1
PWR
NC
NC
F3
H4
-
-
No Connect (leave unconnected)
No Connect (leave unconnected)
(1) PWR = Supply voltage.
2.7.21 Supply and Ground
Table 2-25. Supply and Ground Terminal Functions
PIN NO
SIGNAL NAME
TYPE(1)
DESCRIPTION
ZKB
F6,G6, G7,
G10, G11, H7,
H10, H11, J6,
J7, J10, J11,
J12, K6, K7,
K10, K11,L6
CVDD (Core supply)
PWR
PWR
Core supply voltage pins
RVDD (Internal RAM supply)
DVDD (I/O supply)
H6, H12
Internal ram supply voltage pins
B16, E5, E8,
E9, E12, F5,
F11, F12, G5,
G12, K5, K12,
L5, L11, L12,
M5, M8, M9,
M12, R1, R16
PWR
I/O supply voltage pins
A1, A2, A15,
A16,
B2,
E6, E7, E10,
E11,
F8, F9, F10,
G8, G9,
H8, H9,
J8, J9,
VSS (Ground)
GND
Ground pins
K8, K9,
L7, L8, L9,
L10,
M6, M7, M10,
M11,
T1, T2, T15,
T16
(1) PWR = Supply voltage, GND - Ground.
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3 Device Configuration
3.1 Boot Modes
This device supports a variety of boot modes through an internal ROM bootloader. This device does not
support dedicated hardware boot modes; therefore, all boot modes utilize the internal ROM. The input
states of the BOOT pins are sampled and latched into the BOOTCFG register, which is part of the system
configuration (SYSCFG) module, when device reset is deasserted. Boot mode selection is determined by
the values of the BOOT pins
The following boot modes are supported:
•
NAND Flash boot
–
–
8-bit NAND
16-bit NAND
•
NOR Flash boot
–
–
–
NOR Direct boot (8-bit or 16-bit)
NOR Legacy boot (8-bit or 16-bit)
NOR AIS boot (8-bit or 16-bit)
•
•
HPI Boot
I2C0 / I2C1 Boot
–
–
EEPROM (Master Mode)
External Host (Slave Mode)
•
•
SPI0 / SPI1 Boot
–
–
–
Serial Flash (Master Mode)
SERIAL EEPROM (Master Mode)
External Host (Slave Mode)
UART0 / UART1 / UART2 Boot
External Host
–
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3.2 SYSCFG Module
The following system level features of the chip are controlled by the SYSCFG peripheral:
•
•
•
•
•
Readable Device, Die, and Chip Revision ID
Control of Pin Multiplexing
Priority of bus accesses different bus masters in the system
Capture at power on reset the chip BOOT[15:0] pin values and make them available to software
Special case settings for peripherals:
–
–
–
–
–
Locking of PLL controller settings
Default burst sizes for EDMA3 TC0 and TC1
Selection of the source for the eCAP module input capture (including on chip sources)
McASP AMUTEIN selection and clearing of AMUTE status for the three McASP peripherals
Control of the reference clock source and other side-band signals for both of the integrated USB
PHYs
–
Clock source selection for EMIFA and EMIFB
•
•
Selects the source of emulation suspend signal (from either ARM or DSP) of peripherals supporting
this function.
Control of on-chip inter-processor interrupts for signaling between ARM and DSP
Many registers are accessible only by a host (ARM or DSP) when it is operating in its privileged mode.
(ex. from the kernel, but not from user space code).
Table 3-1. System Configuration (SYSCFG) Module Register Access
BYTE ADDRESS
0x01C1 4000
0x01C14008
0x01C1 400C
0x01C1 4010
0x01C1 4014
0x01C1 4018
0x01C1 4020
0x01C1 4024
0x01C1 4038
0x01C1 403C
0x01C1 4040
0x01C1 4044
0x01C1 40E0
0x01C1 40E4
0x01C1 40E8
0x01C1 40EC
0x01C1 40F0
0x01C1 40F4
0x01C1 40F8
0x01C1 4110
0x01C1 4114
0x01C1 4118
0x01C1 4120
0x01C1 4124
0x01C1 4128
0x01C1 412C
ACRONYM
REVID
REGISTER DESCRIPTION
Revision Identification Register
ACCESS
—
DIEIDR0
DIEIDR1
DIEIDR2
DIEIDR3
DEVIDR0
BOOTCFG
CHIPREVID
KICK0R
Device Identification Register 0
Device Identification Register 1
Device Identification Register 2
Device Identification Register 3
JTAG Identification Register
Boot Configuration Register
Silicon Revision Identification Register
Kick 0 Register
—
—
—
—
—
Privileged mode
Privileged mode
Privileged mode
Privileged mode
—
KICK1R
Kick 1 Register
HOST0CFG
HOST1CFG
IRAWSTAT
IENSTAT
IENSET
Host 0 Configuration Register
Host 1 Configuration Register
Interrupt Raw Status/Set Register
Interrupt Enable Status/Clear Register
Interrupt Enable Register
—
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
—
IENCLR
Interrupt Enable Clear Register
End of Interrupt Register
EOI
FLTADDRR
FLTSTAT
MSTPRI0
MSTPRI1
MSTPRI2
PINMUX0
PINMUX1
PINMUX2
PINMUX3
Fault Address Register
Fault Status Register
Master Priority 0 Register
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Master Priority 1 Register
Master Priority 2 Register
Pin Multiplexing Control 0 Register
Pin Multiplexing Control 1 Register
Pin Multiplexing Control 2 Register
Pin Multiplexing Control 3 Register
50
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Table 3-1. System Configuration (SYSCFG) Module Register Access (continued)
BYTE ADDRESS
0x01C1 4130
0x01C1 4134
0x01C1 4138
0x01C1 413C
0x01C1 4140
0x01C1 4144
0x01C1 4148
0x01C1 414C
0x01C1 4150
0x01C1 4154
0x01C1 4158
0x01C1 415C
0x01C1 4160
0x01C1 4164
0x01C1 4168
0x01C1 416C
0x01C1 4170
0x01C1 4174
0x01C1 4178
0x01C1 417C
0x01C1 4180
0x01C1 4184
0x01C1 4188
0x01C1 418C
ACRONYM
PINMUX4
REGISTER DESCRIPTION
Pin Multiplexing Control 4 Register
ACCESS
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
—
PINMUX5
Pin Multiplexing Control 5 Register
Pin Multiplexing Control 6 Register
Pin Multiplexing Control 7 Register
Pin Multiplexing Control 8 Register
Pin Multiplexing Control 9 Register
Pin Multiplexing Control 10 Register
Pin Multiplexing Control 11 Register
Pin Multiplexing Control 12 Register
Pin Multiplexing Control 13 Register
Pin Multiplexing Control 14 Register
Pin Multiplexing Control 15 Register
Pin Multiplexing Control 16 Register
Pin Multiplexing Control 17 Register
Pin Multiplexing Control 18 Register
Pin Multiplexing Control 19 Register
Suspend Source Register
PINMUX6
PINMUX7
PINMUX8
PINMUX9
PINMUX10
PINMUX11
PINMUX12
PINMUX13
PINMUX14
PINMUX15
PINMUX16
PINMUX17
PINMUX18
PINMUX19
SUSPSRC
CHIPSIG
Chip Signal Register
CHIPSIG_CLR
CFGCHIP0
CFGCHIP1
CFGCHIP2
CFGCHIP3
CFGCHIP4
Chip Signal Clear Register
—
Chip Configuration 0 Register
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Chip Configuration 1 Register
Chip Configuration 2 Register
Chip Configuration 3 Register
Chip Configuration 4 Register
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3.3 Pullup/Pulldown Resistors
Proper board design should ensure that input pins to the device always be at a valid logic level and not
floating. This may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and
internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external
pullup/pulldown resistors.
An external pullup/pulldown resistor needs to be used in the following situations:
•
Boot and Configuration Pins: If the pin is both routed out and 3-stated (not driven), an external
pullup/pulldown resistor is strongly recommended, even if the IPU/IPD matches the desired value/state.
•
Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external
pullup/pulldown resistor to pull the signal to the opposite rail.
For the boot and configuration pins, if they are both routed out and 3-stated (not driven), it is strongly
recommended that an external pullup/pulldown resistor be implemented. Although, internal
pullup/pulldown resistors exist on these pins and they may match the desired configuration value,
providing external connectivity can help ensure that valid logic levels are latched on these device boot and
configuration pins. In addition, applying external pullup/pulldown resistors on the boot and configuration
pins adds convenience to the user in debugging and flexibility in switching operating modes.
Tips for choosing an external pullup/pulldown resistor:
•
Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure
to include the leakage currents of all the devices connected to the net, as well as any internal pullup or
pulldown resistors.
•
Decide a target value for the net. For a pulldown resistor, this should be below the lowest VIL level of
all inputs connected to the net. For a pullup resistor, this should be above the highest VIH level of all
inputs on the net. A reasonable choice would be to target the VOL or VOH levels for the logic family of
the limiting device; which, by definition, have margin to the VIL and VIH levels.
•
•
Select a pullup/pulldown resistor with the largest possible value; but, which can still ensure that the net
will reach the target pulled value when maximum current from all devices on the net is flowing through
the resistor. The current to be considered includes leakage current plus, any other internal and
external pullup/pulldown resistors on the net.
For bidirectional nets, there is an additional consideration which sets a lower limit on the resistance
value of the external resistor. Verify that the resistance is small enough that the weakest output buffer
can drive the net to the opposite logic level (including margin).
•
•
•
Remember to include tolerances when selecting the resistor value.
For pullup resistors, also remember to include tolerances on the IO supply rail.
For most systems, a 1-kΩ resistor can be used to oppose the IPU/IPD while meeting the above
criteria. Users should confirm this resistor value is correct for their specific application.
•
For most systems, a 20-kΩ resistor can be used to compliment the IPU/IPD on the boot and
configuration pins while meeting the above criteria. Users should confirm this resistor value is correct
for their specific application.
•
•
For more detailed information on input current (II), and the low-/high-level input voltages (VIL and VIH)
for the device, see Section 4.2, Recommended Operating Conditions.
For the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal
functions table.
52
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4 Device Operating Conditions
4.1 Absolute Maximum Ratings Over Operating Case Temperature Range
(1)
(Unless Otherwise Noted)
Core
-0.5 V to 1.4 V
-0.5 V to 2 V
(2)
(CVDD, RVDD, RTC_CVDD, PLL0_VDDA )
I/O, 1.8V
(USB0_VDDA18, USB1_VDDA18)
Supply voltage ranges
(2)
I/O, 3.3V
-0.5 V to 3.8V
(2)
(DVDD, USB0_VDDA33, USB1_VDDA33)
VI I/O, 1.2V
(OSCIN, RTC_XI)
-0.3 V to CVDD + 0.3V
-0.3V to DVDD + 0.35V
VI I/O, 3.3V
(Steady State)
VI I/O, 3.3V
DVDD + 20%
up to 20% of Signal
Period
Input voltage ranges
(Transient)
VI I/O, USB 5V Tolerant Pins:
5.25V(3)
(USB0_DM, USB0_DP, USB0_ID, USB1_DM, USB1_DP)
VI I/O, USB0 VBUS
VO I/O, 3.3V
5.50V(3)
-0.5 V to DVDD + 0.3V
(Steady State)
Output voltage ranges
VO I/O, 3.3V
20% of DVDD for up to
20% of the signal period
(Transient Overshoot/Undershoot)
Input or Output Voltages 0.3V above or below their respective power
±20mA
Clamp Current
rails. Limit clamp current that flows through the I/O's internal diode
protection cells.
Commercial
0°C to 90°C
-40°C to 90°C
-40°C to 105°C
-40°C to 125°C
-55°C to 150°C
>2000V
Industrial (D suffix )
Extended (A suffix)
Automotive (T suffix)
(default)
Human Body Model (HBM)(5)
Charged Device Model (CDM)(6)
Operating Junction Temperature ranges,
TJ
Storage temperature range, Tstg
(4)
ESD Stress Voltage, VESD
>500V
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, PLL0_VSSA, OSCVSS, RTC_VSS
(3) Up to a max of 24 hours.
(4) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device.
(5) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001-2010. JEDEC document JEP155 states that 500V HBM allows
safe manufacturing with a standard ESD control process, and manufacturing with less than 500V HBM is possible if necessary
precautions are taken. Pins listed as 1000V may actually have higher performance.
(6) Level listed above is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250V CDM allows safe
manufacturing with a standard ESD control process. Pins listed as 250V may actually have higher performance.
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4.2 Recommended Operating Conditions
MIN
1.14
1.25
0.9
NOM
1.2
1.3
1.2
1.3
1.2
1.3
MAX
1.32
1.35
1.32
1.35
1.32
1.35
UNIT
375 MHz versions
Supply voltage, Core
(CVDD, PLL0_VDDA)
CVDD
V
456 MHz version
375 MHz versions
Supply Voltage, RTC Core
Logic
(1)
RTC_CVDD
V
V
456 MHz version
0.9
375 MHz versions
1.14
1.25
RVDD
Supply Voltage, Internal RAM
Supply voltage, I/O, 1.8V
456 MHz version
1.71
3.0
0
1.8
3.3
0
1.89
3.45
0
V
V
V
(USB0_VDDA18, USB1_VDDA18)
DVDD
VSS
Supply voltage, I/O, 3.3V
(DVDD, USB0_VDDA33, USB1_VDDA33)
Supply ground
(VSS, PLL0_VSSA, OSCVSS(2), RTC_VSS(2)
)
High-level input voltage, I/O, 3.3V
High-level input voltage, RTC_XI
High-level input voltage, OSCIN
Low-level input voltage, I/O, 3.3V
Low-level input voltage, RTC_XI
Low-level input voltage, OSCIN
Input Hysteresis
2
V
V
(3)
VIH
0.7*RTC_CVDD
0.7*CVDD
0.8
V
V
(3)
VIL
0.3*RTC_CVDD
0.3*CVDD
VHYS
USB
160
5
mV
V
USB0_VBUS
4.75
5.25
Transition time, 10%-90%, All Inputs (unless otherwise specified
in the electrical data sections)
tt
0.25P or 10(4)
ns
Commercial
0
-40
-40
-40
0
70
70
°C
°C
Industrial (D suffix)
Operating ambient
TA
temperature range
Extended (A suffix)
85
°C
Automotive (T suffix)
Commercial
105
°C
375 / 456
456
MHz
MHz
MHz
MHz
DSP and ARM
Operating Frequency
(SYSCLK1,6)
Industrial (D suffix)
Extended (A suffix)
Automotive (T suffix)
0
FSYSCLK1,6
0
375
0
375
(1) The RTC provides an option for isolating the RTC_CVDD from the CVDD to reduce current leakage when the RTC is powered
independently. If these power supplies are not isolated (CTRL.SPLITPOWER=0), RTC_CVDD must be equal to or greater than CVDD.
If these power supplies are isolated (CTRL.SPLITPOWER=1), RTC_CVDD may be lower than CVDD.
(2) When an external crystal is used, oscillator (OSC_VSS, RTC_VSS) ground must be kept separate from other grounds and connected
directly to the crystal load capacitor ground. These pins are shorted to VSS on the device itself and should not be connected to VSS on
the circuit board. If a crystal is not used and the clock input is driven directly, then the oscillator VSS may be connected to board ground.
(3) These I/O specifications do not apply to USB I/Os. USB0 I/Os adhere to USB2.0 specification. USB1 I/Os adhere to USB1.1
specification.
(4) Whichever is smaller. P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve
noise immunity on input signals.
54
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4.3 Notes on Recommended Power-On Hours (POH)
The information in the section below is provided solely for your convenience and does not extend or
modify the warranty provided under TI’s standard terms and conditions for TI semiconductor products.
To avoid significant degradation, the device power-on hours (POH) must be limited to the following:
Table 4-1. Recommended Power-On Hours
Silicon
Revision
Operating Junction
Temperature (Tj)
Power-On Hours [POH]
(hours)
Speed Grade
Nominal CVDD Voltage (V)
A
B
B
B
B
B
B
300 MHz
300 MHz
375 MHz
375 MHz
375 MHz
456 MHz
456 MHz
0 to 90 °C
0 to 90 °C
1.2V
1.2V
1.2V
1.2V
1.2V
1.3V
1.3V
100,000
100,000
100,000
75,000(1)
20,000
0 to 90 °C
-40 to 105 °C
-40 to 125 °C
0 to 90 °C
100,000
100,000
-40 to 90 °C
(1) 100,000 POH can be achieved at this temperature condition if the device operation is limited to 345 MHz.
Note: Logic functions and parameter values are not assured out of the range specified in the recommended
operating conditions.
The above notations cannot be deemed a warranty or deemed to extend or modify the warranty under
TI’s standard terms and conditions for TI semiconductor products.
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Device Operating Conditions
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4.4 Electrical Characteristics Over Recommended Ranges of Supply Voltage and
Operating Case Temperature (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
DVDD= 3.15V, IOH = -4 mA
DVDD= 3.15V, IOH = 100 μA
DVDD= 3.15V, IOL = 4mA
MIN
TYP
MAX
UNIT
2.4
V
V
V
V
(1)
(1)
VOH
High-level output voltage (3.3V I/O)
2.95
0.4
0.2
VOL
Low-level output voltage (3.3V I/O)
DVDD= 3.15V, IOL = -100 μA
VI = VSS to DVDD without opposing
internal resistor
±35
-200
300
±40
μA
μA
μA
μA
VI = VSS to DVDD with opposing
-30
50
(3)
internal pullup resistor
II
Input current
(2) (1)
,
VI = VSS to DVDD with opposing
(3)
internal pulldown resistor
VI = VSS to USB1_VDDA33 -
USB1_DM and USB1_DP
(1)
IOH
High-level output current
Low-level output current
I/O Off-state output current
-4
4
mA
mA
μA
pF
(1)
IOL
(4)
IOZ
VO = VDD or VSS; Internal pull disabled
LVCMOS signals
±35
3
CI
Input capacitance
Output capacitance
OSCIN and RTC_XI
2
pF
CO
LVCMOS signals
3
pF
(1) These I/O specifications apply to regular 3.3V IOs and do not apply to USB0 or USB1 unless specifically indicated. USB0 I/Os adhere to
the USB 2.0 specification. USB1 I/Os adhere to the USB 1.1 specification.
(2) II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II
indicates the input leakage current and off-state (Hi-Z) output leakage current.
(3) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
(4) IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current.
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5 Peripheral Information and Electrical Specifications
5.1 Parameter Information
5.1.1 Parameter Information Device-Specific Information
Tester Pin Electronics
Data Sheet Timing Reference Point
42 Ω
3.5 nH
Output
Under
Test
Transmission Line
Z0 = 50 Ω
(see note)
Device Pin
(see note)
4.0 pF
1.85 pF
A. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add or subtract the transmission line delay (2 ns or longer) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the
device pin and the input signals are driven between 0V and the appropriate IO supply rail for the signal.
Figure 5-1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
5.1.1.1 Signal Transition Levels
All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. For 3.3 V I/O,
Vref = 1.65 V. For 1.8 V I/O, Vref = 0.9 V. For 1.2 V I/O, Vref = 0.6 V.
V
ref
Figure 5-2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks,
VOLMAX and VOH MIN for output clocks.
V
ref
= V MIN (or V MIN)
IH OH
V
ref
= V MAX (or V MAX)
IL OL
Figure 5-3. Rise and Fall Transition Time Voltage Reference Levels
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5.2 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
5.3 Power Supplies
5.3.1 Power-on Sequence
The device should be powered-on in the following order:
1. RTC (RTC_CVDD) may be powered from an external device (such as a battery) prior to all other
supplies being applied or powered-up at the same time as CVDD. If the RTC is not used, RTC_CVDD
should be connected to CVDD. RTC_CVDD should not be left unpowered while CVDD is powered.
2. Core logic supplies:
(a) CVDD core logic and RVDD supply
(b) Other 1.2V logic supplies (PLL0_VDDA).
Groups 2a) and 2b) may be powered up together or 2a) first followed by 2b).
3. All 1.8V IO supplies (USB0_VDDA18, USB1_VDDA18).
4. All digital IO and analog 3.3V PHY supplies (DVDD, USB0_VDDA33, USB1_VDDA33).
If both USB0 and USB1 are not used, USB0_VDDA33 and USB1_VDDA33 are not required and may
be left unconnected.
Group 3) and group 4) may be powered on in either order [3 then 4, or 4 then 3] but group 4) must be
powered-on after the core logic supplies.
There is no specific required voltage ramp rate for any of the supplies.
RESET must be maintained active until all power supplies have reached their nominal values.
5.3.2 Power-off Sequence
The power supplies can be powered-off in any order as long as the 3.3V supplies do not remain powered
with the other supplies unpowered.
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5.4 Unused USB0 (USB2.0) and USB1 (USB1.1) Pin Configurations
If one or both USB modules on the device are not used, then some of the power supplies to those
modules may not be required. This can eliminate the requirement for a 1.8V power supply to the USB
modules. The required pin configurations for unused USB modules are shown below.
Table 5-1. Unused USB0 and USB1 Pin Configurations
SIGNAL NAME
Configuration
Configuration
(When USB0 and USB1 are not used)
(When USB0 is used
and USB1 is not used)
USB0_DM
USB0_DP
No connect
No connect
Use as USB0 function
Use as USB0 function
3.3V
USB0_VDDA33
USB0_VDDA18
USB0_ID
No connect
No connect
1.8V
No connect
Use as USB0 function
Use as USB0 function
Use as USB0 or alternate function
USB0_VBUS
No connect
USB0_DRVVBUS/GP4[15]
USB0_VDDA12
No connect or use as alternate function
No connect
Internal USB0 PHY output connected to an
external filter capacitor
USB1_DM
USB1_DP
No connect
No connect
VSS
VSS
USB1_VDDA33
USB1_VDDA18
No connect
No connect
No connect
No connect
AHCLKX0/AHCLKX2/USB_REFCLKIN/
GP2[11]
No connect or use as alternate function
Use as USB0 or alternate function
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5.5 Reset
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5.5.1 Power-On Reset (POR)
A power-on reset (POR) is required to place the device in a known good state after power-up. Power-On
Reset is initiated by bringing RESET and TRST low at the same time. POR sets all of the device internal
logic to its default state. All pins are tri-stated with the exception of RESETOUT, which remains active
through the reset sequence, and RTCK/GP7[14]. If an emulator is driving TCK into the device during
reset, then RTCK/GP7[14] will drive out RTCK. If TCK is not being driven into the device during reset,
then RTCK/GP7[14] will drive low.RESETOUT is an output for use by other controllers in the system that
indicates the device is currently in reset.
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for
the device to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG
port interface and device's emulation logic in the reset state.
TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or
exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by
TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted.
RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE
correctly. Other boundary-scan instructions work correctly independent of current state of RESET. For
maximum reliability, the device includes an internal pulldown on the TRST pin to ensure that TRST will
always be asserted upon power up and the device's internal emulation logic will always be properly
initialized.
JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG
controllers may not drive TRST high but expect the use of a pullup resistor on TRST. When using this type
of JTAG controller, assert TRST to intialize the device after powerup and externally drive TRST high
before attempting any emulation or boundary scan operations.
RTCK/GP7[14] is maintained active through a POR.
A summary of the effects of Power-On Reset is given below:
•
•
•
•
•
All internal logic (including emulation logic and the PLL logic) is reset to its default state
Internal memory is not maintained through a POR
RESETOUT goes active
All device pins go to a high-impedance state
The RTC peripheral is not reset during a POR. A software sequence is required to reset the RTC.
CAUTION: A watchdog reset triggers a POR.
5.5.2 Warm Reset
A warm reset provides a limited reset to the device. Warm Reset is initiated by bringing only RESET low
(TRST is maintained high through a warm reset). Warm reset sets certain portions of the device to their
default state while leaving others unaltered. All pins are tri-stated with the exception of RESETOUT, which
remains active through the reset sequence, and RTCK/GP7[14]. If an emulator is driving TCK into the
device during reset, then RTCK/GP7[14] will drive out RTCK. If TCK is not being driven into the device
during reset, then RTCK/GP7[14] will drive low. RESETOUT is an output for use by other controllers in the
system that indicates the device is currently in reset.
During emulation, the emulator will maintain TRST high and hence only warm reset (not POR) is available
during emulation debug and development.
RTCK/GP7[14] is maintained active through a warm reset.
A summary of the effects of Warm Reset is given below:
•
All internal logic (except for the emulation logic and the PLL logic) is reset to its default state
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•
•
•
•
Internal memory is maintained through a warm reset
RESETOUT goes active
All device pins go to a high-impedance state
The RTC peripheral is not reset during a warm reset. A software sequence is required to reset the
RTC.
5.5.3 Reset Electrical Data Timings
Table 5-2 assumes testing over the recommended operating conditions.
(2)
Table 5-2. Reset Timing Requirements ((1)
,
)
No.
1
MIN
100
20
MAX
UNIT
ns
tw(RSTL)
Pulse width, RESET/TRST low
2
tsu(BPV-RSTH)
th(RSTH-BPV)
Setup time, boot pins valid before RESET/TRST high
Hold time, boot pins valid after RESET/TRST high
RESET high to RESETOUT high; Warm reset
RESET high to RESETOUT high; Power-on Reset
ns
3
20
ns
cycles(3)
4
td(RSTH-
RESETOUTH)
4096
6192
(1) RESETOUT is multiplexed with other pin functions. See the Terminal Functions table, Table 2-5 for details.
(2) For power-on reset (POR), the reset timings in this table refer to RESET and TRST together. For warm reset, the reset timings in this
table refer to RESET only (TRST is held high).
(3) OSCIN cycles.
Power
Supplies
Ramping
Power Supplies Stable
Clock Source Stable
OSCIN
RESET
1
TRST
4
RESETOUT
3
2
Boot Pins
Config
Figure 5-4. Power-On Reset (RESET and TRST active) Timing
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Power Supplies Stable
OSCIN
TRST
1
RESET
4
RESETOUT
3
2
Config
Boot Pins
Driven or Hi-Z
Figure 5-5. Warm Reset (RESET active, TRST high) Timing
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5.6 Crystal Oscillator or External Clock Input
The OMAP-L137 device includes two choices to provide an external clock input, which is fed to the on-
chip PLL to generate high-frequency system clocks. These options are illustrated in Figure 5-6 and
Figure 5-7. For input clock frequencies between 12 and 20 MHz, a crystal with 80 ohm max ESR is
recommended. For input clock frequencies between 20 and 30 MHz, a crystal with 60 ohm max ESR is
recommended. Typical load capacitance values are 10-20 pF, where the load capacitance is the series
combination of C1 and C2.
The CLKMODE bit in the PLLCTL register must be 0 to use the on-chip oscillator. If CLKMODE is set to 1,
the internal oscillator is disabled.
•
•
Figure 5-6 illustrates the option that uses on-chip 1.2V oscillator with external crystal circuit.
Figure 5-7 illustrates the option that uses an external 1.2V clock input.
C2
OSCIN
Clock Input
to PLL
X1
OSCOUT
C1
OSCVSS
Figure 5-6. On-Chip 1.2V Oscillator
Table 5-3. Oscillator Timing Requirements
PARAMETER
MIN
MAX
UNIT
fosc
Oscillator frequency range (OSCIN/OSCOUT)
12
30
MHz
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Clock
Input
to PLL
OSCIN
OSCOUT
NC
OSCVSS
Figure 5-7. External 1.2V Clock Source
Table 5-4. OSCIN Timing Requirements
PARAMETER
OSCIN frequency range (OSCIN)
MIN
MAX
UNIT
MHz
ns
fOSCIN
12
50
tc(OSCIN)
tw(OSCINH)
tw(OSCINL)
tt(OSCIN)
tj(OSCIN)
Cycle time, external clock driven on OSCIN
Pulse width high, external clock on OSCIN
Pulse width low, external clock on OSCIN
Transition time, OSCIN
20
0.4 tc(OSCIN)
0.4 tc(OSCIN)
ns
ns
(1)
0.25P or 10
0.02P
ns
Period jitter, OSCIN
ns
(1) Whichever is smaller. P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve
noise immunity on input signals.
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5.7 Clock PLLs
The OMAP-L137 has one PLL controller that provides clock to different parts of the system. PLL0 provides
clocks (though various dividers) to most of the components of the device.
The PLL controller provides the following:
•
•
•
•
Glitch-Free Transitions (on changing clock settings)
Domain Clocks Alignment
Clock Gating
PLL power down
The various clock outputs given by the controller are as follows:
•
•
Domain Clocks: SYSCLK [1:n]
Auxiliary Clock from reference clock source: AUXCLK
Various dividers that can be used are as follows:
•
•
Post-PLL Divider: POSTDIV
SYSCLK Divider: D1, ¼, Dn
Various other controls supported are as follows:
•
•
PLL Multiplier Control: PLLM
Software programmable PLL Bypass: PLLEN
5.7.1 PLL Device-Specific Information
The OMAP-L137 DSP generates the high-frequency internal clocks it requires through an on-chip PLL.
The PLL requires some external filtering components to reduce power supply noise as shown in Figure 5-
8.
1.14V - 1.32V
50R
PLL0_VDDA
0.1
µF
0.01
µF
VSS
50R
PLL0_VSSA
Ferrite Bead: Murata BLM31PG500SN1L or Equivalent
Figure 5-8. PLL External Filtering Components
The input to the PLL is either from the on-chip oscillator (OSCIN pin) or from an external clock on the
OSCIN pin. The PLL outputs seven clocks that have programmable divider options. Figure 5-9 illustrates
the PLL Topology.
The PLL is disabled by default after a device reset. It must be configured by software according to the
allowable operating conditions listed in Table 5-5 before enabling the DSP to run from the PLL by setting
PLLEN = 1.
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CLKMODE
PLLEN
Square
1
Wave
PLLDIV1 (/1)
PLLDIV2 (/2)
OSCIN
Pre-Div
PLL
Post-Div
1
0
SYSCLK1
Crystal
0
SYSCLK2
PLLM
PLLDIV3 (/3)
PLLDIV4 (/4)
SYSCLK3
SYSCLK4
PLLDIV5 (/3)
PLLDIV6 (/1)
PLLDIV7 (/6)
SYSCLK5
SYSCLK6
SYSCLK7
AUXCLK
EMIFA
0
1
Internal
Clock
Source
DIV4.5
CFGCHIP3[EMA_CLKSRC]
EMIFB
DIV4.5
1
0
Internal
Clock
Source
CFGCHIP3[EMB_CLKSRC]
OBSCLK Pin
14h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
OSCDIV
SYSCLK1
SYSCLK2
SYSCLK3
SYSCLK4
SYSCLK5
SYSCLK6
SYSCLK7
OCSEL[OCSRC]
Figure 5-9. PLL Topology
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Table 5-5. Allowed PLL Operating Conditions
Default
Value
No.
PARAMETER
MIN
MAX
N/A
UNIT
PLLRST: Assertion time during
initialization
1
N/A
1000
ns
2000 N
m
Max PLL Lock Time =
Lock time: The time that the application
has to wait for the PLL to acquire locks
before setting PLLEN, after changing
PREDIV, PLLM, or OSCIN
OSCIN
cycles
2
N/A
/1
N/A
where N = Pre-Divider Ratio
M = PLL Multiplier
3
4
PREDIV
/1
/32
PLL input frequency
( PLLREF)
30 (if internal oscillator is used)
50 (if external clock source is used)
12
MHz
MHz
(1)
5
6
7
PLL multiplier values (PLLM)
x20
N/A
/1
x4
300
/1
x32
600
/32
PLL output frequency. ( PLLOUT )
POSTDIV
(1) The multiplier values must be chosen such that the PLL output frequency (at PLLOUT) is between 300 and 600 MHz, but the frequency
going into the SYSCLK dividers (after the post divider) cannot exceed the maximum clock frequency defined for the device at a given
voltage operating point.
5.7.2 Device Clock Generation
PLL0 is controlled by PLL Controller 0. The PLLC0 manages the clock ratios, alignment, and gating for the
system clocks to the chip. The PLLC is responsible for controlling all modes of the PLL through software,
in terms of pre-division of the clock inputs, multiply factor within the PLL, and post-division for each of the
chip-level clocks from the PLL output. The PLLC also controls reset propagation through the chip, clock
alignment, and test points.
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5.7.3 PLL Controller 0 Registers
Table 5-6. PLL Controller 0 Registers
BYTE
ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01C1 1000
0x01C1 10E4
0x01C1 1100
0x01C1 1104
0x01C1 1110
0x01C1 1114
0x01C1 1118
0x01C1 111C
0x01C1 1120
0x01C1 1124
0x01C1 1128
0x01C1 1138
0x01C1 113C
0x01C1 1140
0x01C1 1144
0x01C1 1148
0x01C1 114C
0x01C1 1150
0x01C1 1160
0x01C1 1164
0x01C1 1168
0x01C1 116C
REVID
RSTYPE
PLLCTL
OCSEL
Revision Identification Register
Reset Type Status Register
PLL Control Register
OBSCLK Select Register
PLLM
PLL Multiplier Control Register
PLL Pre-Divider Control Register
PLL Controller Divider 1 Register
PLL Controller Divider 2 Register
PLL Controller Divider 3 Register
PREDIV
PLLDIV1
PLLDIV2
PLLDIV3
OSCDIV
POSTDIV
PLLCMD
PLLSTAT
ALNCTL
DCHANGE
CKEN
Oscillator Divider 1 Register (OBSCLK)
PLL Post-Divider Control Register
PLL Controller Command Register
PLL Controller Status Register
PLL Controller Clock Align Control Register
PLLDIV Ratio Change Status Register
Clock Enable Control Register
Clock Status Register
CKSTAT
SYSTAT
PLLDIV4
PLLDIV5
PLLDIV6
PLLDIV7
SYSCLK Status Register
PLL Controller Divider 4 Register
PLL Controller Divider 5 Register
PLL Controller Divider 6 Register
PLL Controller Divider 7 Register
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5.8 Interrupts
The OMAP-L137 devices have a large number of interrupts to service the needs of its many peripherals
and subsystems. Both the ARM and C674x CPUs are capable of servicing these interrupts equally. The
interrupts can be selectively enabled or disabled in either of the controllers. Also, the ARM and DSP can
communicate with each other through interrupts controlled by registers in the SYSCFG module.
5.8.1 ARM CPU Interrupts
The ARM9 CPU core supports 2 direct interrupts: FIQ and IRQ. The ARM Interrupt Controller on the
OMAP-L13x extends the number of interrupts to 100, and provides features like programmable masking,
priority, hardware nesting support, and interrupt vector generation. The OMAP-L13x ARM Interrupt
controller is enhanced from previous devices like the DM6446 and DM355.
5.8.1.1 ARM Interrupt Controller (AINTC) Interrupt Signal Hierarchy
On OMAP-L13x, the ARM Interrupt controller organizes interrupts into the following hierarchy:
•
Peripheral Interrupt Requests
Individual Interrupt Sources from Peripherals
100 System Interrupts
–
•
–
One or more Peripheral Interrupt Requests are combined (fixed configuration) to generate a
System Interrupt.
–
After prioritization, the AINTC will provide an interrupt vector based unique to each System Interrupt
•
32 Interrupt Channels
–
–
Each System Interrupt is mapped to one of the 32 Interrupt Channels
Channel Number determines the first level of prioritization, Channel 0 is highest priority and 31
lowest.
–
If more than one system interrupt is mapped to a channel, priority within the channel is determined
by system interrupt number (0 highest priority)
•
•
Host Interrupts (FIQ and IRQ)
–
–
Interrupt Channels 0 and 1 generate the ARM FIQ interrupt
Interrupt Channels 2 through 31 Generate the ARM IRQ interrupt
Debug Interrupts
–
–
Two Debug Interrupts are supported and can be used to trigger events in the debug subsystem
Sources can be selected from any of the System Interrupts or Host Interrupts
5.8.1.2 AINTC Hardware Vector Generation
The AINTC also generates an interrupt vector in hardware for both IRQ and FIQ host interrupts. This may
be used to accelerate interrupt dispatch. A unique vector is generated for each of the 100 system
interrupts. The vector is computed in hardware as:
VECTOR = BASE + (SYSTEM INTERRUPT NUMBER × SIZE)
Where BASE and SIZE are programmable. The computed vector is a 32-bit address which may
dispatched to using a single instruction of type LDR PC, [PC, #-<offset_12>] at the FIQ and IRQ vector
locations (0xFFFF0018 and 0xFFFF001C respectively).
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5.8.1.3 AINTC Hardware Interrupt Nesting Support
Interrupt nesting occurs when an interrupt service routine re-enables interrupts, to allow the CPU to
interrupt the ISR if a higher priority event occurs. The AINTC provides hardware support to facilitate
interrupt nesting. It supports both global and per host interrupt (FIQ and IRQ in this case) automatic
nesting. If enabled, the AINTC will automatically update an internal nesting register that temporarily masks
interrupts at and below the priority of the current interrupt channel. Then if the ISR re-enables interrupts;
only higher priority channels will be able to interrupt it. The nesting level is restored by the ISR by writing
to the nesting level register on completion. Support for nesting can be enabled/disabled by software, with
the option of automatic nesting on a global or per host interrupt basis; or manual nesting.
5.8.1.4 AINTC System Interrupt Assignments on OMAP-L137
System Interrupt assignments for the OMAP-L137 are listed in Table 5-7
Table 5-7. AINTC System Interrupt Assignments
SYSTEM INTERRUPT
INTERRUPT NAME
COMMTX
SOURCE
0
ARM
1
COMMRX
ARM
2
NINT
ARM
3
PRU_EVTOUT0
PRU_EVTOUT1
PRU_EVTOUT2
PRU_EVTOUT3
PRU_EVTOUT4
PRU_EVTOUT5
PRU_EVTOUT6
PRU_EVTOUT7
EDMA3_CC0_CCINT
EDMA3_CC0_CCERRINT
EDMA3_TC0_TCERRINT
EMIFA_INT
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
EDMA Channel Controller Region 0
EDMA Channel Controller
EDMA Transfer Controller 0
EMIFA
IIC0_INT
I2C0
MMCSD_INT0
MMCSD_INT1
PSC0_ALLINT
RTC_IRQS[1:0]
SPI0_INT
MMCSD
MMCSD
PSC0
RTC
SPI0
T64P0_TINT12
T64P0_TINT34
T64P1_TINT12
T64P1_TINT34
UART0_INT
Timer64P0 Interrupt 12
Timer64P0 Interrupt 34
Timer64P1 Interrupt 12
Timer64P1 Interrupt 34
UART0
-
Reserved
MPU_BOOTCFG_ERR
Shared MPU and SYSCFG Address/Protection Error
Interrupt
28
29
30
31
32
33
SYSCFG_CHIPINT0
SYSCFG_CHIPINT1
SYSCFG_CHIPINT2
SYSCFG_CHIPINT3
EDMA3_TC1_TCERRINT
EMAC_C0RXTHRESH
SYSCFG CHIPSIG Register
SYSCFG CHIPSIG Register
SYSCFG CHIPSIG Register
SYSCFG CHIPSIG Register
EDMA Transfer Controller 1
EMAC - Core 0 Receive Threshold Interrupt
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Table 5-7. AINTC System Interrupt Assignments (continued)
SYSTEM INTERRUPT
INTERRUPT NAME
EMAC_C0RX
EMAC_C0TX
EMAC_C0MISC
EMAC_C1RXTHRESH
EMAC_C1RX
EMAC_C1TX
EMAC_C1MISC
EMIF_MEMERR
GPIO_B0INT
GPIO_B1INT
GPIO_B2INT
GPIO_B3INT
GPIO_B4INT
GPIO_B5INT
GPIO_B6INT
GPIO_B7INT
-
SOURCE
EMAC - Core 0 Receive Interrupt
EMAC - Core 0 Transmit Interrupt
EMAC - Core 0 Miscellaneous Interrupt
EMAC - Core 1 Receive Threshold Interrupt
EMAC - Core 1 Receive Interrupt
EMAC - Core 1 Transmit Interrupt
EMAC - Core 1 Miscellaneous Interrupt
EMIFB
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
GPIO Bank 0 Interrupt
GPIO Bank 1 Interrupt
GPIO Bank 2 Interrupt
GPIO Bank 3 Interrupt
GPIO Bank 4 Interrupt
GPIO Bank 5 Interrupt
GPIO Bank 6 Interrupt
GPIO Bank 7 Interrupt
Reserved
IIC1_INT
I2C1
LCDC_INT
LCD Controller
UART_INT1
MCASP_INT
PSC1_ALLINT
SPI1_INT
UART1
McASP0, 1, 2 Combined RX / TX Interrupts
PSC1
SPI1
UHPI_ARMINT
USB0_INT
HPI ARM Interrupt
USB0 Interrupt
USB1_HCINT
USB1_RWAKEUP
UART2_INT
-
USB1 OHCI Host Controller Interrupt
USB1 Remote Wakeup Interrupt
UART2
Reserved
EHRPWM0
HiResTimer / PWM0 Interrupt
HiResTimer / PWM0 Trip Zone Interrupt
HiResTimer / PWM1 Interrupt
HiResTimer / PWM1 Trip Zone Interrupt
HiResTimer / PWM2 Interrupt
HiResTimer / PWM2 Trip Zone Interrupt
ECAP0
EHRPWM0TZ
EHRPWM1
EHRPWM1TZ
EHRPWM2
EHRPWM2TZ
ECAP0
ECAP1
ECAP1
ECAP2
ECAP2
EQEP0
EQEP0
EQEP1
EQEP1
T64P0_CMPINT0
T64P0_CMPINT1
T64P0_CMPINT2
T64P0_CMPINT3
T64P0_CMPINT4
T64P0_CMPINT5
T64P0_CMPINT6
Timer64P0 - Compare 0
Timer64P0 - Compare 1
Timer64P0 - Compare 2
Timer64P0 - Compare 3
Timer64P0 - Compare 4
Timer64P0 - Compare 5
Timer64P0 - Compare 6
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Table 5-7. AINTC System Interrupt Assignments (continued)
SYSTEM INTERRUPT
INTERRUPT NAME
T64P0_CMPINT7
T64P1_CMPINT0
T64P1_CMPINT1
T64P1_CMPINT2
T64P1_CMPINT3
T64P1_CMPINT4
T64P1_CMPINT5
T64P1_CMPINT6
T64P1_CMPINT7
ARMCLKSTOPREQ
-
SOURCE
Timer64P0 - Compare 7
81
82
Timer64P1 - Compare 0
Timer64P1 - Compare 1
Timer64P1 - Compare 2
Timer64P1 - Compare 3
Timer64P1 - Compare 4
Timer64P1 - Compare 5
Timer64P1 - Compare 6
Timer64P1 - Compare 7
PSC0
83
84
85
86
87
88
89
90
91 - 100
Reserved
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5.8.1.5 AINTC Memory Map
Table 5-8. AINTC Memory Map
BYTE ADDRESS
0xFFFE E000
ACRONYM
REGISTER DESCRIPTION
REV
Revision Register
Control Register
Reserved
0xFFFE E004
CR
0xFFFE E008 - 0xFFFE E00F
0xFFFE E010
-
GER
Global Enable Register
Reserved
0xFFFE E014 - 0xFFFE E01B
0xFFFE E01C
-
GNLR
Global Nesting Level Register
System Interrupt Status Indexed Set Register
System Interrupt Status Indexed Clear Register
System Interrupt Enable Indexed Set Register
System Interrupt Enable Indexed Clear Register
Reserved
0xFFFE E020
SISR
0xFFFE E024
SICR
0xFFFE E028
EISR
0xFFFE E02C
EICR
0xFFFE E030
-
0xFFFE E034
HIEISR
Host Interrupt Enable Indexed Set Register
Host Interrupt Enable Indexed Clear Register
Reserved
0xFFFE E038
HIDISR
0xFFFE E03C - 0xFFFE E04F
0xFFFE E050
-
VBR
Vector Base Register
0xFFFE E054
VSR
Vector Size Register
0xFFFE E058
VNR
Vector Null Register
0xFFFE E05C - 0xFFFE E07F
0xFFFE E080
-
Reserved
GPIR
Global Prioritized Index Register
Global Prioritized Vector Register
Reserved
0xFFFE E084
GPVR
0xFFFE E088 - 0xFFFE E1FF
0xFFFE E200 - 0xFFFE E20B
0xFFFE E20C- 0xFFFE E27F
0xFFFE E280 - 0xFFFE E28B
0xFFFE E28C - 0xFFFE E2FF
0xFFFE E300 - 0xFFFE E30C
0xFFFE E30C - 0xFFFE E37F
0xFFFE E380 - 0xFFFE E38B
0xFFFE E38C - 0xFFFE E3FF
0xFFFE E400 - 0xFFFE E458
0xFFFE E459 - 0xFFFE E7FF
0xFFFE E800 - 0xFFFE E81F
0xFFFE E820 - 0xFFFE E8FF
0xFFFE E900 - 0xFFFE E904
0xFFFE E908 - 0xFFFE EEFF
0xFFFE EF00 - 0xFFFE EF04
0xFFFE EF08 - 0xFFFE F0FF
0xFFFE F100 - 0xFFFE F104
0xFFFE F108 - 0xFFFE F4FF
0xFFFE F500
-
SRSR[1] - SRSR[3]
System Interrupt Status Raw / Set Registers
Reserved
-
SECR[1] - SECR[3]
System Interrupt Status Enabled / Clear Registers
Reserved
-
ESR[1] - ESR[3]
System Interrupt Enable Set Registers
Reserved
-
ECR[1] - ECR[3]
System Interrupt Enable Clear Registers
Reserved
-
CMR[0] - CMR[22]
Channel Map Registers (Byte Wide Registers)
Reserved
-
-
Reserved
-
Reserved
HIPIR[1] - HIPIR[2]
Host Interrupt Prioritized Index Registers
Reserved
-
-
-
Reserved
Reserved
HINLR[1] - HINLR[2] Host Interrupt Nesting Level Registers
-
HIER
-
Reserved
Host Interrupt Enable Register
Reserved
0xFFFE F504 - 0xFFFE F5FF
0xFFFE F600
HIPVR[1] - HIPVR[2] Host Interrupt Prioritized Vector Registers
Reserved
0xFFFE F608 - 0xFFFE FFFF
-
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5.8.2 DSP Interrupts
The C674x DSP interrupt controller combines device events into 12 prioritized interrupts. The source for
each of the 12 CPU interrupts is user programmable and is listed in Table 5-9. Also, the interrupt
controller controls the generation of the CPU exception, NMI, and emulation interrupts. Table 5-10
summarizes the C674x interrupt controller registers and memory locations.
Table 5-9. OMAP-L137 DSP Interrupts
EVT#
0
INTERRUPT NAME
EVT0
SOURCE
C674x Int Ctl 0
1
EVT1
C674x Int Ctl 1
2
EVT2
C674x Int Ctl 2
3
EVT3
C674x Int Ctl 3
4
T64P0_TINT12
SYSCFG_CHIPINT2
PRU_EVTOUT0
EHRPWM0
Timer64P0 - TINT12
5
SYSCFG_CHIPSIG Register
PRU Interrupt
6
7
HiResTimer/PWM0 Interrupt
EDMA3 Channel Controller 0 Region 1 interrupt
C674x-ECM
8
EDMA3_CC0_INT1
EMU-DTDMA
EHRPWM0TZ
EMU-RTDXRX
EMU-RTDXTX
IDMAINT0
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
HiResTimer/PWM0 Trip Zone Interrupt
C674x-RTDX
C674x-RTDX
C674x-EMC
IDMAINT1
C674x-EMC
MMCSD_INT0
MMCSD_INT1
PRU_EVTOUT1
EHRPWM1
MMCSD MMC/SD Interrupt
MMCSD SDIO Interrupt
PRU Interrupt
HiResTimer/PWM1 Interrupt
USB0 Interrupt
USB0_INT
USB1_HCINT
USB1_RWAKEUP
PRU_EVTOUT2
EHRPWM1TZ
EHRPWM2
USB1 OHCI Host Controller Interrupt
USB1 Remote Wakeup Interrupt
PRU Interrupt
HiResTimer/PWM1 Trip Zone Interrupt
HiResTimer/PWM2 Interrupt
HiResTimer/PWM2 Trip Zone Interrupt
EMAC - Core 0 Receive Threshold Interrupt
EMAC - Core 0 Receive Interrupt
EMAC - Core 0 Transmit Interrupt
EMAC - Core 0 Miscellaneous Interrupt
EMAC - Core 1 Receive Threshold Interrupt
EMAC - Core 1 Receive Interrupt
EMAC - Core 1 Transmit Interrupt
EMAC - Core 1 Miscellaneous Interrupt
UHPI DSP Interrupt
EHRPWM2TZ
EMAC_C0RXTHRESH
EMAC_C0RX
EMAC_C0TX
EMAC_C0MISC
EMAC_C1RXTHRESH
EMAC_C1RX
EMAC_C1TX
EMAC_C1MISC
UHPI_DSPINT
PRU_EVTOUT3
IIC0_INT
PRU Interrupt
I2C0
SP0_INT
SPI0
UART0_INT
UART0
PRU_EVTOUT5
T64P1_TINT12
PRU Interrupt
Timer64P1 Interrupt 12
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Table 5-9. OMAP-L137 DSP Interrupts (continued)
EVT#
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75 - 77
78
79
80
81
82
83
84
85
86
87
88
89
INTERRUPT NAME
GPIO_B1INT
SOURCE
GPIO Bank 1 Interrupt
I2C1
IIC1_INT
SPI1_INT
SPI1
PRU_EVTOUT6
ECAP0
PRU Interrupt
ECAP0
UART_INT1
UART1
ECAP1
ECAP1
T64P1_TINT34
GPIO_B2INT
Timer64P1 Interrupt 34
GPIO Bank 2 Interrupt
PRU Interrupt
PRU_EVTOUT7
ECAP2
ECAP2
GPIO_B3INT
GPIO Bank 3 Interrupt
EQEP1
EQEP1
GPIO_B4INT
GPIO Bank 4 Interrupt
EMIFA
EMIFA_INT
EDMA3_CC0_ERRINT
EDMA3_TC0_ERRINT
EDMA3_TC1_ERRINT
GPIO_B5INT
EDMA3 Channel Controller 0
EDMA3 Transfer Controller 0
EDMA3 Transfer Controller 1
GPIO Bank 5 Interrupt
EMIFB Memory Error Interrupt
McASP0,1,2 Combined RX/TX Interrupts
GPIO Bank 6 Interrupt
RTC Combined
EMIFB_INT
MCASP_INT
GPIO_B6INT
RTC_IRQS
T64P0_TINT34
GPIO_B0INT
Timer64P0 Interrupt 34
GPIO Bank 0 Interrupt
PRU Interrupt
PRU_EVTOUT4
SYSCFG_CHIPINT3
EQEP0
SYSCFG_CHIPSIG Register
EQEP0
UART2_INT
UART2
PSC0_ALLINT
PSC1_ALLINT
GPIO_B7INT
PSC0
PSC1
GPIO Bank 7 Interrupt
LCD Controller
LCDC_INT
MPU_BOOTCFG_ERR
-
Shared MPU and SYSCFG Address/Protection Error Interrupt
Reserved
T64P0_CMPINT0
T64P0_CMPINT1
T64P0_CMPINT2
T64P0_CMPINT3
T64P0_CMPINT4
T64P0_CMPINT5
T64P0_CMPINT6
T64P0_CMPINT7
T64P1_CMPINT0
T64P1_CMPINT1
T64P1_CMPINT2
T64P1_CMPINT3
Timer64P0 - Compare 0
Timer64P0 - Compare 1
Timer64P0 - Compare 2
Timer64P0 - Compare 3
Timer64P0 - Compare 4
Timer64P0 - Compare 5
Timer64P0 - Compare 6
Timer64P0 - Compare 7
Timer64P1 - Compare 0
Timer64P1 - Compare 1
Timer64P1 - Compare 2
Timer64P1 - Compare 3
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Table 5-9. OMAP-L137 DSP Interrupts (continued)
EVT#
90
INTERRUPT NAME
T64P1_CMPINT4
T64P1_CMPINT5
T64P1_CMPINT6
T64P1_CMPINT7
-
SOURCE
Timer64P1 - Compare 4
Timer64P1 - Compare 5
Timer64P1 - Compare 6
Timer64P1 - Compare 7
Reserved
91
92
93
94 - 95
96
INTERR
C674x-Int Ctl
C674x-EMC
97
EMC_IDMAERR
-
98 - 112
113
Reserved
PMC_ED
C674x-PMC
114 - 115
116
-
Reserved
UMC_ED1
C674x-UMC
117
UMC_ED2
C674x-UMC
118
PDC_INT
C674x-PDC
119
SYS_CMPA
PMC_CMPA
PMC_CMPA
DMC_CMPA
DMC_CMPA
UMC_CMPA
UMC_CMPA
EMC_CMPA
EMC_BUSERR
C674x-SYS
120
C674x-PMC
121
C674x-PMC
122
C674x-DMC
123
C674x-DMC
124
C674x-UMC
125
C674x-UMC
126
C674x-EMC
127
C674x-EMC
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Table 5-10. C674x DSP Interrupt Controller Registers
BYTE ADDRESS
0x0180 0000
0x0180 0004
0x0180 0008
0x0180 000C
0x0180 0020
0x0180 0024
0x0180 0028
0x0180 002C
0x0180 0040
0x0180 0044
0x0180 0048
0x0180 004C
0x0180 0080
0x0180 0084
0x0180 0088
0x0180 008C
0x0180 00A0
0x0180 00A4
0x0180 00A8
0x0180 00AC
0x0180 00C0
0x0180 00C4
0x0180 00C8
0x0180 00CC
0x0180 00E0
0x0180 00E4
0x0180 00E8
0x0180 00EC
0x0180 0104
0x0180 0108
0x0180 010C
ACRONYM
EVTFLAG0
EVTFLAG1
EVTFLAG2
EVTFLAG3
EVTSET0
REGISTER DESCRIPTION
Event flag register 0
Event flag register 1
Event flag register 2
Event flag register 3
Event set register 0
EVTSET1
Event set register 1
EVTSET2
Event set register 2
EVTSET3
Event set register 3
EVTCLR0
Event clear register 0
EVTCLR1
Event clear register 1
EVTCLR2
Event clear register 2
EVTCLR3
Event clear register 3
EVTMASK0
EVTMASK1
EVTMASK2
EVTMASK3
MEVTFLAG0
MEVTFLAG1
MEVTFLAG2
MEVTFLAG3
EXPMASK0
EXPMASK1
EXPMASK2
EXPMASK3
MEXPFLAG0
MEXPFLAG1
MEXPFLAG2
MEXPFLAG3
INTMUX1
Event mask register 0
Event mask register 1
Event mask register 2
Event mask register 3
Masked event flag register 0
Masked event flag register 1
Masked event flag register 2
Masked event flag register 3
Exception mask register 0
Exception mask register 1
Exception mask register 2
Exception mask register 3
Masked exception flag register 0
Masked exception flag register 1
Masked exception flag register 2
Masked exception flag register 3
Interrupt mux register 1
Interrupt mux register 2
Interrupt mux register 3
Reserved
INTMUX2
INTMUX3
0x0180 0140 - 0x0180 0144
0x0180 0180
-
INTXSTAT
INTXCLR
Interrupt exception status
Interrupt exception clear
Dropped interrupt mask register
Event assert register
0x0180 0184
0x0180 0188
INTDMASK
EVTASRT
0x0180 01C0
5.8.3 ARM/DSP Communications Interrupts
Communications Interrupts between the ARM and DSP are part of the SYSCFG module on the OMAP-
L13x family of devices.
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5.9 General-Purpose Input/Output (GPIO)
The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.
When configured as an output, a write to an internal register can control the state driven on the output pin.
When configured as an input, the state of the input is detectable by reading the state of an internal
register. In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different
interrupt/event generation modes. The GPIO peripheral provides generic connections to external devices.
The GPIO pins are grouped into banks of 16 pins per bank (i.e., bank 0 consists of GPIO [0:15]).
The OMAP-L137 GPIO peripheral supports the following:
•
•
Up to 128 Pins on ZKB package configurable as GPIO
External Interrupt and DMA request Capability
–
–
–
–
–
–
Every GPIO pin may be configured to generate an interrupt request on detection of rising and/or
falling edges on the pin.
The interrupt requests within each bank are combined (logical or) to create eight unique bank level
interrupt requests.
The bank level interrupt service routine may poll the INTSTATx register for its bank to determine
which pin(s) have triggered the interrupt.
GPIO Banks 0, 1, 2, 3, 4, 5, 6, and 7 Interrupts assigned to ARM INTC Interrupt Requests 42, 43,
44, 45, 46, 47, 48, and 49 respectively
GPIO Banks 0, 1, 2, 3, 4, 5, 6, and 7 Interrupts assigned to DSP Events 65, 41, 49, 52, 54, 59, 62
and 72 respectively
Additionally, GPIO Banks 0, 1, 2, 3, 4, and 5 Interrupts assigned to EDMA events 6, 7, 22, 23, 28,
and 29 respectively.
•
Set/clear functionality: Firmware writes 1 to corresponding bit position(s) to set or to clear GPIO
signal(s). This allows multiple firmware processes to toggle GPIO output signals without critical section
protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to
anther process during GPIO programming).
•
•
Separate Input/Output registers
Output register in addition to set/clear so that, if preferred by firmware, some GPIO output signals can
be toggled by direct write to the output register(s).
•
Output register, when read, reflects output drive status. This, in addition to the input register reflecting
pin status and open-drain I/O cell, allows wired logic be implemented.
The memory map for the GPIO registers is shown in Table 5-11. See the OMAP-L137 Applications
Processor DSP Peripherals Overview Reference Guide. (SPRUGA6) for more details.
5.9.1 GPIO Register Description(s)
Table 5-11. GPIO Registers
BYTE ADDRESS
0x01E2 6000
0x01E2 6004
0x01E2 6008
ACRONYM
REV
REGISTER DESCRIPTION
Peripheral Revision Register
Reserved
-
BINTEN
GPIO Interrupt Per-Bank Enable Register
GPIO BANKS 0 AND 1
0x01E2 6010
0x01E2 6014
0x01E2 6018
0x01E2 601C
0x01E2 6020
0x01E2 6024
0x01E2 6028
DIR01
GPIO Banks 0 and 1 Direction Register
GPIO Banks 0 and 1 Output Data Register
GPIO Banks 0 and 1 Set Data Register
OUT_DATA01
SET_DATA01
CLR_DATA01
IN_DATA01
GPIO Banks 0 and 1 Clear Data Register
GPIO Banks 0 and 1 Input Data Register
SET_RIS_TRIG01
CLR_RIS_TRIG01
GPIO Banks 0 and 1 Set Rising Edge Interrupt Register
GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register
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Table 5-11. GPIO Registers (continued)
BYTE ADDRESS
ACRONYM
SET_FAL_TRIG01
CLR_FAL_TRIG01
INTSTAT01
REGISTER DESCRIPTION
0x01E2 602C
0x01E2 6030
0x01E2 6034
GPIO Banks 0 and 1 Set Falling Edge Interrupt Register
GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register
GPIO Banks 0 and 1 Interrupt Status Register
GPIO BANKS 2 AND 3
0x01E2 6038
0x01E2 603C
0x01E2 6040
0x01E2 6044
0x01E2 6048
0x01E2 604C
0x01E2 6050
0x01E2 6054
0x01E2 6058
0x01E2 605C
DIR23
GPIO Banks 2 and 3 Direction Register
GPIO Banks 2 and 3 Output Data Register
OUT_DATA23
SET_DATA23
CLR_DATA23
IN_DATA23
GPIO Banks 2 and 3 Set Data Register
GPIO Banks 2 and 3 Clear Data Register
GPIO Banks 2 and 3 Input Data Register
SET_RIS_TRIG23
CLR_RIS_TRIG23
SET_FAL_TRIG23
CLR_FAL_TRIG23
INTSTAT23
GPIO Banks 2 and 3 Set Rising Edge Interrupt Register
GPIO Banks 2 and 3 Clear Rising Edge Interrupt Register
GPIO Banks 2 and 3 Set Falling Edge Interrupt Register
GPIO Banks 2 and 3 Clear Falling Edge Interrupt Register
GPIO Banks 2 and 3 Interrupt Status Register
GPIO BANKS 4 AND 5
0x01E2 6060
0x01E2 6064
0x01E2 6068
0x01E2 606C
0x01E2 6070
0x01E2 6074
0x01E2 6078
0x01E2 607C
0x01E2 6080
0x01E2 6084
DIR45
GPIO Banks 4 and 5 Direction Register
GPIO Banks 4 and 5 Output Data Register
OUT_DATA45
SET_DATA45
CLR_DATA45
IN_DATA45
GPIO Banks 4 and 5 Set Data Register
GPIO Banks 4 and 5 Clear Data Register
GPIO Banks 4 and 5 Input Data Register
SET_RIS_TRIG45
CLR_RIS_TRIG45
SET_FAL_TRIG45
CLR_FAL_TRIG45
INTSTAT45
GPIO Banks 4 and 5 Set Rising Edge Interrupt Register
GPIO Banks 4 and 5 Clear Rising Edge Interrupt Register
GPIO Banks 4 and 5 Set Falling Edge Interrupt Register
GPIO Banks 4 and 5 Clear Falling Edge Interrupt Register
GPIO Banks 4 and 5 Interrupt Status Register
GPIO BANKS 6 AND 7
0x01E2 6088
0x01E2 608C
0x01E2 6090
0x01E2 6094
0x01E2 6098
0x01E2 609C
0x01E2 60A0
0x01E2 60A4
0x01E2 60A8
0x01E2 60AC
DIR67
GPIO Banks 6 and 7 Direction Register
GPIO Banks 6 and 7 Output Data Register
OUT_DATA67
SET_DATA67
CLR_DATA67
IN_DATA67
GPIO Banks 6 and 7 Set Data Register
GPIO Banks 6 and 7 Clear Data Register
GPIO Banks 6 and 7 Input Data Register
SET_RIS_TRIG67
CLR_RIS_TRIG67
SET_FAL_TRIG67
CLR_FAL_TRIG67
INTSTAT67
GPIO Banks 6 and 7 Set Rising Edge Interrupt Register
GPIO Banks 6 and 7 Clear Rising Edge Interrupt Register
GPIO Banks 6 and 7 Set Falling Edge Interrupt Register
GPIO Banks 6 and 7 Clear Falling Edge Interrupt Register
GPIO Banks 6 and 7 Interrupt Status Register
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5.9.2 GPIO Peripheral Input/Output Electrical Data/Timing
Table 5-12. Timing Requirements for GPIO Inputs(1) (see Figure 5-10)
No.
1
PARAMETER
MIN
MAX
UNIT
ns
tw(GPIH)
tw(GPIL)
Pulse duration, GPn[m] as input high
Pulse duration, GPn[m] as input low
2C(1) (2)
2C(1) (2)
2
ns
(1) The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have OMAP-L137
recognize the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to allow OMAP-L137
enough time to access the GPIO register through the internal bus.
(2) C=SYSCLK4 period in ns.
Table 5-13. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see Figure 5-10)
No.
3
PARAMETER
Pulse duration, GPn[m] as output high
Pulse duration, GPn[m] as output low
MIN
MAX
UNIT
ns
tw(GPOH)
tw(GPOL)
2C(1) (2)
2C(1) (2)
4
ns
(1) This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the
GPIO is dependent upon internal bus activity.
(2) C=SYSCLK4 period in ns.
2
1
GPn[m] as input
4
3
GPn[m] as output
Figure 5-10. GPIO Port Timing
5.9.3 GPIO Peripheral External Interrupts Electrical Data/Timing
Table 5-14. Timing Requirements for External Interrupts(1) (see Figure 5-11)
No.
1
PARAMETER
Width of the external interrupt pulse low
Width of the external interrupt pulse high
MIN
2C(1) (2)
MAX
UNIT
ns
tw(ILOW)
tw(IHIGH)
(1) (2)
2
2C
ns
(1) The pulse width given is sufficient to generate an interrupt or an EDMA event. However, if a user wants to have OMAP-L137 recognize
the GPIO changes through software polling of the GPIO register, the GPIO duration must be extended to allow OMAP-L137 enough
time to access the GPIO register through the internal bus.
(2) C=SYSCLK4 period in ns.
2
1
GPn[m] as input
Figure 5-11. GPIO External Interrupt Timing
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5.10 EDMA
Table 5-15 is the list of EDMA3 Channel Contoller Registers and Table 5-16 is the list of EDMA3 Transfer
Controller registers.
Table 5-15. EDMA3 Channel Controller (EDMA3CC) Registers
BYTE ADDRESS
0x01C0 0000
ACRONYM
PID
REGISTER DESCRIPTION
Peripheral Identification Register
0x01C0 0004
CCCFG
EDMA3CC Configuration Register
GLOBAL REGISTERS
0x01C0 0200
0x01C0 0204
0x01C0 0208
0x01C0 020C
0x01C0 0210
0x01C0 0214
0x01C0 0218
0x01C0 021C
0x01C0 0240
0x01C0 0244
0x01C0 0248
0x01C0 024C
0x01C0 0260
0x01C0 0284
0x01C0 0300
0x01C0 0308
0x01C0 0310
0x01C0 0314
0x01C0 0318
0x01C0 031C
0x01C0 0320
0x01C0 0340
0x01C0 0348
0x01C0 0350
0x01C0 0358
0x01C0 0380
0x01C0 0384
0x01C0 0388
0x01C0 038C
0x01C0 0400 - 0x01C0 043C
0x01C0 0440 - 0x01C0 047C
0x01C0 0600
0x01C0 0604
0x01C0 0620
0x01C0 0640
QCHMAP0
QCHMAP1
QCHMAP2
QCHMAP3
QCHMAP4
QCHMAP5
QCHMAP6
QCHMAP7
DMAQNUM0
DMAQNUM1
DMAQNUM2
DMAQNUM3
QDMAQNUM
QUEPRI
QDMA Channel 0 Mapping Register
QDMA Channel 1 Mapping Register
QDMA Channel 2 Mapping Register
QDMA Channel 3 Mapping Register
QDMA Channel 4 Mapping Register
QDMA Channel 5 Mapping Register
QDMA Channel 6 Mapping Register
QDMA Channel 7 Mapping Register
DMA Channel Queue Number Register 0
DMA Channel Queue Number Register 1
DMA Channel Queue Number Register 2
DMA Channel Queue Number Register 3
QDMA Channel Queue Number Register
Queue Priority Register(1)
EMR
Event Missed Register
EMCR
Event Missed Clear Register
QEMR
QDMA Event Missed Register
QEMCR
QDMA Event Missed Clear Register
EDMA3CC Error Register
CCERR
CCERRCLR
EEVAL
EDMA3CC Error Clear Register
Error Evaluate Register
DRAE0
DMA Region Access Enable Register for Region 0
DMA Region Access Enable Register for Region 1
DMA Region Access Enable Register for Region 2
DMA Region Access Enable Register for Region 3
QDMA Region Access Enable Register for Region 0
QDMA Region Access Enable Register for Region 1
QDMA Region Access Enable Register for Region 2
QDMA Region Access Enable Register for Region 3
Event Queue Entry Registers Q0E0-Q0E15
Event Queue Entry Registers Q1E0-Q1E15
Queue 0 Status Register
DRAE1
DRAE2
DRAE3
QRAE0
QRAE1
QRAE2
QRAE3
Q0E0-Q0E15
Q1E0-Q1E15
QSTAT0
QSTAT1
Queue 1 Status Register
QWMTHRA
CCSTAT
Queue Watermark Threshold A Register
EDMA3CC Status Register
GLOBAL CHANNEL REGISTERS
Event Register
0x01C0 1000
0x01C0 1008
ER
ECR
Event Clear Register
(1) On previous architectures, the EDMA3TC priority was controlled by the queue priority register (QUEPRI) in the EDMA3CC memory-
map. However for this device, the priority control for the transfer controllers is controlled by the chip-level registers in the System
Configuration Module. You should use the chip-level registers and not QUEPRI to configure the TC priority.
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Table 5-15. EDMA3 Channel Controller (EDMA3CC) Registers (continued)
BYTE ADDRESS
0x01C0 1010
0x01C0 1018
0x01C0 1020
0x01C0 1028
0x01C0 1030
0x01C0 1038
0x01C0 1040
0x01C0 1050
0x01C0 1058
0x01C0 1060
0x01C0 1068
0x01C0 1070
0x01C0 1078
0x01C0 1080
0x01C0 1084
0x01C0 1088
0x01C0 108C
0x01C0 1090
0x01C0 1094
ACRONYM
ESR
REGISTER DESCRIPTION
Event Set Register
CER
Chained Event Register
Event Enable Register
Event Enable Clear Register
Event Enable Set Register
Secondary Event Register
EER
EECR
EESR
SER
SECR
IER
Secondary Event Clear Register
Interrupt Enable Register
IECR
Interrupt Enable Clear Register
Interrupt Enable Set Register
Interrupt Pending Register
IESR
IPR
ICR
Interrupt Clear Register
IEVAL
QER
Interrupt Evaluate Register
QDMA Event Register
QEER
QEECR
QEESR
QSER
QSECR
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
SHADOW REGION 0 CHANNEL REGISTERS
Event Register
0x01C0 2000
0x01C0 2008
0x01C0 2010
0x01C0 2018
0x01C0 2020
0x01C0 2028
0x01C0 2030
0x01C0 2038
0x01C0 2040
0x01C0 2050
0x01C0 2058
0x01C0 2060
0x01C0 2068
0x01C0 2070
0x01C0 2078
0x01C0 2080
0x01C0 2084
0x01C0 2088
0x01C0 208C
0x01C0 2090
0x01C0 2094
ER
ECR
Event Clear Register
ESR
Event Set Register
CER
Chained Event Register
EER
Event Enable Register
EECR
EESR
SER
Event Enable Clear Register
Event Enable Set Register
Secondary Event Register
Secondary Event Clear Register
Interrupt Enable Register
Interrupt Enable Clear Register
Interrupt Enable Set Register
Interrupt Pending Register
Interrupt Clear Register
SECR
IER
IECR
IESR
IPR
ICR
IEVAL
QER
Interrupt Evaluate Register
QDMA Event Register
QEER
QEECR
QEESR
QSER
QSECR
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
SHADOW REGION 1 CHANNEL REGISTERS
Event Register
0x01C0 2200
0x01C0 2208
0x01C0 2210
0x01C0 2218
0x01C0 2220
ER
ECR
ESR
CER
EER
Event Clear Register
Event Set Register
Chained Event Register
Event Enable Register
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Table 5-15. EDMA3 Channel Controller (EDMA3CC) Registers (continued)
BYTE ADDRESS
ACRONYM
EECR
EESR
SER
REGISTER DESCRIPTION
0x01C0 2228
0x01C0 2230
Event Enable Clear Register
Event Enable Set Register
Secondary Event Register
0x01C0 2238
0x01C0 2240
SECR
IER
Secondary Event Clear Register
Interrupt Enable Register
0x01C0 2250
0x01C0 2258
IECR
Interrupt Enable Clear Register
Interrupt Enable Set Register
Interrupt Pending Register
0x01C0 2260
IESR
0x01C0 2268
IPR
0x01C0 2270
ICR
Interrupt Clear Register
0x01C0 2278
IEVAL
QER
Interrupt Evaluate Register
0x01C0 2280
QDMA Event Register
0x01C0 2284
QEER
QEECR
QEESR
QSER
QSECR
—
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Parameter RAM (PaRAM)
0x01C0 2288
0x01C0 228C
0x01C0 2290
0x01C0 2294
0x01C0 4000 - 0x01C0 4FFF
Table 5-16. EDMA3 Transfer Controller (EDMA3TC) Registers
Transfer Controller 0 Transfer Controller 1
ACRONYM
REGISTER DESCRIPTION
BYTE ADDRESS
0x01C0 8000
0x01C0 8004
0x01C0 8100
0x01C0 8120
0x01C0 8124
0x01C0 8128
0x01C0 812C
0x01C0 8130
0x01C0 8140
0x01C0 8240
0x01C0 8244
0x01C0 8248
0x01C0 824C
0x01C0 8250
0x01C0 8254
0x01C0 8258
0x01C0 825C
0x01C0 8260
0x01C0 8280
0x01C0 8284
0x01C0 8288
0x01C0 8300
0x01C0 8304
0x01C0 8308
0x01C0 830C
0x01C0 8310
BYTE ADDRESS
0x01C0 8400
0x01C0 8404
0x01C0 8500
0x01C0 8520
0x01C0 8524
0x01C0 8528
0x01C0 852C
0x01C0 8530
0x01C0 8540
0x01C0 8640
0x01C0 8644
0x01C0 8648
0x01C0 864C
0x01C0 8650
0x01C0 8654
0x01C0 8658
0x01C0 865C
0x01C0 8660
0x01C0 8680
0x01C0 8684
0x01C0 8688
0x01C0 8700
0x01C0 8704
0x01C0 8708
0x01C0 870C
0x01C0 8710
PID
Peripheral Identification Register
TCCFG
EDMA3TC Configuration Register
TCSTAT
EDMA3TC Channel Status Register
Error Status Register
ERRSTAT
ERREN
Error Enable Register
ERRCLR
ERRDET
ERRCMD
RDRATE
SAOPT
Error Clear Register
Error Details Register
Error Interrupt Command Register
Read Command Rate Register
Source Active Options Register
SASRC
Source Active Source Address Register
Source Active Count Register
SACNT
SADST
Source Active Destination Address Register
Source Active B-Index Register
SABIDX
SAMPPRXY
SACNTRLD
SASRCBREF
SADSTBREF
DFCNTRLD
DFSRCBREF
DFDSTBREF
DFOPT0
Source Active Memory Protection Proxy Register
Source Active Count Reload Register
Source Active Source Address B-Reference Register
Source Active Destination Address B-Reference Register
Destination FIFO Set Count Reload Register
Destination FIFO Set Source Address B-Reference Register
Destination FIFO Set Destination Address B-Reference Register
Destination FIFO Options Register 0
Destination FIFO Source Address Register 0
Destination FIFO Count Register 0
DFSRC0
DFCNT0
DFDST0
Destination FIFO Destination Address Register 0
Destination FIFO B-Index Register 0
DFBIDX0
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Table 5-16. EDMA3 Transfer Controller (EDMA3TC) Registers (continued)
Transfer Controller 0 Transfer Controller 1
ACRONYM
REGISTER DESCRIPTION
BYTE ADDRESS
0x01C0 8314
0x01C0 8340
0x01C0 8344
0x01C0 8348
0x01C0 834C
0x01C0 8350
0x01C0 8354
0x01C0 8380
0x01C0 8384
0x01C0 8388
0x01C0 838C
0x01C0 8390
0x01C0 8394
0x01C0 83C0
0x01C0 83C4
0x01C0 83C8
0x01C0 83CC
0x01C0 83D0
0x01C0 83D4
BYTE ADDRESS
0x01C0 8714
0x01C0 8740
0x01C0 8744
0x01C0 8748
0x01C0 874C
0x01C0 8750
0x01C0 8754
0x01C0 8780
0x01C0 8784
0x01C0 8788
0x01C0 878C
0x01C0 8790
0x01C0 8794
0x01C0 87C0
0x01C0 87C4
0x01C0 87C8
0x01C0 87CC
0x01C0 87D0
0x01C0 87D4
DFMPPRXY0
DFOPT1
Destination FIFO Memory Protection Proxy Register 0
Destination FIFO Options Register 1
DFSRC1
Destination FIFO Source Address Register 1
Destination FIFO Count Register 1
DFCNT1
DFDST1
Destination FIFO Destination Address Register 1
Destination FIFO B-Index Register 1
DFBIDX1
DFMPPRXY1
DFOPT2
Destination FIFO Memory Protection Proxy Register 1
Destination FIFO Options Register 2
DFSRC2
Destination FIFO Source Address Register 2
Destination FIFO Count Register 2
DFCNT2
DFDST2
Destination FIFO Destination Address Register 2
Destination FIFO B-Index Register 2
DFBIDX2
DFMPPRXY2
DFOPT3
Destination FIFO Memory Protection Proxy Register 2
Destination FIFO Options Register 3
DFSRC3
Destination FIFO Source Address Register 3
Destination FIFO Count Register 3
DFCNT3
DFDST3
Destination FIFO Destination Address Register 3
Destination FIFO B-Index Register 3
DFBIDX3
DFMPPRXY3
Destination FIFO Memory Protection Proxy Register 3
Table 5-17 shows an abbreviation of the set of registers which make up the parameter set for each of 128
EDMA events. Each of the parameter register sets consist of 8 32-bit word entries. Table 5-18 shows the
parameter set entry registers with relative memory address locations within each of the parameter sets.
Table 5-17. EDMA Parameter Set RAM
BYTE ADDRESS RANGE
0x01C0 4000 - 0x01C0 401F
0x01C0 4020 - 0x01C0 403F
0x01C0 4040 - 0x01cC0 405F
0x01C0 4060 - 0x01C0 407F
0x01C0 4080 - 0x01C0 409F
0x01C0 40A0 - 0x01C0 40BF
...
DESCRIPTION
Parameters Set 0 (8 32-bit words)
Parameters Set 1 (8 32-bit words)
Parameters Set 2 (8 32-bit words)
Parameters Set 3 (8 32-bit words)
Parameters Set 4 (8 32-bit words)
Parameters Set 5 (8 32-bit words)
...
0x01C0 4FC0 - 0x01C0 4FDF
0x01C0 4FE0 - 0x01C0 4FFF
Parameters Set 126 (8 32-bit words)
Parameters Set 127 (8 32-bit words)
Table 5-18. Parameter Set Entries
BYTE OFFSET ADDRESS
WITHIN THE PARAMETER SET
ACRONYM
PARAMETER ENTRY
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
OPT
SRC
Option
Source Address
A_B_CNT
DST
A Count, B Count
Destination Address
SRC_DST_BIDX
LINK_BCNTRLD
SRC_DST_CIDX
CCNT
Source B Index, Destination B Index
Link Address, B Count Reload
Source C Index, Destination C Index
C Count
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Table 5-19. EDMA Events
Event
Event Name / Source
Event
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Event Name / Source
MMCSD Receive
MMCSD Transmit
SPI1 Receive
0
1
McASP0 Receive
McASP0 Transmit
McASP1 Receive
McASP1 Transmit
McASP2 Receive
McASP2 Transmit
GPIO Bank 0 Interrupt
GPIO Bank 1 Interrupt
UART0 Receive
2
3
SPI1 Transmit
4
PRU_EVENTOUT6
PRU_EVENTOUT7
GPIO Bank 2 Interrupt
GPIO Bank 3 Interrupt
I2C0 Receive
5
6
7
8
9
UART0 Transmit
I2C0 Transmit
10
11
12
13
14
15
Timer64P0 Event Out 12
Timer64P0 Event Out 34
UART1 Receive
I2C1 Receive
I2C1 Transmit
GPIO Bank 4 Interrupt
GPIO Bank 5 Interrupt
UART2 Receive
UART1 Transmit
SPI0 Receive
SPI0 Transmit
UART2 Transmit
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5.11 External Memory Interface A (EMIFA)
EMIFA is one of two external memory interfaces supported on the OMAP-L137. It is primarily intended to
support asynchronous memory types, such as NAND and NOR flash and Asynchronous SRAM. However
on OMAP-L137 EMIFA also provides a secondary interface to SDRAM.
5.11.1 EMIFA Asynchronous Memory Support
EMIFA supports asynchronous:
•
•
•
SRAM memories
NAND Flash memories
NOR Flash memories
The EMIFA data bus width is up to 16-bits on the ZKB package. The device supports up to fifteen address
lines and an external wait/interrupt input. Up to four asynchronous chip selects are supported by EMIFA
(EMA_CS[5:2]) . All four chip selects are available on the ZKB package.
Each chip select has the following individually programmable attributes:
•
•
•
•
•
•
•
Data Bus Width
Read cycle timings: setup, hold, strobe
Write cycle timings: setup, hold, strobe
Bus turn around time
Extended Wait Option With Programmable Timeout
Select Strobe Option
NAND flash controller supports 1-bit and 4-bit ECC calculation on blocks of 512 bytes.
5.11.2 EMIFA Synchronous DRAM Memory Support
The OMAP-L137 ZKB package supports 16-bit SDRAM in addition to the asynchronous memories listed in
Section 5.11.1. It has a single SDRAM chip select (EMA_CS[0]). SDRAM configurations that are
supported are:
•
•
•
•
•
One, Two, and Four Bank SDRAM devices
Devices with Eight, Nine, Ten, and Eleven Column Address
CAS Latency of two or three clock cycles
Sixteen Bit Data Bus Width
3.3V LVCMOS Interface
Additionally, the SDRAM interface of EMIFA supports placing the SDRAM in Self Refresh and Powerdown
Modes. Self Refresh mode allows the SDRAM to be put into a low power state while still retaining memory
contents; since the SDRAM will continue to refresh itself even without clocks from the DSP. Powerdown
mode achieves even lower power, except the DSP must periodically wake the SDRAM up and issue
refreshes if data retention is required.
Finally, note that the EMIFA does not support Mobile SDRAM devices. Table 5-20 below shows the
supported SDRAM configurations for EMIFA.
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Table 5-20. EMIFA Supported SDRAM Configurations(1)
SDRAM
Memory
Data Bus
Width
Memory
Density
(Mbits)
Number of EMIFB Data
Total Memory
(Mbits)
Total Memory
(Mbytes)
Rows
Columns
Banks
Memories
Bus Size
(bits)
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
8
8
1
2
4
1
2
4
1
2
4
1
2
4
1
2
4
1
2
4
1
2
4
1
2
4
32
64
4
8
32
64
8
128
64
16
8
128
64
9
9
128
256
128
256
512
256
512
1024
32
16
32
16
32
64
32
64
128
4
128
256
128
256
512
256
512
1024
16
9
16
10
10
10
11
11
11
8
8
64
8
32
8
128
64
16
8
64
9
32
9
128
256
128
256
512
256
512
1024
16
32
16
32
64
32
64
128
64
9
128
64
8
10
10
10
11
11
11
128
256
128
256
512
(1) The shaded cells indicate configurations that are possible on the EMIFA interface but as of this writing SDRAM memories capable of
supporting these densities are not available in the market.
5.11.3 EMIFA SDRAM Loading Limitations
EMIFA supports SDRAM up to 100 MHz with up to two SDRAM or asynchronous memory loads.
Additional loads will limit the SDRAM operation to lower speeds and the maximum speed should be
confirmed by board simulation using IBIS models.
5.11.4 EMIFA Connection Examples
Figure 5-12 illustrates an example of how SDRAM, NOR, and NAND flash devices might be connected to
EMIFA of a OMAP-L137 device simultaneously. The SDRAM chip select must be EMA_CS[0]. Note that
the NOR flash is connected to EMA_CS[2] and the NAND flash is connected to EMA_CS[3] in this
example. Note that any type of asynchronous memory may be connected to EMA_CS[5:2].
The on-chip bootloader makes some assumptions on which chip select the contains the boot image, and
this depends on the boot mode. For NOR boot mode; the on-chip bootloader requires that the image be
stored in NOR flash on EMA_CS[2]. For NAND boot mode, the bootloader requires that the boot image is
stored in NAND flash on EMA_CS[3]. It is always possible to have the image span multiple chip selects,
but this must be supported by second stage boot code stored in the external flash.
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A likely use case with more than one EMIFA chip select used for NAND flash is illustrated in Figure 5-13.
This figure shows how two multiplane NAND flash devices with two chip selects each would connect to the
EMIFA. In this case if NAND is the boot memory, then the boot image needs to be stored in the NAND
area selected by EMA_CS[3]. Part of the application image could spill over into the NAND regions
selected by other EMIFA chip selects; but would rely on the code stored in the EMA_CS[3] area to
bootload it.
EMA_CS[0]
EMA_CAS
CE
CAS
EMIFA
EMA_RAS
RAS
EMA_WE
WE
SDRAM
2M x 16 x 4
Bank
EMA_CLK
CLK
EMA_SDCKE
EMA_BA[1:0]
EMA_A[12:0]
CKE
BA[1:0]
A[11:0]
LDQM
UDQM
DQ[15:0]
EMA_WE_DQM[0]
EMA_WE_DQM[1]
EMA_D[15:0]
EMA_CS[2]
EMA_CS[3]
EMA_WAIT
EMA_OE
A[0]
A[12:1]
DQ[15:0]
CE
GPIO
(6 Pins)
RESET
NOR
FLASH
512K x 16
WE
RESET
OE
RESET
A[18:13]
...
RY/BY
EMA_A[1]
EMA_A[2]
ALE
CLE
DQ[15:0]
CE
NAND
FLASH
1Gb x 16
DVDD
WE
RE
RB
Figure 5-12. OMAP-L137 Connection Diagram: SDRAM, NOR, NAND
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EMA_A[1]
EMA_A[2]
EMA_D[7:0]
EMA_CS[2]
EMA_CS[3]
EMA_WE
ALE
CLE
DQ[7:0]
NAND
FLASH
x8,
MultiPlane
CE1
CE2
WE
EMA_OE
RE
EMIFA
R/B1
R/B2
EMA_WAIT
DVDD
ALE
CLE
DQ[7:0]
NAND
FLASH
x8,
MultiPlane
EMA_CS[4]
EMA_CS[5]
CE1
CE2
WE
RE
R/B1
R/B2
Figure 5-13. OMAP-L137 EMIFA Connection Diagram: Multiple NAND Flash Planes
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5.11.5 External Memory Interface A (EMIFA) Registers
Table 5-21 is a list of the EMIF registers. For more information about these registers, see the C674x DSP
External Memory Interface (EMIF) User's Guide (literature number SPRUFL6).
Table 5-21. External Memory Interface (EMIFA) Registers
BYTE ADDRESS
0x6800 0000
0x6800 0004
0x6800 0008
0x6800 000C
0x6800 0010
0x6800 0014
0x6800 0018
0x6800 001C
0x6800 0020
0x6800 003C
0x6800 0040
0x6800 0044
0x6800 0048
0x6800 004C
0x6800 0060
0x6800 0064
0x6800 0070
0x6800 0074
0x6800 0078
0x6800 007C
0x6800 00BC
0x6800 00C0
0x6800 00C4
0x6800 00C8
0x6800 00CC
0x6800 00D0
0x6800 00D4
0x6800 00D8
0x6800 00DC
ACRONYM
MIDR
REGISTER DESCRIPTION
Module ID Register
AWCC
Asynchronous Wait Cycle Configuration Register
SDRAM Configuration Register
SDCR
SDRCR
SDRAM Refresh Control Register
Asynchronous 1 Configuration Register
Asynchronous 2 Configuration Register
Asynchronous 3 Configuration Register
Asynchronous 4 Configuration Register
SDRAM Timing Register
CE2CFG
CE3CFG
CE4CFG
CE5CFG
SDTIMR
SDSRETR
INTRAW
SDRAM Self Refresh Exit Timing Register
EMIFA Interrupt Raw Register
INTMSK
EMIFA Interrupt Mask Register
INTMSKSET
INTMSKCLR
NANDFCR
NANDFSR
NANDF1ECC
NANDF2ECC
NANDF3ECC
NANDF4ECC
EMIFA Interrupt Mask Set Register
EMIFA Interrupt Mask Clear Register
NAND Flash Control Register
NAND Flash Status Register
NAND Flash 1 ECC Register (CS2 Space)
NAND Flash 2 ECC Register (CS3 Space)
NAND Flash 3 ECC Register (CS4 Space)
NAND Flash 4 ECC Register (CS5 Space)
NAND4BITECCLOAD NAND Flash 4-Bit ECC Load Register
NAND4BITECC1
NAND4BITECC2
NAND4BITECC3
NAND4BITECC4
NANDERRADD1
NANDERRADD2
NANDERRVAL1
NANDERRVAL2
NAND Flash 4-Bit ECC Register 1
NAND Flash 4-Bit ECC Register 2
NAND Flash 4-Bit ECC Register 3
NAND Flash 4-Bit ECC Register 4
NAND Flash 4-Bit ECC Error Address Register 1
NAND Flash 4-Bit ECC Error Address Register 2
NAND Flash 4-Bit ECC Error Value Register 1
NAND Flash 4-Bit ECC Error Value Register 2
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5.11.6 EMIFA Electrical Data/Timing
Table 5-22 through Table 5-25 assume testing over recommended operating conditions.
Table 5-22. EMIFA SDRAM Interface Timing Requirements
No.
19
PARAMETER
MIN MAX UNIT
tsu(DV-CLKH)
th(CLKH-DIV)
Input setup time, read data valid on EMA_D[15:0] before EMA_CLK rising
Input hold time, read data valid on EMA_D[15:0] after EMA_CLK rising
1.3
1.5
ns
ns
20
Table 5-23. EMIFA SDRAM Interface Switching Characteristics
No.
1
PARAMETER
MIN MAX UNIT
tc(CLK)
Cycle time, EMIF clock EMA_CLK
10
3
ns
ns
ns
ns
ns
ns
ns
2
tw(CLK)
Pulse width, EMIF clock EMA_CLK high or low
Delay time, EMA_CLK rising to EMA_CS[0] valid
Output hold time, EMA_CLK rising to EMA_CS[0] invalid
Delay time, EMA_CLK rising to EMA_WE_DQM[1:0] valid
Output hold time, EMA_CLK rising to EMA_WE_DQM[1:0] invalid
Delay time, EMA_CLK rising to EMA_A[12:0] and EMA_BA[1:0] valid
3
td(CLKH-CSV)
toh(CLKH-CSIV)
td(CLKH-DQMV)
toh(CLKH-DQMIV)
td(CLKH-AV)
7
7
7
4
1
1
5
6
7
Output hold time, EMA_CLK rising to EMA_A[12:0] and EMA_BA[1:0]
invalid
8
toh(CLKH-AIV)
1
ns
9
td(CLKH-DV)
Delay time, EMA_CLK rising to EMA_D[15:0] valid
Output hold time, EMA_CLK rising to EMA_D[15:0] invalid
Delay time, EMA_CLK rising to EMA_RAS valid
7
7
7
7
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
11
12
13
14
15
16
17
18
toh(CLKH-DIV)
td(CLKH-RASV)
toh(CLKH-RASIV)
td(CLKH-CASV)
toh(CLKH-CASIV)
td(CLKH-WEV)
toh(CLKH-WEIV)
tdis(CLKH-DHZ)
tena(CLKH-DLZ)
1
1
1
1
1
Output hold time, EMA_CLK rising to EMA_RAS invalid
Delay time, EMA_CLK rising to EMA_CAS valid
Output hold time, EMA_CLK rising to EMA_CAS invalid
Delay time, EMA_CLK rising to EMA_WE valid
Output hold time, EMA_CLK rising to EMA_WE invalid
Delay time, EMA_CLK rising to EMA_D[15:0] 3-stated
Output hold time, EMA_CLK rising to EMA_D[15:0] driving
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1
BASIC SDRAM
WRITE OPERATION
2
2
EMA_CLK
EMA_CS[0]
3
5
7
7
9
4
6
EMA_WE_DQM[1:0]
EMA_BA[1:0]
8
8
EMA_A[12:0]
10
EMA_D[15:0]
EMA_RAS
EMA_CAS
EMA_WE
11
12
13
15
16
Figure 5-14. EMIFA Basic SDRAM Write Operation
1
BASIC SDRAM
READ OPERATION
2
2
EMA_CLK
EMA_CS[0]
3
5
7
7
4
6
EMA_WE_DQM[1:0]
EMA_BA[1:0]
8
8
EMA_A[12:0]
19
20
2 EM_CLK Delay
17
18
EMA_D[15:0]
EMA_RAS
11
12
13
14
EMA_CAS
EMA_WE
Figure 5-15. EMIFA Basic SDRAM Read Operation
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Table 5-24. EMIFA Asynchronous Memory Timing Requirements(1)
PARAMETER
READS and WRITES
MIN
NOM
MAX
UNIT
E
2
tc(CLK)
Cycle time, EMIFA module clock
10
2E
ns
ns
tw(EM_WAIT)
Pulse duration, EM_WAIT assertion and deassertion
READS
12
13
14
tsu(EMDV-EMOEH)
th(EMOEH-EMDIV)
tsu (EMOEL-EMWAIT)
Setup time, EM_D[15:0] valid before EM_OE high
Hold time, EM_D[15:0] valid after EM_OE high
Setup Time, EM_WAIT asserted before end of Strobe Phase(2)
WRITES
3
0
ns
ns
ns
4E+3
28
tsu (EMWEL-EMWAIT)
Setup Time, EM_WAIT asserted before end of Strobe Phase(2)
4E+3
ns
(1) E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL output clock divided by 4.5. As an example, when
SYSCLK3 is selected and set to 100MHz, E=10ns.
(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended
wait states. Figure 5-18 and Figure 5-19 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
Table 5-25. EMIFA Asynchronous Memory Switching Characteristics(1) (2) (3)
No.
PARAMETER
MIN
NOM
MAX
UNIT
READS and WRITES
1
td(TURNAROUND)
Turn around time
(TA)*E - 3
(TA)*E
(TA)*E + 3
ns
READS
(RS+RST+RH)*E
- 3
(RS+RST+RH)*E
+ 3
EMIF read cycle time (EW = 0)
EMIF read cycle time (EW = 1)
(RS+RST+RH)*E
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
4
5
tc(EMRCYCLE)
(RS+RST+RH+(E (RS+RST+RH+(EW (RS+RST+RH+(E
WC*16))*E - 3
C*16))*E
WC*16))*E + 3
Output setup time, EMA_CE[5:2] low to
EMA_OE low (SS = 0)
(RS)*E-3
(RS)*E
(RS)*E+3
tsu(EMCEL-EMOEL)
Output setup time, EMA_CE[5:2] low to
EMA_OE low (SS = 1)
-3
(RH)*E - 3
-3
0
(RH)*E
0
+3
(RH)*E + 3
+3
Output hold time, EMA_OE high to
EMA_CE[5:2] high (SS = 0)
th(EMOEH-EMCEH)
Output hold time, EMA_OE high to
EMA_CE[5:2] high (SS = 1)
Output setup time, EMA_BA[1:0] valid to
EMA_OE low
6
7
8
9
tsu(EMBAV-EMOEL)
th(EMOEH-EMBAIV)
tsu(EMBAV-EMOEL)
th(EMOEH-EMAIV)
(RS)*E-3
(RH)*E-3
(RS)*E-3
(RS)*E
(RH)*E
(RS)*E
(RS)*E+3
(RH)*E+3
(RS)*E+3
Output hold time, EMA_OE high to
EMA_BA[1:0] invalid
Output setup time, EMA_A[13:0] valid to
EMA_OE low
Output hold time, EMA_OE high to
EMA_A[13:0] invalid
(RH)*E-3
(RH)*E
(RST)*E
(RH)*E+3
ns
ns
ns
EMA_OE active low width (EW = 0)
(RST)*E-3
(RST)*E+3
10 tw(EMOEL)
(RST+(EWC*16))
*E-3
(RST+(EWC*16))
*E+3
EMA_OE active low width (EW = 1)
(RST+(EWC*16))*E
td(EMWAITH-
EMOEH)
Delay time from EMA_WAIT deasserted to
EMA_OE high
11
3E-3
4E
4E+3
ns
WRITES
(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,
MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle
Configuration Registers. These support the following range of values: TA[4-1], RS[16-1], RST[64-1], RH[8-1], WS[16-1], WST[64-1],
WH[8-1], and MEW[1-256].
(2) E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL output clock divided by 4.5. As an example, when
SYSCLK3 is selected and set to 100MHz, E=10ns.
(3) EWC = external wait cycles determined by EMA_WAIT input signal. EWC supports the following range of values EWC[256-1]. Note that
the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register.
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UNIT
Table 5-25. EMIFA Asynchronous Memory Switching Characteristics(1) (2) (3) (continued)
No.
PARAMETER
MIN
NOM
MAX
(WS+WST+WH)*
E-3
(WS+WST+WH)*
E+3
EMIF write cycle time (EW = 0)
(WS+WST+WH)*E
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15 tc(EMWCYCLE)
(WS+WST+WH+( (WS+WST+WH+(E (WS+WST+WH+(
EWC*16))*E - 3
EMIF write cycle time (EW = 1)
WC*16))*E
EWC*16))*E + 3
Output setup time, EMA_CE[5:2] low to
EMA_WE low (SS = 0)
(WS)*E - 3
(WS)*E
(WS)*E + 3
16 tsu(EMCEL-EMWEL)
Output setup time, EMA_CE[5:2] low to
EMA_WE low (SS = 1)
-3
(WH)*E-3
-3
0
(WH)*E
0
+3
(WH)*E+3
+3
Output hold time, EMA_WE high to
EMA_CE[5:2] high (SS = 0)
17 th(EMWEH-EMCEH)
Output hold time, EMA_WE high to
EMA_CE[5:2] high (SS = 1)
tsu(EMDQMV-
EMWEL)
Output setup time, EMA_BA[1:0] valid to
EMA_WE low
18
19
(WS)*E-3
(WH)*E-3
(WS)*E-3
(WH)*E-3
(WS)*E-3
(WS)*E
(WH)*E
(WS)*E
(WH)*E
(WS)*E
(WS)*E+3
(WH)*E+3
(WS)*E+3
(WH)*E+3
(WS)*E+3
th(EMWEH-
EMDQMIV)
Output hold time, EMA_WE high to
EMA_BA[1:0] invalid
Output setup time, EMA_BA[1:0] valid to
EMA_WE low
20 tsu(EMBAV-EMWEL)
Output hold time, EMA_WE high to
EMA_BA[1:0] invalid
21 th(EMWEH-EMBAIV)
22 tsu(EMAV-EMWEL)
23 th(EMWEH-EMAIV)
Output setup time, EMA_A[13:0] valid to
EMA_WE low
Output hold time, EMA_WE high to
EMA_A[13:0] invalid
(WH)*E-3
(WH)*E
(WST)*E
(WH)*E+3
ns
ns
ns
EMA_WE active low width (EW = 0)
(WST)*E-3
(WST)*E+3
24 tw(EMWEL)
(WST+(EWC*16))
*E-3
(WST+(EWC*16))
*E+3
EMA_WE active low width (EW = 1)
(WST+(EWC*16))*E
td(EMWAITH-
EMWEH)
Delay time from EMA_WAIT deasserted to
EMA_WE high
25
3E-3
(WS)*E-3
(WH)*E-3
4E
(WS)*E
(WH)*E
4E+3
(WS)*E+3
(WH)*E+3
ns
ns
ns
Output setup time, EMA_D[15:0] valid to
EMA_WE low
26 tsu(EMDV-EMWEL)
Output hold time, EMA_WE high to
EMA_D[15:0] invalid
27 th(EMWEH-EMDIV)
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3
1
EMA_CS[5:2]
EMA_BA[1:0]
EMA_A[12:0]
EMA_WE_DQM[1:0]
4
8
5
9
7
6
10
EMA_OE
13
12
EMA_D[15:0]
EMA_WE
Figure 5-16. Asynchronous Memory Read Timing for EMIFA
15
1
EMA_CS[5:2]
EMA_BA[1:0]
EMA_A[12:0]
EMA_WE_DQM[1:0]
16
18
20
22
17
19
21
23
24
EMA_WE
26
27
EMA_D[15:0]
EMA_OE
Figure 5-17. Asynchronous Memory Write Timing for EMIFA
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SETUP
STROBE
Extended Due to EMA_WAIT
STROBE HOLD
EMA_CS[5:2]
EMA_BA[1:0]
EMA_A[12:0]
EMA_D[15:0]
14
11
EMA_OE
2
2
EMA_WAIT
Asserted
Deasserted
Figure 5-18. EMA_WAIT Read Timing Requirements
Figure 5-19. EMA_WAIT Write Timing Requirements
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5.12 External Memory Interface B (EMIFB)
Figure 5-20 illustrates a high-level view of the EMIFB and its connections within the device. Multiple
requesters have access to EMIFB through a switched central resource (indicated as crossbar in the
figure). The EMIFB implements a split transaction internal bus, allowing concurrence between reads and
writes from the various requesters.
EMIFB
Registers
CPU
EMB_CS
EMB_CAS
EDMA
Cmd/Write
FIFO
EMB_RAS
EMB_WE
Crossbar
MPU2
Master
Peripherals
(USB, UHPI...)
EMB_CLK
SDRAM
Interface
EMB_SDCKE
EMB_BA[1:0]
EMB_A[x:0]
Read
FIFO
EMB_D[x:0]
EMB_WE_DQM[x:0]
Figure 5-20. EMIFB Functional Block Diagram
EMIFB supports a 3.3V LVCMOS Interface.
5.12.1 EMIFB SDRAM Loading Limitations
EMIFB supports SDRAM up to 152MHz with up to two SDRAM or asynchronous memory loads. Additional
loads will limit the SDRAM operation to lower speeds and the maximum speed should be confirmed by
board simulation using IBIS models.
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5.12.2 Interfacing to SDRAM
The EMIFB supports a glueless interface to SDRAM devices with the following characteristics:
•
•
•
•
Pre-charge bit is A[10]
Supports 8, 9, 10 or 11 column address bits
Supports up to 13 row address bits
Supports 1, 2 or 4 internal banks
Table 5-26 shows the supported SDRAM configurations for EMIFB.
Table 5-26. EMIFB Supported SDRAM Configurations(1)
SDRAM
Memory
Data Bus
Width
Memory
Density
(Mbits)
Number of EMIFB Data
Total Memory
(Mbits)
Total Memory
(Mbytes)
Rows
Columns
Banks
Memories
Bus Size
(bits)
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
8
8
1
2
4
1
2
4
1
2
4
1
2
4
1
2
4
1
2
4
1
2
4
1
2
4
64
128
256
128
256
512
256
512
1024
512
1024
2048
64
8
16
64
128
256
128
256
512
256
512
1024
512
1024
2048
32
8
32
9
16
9
32
9
64
32
10
10
10
11
11
11
8
32
64
128
64
128
256
8
8
128
256
128
256
512
256
512
1024
512
1024
2048
16
64
8
32
128
64
9
16
9
32
128
256
128
256
512
256
512
1024
9
64
16
10
10
10
11
11
11
32
64
128
64
128
256
(1) The shaded cells indicate configurations that are possible on the EMIFB interface but as of this writing SDRAM memories capable of
supporting these densities are not available in the market.
Figure 5-21 shows an interface between the EMIFB and a 2M × 16 × 4 bank SDRAM device. In addition,
Figure 5-22 shows an interface between the EMIFB and a 2M × 32 × 4 bank SDRAM device and Figure 5-
23 shows an interface between the EMIFB and two 4M × 16 × 4 bank SDRAM devices. Refer to Table 5-
27, as an example that shows additional list of commonly-supported SDRAM devices and the required
connections for the address pins. Note that in Table 5-27, page size/column size (not indicated in the
table) is varied to get the required addressability range.
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SDRAM
2M x 16 x 4
Bank
EMIFB
EMB_CS
CE
EMB_CAS
EMB_RAS
CAS
RAS
EMB_WE
WE
EMB_CLK
CLK
EMB_SDCKE
EMB_BA[1:0]
EMB_A[11:0]
EMB_WE_DQM[0]
EMB_WE_DQM[1]
EMB_D[15:0]
CKE
BA[1:0]
A[11:0]
LDQM
UDQM
DQ[15:0]
Figure 5-21. EMIFB to 2M × 16 × 4 bank SDRAM Interface
SDRAM
2M x 32 x 4
Bank
EMIFB
EMB_CS
CE
EMB_CAS
EMB_RAS
CAS
RAS
WE
EMB_WE
EMB_CLK
CLK
CKE
EMB_SDCKE
EMB_BA[1:0]
EMB_A[11:0]
EMB_WE_DQM[3:0]
EMB_D[31:0]
BA[1:0]
A[11:0]
DQM[3:0]
DQ[31:0]
Figure 5-22. EMIFB to 2M × 32 × 4 bank SDRAM Interface
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SDRAM
4M x 16 x 4
Bank
EMIFB
EMB_CS
EMB_CAS
CE
CAS
RAS
WE
EMB_RAS
EMB_WE
EMB_CLK
CLK
CKE
EMB_SDCKE
EMB_BA[1:0]
EMB_A[12:0]
EMB_WE_DQM[0]
EMB_WE_DQM[1]
EMB_D[15:0]
EMB_WE_DQM[2]
EMB_WE_DQM[3]
EMB_D[31:16]
BA[1:0]
A[12:0]
LDQM
UDQM
DQ[15:0]
SDRAM
4M x 16 x 4
Bank
CE
CAS
RAS
WE
CLK
CKE
BA[1:0]
A[12:0]
LDQM
UDQM
DQ[15:0]
Figure 5-23. EMIFB to Dual 4M × 16 × 4 bank SDRAM Interface
Table 5-27. Example of 16/32-bit EMIFB Address Pin Connections
SDRAM SIZE
WIDTH
BANKS
MEMORY
SDRAM
EMIFB
ADDRESS PINS
64M bits
×16
4
A[11:0]
EMB_A[11:0]
A[10:0]
×32
×16
×32
×16
×32
×16
×32
4
4
4
4
4
4
4
SDRAM
EMIFB
EMB_A[10:0]
A[11:0]
128M bits
256M bits
512M bits
SDRAM
EMIFB
EMB_A[11:0]
A[11:0]
SDRAM
EMIFB
EMB_A[11:0]
A[12:0]
SDRAM
EMIFB
EMB_A[12:0]
A[11:0]
SDRAM
EMIFB
EMB_A[11:0]
A[12:0]
SDRAM
EMIFB
EMB_A[12:0]
A[12:0]
SDRAM
EMIFB
EMB_A[12:0]
Table 5-28 is a list of the EMIFB registers.
Table 5-28. EMIFB Base Controller Registers
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0xB000 0000
MIDR
Module ID Register
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Table 5-28. EMIFB Base Controller Registers (continued)
BYTE ADDRESS
ACRONYM
SDCFG
SDRFC
SDTIM1
SDTIM2
SDCFG2
BPRIO
PC1
REGISTER DESCRIPTION
0xB000 0008
0xB000 000C
0xB000 0010
0xB000 0014
0xB000 001C
0xB000 0020
0xB000 0040
0xB000 0044
0xB000 0048
0xB000 004C
0xB000 0050
0xB000 00C0
0xB000 00C4
0xB000 00C8
0xB000 00CC
SDRAM Configuration Register
SDRAM Refresh Control Register
SDRAM Timing Register 1
SDRAM Timing Register 2
SDRAM Configuration 2 Register
Peripheral Bus Burst Priority Register
Performance Counter 1 Register
Performance Counter 2 Register
Performance Counter Configuration Register
Performance Counter Master Region Select Register
Performance Counter Time Register
Interrupt Raw Register
PC2
PCC
PCMRS
PCT
IRR
IMR
Interrupt Mask Register
IMSR
Interrupt Mask Set Register
IMCR
Interrupt Mask Clear Register
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5.12.3 EMIFB Electrical Data/Timing
Table 5-29. EMIFB SDRAM Interface Timing Requirements
No.
19
PARAMETER
MIN
MAX
MAX
UNIT
ns
Input setup time, read data valid on EMB_D[31:0] before EMB_CLK
rising
tsu(DV-CLKH)
th(CLKH-DIV)
0.8
20
Input hold time, read data valid on EMB_D[31:0] after EMB_CLK rising
1.5
ns
Table 5-30. EMIFB SDRAM Interface Switching Characteristics
No.
1
PARAMETER
MIN
6.579
2.63
UNIT
ns
tc(CLK)
Cycle time, EMIF clock EMB_CLK
2
tw(CLK)
Pulse width, EMIF clock EMB_CLK high or low
ns
3
td(CLKH-CSV)
toh(CLKH-CSIV)
td(CLKH-DQMV)
toh(CLKH-DQMIV)
td(CLKH-AV)
Delay time, EMB_CLK rising to EMB_CS[0] valid
Output hold time, EMB_CLK rising to EMB_CS[0] invalid
Delay time, EMB_CLK rising to EMB_WE_DQM[3:0] valid
Output hold time, EMB_CLK rising to EMB_WE_DQM[3:0] invalid
Delay time, EMB_CLK rising to EMB_A[12:0] and EMB_BA[1:0] valid
5.1
5.1
5.1
ns
4
0.9
0.9
ns
5
ns
6
ns
7
ns
Output hold time, EMB_CLK rising to EMB_A[12:0] and EMB_BA[1:0]
invalid
8
toh(CLKH-AIV)
0.9
ns
9
td(CLKH-DV)
Delay time, EMB_CLK rising to EMB_D[31:0] valid
Output hold time, EMB_CLK rising to EMB_D[31:0] invalid
Delay time, EMB_CLK rising to EMB_RAS valid
5.1
5.1
5.1
5.1
5.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
11
12
13
14
15
16
17
18
toh(CLKH-DIV)
td(CLKH-RASV)
toh(CLKH-RASIV)
td(CLKH-CASV)
toh(CLKH-CASIV)
td(CLKH-WEV)
toh(CLKH-WEIV)
tdis(CLKH-DHZ)
tena(CLKH-DLZ)
0.9
0.9
0.9
0.9
0.9
Output hold time, EMB_CLK rising to EMB_RAS invalid
Delay time, EMB_CLK rising to EMB_CAS valid
Output hold time, EMB_CLK rising to EMB_CAS invalid
Delay time, EMB_CLK rising to EMB_WE valid
Output hold time, EMB_CLK rising to EMB_WE invalid
Delay time, EMB_CLK rising to EMB_D[31:0] 3-stated
Output hold time, EMB_CLK rising to EMB_D[31:0] driving
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1
BASIC SDRAM
WRITE OPERATION
2
2
EMB_CLK
3
5
7
7
9
4
EMB_CS[0]
6
EMB_WE_DQM[3:0]
EMB_BA[1:0]
8
8
EMB_A[12:0]
10
EMB_D[31:0]
EMB_RAS
EMB_CAS
EMB_WE
11
12
13
15
16
Figure 5-24. EMIFB Basic SDRAM Write Operation
1
BASIC SDRAM
READ OPERATION
2
2
EMB_CLK
EMB_CS[0]
3
5
7
7
4
6
EMB_WE_DQM[3:0]
EMB_BA[1:0]
8
8
EMB_A[12:0]
19
20
2 EM_CLK Delay
17
18
EMB_D[31:0]
EMB_RAS
11
12
13
14
EMB_CAS
EMB_WE
Figure 5-25. EMIFB Basic SDRAM Read Operation
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5.13 Memory Protection Units
The MPU performs memory protection checking. It receives requests from a bus master in the system and
checks the address against the fixed and programmable regions to see if the access is allowed. If allowed,
the transfer is passed unmodified to its output bus (to the targeted address). If the transfer is illegal (fails
the protection check) then the MPU does not pass the transfer to the output bus but rather services the
transfer internally back to the input bus (to prevent a hang) returning the fault status to the requestor as
well as generating an interrupt about the fault. The following features are supported by the MPU:
•
•
•
•
•
•
•
Provides memory protection for fixed and programmable address ranges
Supports multiple programmable address region
Supports secure and debug access privileges
Supports read, write, and execute access privileges
Supports privid(8) associations with ranges
Generates an interrupt when there is a protection violation, and saves violating transfer parameters
MMR access is also protected
Table 5-31. MPU1 Configuration Registers
MPU1
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01E1 4000
REVID
CONFIG
Revision ID
0x01E1 4004
Configuration
0x01E1 4010
IRAWSTAT
IENSTAT
Interrupt raw status/set
0x01E1 4014
Interrupt enable status/clear
0x01E1 4018
IENSET
Interrupt enable
0x01E1 401C
IENCLR
Interrupt enable clear
0x01E1 4020 - 0x01E1 41FF
0x01E1 4200
-
Reserved
PROG1_MPSAR
PROG1_MPEAR
PROG1_MPPA
-
Programmable range 1, start address
Programmable range 1, end address
Programmable range 1, memory page protection attributes
Reserved
0x01E1 4204
0x01E1 4208
0x01E1 420C - 0x01E1 420F
0x01E1 4210
PROG2_MPSAR
PROG2_MPEAR
PROG2_MPPA
-
Programmable range 2, start address
Programmable range 2, end address
Programmable range 2, memory page protection attributes
Reserved
0x01E1 4214
0x01E1 4218
0x01E1 421C - 0x01E1 421F
0x01E1 4220
PROG3_MPSAR
PROG3_MPEAR
PROG3_MPPA
-
Programmable range 3, start address
Programmable range 3, end address
Programmable range 3, memory page protection attributes
Reserved
0x01E1 4224
0x01E1 4228
0x01E1 422C - 0x01E1 422F
0x01E1 4230
PROG4_MPSAR
PROG4_MPEAR
PROG4_MPPA
-
Programmable range 4, start address
Programmable range 4, end address
Programmable range 4, memory page protection attributes
Reserved
0x01E1 4234
0x01E1 4238
0x01E1 423C - 0x01E1 423F
0x01E1 4240
PROG5_MPSAR
PROG5_MPEAR
PROG5_MPPA
-
Programmable range 5, start address
Programmable range 5, end address
Programmable range 5, memory page protection attributes
Reserved
0x01E1 4244
0x01E1 4248
0x01E1 424C - 0x01E1 424F
0x01E1 4250
PROG6_MPSAR
PROG6_MPEAR
PROG6_MPPA
-
Programmable range 6, start address
Programmable range 6, end address
Programmable range 6, memory page protection attributes
Reserved
0x01E1 4254
0x01E1 4258
0x01E1 425C - 0x01E1 42FF
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Table 5-31. MPU1 Configuration Registers (continued)
MPU1
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01E14300
FLTADDRR
FLTSTAT
FLTCLR
-
Fault address
Fault status
Fault clear
Reserved
0x01E1 4304
0x01E1 4308
0x01E1 430C - 0x01E1 4FFF
Table 5-32. MPU2 Configuration Registers
MPU2
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01E1 5000
0x01E1 5004
REVID
CONFIG
Revision ID
Configuration
0x01E1 5010
IRAWSTAT
IENSTAT
Interrupt raw status/set
0x01E1 5014
Interrupt enable status/clear
0x01E1 5018
IENSET
Interrupt enable
0x01E1 501C
IENCLR
Interrupt enable clear
0x01E1 5020 - 0x01E1 50FF
0x01E1 5100
-
Reserved
FXD_MPSAR
FXD_MPEAR
FXD_MPPA
-
Fixed range start address
0x01E1 5104
Fixed range end start address
Fixed range memory page protection attributes
Reserved
0x01E1 5108
0x01E1 510C - 0x01E1 51FF
0x01E1 5200
PROG1_MPSAR
PROG1_MPEAR
PROG1_MPPA
-
Programmable range 1, start address
Programmable range 1, end address
Programmable range 1, memory page protection attributes
Reserved
0x01E1 5204
0x01E1 5208
0x01E1 520C - 0x01E1 520F
0x01E1 5210
PROG2_MPSAR
PROG2_MPEAR
PROG2_MPPA
-
Programmable range 2, start address
Programmable range 2, end address
Programmable range 2, memory page protection attributes
Reserved
0x01E1 5214
0x01E1 5218
0x01E1 521C - 0x01E1 521F
0x01E1 5220
PROG3_MPSAR
PROG3_MPEAR
PROG3_MPPA
-
Programmable range 3, start address
Programmable range 3, end address
Programmable range 3, memory page protection attributes
Reserved
0x01E1 5224
0x01E1 5228
0x01E1 522C - 0x01E1 522F
0x01E1 5230
PROG4_MPSAR
PROG4_MPEAR
PROG4_MPPA
-
Programmable range 4, start address
Programmable range 4, end address
Programmable range 4, memory page protection attributes
Reserved
0x01E1 5234
0x01E1 5238
0x01E1 523C - 0x01E1 523F
0x01E1 5240
PROG5_MPSAR
PROG5_MPEAR
PROG5_MPPA
-
Programmable range 5, start address
Programmable range 5, end address
Programmable range 5, memory page protection attributes
Reserved
0x01E1 5244
0x01E1 5248
0x01E1 524C - 0x01E1 524F
0x01E1 5250
PROG6_MPSAR
PROG6_MPEAR
PROG6_MPPA
-
Programmable range 6, start address
Programmable range 6, end address
Programmable range 6, memory page protection attributes
Reserved
0x01E1 5254
0x01E1 5258
0x01E1 525C - 0x01E1 525F
0x01E1 5260
PROG7_MPSAR
PROG7_MPEAR
PROG7_MPPA
-
Programmable range 7, start address
Programmable range 7, end address
Programmable range 7, memory page protection attributes
Reserved
0x01E1 5264
0x01E1 5268
0x01E1 526C - 0x01E1 526F
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Table 5-32. MPU2 Configuration Registers (continued)
MPU2
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01E1 5270
0x01E1 5274
PROG8_MPSAR
PROG8_MPEAR
PROG8_MPPA
-
Programmable range 8, start address
Programmable range 8, end address
Programmable range 8, memory page protection attributes
Reserved
0x01E1 5278
0x01E1 527C - 0x01E1 527F
0x01E1 5280
PROG9_MPSAR
PROG9_MPEAR
PROG9_MPPA
-
Programmable range 9, start address
Programmable range 9, end address
Programmable range 9, memory page protection attributes
Reserved
0x01E1 5284
0x01E1 5288
0x01E1 528C - 0x01E1 528F
0x01E1 5290
PROG10_MPSAR
PROG10_MPEAR
PROG10_MPPA
-
Programmable range 10, start address
Programmable range 10, end address
Programmable range 10, memory page protection attributes
Reserved
0x01E1 5294
0x01E1 5298
0x01E1 529C - 0x01E1 529F
0x01E1 52A0
PROG11_MPSAR
PROG11_MPEAR
PROG11_MPPA
-
Programmable range 11, start address
Programmable range 11, end address
Programmable range 11, memory page protection attributes
Reserved
0x01E1 52A4
0x01E1 52A8
0x01E1 52AC - 0x01E1 52AF
0x01E1 52B0
PROG12_MPSAR
PROG12_MPEAR
PROG12_MPPA
-
Programmable range 12, start address
Programmable range 12, end address
Programmable range 12, memory page protection attributes
Reserved
0x01E1 52B4
0x01E1 52B8
0x01E1 52BC - 0x01E1 52FF
0x01E1 5300
FLTADDRR
FLTSTAT
Fault address
0x01E1 5304
Fault status
0x01E1 5308
FLTCLR
Fault clear
0x01E1 530C - 0x01E1 5FFF
-
Reserved
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5.14 MMC / SD / SDIO (MMCSD)
5.14.1 MMCSD Peripheral Description
The OMAP-L137 includes an MMCSD controller which is compliant with MMC V4.0, Secure Digital Part 1
Physical Layer Specification V1.1 and Secure Digital Input Output (SDIO) V2.0 specifications.
The MMC/SD Controller has following features:
•
•
•
•
•
•
•
•
MultiMediaCard (MMC) support
Secure Digital (SD) Memory Card support
MMC/SD protocol support
SD high capacity support
SDIO protocol support
Programmable clock frequency
512 bit Read/Write FIFO to lower system overhead
Slave EDMA transfer capability
The OMAP-L137 MMC/SD Controller does not support SPI mode.
5.14.2 MMCSD Peripheral Register Description(s)
Table 5-33. Multimedia Card/Secure Digital (MMC/SD) Card Controller Registers
BYTE
ACRONYM
REGISTER DESCRIPTION
ADDRESS
0x01C4 0000
0x01C4 0004
0x01C4 0008
0x01C4 000C
0x01C4 0010
0x01C4 0014
0x01C4 0018
0x01C4 001C
0x01C4 0020
0x01C4 0024
0x01C4 0028
0x01C4 002C
0x01C4 0030
0x01C4 0034
0x01C4 0038
0x01C4 003C
0x01C4 0040
0x01C4 0044
0x01C4 0048
0x01C4 0050
0x01C4 0064
0x01C4 0068
0x01C4 006C
0x01C4 0070
0x01C4 0074
MMCCTL
MMCCLK
MMC Control Register
MMC Memory Clock Control Register
MMC Status Register 0
MMCST0
MMCST1
MMC Status Register 1
MMCIM
MMC Interrupt Mask Register
MMC Response Time-Out Register
MMC Data Read Time-Out Register
MMC Block Length Register
MMC Number of Blocks Register
MMC Number of Blocks Counter Register
MMC Data Receive Register
MMC Data Transmit Register
MMC Command Register
MMCTOR
MMCTOD
MMCBLEN
MMCNBLK
MMCNBLC
MMCDRR
MMCDXR
MMCCMD
MMCARGHL
MMCRSP01
MMCRSP23
MMCRSP45
MMCRSP67
MMCDRSP
MMCCIDX
SDIOCTL
MMC Argument Register
MMC Response Register 0 and 1
MMC Response Register 2 and 3
MMC Response Register 4 and 5
MMC Response Register 6 and 7
MMC Data Response Register
MMC Command Index Register
SDIO Control Register
SDIOST0
SDIO Status Register 0
SDIOIEN
SDIO Interrupt Enable Register
SDIO Interrupt Status Register
MMC FIFO Control Register
SDIOIST
MMCFIFOCTL
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5.14.3 MMC/SD Electrical Data/Timing
Table 5-34. Timing Requirements for MMC/SD Module
(see Figure 5-27 and Figure 5-29)
No.
1
PARAMETER
MIN
3.2
1.5
3.2
1.5
MAX
UNIT
ns
tsu(CMDV-CLKH)
th(CLKH-CMDV)
tsu(DATV-CLKH)
th(CLKH-DATV)
Setup time, MMCSD_CMD valid before MMCSD_CLK high
Hold time, MMCSD_CMD valid after MMCSD_CLK high
Setup time, MMCSD_DATx valid before MMCSD_CLK high
Hold time, MMCSD_DATx valid after MMCSD_CLK high
2
ns
3
ns
4
ns
Table 5-35. Switching Characteristics Over Recommended Operating Conditions for MMC/SD Module
(see Figure 5-26 through Figure 5-29)
No.
7
PARAMETER
MIN
0
MAX
52
UNIT
MHz
KHz
ns
f(CLK)
Operating frequency, MMCSD_CLK
Identification mode frequency, MMCSD_CLK
Pulse width, MMCSD_CLK low
8
f(CLK_ID)
tW(CLKL)
tW(CLKH)
tr(CLK)
0
400
9
6.5
6.5
10
11
12
13
14
Pulse width, MMCSD_CLK high
ns
Rise time, MMCSD_CLK
3
ns
tf(CLK)
Fall time, MMCSD_CLK
3
ns
td(CLKL-CMD)
td(CLKL-DAT)
Delay time, MMCSD_CLK low to MMCSD_CMD transition
Delay time, MMCSD_CLK low to MMCSD_DATx transition
-4.5
-4.5
2.5
2.5
ns
ns
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10
9
7
MMCSD_CLK
MMCSD_CMD
13
13
13
Valid
13
START
XMIT
Valid
Valid
END
Figure 5-26. MMC/SD Host Command Timing
9
10
7
MMCSD_CLK
MMCSD_CMD
1
2
Valid
START
XMIT
Valid
Valid
END
Figure 5-27. MMC/SD Card Response Timing
10
9
7
MMCSD_CLK
MMCSD_DATx
14
14
14
Dx
14
START
D0
D1
END
Figure 5-28. MMC/SD Host Write Timing
9
10
7
MMCSD_CLK
MMCSD_DATx
4
4
3
3
Start
D0
D1
Dx
End
Figure 5-29. MMC/SD Host Read and Card CRC Status Timing
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5.15 Ethernet Media Access Controller (EMAC)
The Ethernet Media Access Controller (EMAC) provides an efficient interface between OMAP-L137 and
the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100
Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.
The EMAC controls the flow of packet data from the OMAP-L137 device to the PHY. The MDIO module
controls PHY configuration and status monitoring.
Both the EMAC and the MDIO modules interface to the OMAP-L137 device through a custom interface
that allows efficient data transmission and reception. This custom interface is referred to as the EMAC
control module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used
to multiplex and control interrupts.
5.15.1 EMAC Peripheral Register Description(s)
Table 5-36. Ethernet Media Access Controller (EMAC) Registers
BYTE ADDRESS
0x01E2 3000
0x01E2 3004
0x01E2 3008
0x01E2 3010
0x01E2 3014
0x01E2 3018
0x01E2 3080
0x01E2 3084
0x01E2 3088
0x01E2 308C
0x01E2 3090
0x01E2 3094
0x01E2 30A0
0x01E2 30A4
0x01E2 30A8
0x01E2 30AC
0x01E2 30B0
0x01E2 30B4
0x01E2 30B8
0x01E2 30BC
0x01E2 3100
0x01E2 3104
0x01E2 3108
0x01E2 310C
0x01E2 3110
0x01E2 3114
0x01E2 3120
0x01E2 3124
0x01E2 3128
0x01E2 312C
0x01E2 3130
0x01E2 3134
0x01E2 3138
0x01E2 313C
ACRONYM
TXREV
REGISTER DESCRIPTION
Transmit Revision Register
TXCONTROL
Transmit Control Register
TXTEARDOWN
Transmit Teardown Register
RXREV
Receive Revision Register
RXCONTROL
Receive Control Register
RXTEARDOWN
Receive Teardown Register
TXINTSTATRAW
TXINTSTATMASKED
TXINTMASKSET
TXINTMASKCLEAR
MACINVECTOR
Transmit Interrupt Status (Unmasked) Register
Transmit Interrupt Status (Masked) Register
Transmit Interrupt Mask Set Register
Transmit Interrupt Clear Register
MAC Input Vector Register
MACEOIVECTOR
RXINTSTATRAW
RXINTSTATMASKED
RXINTMASKSET
RXINTMASKCLEAR
MACINTSTATRAW
MACINTSTATMASKED
MACINTMASKSET
MACINTMASKCLEAR
RXMBPENABLE
RXUNICASTSET
RXUNICASTCLEAR
RXMAXLEN
MAC End Of Interrupt Vector Register
Receive Interrupt Status (Unmasked) Register
Receive Interrupt Status (Masked) Register
Receive Interrupt Mask Set Register
Receive Interrupt Mask Clear Register
MAC Interrupt Status (Unmasked) Register
MAC Interrupt Status (Masked) Register
MAC Interrupt Mask Set Register
MAC Interrupt Mask Clear Register
Receive Multicast/Broadcast/Promiscuous Channel Enable Register
Receive Unicast Enable Set Register
Receive Unicast Clear Register
Receive Maximum Length Register
RXBUFFEROFFSET
RXFILTERLOWTHRESH
RX0FLOWTHRESH
RX1FLOWTHRESH
RX2FLOWTHRESH
RX3FLOWTHRESH
RX4FLOWTHRESH
RX5FLOWTHRESH
RX6FLOWTHRESH
RX7FLOWTHRESH
Receive Buffer Offset Register
Receive Filter Low Priority Frame Threshold Register
Receive Channel 0 Flow Control Threshold Register
Receive Channel 1 Flow Control Threshold Register
Receive Channel 2 Flow Control Threshold Register
Receive Channel 3 Flow Control Threshold Register
Receive Channel 4 Flow Control Threshold Register
Receive Channel 5 Flow Control Threshold Register
Receive Channel 6 Flow Control Threshold Register
Receive Channel 7 Flow Control Threshold Register
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Table 5-36. Ethernet Media Access Controller (EMAC) Registers (continued)
BYTE ADDRESS
ACRONYM
RX0FREEBUFFER
RX1FREEBUFFER
RX2FREEBUFFER
RX3FREEBUFFER
RX4FREEBUFFER
RX5FREEBUFFER
RX6FREEBUFFER
RX7FREEBUFFER
MACCONTROL
MACSTATUS
EMCONTROL
FIFOCONTROL
MACCONFIG
SOFTRESET
MACSRCADDRLO
MACSRCADDRHI
MACHASH1
MACHASH2
BOFFTEST
TPACETEST
RXPAUSE
REGISTER DESCRIPTION
Receive Channel 0 Free Buffer Count Register
Receive Channel 1 Free Buffer Count Register
Receive Channel 2 Free Buffer Count Register
Receive Channel 3 Free Buffer Count Register
Receive Channel 4 Free Buffer Count Register
Receive Channel 5 Free Buffer Count Register
Receive Channel 6 Free Buffer Count Register
Receive Channel 7 Free Buffer Count Register
MAC Control Register
0x01E2 3140
0x01E2 3144
0x01E2 3148
0x01E2 314C
0x01E2 3150
0x01E2 3154
0x01E2 3158
0x01E2 315C
0x01E2 3160
0x01E2 3164
0x01E2 3168
0x01E2 316C
0x01E2 3170
0x01E2 3174
0x01E2 31D0
0x01E2 31D4
0x01E2 31D8
0x01E2 31DC
0x01E2 31E0
0x01E2 31E4
0x01E2 31E8
0x01E2 31EC
0x01E2 3200 - 0x01E2 32FC
0x01E2 3500
0x01E2 3504
0x01E2 3508
0x01E2 3600
0x01E2 3604
0x01E2 3608
0x01E2 360C
0x01E2 3610
0x01E2 3614
0x01E2 3618
0x01E2 361C
0x01E2 3620
0x01E2 3624
0x01E2 3628
0x01E2 362C
0x01E2 3630
0x01E2 3634
0x01E2 3638
0x01E2 363C
0x01E2 3640
0x01E2 3644
0x01E2 3648
0x01E2 364C
0x01E2 3650
MAC Status Register
Emulation Control Register
FIFO Control Register
MAC Configuration Register
Soft Reset Register
MAC Source Address Low Bytes Register
MAC Source Address High Bytes Register
MAC Hash Address Register 1
MAC Hash Address Register 2
Back Off Test Register
Transmit Pacing Algorithm Test Register
Receive Pause Timer Register
TXPAUSE
Transmit Pause Timer Register
(see Table 5-37)
MACADDRLO
MACADDRHI
MACINDEX
TX0HDP
EMAC Statistics Registers
MAC Address Low Bytes Register, Used in Receive Address Matching
MAC Address High Bytes Register, Used in Receive Address Matching
MAC Index Register
Transmit Channel 0 DMA Head Descriptor Pointer Register
Transmit Channel 1 DMA Head Descriptor Pointer Register
Transmit Channel 2 DMA Head Descriptor Pointer Register
Transmit Channel 3 DMA Head Descriptor Pointer Register
Transmit Channel 4 DMA Head Descriptor Pointer Register
Transmit Channel 5 DMA Head Descriptor Pointer Register
Transmit Channel 6 DMA Head Descriptor Pointer Register
Transmit Channel 7 DMA Head Descriptor Pointer Register
Receive Channel 0 DMA Head Descriptor Pointer Register
Receive Channel 1 DMA Head Descriptor Pointer Register
Receive Channel 2 DMA Head Descriptor Pointer Register
Receive Channel 3 DMA Head Descriptor Pointer Register
Receive Channel 4 DMA Head Descriptor Pointer Register
Receive Channel 5 DMA Head Descriptor Pointer Register
Receive Channel 6 DMA Head Descriptor Pointer Register
Receive Channel 7 DMA Head Descriptor Pointer Register
Transmit Channel 0 Completion Pointer Register
Transmit Channel 1 Completion Pointer Register
Transmit Channel 2 Completion Pointer Register
Transmit Channel 3 Completion Pointer Register
Transmit Channel 4 Completion Pointer Register
TX1HDP
TX2HDP
TX3HDP
TX4HDP
TX5HDP
TX6HDP
TX7HDP
RX0HDP
RX1HDP
RX2HDP
RX3HDP
RX4HDP
RX5HDP
RX6HDP
RX7HDP
TX0CP
TX1CP
TX2CP
TX3CP
TX4CP
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Table 5-36. Ethernet Media Access Controller (EMAC) Registers (continued)
BYTE ADDRESS
0x01E2 3654
0x01E2 3658
0x01E2 365C
0x01E2 3660
0x01E2 3664
0x01E2 3668
0x01E2 366C
0x01E2 3670
0x01E2 3674
0x01E2 3678
0x01E2 367C
ACRONYM
TX5CP
TX6CP
TX7CP
RX0CP
RX1CP
RX2CP
RX3CP
RX4CP
RX5CP
RX6CP
RX7CP
REGISTER DESCRIPTION
Transmit Channel 5 Completion Pointer Register
Transmit Channel 6 Completion Pointer Register
Transmit Channel 7 Completion Pointer Register
Receive Channel 0 Completion Pointer Register
Receive Channel 1 Completion Pointer Register
Receive Channel 2 Completion Pointer Register
Receive Channel 3 Completion Pointer Register
Receive Channel 4 Completion Pointer Register
Receive Channel 5 Completion Pointer Register
Receive Channel 6 Completion Pointer Register
Receive Channel 7 Completion Pointer Register
Table 5-37. EMAC Statistics Registers
BYTE
ADDRESS
ACRONYM
REGISTER DESCRIPTION
Good Receive Frames Register
0x01E2 3200
RXGOODFRAMES
RXBCASTFRAMES
Broadcast Receive Frames Register
(Total number of good broadcast frames received)
0x01E2 3204
Multicast Receive Frames Register
(Total number of good multicast frames received)
0x01E2 3208
0x01E2 320C
0x01E2 3210
RXMCASTFRAMES
RXPAUSEFRAMES
RXCRCERRORS
Pause Receive Frames Register
Receive CRC Errors Register
(Total number of frames received with CRC errors)
Receive Alignment/Code Errors Register
(Total number of frames received with alignment/code errors)
0x01E2 3214
0x01E2 3218
0x01E2 321C
0x01E2 3220
RXALIGNCODEERRORS
RXOVERSIZED
Receive Oversized Frames Register
(Total number of oversized frames received)
Receive Jabber Frames Register
(Total number of jabber frames received)
RXJABBER
Receive Undersized Frames Register
(Total number of undersized frames received)
RXUNDERSIZED
0x01E2 3224
0x01E2 3228
0x01E2 322C
RXFRAGMENTS
RXFILTERED
Receive Frame Fragments Register
Filtered Receive Frames Register
Received QOS Filtered Frames Register
RXQOSFILTERED
Receive Octet Frames Register
(Total number of received bytes in good frames)
0x01E2 3230
0x01E2 3234
RXOCTETS
Good Transmit Frames Register
(Total number of good frames transmitted)
TXGOODFRAMES
0x01E2 3238
0x01E2 323C
0x01E2 3240
0x01E2 3244
0x01E2 3248
0x01E2 324C
0x01E2 3250
0x01E2 3254
0x01E2 3258
0x01E2 325C
0x01E2 3260
0x01E2 3264
TXBCASTFRAMES
TXMCASTFRAMES
TXPAUSEFRAMES
TXDEFERRED
Broadcast Transmit Frames Register
Multicast Transmit Frames Register
Pause Transmit Frames Register
Deferred Transmit Frames Register
Transmit Collision Frames Register
Transmit Single Collision Frames Register
Transmit Multiple Collision Frames Register
Transmit Excessive Collision Frames Register
Transmit Late Collision Frames Register
Transmit Underrun Error Register
TXCOLLISION
TXSINGLECOLL
TXMULTICOLL
TXEXCESSIVECOLL
TXLATECOLL
TXUNDERRUN
TXCARRIERSENSE
TXOCTETS
Transmit Carrier Sense Errors Register
Transmit Octet Frames Register
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Table 5-37. EMAC Statistics Registers (continued)
BYTE
ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01E2 3268
0x01E2 326C
0x01E2 3270
0x01E2 3274
0x01E2 3278
0x01E2 327C
0x01E2 3280
0x01E2 3284
0x01E2 3288
0x01E2 328C
FRAME64
Transmit and Receive 64 Octet Frames Register
FRAME65T127
Transmit and Receive 65 to 127 Octet Frames Register
Transmit and Receive 128 to 255 Octet Frames Register
Transmit and Receive 256 to 511 Octet Frames Register
Transmit and Receive 512 to 1023 Octet Frames Register
Transmit and Receive 1024 to 1518 Octet Frames Register
Network Octet Frames Register
FRAME128T255
FRAME256T511
FRAME512T1023
FRAME1024TUP
NETOCTETS
RXSOFOVERRUNS
RXMOFOVERRUNS
RXDMAOVERRUNS
Receive FIFO or DMA Start of Frame Overruns Register
Receive FIFO or DMA Middle of Frame Overruns Register
Receive DMA Start of Frame and Middle of Frame Overruns Register
Table 5-38. EMAC Control Module Registers
BYTE ADDRESS
0x01E2 2000
0x01E2 2004
0x01E2 200C
0x01E2 2010
0x01E2 2014
0x01E2 2018
0x01E2 201C
0x01E2 2020
0x01E2 2024
0x01E2 2028
0x01E2 202C
0x01E2 2030
0x01E2 2034
0x01E2 2038
0x01E2 203C
0x01E2 2040
0x01E2 2044
0x01E2 2048
0x01E2 204C
0x01E2 2050
0x01E2 2054
0x01E2 2058
0x01E2 205C
0x01E2 2060
0x01E2 2064
0x01E2 2068
0x01E2 206C
0x01E2 2070
0x01E2 2074
0x01E2 2078
0x01E2 207C
0x01E2 2080
0x01E2 2084
ACRONYM
REGISTER DESCRIPTION
REV
SOFTRESET
INTCONTROL
C0RXTHRESHEN
C0RXEN
EMAC Control Module Revision Register
EMAC Control Module Software Reset Register
EMAC Control Module Interrupt Control Register
EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Enable Register
EMAC Control Module Interrupt Core 0 Receive Interrupt Enable Register
EMAC Control Module Interrupt Core 0 Transmit Interrupt Enable Register
EMAC Control Module Interrupt Core 0 Miscellaneous Interrupt Enable Register
EMAC Control Module Interrupt Core 1 Receive Threshold Interrupt Enable Register
EMAC Control Module Interrupt Core 1 Receive Interrupt Enable Register
EMAC Control Module Interrupt Core 1 Transmit Interrupt Enable Register
EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Enable Register
EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Enable Register
EMAC Control Module Interrupt Core 2 Receive Interrupt Enable Register
EMAC Control Module Interrupt Core 2 Transmit Interrupt Enable Register
EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Enable Register
EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Status Register
EMAC Control Module Interrupt Core 0 Receive Interrupt Status Register
EMAC Control Module Interrupt Core 0 Transmit Interrupt Status Register
EMAC Control Module Interrupt Core 0 Miscellaneous Interrupt Status Register
EMAC Control Module Interrupt Core 1 Receive Threshold Interrupt Status Register
EMAC Control Module Interrupt Core 1 Receive Interrupt Status Register
EMAC Control Module Interrupt Core 1 Transmit Interrupt Status Register
EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Status Register
EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Status Register
EMAC Control Module Interrupt Core 2 Receive Interrupt Status Register
EMAC Control Module Interrupt Core 2 Transmit Interrupt Status Register
EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Status Register
EMAC Control Module Interrupt Core 0 Receive Interrupts Per Millisecond Register
EMAC Control Module Interrupt Core 0 Transmit Interrupts Per Millisecond Register
EMAC Control Module Interrupt Core 1 Receive Interrupts Per Millisecond Register
EMAC Control Module Interrupt Core 1 Transmit Interrupts Per Millisecond Register
EMAC Control Module Interrupt Core 2 Receive Interrupts Per Millisecond Register
EMAC Control Module Interrupt Core 2 Transmit Interrupts Per Millisecond Register
C0TXEN
C0MISCEN
C1RXTHRESHEN
C1RXEN
C1TXEN
C1MISCEN
C2RXTHRESHEN
C2RXEN
C2TXEN
C2MISCEN
C0RXTHRESHSTAT
C0RXSTAT
C0TXSTAT
C0MISCSTAT
C1RXTHRESHSTAT
C1RXSTAT
C1TXSTAT
C1MISCSTAT
C2RXTHRESHSTAT
C2RXSTAT
C2TXSTAT
C2MISCSTAT
C0RXIMAX
C0TXIMAX
C1RXIMAX
C1TXIMAX
C2RXIMAX
C2TXIMAX
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Table 5-39. EMAC Control Module RAM
BYTE ADRESS
REGISTER DESCRIPTION
EMAC Local Buffer Descriptor Memory
0x01E2 0000 - 0x01E2 1FFF
Table 5-40. RMII Timing Requirements
No.
1
PARAMETER
MIN
TYP MAX UNIT
tc(REFCLK)
Cycle Time, RMII_MHZ_50_CLK
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
tw(REFCLKH)
Pulse Width, RMII_MHZ_50_CLK High
7
7
4
2
4
2
4
2
13
13
3
tw(REFCLKL)
Pulse Width, RMII_MHZ_50_CLK Low
6
tsu(RXD-REFCLK)
th(REFCLK-RXD)
tsu(CRSDV-REFCLK)
th(REFCLK-CRSDV)
tsu(RXER-REFCLK)
th(REFCLKR-RXER)
Input Setup Time, RXD Valid before RMII_MHZ_50_CLK High
Input Hold Time, RXD Valid after RMII_MHZ_50_CLK High
Input Setup Time, CRSDV Valid before RMII_MHZ_50_CLK High
Input Hold Time, CRSDV Valid after RMII_MHZ_50_CLK High
Input Setup Time, RXER Valid before RMII_MHZ_50_CLK High
Input Hold Time, RXER Valid after RMII_MHZ_50_CLK High
7
8
9
10
11
Note: Per the RMII industry specification, the RMII reference clock (RMII_MHZ_50_CLK) must have jitter
tolerance of 50 ppm or less.
Table 5-41. RMII Switching Characteristics
No.
4
PARAMETER
MIN
2.5
TYP MAX UNIT
td(REFCLK-TXD)
td(REFCLK-TXEN)
Output Delay Time, RMII_MHZ_50_CLK High to TXD Valid
Output Delay Time, RMII_MHZ_50_CLK High to TXEN Valid
13
13
ns
ns
5
2.5
1
2
3
RMII_MHz_50_CLK
5
5
RMII_TXEN
4
RMII_TXD[1:0]
6
7
RMII_RXD[1:0]
RMII_CRS_DV
8
9
10
11
RMII_RXER
Figure 5-30. RMII Timing Diagram
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5.16 Management Data Input/Output (MDIO)
The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to
enumerate all PHY devices in the system.
The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to
interrogate and control Ethernet PHY(s) using a shared two-wire bus. Host software uses the MDIO
module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the
negotiation results, and configure required parameters in the EMAC module for correct operation. The
module is designed to allow almost transparent operation of the MDIO interface, with very little
maintenance from the core processor. Only one PHY may be connected at any given time.
For more detailed information on the MDIO peripheral, see the OMAP-L137 Applications Processor DSP
Peripherals Overview Reference Guide. (SPRUGA6).
5.16.1 MDIO Registers
For a list of supported MDIO registers see Table 5-42 [MDIO Registers].
Table 5-42. MDIO Register Memory Map
BYTE ADDRESS
0x01E2 4000
ACRONYM
REV
REGISTER DESCRIPTION
Revision Identification Register
0x01E2 4004
CONTROL
ALIVE
MDIO Control Register
0x01E2 4008
MDIO PHY Alive Status Register
0x01E2 400C
LINK
MDIO PHY Link Status Register
0x01E2 4010
LINKINTRAW
LINKINTMASKED
–
MDIO Link Status Change Interrupt (Unmasked) Register
MDIO Link Status Change Interrupt (Masked) Register
Reserved
0x01E2 4014
0x01E2 4018
0x01E2 4020
USERINTRAW
USERINTMASKED
USERINTMASKSET
MDIO User Command Complete Interrupt (Unmasked) Register
MDIO User Command Complete Interrupt (Masked) Register
MDIO User Command Complete Interrupt Mask Set Register
0x01E2 4024
0x01E2 4028
0x01E2 402C
USERINTMASKCLEAR MDIO User Command Complete Interrupt Mask Clear Register
0x01E2 4030 - 0x01E2 407C
0x01E2 4080
–
Reserved
USERACCESS0
USERPHYSEL0
USERACCESS1
USERPHYSEL1
–
MDIO User Access Register 0
MDIO User PHY Select Register 0
MDIO User Access Register 1
MDIO User PHY Select Register 1
Reserved
0x01E2 4084
0x01E2 4088
0x01E2 408C
0x01E2 4090 - 0x01E2 47FF
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5.16.2 Management Data Input/Output (MDIO) Electrical Data/Timing
Table 5-43. Timing Requirements for MDIO Input (see Figure 5-31 and Figure 5-32)
No.
1
PARAMETER
MIN
400
180
MAX
UNIT
ns
tc(MDIO_CLK)
tw(MDIO_CLK)
tt(MDIO_CLK)
Cycle time, MDIO_CLK
2
Pulse duration, MDIO_CLK high/low
Transition time, MDIO_CLK
ns
3
5
ns
4
tsu(MDIO-MDIO_CLKH) Setup time, MDIO_D data input valid before MDIO_CLK high
10
0
ns
5
th(MDIO_CLKH-MDIO)
Hold time, MDIO_D data input valid after MDIO_CLK high
ns
1
3
3
MDIO_CLK
4
5
MDIO_D
(input)
Figure 5-31. MDIO Input Timing
Table 5-44. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
(see Figure 5-32)
No.
PARAMETER
MIN
MAX
UNIT
7
td(MDIO_CLKL-MDIO)
Delay time, MDIO_CLK low to MDIO_D data output valid
0
100
ns
1
MDIO_CLK
7
MDIO_D
(output)
Figure 5-32. MDIO Output Timing
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5.17 Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2)
The McASP serial port is specifically designed for multichannel audio applications. Its key features are:
•
•
•
Flexible clock and frame sync generation logic and on-chip dividers
Up to sixteen transmit or receive data pins and serializers
Large number of serial data format options, including:
–
–
–
–
–
TDM Frames with 2 to 32 time slots per frame (periodic) or 1 slot per frame (burst)
Time slots of 8,12,16, 20, 24, 28, and 32 bits
First bit delay 0, 1, or 2 clocks
MSB or LSB first bit order
Left- or right-aligned data words within time slots
•
•
•
DIT Mode (optional) with 384-bit Channel Status and 384-bit User Data registers
Extensive error checking and mute generation logic
All unused pins GPIO-capable
Additionally, while the OMAP-L13x McASP modules are backward compatible with the McASP on
previous devices; the OMAP-L13x McASP includes the following new features:
•
Transmit & Receive FIFO Buffers for each McASP. Allows the McASP to operate at a higher sample
rate by making it more tolerant to DMA latency.
•
Dynamic Adjustment of Clock Dividers
–
Clock Divider Value may be changed without resetting the McASP
The three McASPs on the OMAP-L137 are configured with the following options:
Table 5-45. OMAP-L137 McASP Configurations(1)
Module
Serializers
AFIFO
DIT
OMAP-L137 Pins
64 Word RX
64 Word TX
AXR0[15:0], AHCLKR0, ACLKR0, AFSR0, AHCLKX0, ACLKX0,
AFSX0, AMUTE0
McASP0
16
N
64 Word RX
64 Word TX
AXR1[11:10], AXR1[8:0], AHCLKR1, ACLKR1, AFSR1, AHCLKX1,
ACLKX1, AFSX1, AMUTE1
McASP1
McASP2
12
4
N
Y
16 Word RX
16 Word TX
AXR2[3:0], AHCLKR2, ACLKR2, AFSR2, AHCLKX2, ACLKX2,
AFSX2, AMUTE2
(1) Pins available are the maximum number of pins that may be configured for a particular McASP; not including pin multiplexing.
Pins Function
AHCLKRx Receive Master Clock
Receive Logic
Clock/Frame Generator
State Machine
Peripheral
Configuration
Bus
GIO
Control
ACLKRx
AFSRx
Receive Bit Clock
Receive Left/Right Clock or Frame Sync
The McASPs DO NOT have
dedicated AMUTEINx pins.
AMUTEINx
AMUTEx
Clock Check and
Error Detection
DIT RAM
384 C
384 U
AFSXx
ACLKXx
AHCLKXx
Transmit Left/Right Clock or Frame Sync
Transmit Bit Clock
Transmit Master Clock
Transmit Logic
Clock/Frame Generator
State Machine
Optional
Transmit
Formatter
Serializer 0
Serializer 1
AXRx[0]
AXRx[1]
Transmit/Receive Serial Data Pin
Transmit/Receive Serial Data Pin
McASP
DMA Bus
(Dedicated)
Receive
Formatter
Serializer y
AXRx[y]
Transmit/Receive Serial Data Pin
McASPx (x = 0, 1, 2)
Figure 5-33. McASP Block Diagram
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5.17.1 McASP Peripheral Registers Description(s)
Registers for the McASP are summarized in Table 5-46. The registers are accessed through the
peripheral configuration port. The receive buffer registers (RBUF) and transmit buffer registers (XBUF) can
also be accessed through the DMA port, as listed in Table 5-47
Registers for the McASP Audio FIFO (AFIFO) are summarized in Table 5-48. Note that the AFIFO Write
FIFO (WFIFO) and Read FIFO (RFIFO) have independent control and status registers. The AFIFO control
registers are accessed through the peripheral configuration port.
Table 5-46. McASP Registers Accessed Through Peripheral Configuration Port
McASP0
BYTE
McASP1
BYTE
McASP2
BYTE
ACRONYM
REGISTER DESCRIPTION
ADDRESS
ADDRESS
ADDRESS
0x01D0 0000
0x01D0 0010
0x01D0 0014
0x01D0 0018
0x01D0 001C
0x01D0 001C
0x01D0 4000
0x01D0 4010
0x01D0 4014
0x01D0 4018
0x01D0 401C
0x01D0 401C
0x01D0 8000
0x01D0 8010
0x01D0 8014
0x01D0 8018
0x01D0 801C
0x01D0 801C
REV
PFUNC
PDIR
Revision identification register
Pin function register
Pin direction register
PDOUT
PDIN
Pin data output register
Read returns: Pin data input register
PDSET
Writes affect: Pin data set register
(alternate write address: PDOUT)
0x01D0 0020
0x01D0 0044
0x01D0 0048
0x01D0 004C
0x01D0 0050
0x01D0 0060
0x01D0 4020
0x01D0 4044
0x01D0 4048
0x01D0 404C
0x01D0 4050
0x01D0 4060
0x01D0 8020
0x01D0 8044
0x01D0 8048
0x01D0 804C
0x01D0 8050
0x01D0 8060
PDCLR
GBLCTL
AMUTE
Pin data clear register (alternate write address: PDOUT)
Global control register
Audio mute control register
DLBCTL
DITCTL
Digital loopback control register
DIT mode control register
RGBLCTL
Receiver global control register: Alias of GBLCTL, only receive bits
are affected - allows receiver to be reset independently from
transmitter
0x01D0 0064
0x01D0 0068
0x01D0 006C
0x01D0 0070
0x01D0 0074
0x01D0 0078
0x01D0 007C
0x01D0 0080
0x01D0 0084
0x01D0 0088
0x01D0 008C
0x01D0 00A0
0x01D0 4064
0x01D0 4068
0x01D0 406C
0x01D0 4070
0x01D0 4074
0x01D0 4078
0x01D0 407C
0x01D0 4080
0x01D0 4084
0x01D0 4088
0x01D0 408C
0x01D0 40A0
0x01D0 8064
0x01D0 8068
0x01D0 806C
0x01D0 8070
0x01D0 8074
0x01D0 8078
0x01D0 807C
0x01D0 8080
0x01D0 8084
0x01D0 8088
0x01D0 808C
0x01D0 80A0
RMASK
RFMT
Receive format unit bit mask register
Receive bit stream format register
Receive frame sync control register
Receive clock control register
AFSRCTL
ACLKRCTL
AHCLKRCTL Receive high-frequency clock control register
RTDM
RINTCTL
RSTAT
Receive TDM time slot 0-31 register
Receiver interrupt control register
Receiver status register
RSLOT
Current receive TDM time slot register
Receive clock check control register
Receiver DMA event control register
RCLKCHK
REVTCTL
XGBLCTL
Transmitter global control register. Alias of GBLCTL, only transmit
bits are affected - allows transmitter to be reset independently from
receiver
0x01D0 00A4
0x01D0 00A8
0x01D0 00AC
0x01D0 00B0
0x01D0 00B4
0x01D0 00B8
0x01D0 00BC
0x01D0 00C0
0x01D0 00C4
0x01D0 00C8
0x01D0 40A4
0x01D0 40A8
0x01D0 40AC
0x01D0 40B0
0x01D0 40B4
0x01D0 40B8
0x01D0 40BC
0x01D0 40C0
0x01D0 40C4
0x01D0 40C8
0x01D0 80A4
0x01D0 80A8
0x01D0 80AC
0x01D0 80B0
0x01D0 80B4
0x01D0 80B8
0x01D0 80BC
0x01D0 80C0
0x01D0 80C4
0x01D0 80C8
XMASK
XFMT
Transmit format unit bit mask register
Transmit bit stream format register
Transmit frame sync control register
Transmit clock control register
AFSXCTL
ACLKXCTL
AHCLKXCTL Transmit high-frequency clock control register
XTDM
XINTCTL
XSTAT
Transmit TDM time slot 0-31 register
Transmitter interrupt control register
Transmitter status register
XSLOT
Current transmit TDM time slot register
Transmit clock check control register
XCLKCHK
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Table 5-46. McASP Registers Accessed Through Peripheral Configuration Port (continued)
McASP0
BYTE
McASP1
BYTE
McASP2
BYTE
ACRONYM
REGISTER DESCRIPTION
ADDRESS
ADDRESS
ADDRESS
0x01D0 00CC
0x01D0 0100
0x01D0 0104
0x01D0 0108
0x01D0 010C
0x01D0 0110
0x01D0 0114
0x01D0 0118
0x01D0 011C
0x01D0 0120
0x01D0 0124
0x01D0 0128
0x01D0 012C
0x01D0 0130
0x01D0 0134
0x01D0 0138
0x01D0 013C
0x01D0 0140
0x01D0 0144
0x01D0 0148
0x01D0 014C
0x01D0 0150
0x01D0 0154
0x01D0 0158
0x01D0 015C
0x01D0 0180
0x01D0 0184
0x01D0 0188
0x01D0 018C
0x01D0 0190
0x01D0 0194
0x01D0 0198
0x01D0 019C
0x01D0 01A0
0x01D0 01A4
0x01D0 01A8
0x01D0 01AC
0x01D0 01B0
0x01D0 01B4
0x01D0 01B8
0x01D0 01BC
0x01D0 0200
0x01D0 0204
0x01D0 0208
0x01D0 020C
0x01D0 40CC
0x01D0 4100
0x01D0 4104
0x01D0 4108
0x01D0 410C
0x01D0 4110
0x01D0 4114
0x01D0 4118
0x01D0 411C
0x01D0 4120
0x01D0 4124
0x01D0 4128
0x01D0 412C
0x01D0 4130
0x01D0 4134
0x01D0 4138
0x01D0 413C
0x01D0 4140
0x01D0 4144
0x01D0 4148
0x01D0 414C
0x01D0 4150
0x01D0 4154
0x01D0 4158
0x01D0 415C
0x01D0 4180
0x01D0 4184
0x01D0 4188
0x01D0 418C
0x01D0 4190
0x01D0 4194
0x01D0 4198
0x01D0 419C
0x01D0 41A0
0x01D0 41A4
0x01D0 41A8
0x01D0 41AC
0x01D0 41B0
0x01D0 41B4
0x01D0 41B8
0x01D0 41BC
0x01D0 4200
0x01D0 4204
0x01D0 4208
0x01D0 420C
0x01D0 80CC
0x01D0 8100
0x01D0 8104
0x01D0 8108
0x01D0 810C
0x01D0 8110
0x01D0 8114
0x01D0 8118
0x01D0 811C
0x01D0 8120
0x01D0 8124
0x01D0 8128
0x01D0 812C
0x01D0 8130
0x01D0 8134
0x01D0 8138
0x01D0 813C
0x01D0 8140
0x01D0 8144
0x01D0 8148
0x01D0 814C
0x01D0 8150
0x01D0 8154
0x01D0 8158
0x01D0 815C
0x01D0 8180
0x01D0 8184
0x01D0 8188
0x01D0 818C
0x01D0 8190
0x01D0 8194
0x01D0 8198
0x01D0 819C
0x01D0 81A0
0x01D0 81A4
0x01D0 81A8
0x01D0 81AC
0x01D0 81B0
0x01D0 81B4
0x01D0 81B8
0x01D0 81BC
0x01D0 8200
0x01D0 8204
0x01D0 8208
0x01D0 820C
XEVTCTL
DITCSRA0
DITCSRA1
DITCSRA2
DITCSRA3
DITCSRA4
DITCSRA5
DITCSRB0
DITCSRB1
DITCSRB2
DITCSRB3
DITCSRB4
DITCSRB5
DITUDRA0
DITUDRA1
DITUDRA2
DITUDRA3
DITUDRA4
DITUDRA5
DITUDRB0
DITUDRB1
DITUDRB2
DITUDRB3
DITUDRB4
DITUDRB5
SRCTL0
Transmitter DMA event control register
Left (even TDM time slot) channel status register (DIT mode) 0
Left (even TDM time slot) channel status register (DIT mode) 1
Left (even TDM time slot) channel status register (DIT mode) 2
Left (even TDM time slot) channel status register (DIT mode) 3
Left (even TDM time slot) channel status register (DIT mode) 4
Left (even TDM time slot) channel status register (DIT mode) 5
Right (odd TDM time slot) channel status register (DIT mode) 0
Right (odd TDM time slot) channel status register (DIT mode) 1
Right (odd TDM time slot) channel status register (DIT mode) 2
Right (odd TDM time slot) channel status register (DIT mode) 3
Right (odd TDM time slot) channel status register (DIT mode) 4
Right (odd TDM time slot) channel status register (DIT mode) 5
Left (even TDM time slot) channel user data register (DIT mode) 0
Left (even TDM time slot) channel user data register (DIT mode) 1
Left (even TDM time slot) channel user data register (DIT mode) 2
Left (even TDM time slot) channel user data register (DIT mode) 3
Left (even TDM time slot) channel user data register (DIT mode) 4
Left (even TDM time slot) channel user data register (DIT mode) 5
Right (odd TDM time slot) channel user data register (DIT mode) 0
Right (odd TDM time slot) channel user data register (DIT mode) 1
Right (odd TDM time slot) channel user data register (DIT mode) 2
Right (odd TDM time slot) channel user data register (DIT mode) 3
Right (odd TDM time slot) channel user data register (DIT mode) 4
Right (odd TDM time slot) channel user data register (DIT mode) 5
Serializer control register 0
SRCTL1
Serializer control register 1
SRCTL2
Serializer control register 2
SRCTL3
Serializer control register 3
SRCTL4
Serializer control register 4
SRCTL5
Serializer control register 5
SRCTL6
Serializer control register 6
SRCTL7
Serializer control register 7
SRCTL8
Serializer control register 8
SRCTL9
Serializer control register 9
SRCTL10
SRCTL11
SRCTL12
SRCTL13
SRCTL14
SRCTL15
XBUF0(1)
XBUF1(1)
XBUF2(1)
XBUF3(1)
Serializer control register 10
Serializer control register 11
Serializer control register 12
Serializer control register 13
Serializer control register 14
Serializer control register 15
Transmit buffer register for serializer 0
Transmit buffer register for serializer 1
Transmit buffer register for serializer 2
Transmit buffer register for serializer 3
(1) Writes to XRBUF originate from peripheral configuration port only when XBUSEL = 1 in XFMT.
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Table 5-46. McASP Registers Accessed Through Peripheral Configuration Port (continued)
McASP0
BYTE
McASP1
BYTE
McASP2
BYTE
ACRONYM
REGISTER DESCRIPTION
ADDRESS
ADDRESS
ADDRESS
0x01D0 0210
0x01D0 0214
0x01D0 0218
0x01D0 021C
0x01D0 0220
0x01D0 0224
0x01D0 0228
0x01D0 022C
0x01D0 0230
0x01D0 0234
0x01D0 0238
0x01D0 023C
0x01D0 0280
0x01D0 0284
0x01D0 0288
0x01D0 028C
0x01D0 0290
0x01D0 0294
0x01D0 0298
0x01D0 029C
0x01D0 02A0
0x01D0 02A4
0x01D0 02A8
0x01D0 02AC
0x01D0 02B0
0x01D0 02B4
0x01D0 02B8
0x01D0 02BC
0x01D0 4210
0x01D0 4214
0x01D0 4218
0x01D0 421C
0x01D0 4220
0x01D0 4224
0x01D0 4228
0x01D0 422C
0x01D0 4230
0x01D0 4234
0x01D0 4238
0x01D0 423C
0x01D0 4280
0x01D0 4284
0x01D0 4288
0x01D0 428C
0x01D0 4290
0x01D0 4294
0x01D0 4298
0x01D0 429C
0x01D0 42A0
0x01D0 42A4
0x01D0 42A8
0x01D0 42AC
0x01D0 42B0
0x01D0 42B4
0x01D0 42B8
0x01D0 42BC
0x01D0 8210
0x01D0 8214
0x01D0 8218
0x01D0 821C
0x01D0 8220
0x01D0 8224
0x01D0 8228
0x01D0 822C
0x01D0 8230
0x01D0 8234
0x01D0 8238
0x01D0 823C
0x01D0 8280
0x01D0 8284
0x01D0 8288
0x01D0 828C
0x01D0 8290
0x01D0 8294
0x01D0 8298
0x01D0 829C
0x01D0 82A0
0x01D0 82A4
0x01D0 82A8
0x01D0 82AC
0x01D0 82B0
0x01D0 82B4
0x01D0 82BB
0x01D0 82BC
XBUF4(1)
XBUF5(1)
XBUF6(1)
XBUF7(1)
XBUF8(1)
XBUF9(1)
XBUF10(1)
XBUF11(1)
XBUF12(1)
XBUF13(1)
XBUF14(1)
XBUF15(1)
RBUF0(2)
RBUF1(2)
RBUF2(3)
RBUF3(3)
RBUF4(3)
RBUF5(3)
RBUF6(3)
RBUF7(3)
RBUF8(3)
RBUF9(3)
RBUF10(3)
RBUF11(3)
RBUF12(3)
RBUF13(3)
RBUF14(3)
RBUF15(3)
Transmit buffer register for serializer 4
Transmit buffer register for serializer 5
Transmit buffer register for serializer 6
Transmit buffer register for serializer 7
Transmit buffer register for serializer 8
Transmit buffer register for serializer 9
Transmit buffer register for serializer 10
Transmit buffer register for serializer 11
Transmit buffer register for serializer 12
Transmit buffer register for serializer 13
Transmit buffer register for serializer 14
Transmit buffer register for serializer 15
Receive buffer register for serializer 0
Receive buffer register for serializer 1
Receive buffer register for serializer 2
Receive buffer register for serializer 3
Receive buffer register for serializer 4
Receive buffer register for serializer 5
Receive buffer register for serializer 6
Receive buffer register for serializer 7
Receive buffer register for serializer 8
Receive buffer register for serializer 9
Receive buffer register for serializer 10
Receive buffer register for serializer 11
Receive buffer register for serializer 12
Receive buffer register for serializer 13
Receive buffer register for serializer 14
Receive buffer register for serializer 15
(2) Reads from XRBUF originate on peripheral configuration port only when RBUSEL = 1 in RFMT.
(3) Reads from XRBUF originate on peripheral configuration port only when RBUSEL = 1 in RFMT.
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Table 5-47. McASP Registers Accessed Through DMA Port
Hex
Address
Register
Name
McASP0
BYTE
McASP1
BYTE
McASP2
BYTE
REGISTER DESCRIPTION
ADDRESS ADDRESS ADDRESS
Read
Accesses
RBUF
01D0 2000 01D0 6000 01D0 A000
Receive buffer DMA port address. Cycles through receive serializers,
skipping over transmit serializers and inactive serializers. Starts at the
lowest serializer at the beginning of each time slot. Reads from DMA port
only if XBUSEL = 0 in XFMT.
Write
Accesses
XBUF
01D0 2000 01D0 6000 01D0 A000
Transmit buffer DMA port address. Cycles through transmit serializers,
skipping over receive and inactive serializers. Starts at the lowest
serializer at the beginning of each time slot. Writes to DMA port only if
RBUSEL = 0 in RFMT.
Table 5-48. McASP AFIFO Registers Accessed Through Peripheral Configuration Port
McASP0
McASP1
McASP2
ACRONYM
REGISTER DESCRIPTION
BYTE ADDRESS
0x01D0 1000
0x01D0 1010
0x01D0 1014
0x01D0 1018
0x01D0 101C
BYTE ADDRESS
BYTE ADDRESS
0x01D0 5000
0x01D0 5010
0x01D0 5014
0x01D0 5018
0x01D0 501C
0x01D0 9000
0x01D0 9010
0x01D0 9014
0x01D0 9018
0x01D0 901C
AFIFOREV
WFIFOCTL
WFIFOSTS
RFIFOCTL
RFIFOSTS
AFIFO revision identification register
Write FIFO control register
Write FIFO status register
Read FIFO control register
Read FIFO status register
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5.17.2 McASP Electrical Data/Timing
5.17.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
Table 5-49 and Table 5-50 assume testing over recommended operating conditions (see Figure 5-34 and
Figure 5-35).
Table 5-49. McASP0 Timing Requirements(1) (2)
No.
PARAMATER
MIN
MAX
UNIT
Cycle time, AHCLKR0 external, AHCLKR0 input
Cycle time, AHCLKX0 external, AHCLKX0 input
Pulse duration, AHCLKR0 external, AHCLKR0 input
Pulse duration, AHCLKX0 external, AHCLKX0 input
Cycle time, ACLKR0 external, ACLKR0 input
25
25
1
tc(AHCLKRX)
tw(AHCLKRX)
tc(ACLKRX)
tw(ACLKRX)
ns
12.5
12.5
2
3
4
ns
ns
ns
greater of 2P or 25
Cycle time, ACLKX0 external, ACLKX0 input
greater of 2P or 25
Pulse duration, ACLKR0 external, ACLKR0 input
Pulse duration, ACLKX0 external, ACLKX0 input
Setup time, AFSR0 input to ACLKR0 internal(3)
Setup time, AFSX0 input to ACLKX0 internal
12.5
12.5
9.4
9.4
2.9
2.9
2.9
2.9
-1.2
-1.2
0.9
0.9
0.9
0.9
9.4
9.4
2.9
2.9
2.9
2.9
-1.3
-1.3
0.5
0.5
0.5
0.5
Setup time, AFSR0 input to ACLKR0 external input(3)
Setup time, AFSX0 input to ACLKX0 external input
Setup time, AFSR0 input to ACLKR0 external output(3)
Setup time, AFSX0 input to ACLKX0 external output
Hold time, AFSR0 input after ACLKR0 internal(3)
Hold time, AFSX0 input after ACLKX0 internal
Hold time, AFSR0 input after ACLKR0 external input(3)
Hold time, AFSX0 input after ACLKX0 external input
Hold time, AFSR0 input after ACLKR0 external output(3)
Hold time, AFSX0 input after ACLKX0 external output
Setup time, AXR0[n] input to ACLKR0 internal(3)
Setup time, AXR0[n] input to ACLKX0 internal(4)
Setup time, AXR0[n] input to ACLKR0 external input(3)
Setup time, AXR0[n] input to ACLKX0 external input(4)
Setup time, AXR0[n] input to ACLKR0 external output(3)
Setup time, AXR0[n] input to ACLKX0 external output(4)
Hold time, AXR0[n] input after ACLKR0 internal(3)
Hold time, AXR0[n] input after ACLKX0 internal(4)
Hold time, AXR0[n] input after ACLKR0 external input(3)
Hold time, AXR0[n] input after ACLKX0 external input(4)
Hold time, AXR0[n] input after ACLKR0 external output(3)
Hold time, AXR0[n] input after ACLKX0 external output(4)
5
6
7
8
tsu(AFSRX-ACLKRX)
th(ACLKRX-AFSRX)
tsu(AXR-ACLKRX)
th(ACLKRX-AXR)
ns
ns
ns
ns
(1) ACLKX0 internal – McASP0 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) P = SYSCLK2 period
(3) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
(4) McASP0 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX0
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Table 5-50. McASP0 Switching Characteristics(1)
PARAMETER
MIN
MAX
UNIT
Cycle time, AHCLKR0 internal, AHCLKR0 output
Cycle time, AHCLKR0 external, AHCLKR0 output
Cycle time, AHCLKX0 internal, AHCLKX0 output
Cycle time, AHCLKX0 external, AHCLKX0 output
Pulse duration, AHCLKR0 internal, AHCLKR0 output
Pulse duration, AHCLKR0 external, AHCLKR0 output
Pulse duration, AHCLKX0 internal, AHCLKX0 output
Pulse duration, AHCLKX0 external, AHCLKX0 output
Cycle time, ACLKR0 internal, ACLKR0 output
Cycle time, ACLKR0 external, ACLKR0 output
Cycle time, ACLKX0 internal, ACLKX0 output
Cycle time, ACLKX0 external, ACLKX0 output
Pulse duration, ACLKR0 internal, ACLKR0 output
Pulse duration, ACLKR0 external, ACLKR0 output
Pulse duration, ACLKX0 internal, ACLKX0 output
Pulse duration, ACLKX0 external, ACLKX0 output
Delay time, ACLKR0 internal, AFSR output(7)
Delay time, ACLKX0 internal, AFSX output
Delay time, ACLKR0 external input, AFSR output(7)
Delay time, ACLKX0 external input, AFSX output
Delay time, ACLKR0 external output, AFSR output(7)
Delay time, ACLKX0 external output, AFSX output
Delay time, ACLKX0 internal, AXR0[n] output
Delay time, ACLKX0 external input, AXR0[n] output
Delay time, ACLKX0 external output, AXR0[n] output
Disable time, ACLKX0 internal, AXR0[n] output
Disable time, ACLKX0 external input, AXR0[n] output
Disable time, ACLKX0 external output, AXR0[n] output
25
25
25
25
9
tc(AHCLKRX)
ns
(AHR/2) – 2.5(2)
(AHR/2) – 2.5(2)
(AHX/2) – 2.5(3)
(AHX/2) – 2.5(3)
10
11
12
tw(AHCLKRX)
tc(ACLKRX)
tw(ACLKRX)
ns
ns
ns
greater of 2P or 25(4)
greater of 2P or 25(4)
greater of 2P or 25(4)
greater of 2P or 25(4)
(AR/2) – 2.5(5)
(AR/2) – 2.5(5)
(AX/2) – 2.5(6)
(AX/2) – 2.5(6)
0
0
5.8
5.8
11.6
11.6
11.6
11.6
5.8
2.5
2.5
2.5
2.5
0
13
td(ACLKRX-AFSRX)
ns
14
15
td(ACLKX-AXRV)
2.5
2.5
0
11.6
11.6
5.8
ns
ns
tdis(ACLKX-AXRHZ)
3
11.6
11.6
3
(1) McASP0 ACLKX0 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKR0CTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) AHR - Cycle time, AHCLKR0.
(3) AHX - Cycle time, AHCLKX0.
(4) P = SYSCLK2 period
(5) AR - ACLKR0 period.
(6) AX - ACLKX0 period.
(7) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
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5.17.2.2 Multichannel Audio Serial Port 1 (McASP1) Timing
Table 5-51 and Table 5-52 assume testing over recommended operating conditions (see Figure 5-34 and
Figure 5-35).
Table 5-51. McASP1 Timing Requirements(1) (2)
No.
PARAMATER
MIN
MAX
UNIT
Cycle time, AHCLKR1 external, AHCLKR1 input
Cycle time, AHCLKX1 external, AHCLKX1 input
Pulse duration, AHCLKR1 external, AHCLKR1 input
Pulse duration, AHCLKX1 external, AHCLKX1 input
Cycle time, ACLKR1 external, ACLKR1 input
25
25
1
tc(AHCLKRX)
tw(AHCLKRX)
tc(ACLKRX)
tw(ACLKRX)
ns
12.5
12.5
2
3
4
ns
ns
ns
greater of 2P or 25
Cycle time, ACLKX1 external, ACLKX1 input
greater of 2P or 25
Pulse duration, ACLKR1 external, ACLKR1 input
Pulse duration, ACLKX1 external, ACLKX1 input
Setup time, AFSR1 input to ACLKR1 internal(3)
Setup time, AFSX1 input to ACLKX1 internal
12.5
12.5
10.4
10.4
2.6
Setup time, AFSR1 input to ACLKR1 external input(3)
Setup time, AFSX1 input to ACLKX1 external input
Setup time, AFSR1 input to ACLKR1 external output(3)
Setup time, AFSX1 input to ACLKX1 external output
Hold time, AFSR1 input after ACLKR1 internal(3)
Hold time, AFSX1 input after ACLKX1 internal
Hold time, AFSR1 input after ACLKR1 external input(3)
Hold time, AFSX1 input after ACLKX1 external input
Hold time, AFSR1 input after ACLKR1 external output(3)
Hold time, AFSX1 input after ACLKX1 external output
Setup time, AXR1[n] input to ACLKR1 internal(3)
Setup time, AXR1[n] input to ACLKX1 internal(4)
Setup time, AXR1[n] input to ACLKR1 external input(3)
Setup time, AXR1[n] input to ACLKX1 external input(4)
Setup time, AXR1[n] input to ACLKR1 external output(3)
Setup time, AXR1[n] input to ACLKX1 external output(4)
Hold time, AXR1[n] input after ACLKR1 internal(3)
Hold time, AXR1[n] input after ACLKX1 internal(4)
Hold time, AXR1[n] input after ACLKR1 external input(3)
Hold time, AXR1[n] input after ACLKX1 external input(4)
Hold time, AXR1[n] input after ACLKR1 external output(3)
Hold time, AXR1[n] input after ACLKX1 external output(4)
5
6
7
8
tsu(AFSRX-ACLKRX)
th(ACLKRX-AFSRX)
tsu(AXR-ACLKRX)
th(ACLKRX-AXR)
ns
ns
ns
ns
2.6
2.6
2.6
-1.9
-1.9
0.7
0.7
0.7
0.7
10.4
10.4
2.6
2.6
2.6
2.6
-1.8
-1.8
0.5
0.5
0.5
0.5
(1) ACLKX1 internal – McASP1 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX1 external input – McASP1 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX1 external output – McASP1 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR1 internal – McASP1 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR1 external input – McASP1 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR1 external output – McASP1 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) P = SYSCLK2 period
(3) McASP1 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR1
(4) McASP1 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX1
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Table 5-52. McASP1 Switching Characteristics(1)
PARAMETER
MIN
MAX
UNIT
Cycle time, AHCLKR1 internal, AHCLKR1 output
Cycle time, AHCLKR1 external, AHCLKR1 output
Cycle time, AHCLKX1 internal, AHCLKX1 output
Cycle time, AHCLKX1 external, AHCLKX1 output
Pulse duration, AHCLKR1 internal, AHCLKR1 output
Pulse duration, AHCLKR1 external, AHCLKR1 output
Pulse duration, AHCLKX1 internal, AHCLKX1 output
Pulse duration, AHCLKX1 external, AHCLKX1 output
Cycle time, ACLKR1 internal, ACLKR1 output
Cycle time, ACLKR1 external, ACLKR1 output
Cycle time, ACLKX1 internal, ACLKX1 output
Cycle time, ACLKX1 external, ACLKX1 output
Pulse duration, ACLKR1 internal, ACLKR1 output
Pulse duration, ACLKR1 external, ACLKR1 output
Pulse duration, ACLKX1 internal, ACLKX1 output
Pulse duration, ACLKX1 external, ACLKX1 output
Delay time, ACLKR1 internal, AFSR output(7)
Delay time, ACLKX1 internal, AFSX output
Delay time, ACLKR1 external input, AFSR output(7)
Delay time, ACLKX1 external input, AFSX output
Delay time, ACLKR1 external output, AFSR output(7)
Delay time, ACLKX1 external output, AFSX output
Delay time, ACLKX1 internal, AXR1[n] output
Delay time, ACLKX1 external input, AXR1[n] output
Delay time, ACLKX1 external output, AXR1[n] output
Disable time, ACLKX1 internal, AXR1[n] output
Disable time, ACLKX1 external input, AXR1[n] output
Disable time, ACLKX1 external output, AXR1[n] output
25
25
25
25
9
tc(AHCLKRX)
ns
(AHR/2) – 2.5(2)
(AHR/2) – 2.5(2)
(AHX/2) – 2.5(3)
(AHX/2) – 2.5(3)
10
11
12
tw(AHCLKRX)
tc(ACLKRX)
tw(ACLKRX)
ns
ns
ns
greater of 2P or 25(4)
greater of 2P or 25(4)
greater of 2P or 25(4)
greater of 2P or 25(4)
(AR/2) – 2.5(5)
(AR/2) – 2.5(5)
(AX/2) – 2.5(6)
(AX/2) – 2.5(6)
0.5
0.5
3.4
3.4
3.4
3.4
0.5
3.4
3.4
0.5
3.9
3.9
6.7
6.7
13.8
13.8
13.8
13.8
6.7
13
td(ACLKRX-AFSRX)
ns
14
15
td(ACLKX-AXRV)
13.8
13.8
6.7
ns
ns
tdis(ACLKX-AXRHZ)
13.8
13.8
(1) McASP1 ACLKX1 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
McASP1 ACLKX1 external input – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
McASP1 ACLKX1 external output – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
McASP1 ACLKR1 internal – ACLKR1CTL.CLKRM = 1, PDIR.ACLKR =1
McASP1 ACLKR1 external input – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
McASP1 ACLKR1 external output – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) AHR - Cycle time, AHCLKR1.
(3) AHX - Cycle time, AHCLKX1.
(4) P = SYSCLK2 period
(5) AR - ACLKR1 period.
(6) AX - ACLKX1 period.
(7) McASP1 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR1
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5.17.2.3 Multichannel Audio Serial Port 2 (McASP2) Timing
Table 5-53 and Table 5-54 assume testing over recommended operating conditions (see Figure 5-34 and
Figure 5-35).
Table 5-53. McASP2 Timing Requirements(1) (2)
NO.
MIN
MAX
UNIT
Cycle time, AHCLKR2 external, AHCLKR2 input
Cycle time, AHCLKX2 external, AHCLKX2 input
Pulse duration, AHCLKR2 external, AHCLKR2 input
Pulse duration, AHCLKX2 external, AHCLKX2 input
Cycle time, ACLKR2 external, ACLKR2 input
15
15
1
tc(AHCLKRX)
tw(AHCLKRX)
tc(ACLKRX)
tw(ACLKRX)
ns
7.5
7.5
2
3
4
ns
ns
ns
greater of 2P or 15
Cycle time, ACLKX2 external, ACLKX2 input
greater of 2P or 15
Pulse duration, ACLKR2 external, ACLKR2 input
Pulse duration, ACLKX2 external, ACLKX2 input
Setup time, AFSR2 input to ACLKR2 internal(3)
Setup time, AFSX2 input to ACLKX2 internal
7.5
7.5
10
10
Setup time, AFSR2 input to ACLKR2 external input(3)
Setup time, AFSX2 input to ACLKX2 external input
Setup time, AFSR2 input to ACLKR2 external output(3)
Setup time, AFSX2 input to ACLKX2 external output
Hold time, AFSR2 input after ACLKR2 internal(3)
Hold time, AFSX2 input after ACLKX2 internal
1.6
1.6
1.6
1.6
-1.7
-1.7
1.3
1.3
1.3
1.3
10
5
6
7
8
tsu(AFSRX-ACLKRX)
th(ACLKRX-AFSRX)
tsu(AXR-ACLKRX)
th(ACLKRX-AXR)
ns
ns
ns
ns
Hold time, AFSR2 input after ACLKR2 external input(3)
Hold time, AFSX2 input after ACLKX2 external input
Hold time, AFSR2 input after ACLKR2 external output(3)
Hold time, AFSX2 input after ACLKX2 external output
Setup time, AXR2[n] input to ACLKR2 internal(3)
Setup time, AXR2[n] input to ACLKX2 internal(4)
Setup time, AXR2[n] input to ACLKR2 external input(3)
Setup time, AXR2[n] input to ACLKX2 external input(4)
Setup time, AXR2[n] input to ACLKR2 external output(3)
Setup time, AXR2[n] input to ACLKX2 external output(4)
Hold time, AXR2[n] input after ACLKR2 internal(3)
Hold time, AXR2[n] input after ACLKX2 internal(4)
Hold time, AXR2[n] input after ACLKR2 external input(3)
Hold time, AXR2[n] input after ACLKX2 external input(4)
Hold time, AXR2[n] input after ACLKR2 external output(3)
Hold time, AXR2[n] input after ACLKX2 external output(4)
10
1.6
1.6
1.6
1.6
-1.7
-1.7
1.3
1.3
1.3
1.3
(1) ACLKX2 internal – McASP2 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX2 external input – McASP2 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX2 external output – McASP2 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR2 internal – McASP2 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR2 external input – McASP2 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR2 external output – McASP2 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) P = SYSCLK2 period
(3) McASP2 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR2
(4) McASP2 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX2
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Table 5-54. McASP2 Switching Characteristics(1)
PARAMETER
MIN
MAX
UNIT
Cycle time, AHCLKR2 internal, AHCLKR2 output
Cycle time, AHCLKR2 external, AHCLKR2 output
Cycle time, AHCLKX2 internal, AHCLKX2 output
Cycle time, AHCLKX2 external, AHCLKX2 output
Pulse duration, AHCLKR2 internal, AHCLKR2 output
Pulse duration, AHCLKR2 external, AHCLKR2 output
Pulse duration, AHCLKX2 internal, AHCLKX2 output
Pulse duration, AHCLKX2 external, AHCLKX2 output
Cycle time, ACLKR2 internal, ACLKR2 output
Cycle time, ACLKR2 external, ACLKR2 output
Cycle time, ACLKX2 internal, ACLKX2 output
Cycle time, ACLKX2 external, ACLKX2 output
Pulse duration, ACLKR2 internal, ACLKR2 output
Pulse duration, ACLKR2 external, ACLKR2 output
Pulse duration, ACLKX2 internal, ACLKX2 output
Pulse duration, ACLKX2 external, ACLKX2 output
Delay time, ACLKR2 internal, AFSR output(7)
Delay time, ACLKX2 internal, AFSX output
Delay time, ACLKR2 external input, AFSR output(7)
Delay time, ACLKX2 external input, AFSX output
Delay time, ACLKR2 external output, AFSR output(7)
Delay time, ACLKX2 external output, AFSX output
Delay time, ACLKX2 internal, AXR2[n] output
Delay time, ACLKX2 external input, AXR2[n] output
Delay time, ACLKX2 external output, AXR2[n] output
Disable time, ACLKX2 internal, AXR2[n] output
Disable time, ACLKX2 external input, AXR2[n] output
Disable time, ACLKX2 external output, AXR2[n] output
15
15
15
15
9
tc(AHCLKRX)
ns
(AHR/2) – 2.5(2)
(AHR/2) – 2.5(2)
(AHX/2) – 2.5(3)
(AHX/2) – 2.5(3)
10
11
12
tw(AHCLKRX)
tc(ACLKRX)
tw(ACLKRX)
ns
ns
ns
greater of 2P or 15(4)
greater of 2P or 15(4)
greater of 2P or 15(4)
greater of 2P or 15(4)
(AR/2) – 2.5(5)
(AR/2) – 2.5(5)
(AX/2) – 2.5(6)
(AX/2) – 2.5(6)
-1.4
-1.4
2.1
2.1
2.1
2.1
-1.4
2.1
2.1
-1.4
2.9
2.9
2.8
2.8
10
10
10
10
2.8
10
10
2.8
10
10
13
td(ACLKRX-AFSRX)
ns
14
15
td(ACLKX-AXRV)
ns
ns
tdis(ACLKX-AXRHZ)
(1) McASP2 ACLKX2 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
McASP2 ACLKX2 external input – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
McASP2 ACLKX2 external output – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
McASP2 ACLKR2 internal – ACLKR2CTL.CLKRM = 1, PDIR.ACLKR =1
McASP2 ACLKR2 external input – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
McASP2 ACLKR2 external output – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) AHR - Cycle time, AHCLKR2.
(3) AHX - Cycle time, AHCLKX2.
(4) P = SYSCLK2 period
(5) AR - ACLKR2 period.
(6) AX - ACLKX2 period.
(7) McASP2 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR2
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2
1
2
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
4
3
4
(A)
ACLKR/X (CLKRP = CLKXP = 0)
(B)
ACLKR/X (CLKRP = CLKXP = 1)
6
5
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
8
7
AXR[n] (Data In/Receive)
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
Figure 5-34. McASP Input Timings
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10
10
9
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
12
11
12
(A)
ACLKR/X (CLKRP = CLKXP = 1)
(B)
ACLKR/X (CLKRP = CLKXP = 0)
13
13
13
13
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
AXR[n] (Data Out/Transmit)
13
13
13
14
15
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
Figure 5-35. McASP Output Timings
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5.18 Serial Peripheral Interface Ports (SPI0, SPI1)
Figure 5-36 is a block diagram of the SPI module, which is a simple shift register and buffer plus control
logic. Data is written to the shift register before transmission occurs and is read from the buffer at the end
of transmission. The SPI can operate either as a master, in which case, it initiates a transfer and drives
the SPIx_CLK pin, or as a slave. Four clock phase and polarity options are supported as well as many
data formatting options.
SPIx_SIMO
SPIx_SOMI
Peripheral
16-Bit Shift Register
16-Bit Buffer
Configuration Bus
SPIx_ENA
SPIx_SCS
SPIx_CLK
State
Machine
GPIO
Control
(all pins)
Interrupt and
Clock
Control
DMA Requests
Figure 5-36. Block Diagram of SPI Module
The SPI supports 3-, 4-, and 5-pin operation with three basic pins (SPIx_CLK, SPIx_SIMO, and
SPIx_SOMI) and two optional pins (SPIx_SCS, SPIx_ENA).
The optional SPIx_SCS (Slave Chip Select) pin is most useful to enable in slave mode when there are
other slave devices on the same SPI port. The OMAP-L137 will only shift data and drive the SPIx_SOMI
pin when SPIx_SCS is held low.
In slave mode, SPIx_ENA is an optional output. The SPIx_ENA output provides the status of the internal
transmit buffer (SPIDAT0/1 registers). In four-pin mode with the enable option, SPIx_ENA is asserted only
when the transmit buffer is full, indicating that the slave is ready to begin another transfer. In five-pin
mode, the SPIx_ENA is additionally qualified by SPIx_SCS being asserted. This allows a single
handshake line to be shared by multiple slaves on the same SPI bus.
In master mode, the SPIx_ENA pin is an optional input and the master can be configured to delay the start
of the next transfer until the slave asserts SPIx_ENA. The addition of this handshake signal simplifies SPI
communications and, on average, increases SPI bus throughput since the master does not need to delay
each transfer long enough to allow for the worst-case latency of the slave device. Instead, each transfer
can begin as soon as both the master and slave have actually serviced the previous SPI transfer.
Although the SPI module supports two interrupt outputs, SPIx_INT1 is the only interrupt connected on this
device.
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Optional − Slave Chip Select
Optional Enable (Ready)
SPIx_SCS
SPIx_ENA
SPIx_CLK
SPIx_SOMI
SPIx_SIMO
SPIx_SCS
SPIx_ENA
SPIx_CLK
SPIx_SOMI
SPIx_SIMO
MASTER SPI
SLAVE SPI
Figure 5-37. Illustration of SPI Master-to-SPI Slave Connection
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5.18.1 SPI Peripheral Registers Description(s)
Table 5-55 is a list of the SPI registers.
Table 5-55. SPIx Configuration Registers
SPI0
BYTE ADDRESS
SPI1
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01C4 1000
0x01C4 1004
0x01C4 1008
0x01C4 100C
0x01C4 1010
0x01C4 1014
0x01C4 1018
0x01C4 101C
0x01C4 1020
0x01C4 1024
0x01C4 1028
0x01C4 102C
0x01C4 1030
0x01C4 1034
0x01C4 1038
0x01C4 103C
0x01C4 1040
0x01C4 1044
0x01C4 1048
0x01C4 104C
0x01C4 1050
0x01C4 1054
0x01C4 1058
0x01C4 105C
0x01C4 1060
0x01C4 1064
0x01E1 2000
0x01E1 2004
0x01E1 2008
0x01E1 200C
0x01E1 2010
0x01E1 2014
0x01E1 2018
0x01E1 201C
0x01E1 2020
0x01E1 2024
0x01E1 2028
0x01E1 202C
0x01E1 2030
0x01E1 2034
0x01E1 2038
0x01E1 203C
0x01E1 2040
0x01E1 2044
0x01E1 2048
0x01E1 204C
0x01E1 2050
0x01E1 2054
0x01E1 2058
0x01E1 205C
0x01E1 2060
0x01E1 2064
SPIGCR0
SPIGCR1
SPIINT0
SPILVL
Global Control Register 0
Global Control Register 1
Interrupt Register
Interrupt Level Register
SPIFLG
Flag Register
SPIPC0
Pin Control Register 0 (Pin Function)
Pin Control Register 1 (Pin Direction)
Pin Control Register 2 (Pin Data In)
Pin Control Register 3 (Pin Data Out)
Pin Control Register 4 (Pin Data Set)
Pin Control Register 5 (Pin Data Clear)
Reserved - Do not write to this register
Reserved - Do not write to this register
Reserved - Do not write to this register
Shift Register 0 (without format select)
Shift Register 1 (with format select)
Buffer Register
SPIPC1
SPIPC2
SPIPC3
SPIPC4
SPIPC5
Reserved
Reserved
Reserved
SPIDAT0
SPIDAT1
SPIBUF
SPIEMU
SPIDELAY
SPIDEF
Emulation Register
Delay Register
Default Chip Select Register
Format Register 0
SPIFMT0
SPIFMT1
SPIFMT2
SPIFMT3
Reserved
INTVEC1
Format Register 1
Format Register 2
Format Register 3
Reserved - Do not write to this register
Interrupt Vector for SPI INT1
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5.18.2 SPI Electrical Data/Timing
5.18.2.1 Serial Peripheral Interface (SPI) Timing
Table 5-56 through Table 5-71 assume testing over recommended operating conditions (see Figure 5-38
through Figure 5-41).
Table 5-56. General Timing Requirements for SPI0 Master Modes(1)
No.
1
PARAMETER
MIN
MAX
UNIT
ns
tc(SPC)M
Cycle Time, SPI0_CLK, All Master Modes
Pulse Width High, SPI0_CLK, All Master Modes
Pulse Width Low, SPI0_CLK, All Master Modes
greater of 3P or 20
0.5tc(SPC)M - 1
0.5tc(SPC)M - 1
256P
5
2
tw(SPCH)M
tw(SPCL)M
ns
3
ns
Polarity = 0, Phase = 0,
to SPI0_CLK rising
Polarity = 0, Phase = 1,
to SPI0_CLK rising
- 0.5tc(SPC)M + 5
Delay, initial data bit valid on
SPI0_SIMO after initial edge
on SPI0_CLK(2)
4
5
6
7
8
td(SIMO_SPC)M
td(SPC_SIMO)M
toh(SPC_SIMO)M
tsu(SOMI_SPC)M
tih(SPC_SOMI)M
ns
ns
ns
ns
ns
Polarity = 1, Phase = 0,
to SPI0_CLK falling
5
Polarity = 1, Phase = 1,
to SPI0_CLK falling
- 0.5tc(SPC)M + 5
Polarity = 0, Phase = 0,
from SPI0_CLK rising
5
5
5
5
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Delay, subsequent bits valid
on SPI0_SIMO after transmit
edge of SPI0_CLK
Polarity = 1, Phase = 0,
from SPI0_CLK falling
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M -3
Polarity = 0, Phase = 1,
from SPI0_CLK rising
0.5tc(SPC)M -3
Output hold time, SPI0_SIMO
valid after
receive edge of SPI0_CLK
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5tc(SPC)M -3
Polarity = 1, Phase = 1,
from SPI0_CLK falling
0.5tc(SPC)M -3
Polarity = 0, Phase = 0,
to SPI0_CLK falling
0
0
0
0
5
5
5
5
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Input Setup Time, SPI0_SOMI
valid before
receive edge of SPI0_CLK
Polarity = 1, Phase = 0,
to SPI0_CLK rising
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
from SPI0_CLK rising
Input Hold Time, SPI0_SOMI
valid after
receive edge of SPI0_CLK
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
(1) P = SYSCLK2 period
(2) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on
SPI0_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI0_SOMI.
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Table 5-57. General Timing Requirements for SPI0 Slave Modes(1)
No.
9
PARAMETER
MIN
MAX
UNIT
ns
tc(SPC)S
Cycle Time, SPI0_CLK, All Slave Modes
Pulse Width High, SPI0_CLK, All Slave Modes
Pulse Width Low, SPI0_CLK, All Slave Modes
greater of 3P or 40
10
11
tw(SPCH)S
tw(SPCL)S
18
18
ns
ns
Polarity = 0, Phase = 0,
to SPI0_CLK rising
2P
2P
2P
2P
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Setup time, transmit data written to
SPI before initial clock edge from
master.(2) (3)
12
13
14
15
16
tsu(SOMI_SPC)S
td(SPC_SOMI)S
toh(SPC_SOMI)S
tsu(SIMO_SPC)S
tih(SPC_SIMO)S
ns
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
from SPI0_CLK rising
18.5
Polarity = 0, Phase = 1,
from SPI0_CLK falling
18.5
18.5
18.5
Delay, subsequent bits valid on
SPI0_SOMI after transmit edge of
SPI0_CLK
ns
ns
ns
ns
Polarity = 1, Phase = 0,
from SPI0_CLK falling
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)S -3
Polarity = 0, Phase = 1,
from SPI0_CLK rising
0.5tc(SPC)S -3
Output hold time, SPI0_SOMI valid
after
receive edge of SPI0_CLK
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5tc(SPC)S -3
Polarity = 1, Phase = 1,
from SPI0_CLK falling
0.5tc(SPC)S -3
Polarity = 0, Phase = 0,
to SPI0_CLK falling
0
0
0
0
5
5
5
5
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Input Setup Time, SPI0_SIMO valid
before
receive edge of SPI0_CLK
Polarity = 1, Phase = 0,
to SPI0_CLK rising
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
from SPI0_CLK rising
Input Hold Time, SPI0_SIMO valid
after
receive edge of SPI0_CLK
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
(1) P = SYSCLK2 period
(2) First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on
SPI0_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI0_SIMO.
(3) Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus
cycles must be accounted for to allow data to be written to the SPI module by the DSP CPU.
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Table 5-58. Additional(1) SPI0 Master Timings, 4-Pin Enable Option(2) (3)
PARAMATER
MIN
MAX
UNIT
Polarity = 0, Phase = 0,
to SPI0_CLK rising
3P + 3.6
Polarity = 0, Phase = 1,
to SPI0_CLK rising
0.5tc(SPC)M + 3P + 3.6
3P + 3.6
Delay from slave assertion of
SPI0_ENA active to first SPI0_CLK
from master.(4)
17
td(ENA_SPC)M
ns
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5tc(SPC)M + 3P + 3.6
0.5tc(SPC)M + P + 5
P + 5
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Max delay for slave to deassert
SPI0_ENA after final SPI0_CLK edge
to ensure master does not begin the
next transfer.(5)
18
td(SPC_ENA)M
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5tc(SPC)M + P + 5
P + 5
Polarity = 1, Phase = 1,
from SPI0_CLK rising
(1) These parameters are in addition to the general timings for SPI master modes (Table 5-56).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI0_ENA assertion.
(5) In the case where the master SPI is ready with new data before SPI0_EN A deassertion.
Table 5-59. Additional(1) SPI0 Master Timings, 4-Pin Chip Select Option(2) (3)
No.
PARAMATER
MIN
MAX
UNIT
Polarity = 0, Phase = 0,
to SPI0_CLK rising
2P - 5
Polarity = 0, Phase = 1,
to SPI0_CLK rising
0.5tc(SPC)M + 2P - 5
2P - 5
Delay from SPI0_SCS active to first
SPI0_CLK(4) (5)
19
td(SCS_SPC)M
ns
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5tc(SPC)M + 2P - 5
0.5tc(SPC)M + P - 3
P - 3
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Delay from final SPI0_CLK edge to
master deasserting SPI0_SCS
20
td(SPC_SCS)M
ns
(6) (7)
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5tc(SPC)M + P - 3
P - 3
Polarity = 1, Phase = 1,
from SPI0_CLK rising
(1) These parameters are in addition to the general timings for SPI master modes (Table 5-56).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI0_SCS assertion.
(5) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(6) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain
asserted.
(7) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
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UNIT
Table 5-60. Additional(1) SPI0 Master Timings, 5-Pin Option(2) (3)
No.
PARAMATER
MIN
MAX
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M + P + 5
P + 5
Max delay for slave to
Polarity = 0, Phase = 1,
from SPI0_CLK falling
deassert SPI0_ENA after final
SPI0_CLK edge to ensure
master does not begin the
next transfer.(4)
18
td(SPC_ENA)M
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5tc(SPC)M + P + 5
P + 5
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M + P - 3
P - 3
0.5tc(SPC)M + P -3
P - 3
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Delay from final SPI0_CLK
edge to
20
21
22
td(SPC_SCS)M
td(SCSL_ENAL)M
td(SCS_SPC)M
ns
ns
ns
master deasserting
Polarity = 1, Phase = 0,
from SPI0_CLK rising
(5) (6)
SPI0_SCS
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Max delay for slave SPI to drive SPI0_ENA valid after
master asserts SPI0_SCS to delay the
master from beginning the next transfer,
C2TDELAY + P
Polarity = 0, Phase = 0,
to SPI0_CLK rising
2P -5
0.5tc(SPC)M + 2P -5
2P -5
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Delay from SPI0_SCS active
to first SPI0_CLK(7) (8) (9)
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5tc(SPC)M + 2P -5
Polarity = 0, Phase = 0,
to SPI0_CLK rising
3P + 3.6
0.5tc(SPC)M + 3P + 3.6
3P + 3.6
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Delay from assertion of
SPI0_ENA low to first
SPI0_CLK edge.(10)
23
td(ENA_SPC)M
ns
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5tc(SPC)M + 3P + 3.6
(1) These parameters are in addition to the general timings for SPI master modes (Table 5-57).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI0_ENA deassertion.
(5) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain
asserted.
(6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
(7) If SPI0_ENA is asserted immediately such that the transmission is not delayed by SPI0_ENA.
(8) In the case where the master SPI is ready with new data before SPI0_SCS assertion.
(9) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(10) If SPI0_ENA was initially deasserted high and SPI0_CLK is delayed.
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Table 5-61. Additional(1) SPI0 Slave Timings, 4-Pin Enable Option(2) (3)
PARAMATER
MIN
MAX
2.5 P + 18.5
– 0.5tc(SPC)M + 1.5 P -3 – 0.5tc(SPC)M + 2.5 P + 18.5
1.5 P -3 2.5 P + 18.5
– 0.5tc(SPC)M + 1.5 P -3 – 0.5tc(SPC)M + 2.5 P + 18.5
UNIT
Polarity = 0, Phase = 0,
from SPI0_CLK falling
1.5 P -3
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Delay from final
SPI0_CLK edge to
slave deasserting
SPI0_ENA.
24
td(SPC_ENAH)S
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
(1) These parameters are in addition to the general timings for SPI slave modes (Table 5-57).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
Table 5-62. Additional(1) SPI0 Slave Timings, 4-Pin Chip Select Option(2) (3)
No.
PARAMATER
MIN
MAX
UNIT
Required delay from SPI0_SCS asserted at slave to first
SPI0_CLK edge at slave.
25
td(SCSL_SPC)S
2P
ns
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M + P+5
P+5
Polarity = 0, Phase = 1,
Required delay from final
from SPI0_CLK falling
26
td(SPC_SCSH)S
SPI0_CLK edge before
ns
Polarity = 1, Phase = 0,
SPI0_SCS is deasserted.
0.5tc(SPC)M + P+5
P+5
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Delay from master asserting SPI0_SCS to slave driving
SPI0_SOMI valid
27
28
tena(SCSL_SOMI)S
tdis(SCSH_SOMI)S
P + 18.5
P + 18.5
ns
ns
Delay from master deasserting SPI0_SCS to slave 3-stating
SPI0_SOMI
(1) These parameters are in addition to the general timings for SPI slave modes (Table 5-57).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
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Table 5-63. Additional(1) SPI0 Slave Timings, 5-Pin Option(2) (3)
No.
PARAMATER
MIN
MAX
UNIT
Required delay from SPI0_SCS asserted at slave to first
SPI0_CLK edge at slave.
25
td(SCSL_SPC)S
2P
ns
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M + P +
5
Polarity = 0, Phase = 1,
from SPI0_CLK falling
P + 5
Required delay from final SPI0_CLK
edge before SPI0_SCS is
deasserted.
26
td(SPC_SCSH)S
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5tc(SPC)M + P +
5
Polarity = 1, Phase = 1,
from SPI0_CLK rising
P + 5
Delay from master asserting SPI0_SCS to slave driving
SPI0_SOMI valid
27
28
29
tena(SCSL_SOMI)S
tdis(SCSH_SOMI)S
tena(SCSL_ENA)S
P + 18.5
P + 18.5
ns
ns
ns
Delay from master deasserting SPI0_SCS to slave 3-stating
SPI0_SOMI
Delay from master deasserting SPI0_SCS to slave driving
SPI0_ENA valid
18.5
2.5 P + 18.5
2.5 P + 18.5
2.5 P + 18.5
2.5 P + 18.5
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
Delay from final clock receive edge
from SPI0_CLK rising
30
tdis(SPC_ENA)S
on SPI0_CLK to slave 3-stating or
ns
driving high SPI0_ENA.(4)
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
(1) These parameters are in addition to the general timings for SPI slave modes (Table 5-57).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
(4) SPI0_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is 3-
stated. If 3-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying
several SPI slave devices to a single master.
Table 5-64. General Timing Requirements for SPI1 Master Modes(1)
No.
1
PARAMATER
MIN
MAX
UNIT
256P ns
tc(SPC)M
Cycle Time, SPI1_CLK, All Master Modes
Pulse Width High, SPI1_CLK, All Master Modes
Pulse Width Low, SPI1_CLK, All Master Modes
greater of 3P or 20 ns
0.5tc(SPC)M - 1
2
tw(SPCH)M
tw(SPCL)M
ns
ns
3
0.5tc(SPC)M - 1
Polarity = 0, Phase =
0,
5
to SPI1_CLK rising
Polarity = 0, Phase =
1,
to SPI1_CLK rising
- 0.5tc(SPC)M + 5
Delay, initial data bit valid on
SPI1_SIMO to initial edge on
SPI1_CLK(2)
4
td(SIMO_SPC)M
ns
Polarity = 1, Phase =
0,
5
to SPI1_CLK falling
Polarity = 1, Phase =
1,
- 0.5tc(SPC)M + 5
to SPI1_CLK falling
(1) P = SYSCLK2 period
(2) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on
SPI1_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI1_SOMI.
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Table 5-64. General Timing Requirements for SPI1 Master Modes(1) (continued)
PARAMATER
MIN
MAX
UNIT
Polarity = 0, Phase =
0,
from SPI1_CLK rising
5
5
5
5
Polarity = 0, Phase =
1,
from SPI1_CLK falling
Delay, subsequent bits valid on
SPI1_SIMO after transmit edge of
SPI1_CLK
5
6
7
8
td(SPC_SIMO)M
ns
Polarity = 1, Phase =
0,
from SPI1_CLK falling
Polarity = 1, Phase =
1,
from SPI1_CLK rising
Polarity = 0, Phase =
0,
from SPI1_CLK falling
0.5tc(SPC)M -3
Polarity = 0, Phase =
1,
from SPI1_CLK rising
0.5tc(SPC)M -3
Output hold time, SPI1_SIMO valid
after
receive edge of SPI1_CLK
toh(SPC_SIMO)M
tsu(SOMI_SPC)M
tih(SPC_SOMI)M
ns
ns
ns
Polarity = 1, Phase =
0,
from SPI1_CLK rising
0.5tc(SPC)M -3
Polarity = 1, Phase =
1,
from SPI1_CLK falling
0.5tc(SPC)M -3
Polarity = 0, Phase =
0,
to SPI1_CLK falling
0
0
0
0
5
5
5
5
Polarity = 0, Phase =
1,
to SPI1_CLK rising
Input Setup Time, SPI1_SOMI valid
before
receive edge of SPI1_CLK
Polarity = 1, Phase =
0,
to SPI1_CLK rising
Polarity = 1, Phase =
1,
to SPI1_CLK falling
Polarity = 0, Phase =
0,
from SPI1_CLK falling
Polarity = 0, Phase =
1,
from SPI1_CLK rising
Input Hold Time, SPI1_SOMI valid
after
receive edge of SPI1_CLK
Polarity = 1, Phase =
0,
from SPI1_CLK rising
Polarity = 1, Phase =
1,
from SPI1_CLK falling
Table 5-65. General Timing Requirements for SPI1 Slave Modes(1)
No.
9
PARAMATER
MIN
MAX
UNIT
ns
tc(SPC)S
Cycle Time, SPI1_CLK, All Slave Modes
Pulse Width High, SPI1_CLK, All Slave Modes
Pulse Width Low, SPI1_CLK, All Slave Modes
greater of 3P or 40 ns
10
11
tw(SPCH)S
tw(SPCL)S
18
18
ns
ns
(1) P = SYSCLK2 period
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UNIT
Table 5-65. General Timing Requirements for SPI1 Slave Modes(1) (continued)
No.
PARAMATER
MIN
MAX
Polarity = 0, Phase = 0,
to SPI1_CLK rising
2P
2P
2P
2P
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Setup time, transmit data written to
SPI before initial clock edge from
master.(2) (3)
12
tsu(SOMI_SPC)S
td(SPC_SOMI)S
toh(SPC_SOMI)S
tsu(SIMO_SPC)S
tih(SPC_SIMO)S
ns
Polarity = 1, Phase = 0,
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
Polarity = 0, Phase = 0,
from SPI1_CLK rising
19
Polarity = 0, Phase = 1,
from SPI1_CLK falling
19
ns
19
Delay, subsequent bits valid on
SPI1_SOMI after transmit edge of
SPI1_CLK
13
14
15
16
Polarity = 1, Phase = 0,
from SPI1_CLK falling
Polarity = 1, Phase = 1,
from SPI1_CLK rising
19
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)S -3
Polarity = 0, Phase = 1,
from SPI1_CLK rising
0.5tc(SPC)S -3
Output hold time, SPI1_SOMI valid
after
receive edge of SPI1_CLK
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5tc(SPC)S -3
Polarity = 1, Phase = 1,
from SPI1_CLK falling
0.5tc(SPC)S -3
Polarity = 0, Phase = 0,
to SPI1_CLK falling
0
0
0
0
5
5
5
5
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Input Setup Time, SPI1_SIMO valid
before
receive edge of SPI1_CLK
ns
Polarity = 1, Phase = 0,
to SPI1_CLK rising
Polarity = 1, Phase = 1,
to SPI1_CLK falling
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Polarity = 0, Phase = 1,
from SPI1_CLK rising
Input Hold Time, SPI1_SIMO valid
after
receive edge of SPI1_CLK
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK falling
(2) First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on
SPI1_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI1_SIMO.
(3) Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus
cycles must be accounted for to allow data to be written to the SPI module by the DSP CPU.
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Table 5-66. Additional(1) SPI1 Master Timings, 4-Pin Enable Option(2) (3)
PARAMETER
MIN
MAX
UNIT
Polarity = 0, Phase = 0,
to SPI1_CLK rising
3P + 3
Polarity = 0, Phase = 1,
to SPI1_CLK rising
0.5tc(SPC)M + 3P + 3
3P + 3
Delay from slave assertion of
SPI1_ENA active to first SPI1_CLK
from master.(4)
17
td(EN A_SPC)M
ns
Polarity = 1, Phase = 0,
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5tc(SPC)M + 3P + 3
0.5tc(SPC)M + P + 5
P + 5
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Max delay for slave to deassert
SPI1_ENA after final SPI1_CLK edge
to ensure master does not begin the
next transfer.(5)
18
td(SPC_ENA)M
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5tc(SPC)M + P + 5
P + 5
Polarity = 1, Phase = 1,
from SPI1_CLK rising
(1) These parameters are in addition to the general timings for SPI master modes (Table 5-64).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI1_ENA assertion.
(5) In the case where the master SPI is ready with new data before SPI1_ENA deassertion.
Table 5-67. Additional(1) SPI1 Master Timings, 4-Pin Chip Select Option(2) (3)
No.
PARAMATER
MIN
MAX
UNIT
Polarity = 0, Phase = 0,
to SPI1_CLK rising
2P -5
Polarity = 0, Phase = 1,
to SPI1_CLK rising
0.5tc(SPC)M + 2P -5
2P -5
Delay from SPI1_SCS active to first
SPI1_CLK(4) (5)
19
td(SCS_SPC)M
ns
Polarity = 1, Phase = 0,
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5tc(SPC)M + 2P -5
0.5tc(SPC)M + P - 3
P - 3
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Delay from final SPI1_CLK edge to
master deasserting SPI1_SCS
20
td(SPC_SCS)M
ns
(6) (7)
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5tc(SPC)M + P -3
P - 3
Polarity = 1, Phase = 1,
from SPI1_CLK rising
(1) These parameters are in addition to the general timings for SPI master modes (Table 5-64).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI1_SCS assertion.
(5) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(6) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain
asserted.
(7) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
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UNIT
Table 5-68. Additional(1) SPI1 Master Timings, 5-Pin Option(2) (3)
No.
PARAMATER
MIN
MAX
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)M+P+5
P+5
Max delay for slave to
Polarity = 0, Phase = 1,
from SPI1_CLK falling
deassert SPI1_ENA after final
SPI1_CLK edge to ensure
master does not begin the
next transfer.(4)
18
td(SPC_ENA)M
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5tc(SPC)M+P+5
P+5
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)M + P -3
P - 3
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Delay from final SPI1_CLK
edge to
20
21
22
td(SPC_SCS)M
td(SCSL_ENAL)M
td(SCS_SPC)M
ns
ns
ns
master deasserting
Polarity = 1, Phase = 0,
from SPI1_CLK rising
(5) (6)
0.5tc(SPC)M+ P -3
P - 3
SPI1_SCS
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Max delay for slave SPI to drive SPI1_ENA valid after
master asserts SPI1_SCS to delay the
master from beginning the next transfer,
C2TDELAY + P
Polarity = 0, Phase = 0,
to SPI1_CLK rising
2P -5
0.5tc(SPC)M + 2P -5
2P -5
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Delay from SPI1_SCS active
to first SPI1_CLK(7) (8) (9)
Polarity = 1, Phase = 0,
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5tc(SPC)M + 2P -5
Polarity = 0, Phase = 0,
to SPI1_CLK rising
3P + 3
0.5tc(SPC)M + 3P + 3
3P + 3
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Delay from assertion of
SPI1_ENA low to first
SPI1_CLK edge.(10)
23
td(ENA_SPC)M
ns
Polarity = 1, Phase = 0,
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5tc(SPC)M + 3P + 3
(1) These parameters are in addition to the general timings for SPI master modes (Table 5-65).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI1_ENA deassertion.
(5) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain
asserted.
(6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
(7) If SPI1_ENA is asserted immediately such that the transmission is not delayed by SPI1_ENA.
(8) In the case where the master SPI is ready with new data before SPI1_SCS assertion.
(9) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(10) If SPI1_ENA was initially deasserted high and SPI1_CLK is delayed.
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Table 5-69. Additional(1) SPI1 Slave Timings, 4-Pin Enable Option(2) (3)
PARAMETER
MIN
MAX
UNIT
Polarity = 0, Phase = 0,
from SPI1_CLK falling
1.5 P -3
2.5 P + 19
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Delay from final
– 0.5tc(SPC)M + 1.5 P -3
1.5 P -3
– 0.5tc(SPC)M + 2.5 P + 19
2.5 P + 19
SPI1_CLK edge to
slave deasserting
SPI1_ENA.
24
td(SPC_ENAH)S
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
– 0.5tc(SPC)M + 1.5 P -3
– 0.5tc(SPC)M + 2.5 P + 19
(1) These parameters are in addition to the general timings for SPI slave modes (Table 5-65).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
Table 5-70. Additional(1) SPI1 Slave Timings, 4-Pin Chip Select Option(2) (3)
No.
PARAMETER
MIN
MAX
UNIT
Required delay from SPI1_SCS asserted at slave to first
SPI1_CLK edge at slave.
25
td(SCSL_SPC)S
2P
ns
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)M + P + 5
P + 5
Polarity = 0, Phase = 1,
Required delay from final
from SPI1_CLK falling
26
td(SPC_SCSH)S
SPI1_CLK edge before
ns
Polarity = 1, Phase = 0,
SPI1_SCS is deasserted.
0.5tc(SPC)M + P + 5
P + 5
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Delay from master asserting SPI1_SCS to slave driving
SPI1_SOMI valid
27
28
tena(SCSL_SOMI)S
tdis(SCSH_SOMI)S
P + 19
ns
ns
Delay from master deasserting SPI1_SCS to slave 3-stating
SPI1_SOMI
P + 19
(1) These parameters are in addition to the general timings for SPI slave modes (Table 5-65).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
Table 5-71. Additional(1) SPI1 Slave Timings, 5-Pin Option(2) (3)
No.
PARAMETER
MIN
MAX
UNIT
Required delay from SPI1_SCS asserted at slave to first
SPI1_CLK edge at slave.
25
td(SCSL_SPC)S
2P
ns
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)M + P +
5
Polarity = 0, Phase = 1,
from SPI1_CLK falling
P + 5
Required delay from final SPI1_CLK
edge before SPI1_SCS is
deasserted.
26
td(SPC_SCSH)S
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5tc(SPC)M + P +
5
Polarity = 1, Phase = 1,
from SPI1_CLK rising
P + 5
Delay from master asserting SPI1_SCS to slave driving
SPI1_SOMI valid
27
28
29
tena(SCSL_SOMI)S
tdis(SCSH_SOMI)S
tena(SCSL_ENA)S
P + 19
P + 19
19
ns
ns
ns
Delay from master deasserting SPI1_SCS to slave 3-stating
SPI1_SOMI
Delay from master deasserting SPI1_SCS to slave driving
SPI1_ENA valid
(1) These parameters are in addition to the general timings for SPI slave modes (Table 5-65).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
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UNIT
Table 5-71. Additional(1) SPI1 Slave Timings, 5-Pin Option(2) (3) (continued)
No.
PARAMETER
MIN
MAX
Polarity = 0, Phase = 0,
from SPI1_CLK falling
2.5 P + 19
2.5 P + 19
2.5 P + 19
2.5 P + 19
Polarity = 0, Phase = 1,
from SPI1_CLK rising
Delay from final clock receive edge
on SPI1_CLK to slave 3-stating or
driving high SPI1_ENA.(4)
30
tdis(SPC_ENA)S
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK falling
(4) SPI1_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is 3-
stated. If 3-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying
several SPI slave devices to a single master.
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1
MASTER MODE
POLARITY = 0 PHASE = 0
2
3
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
5
4
6
MO(0)
7
MO(1)
MO(n−1)
MO(n)
MI(n)
8
MI(0)
MI(1)
MI(n−1)
MASTER MODE
POLARITY = 0 PHASE = 1
4
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
6
5
MO(0)
7
MO(1)
MI(1)
MO(n−1)
MI(n−1)
MO(n)
MI(n)
8
MI(0)
4
MASTER MODE
POLARITY = 1 PHASE = 0
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
5
6
MO(0)
7
MO(1)
MI(1)
MO(n−1)
MO(n)
MI(n)
8
MI(0)
MI(n−1)
MASTER MODE
POLARITY = 1 PHASE = 1
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
5
4
6
MO(0)
7
MO(1)
MI(1)
MO(n−1)
MI(n−1)
MO(n)
MI(n)
8
MI(0)
Figure 5-38. SPI Timings—Master Mode
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9
SLAVE MODE
POLARITY = 0 PHASE = 0
12
10
15
11
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
16
SI(0)
SI(1)
13
SI(n−1)
SI(n)
14
SO(0)
SO(1)
SO(n−1)
SO(n)
12
SLAVE MODE
POLARITY = 0 PHASE = 1
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
15
SI(0)
16
SI(1)
SI(n−1)
SI(n)
13
SO(1)
14
SO(0)
SO(n−1)
SO(n)
SLAVE MODE
POLARITY = 1 PHASE = 0
12
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
15
16
SI(0)
SI(1)
SI(n−1)
SI(n)
13
SO(1)
14
SO(n−1)
SO(0)
SO(n)
SLAVE MODE
POLARITY = 1 PHASE = 1
12
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
15
16
SI(0)
SI(1)
SI(n−1)
SI(n)
13
SO(1)
14
SO(0)
SO(n−1)
SO(n)
Figure 5-39. SPI Timings—Slave Mode
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MASTER MODE 4 PIN WITH ENABLE
17
18
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
SPIx_ENA
MO(0)
MI(0)
MO(n)
MI(n)
MO(n−1)
MI(n−1)
MO(1)
MI(1)
MASTER MODE 4 PIN WITH CHIP SELECT
19
20
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
SPIx_SCS
MO(0)
MO(n)
MI(n)
MO(n−1)
MI(n−1)
MO(1)
MI(1)
MI(0)
MASTER MODE 5 PIN
23
22
20
MO(1)
18
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
MO(0)
MO(n−1)
MO(n)
MI(0)
MI(1)
MI(n−1)
MI(n)
21
(A)
(A)
SPIx_ENA
SPIx_SCS
DESEL
DESEL
A. DESELECTED IS PROGRAMMABLE EITHER HIGH OR
3−STATE (REQUIRES EXTERNAL PULLUP)
Figure 5-40. SPI Timings—Master Mode (4-Pin and 5-Pin)
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SLAVE MODE 4 PIN WITH ENABLE
24
SPIx_CLK
SPIx_SOMI
SPIx_SIMO
SPIx_ENA
SO(0)
SI(0)
SO(1)
SO(n−1) SO(n)
SI(n−1) SI(n)
SI(1)
SLAVE MODE 4 PIN WITH CHIP SELECT
25
26
SPIx_CLK
27
28
SO(n−1)
SPIx_SOMI
SPIx_SIMO
SPIx_SCS
SO(0)
SO(1)
SO(n)
SI(0)
SI(1)
SI(n−1)
SI(n)
SLAVE MODE 5 PIN
25
26
30
SPIx_CLK
27
29
28
SO(1)
SPIx_SOMI
SPIx_SIMO
SO(0)
SI(0)
SO(n−1)
SO(n)
SI(1)
SI(n−1) SI(n)
SPIx_ENA
SPIx_SCS
(A)
(A)
DESEL
DESEL
A. DESELECTED IS PROGRAMMABLE EITHER HIGH OR
3−STATE (REQUIRES EXTERNAL PULLUP)
Figure 5-41. SPI Timings—Slave Mode (4-Pin and 5-Pin)
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5.19 Enhanced Capture (eCAP) Peripheral
The OMAP-L137 device contains up to three enhanced capture (eCAP) modules. Figure 5-42 shows a
functional block diagram of a module. See the OMAP-L137 Applications Processor DSP Peripherals
Overview Reference Guide. (SPRUGA6) for more details.
Uses for ECAP include:
•
•
•
•
Speed measurements of rotating machinery (e.g. toothed sprockets sensed via Hall sensors)
Elapsed time measurements between position sensor triggers
Period and duty cycle measurements of Pulse train signals
Decoding current or voltage amplitude derived from cuty cycle encoded current/voltage sensors
The ECAP module described in this specification includes the following features:
•
•
•
•
•
•
•
•
•
32 bit time base
4 event time-stamp registers (each 32 bits)
Edge polarity selection for up to 4 sequenced time-stamp capture events
Interrupt on either of the 4 events
Single shot capture of up to 4 event time-stamps
Continuous mode capture of time-stamps in a 4 deep circular buffer
Absolute time-stamp capture
Difference mode time-stamp capture
All the above resources are dedicated to a single input pin
The eCAP modules are clocked at the SYSCLK2 rate.
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CTRPHS
(phase register−32 bit)
SYNCIn
APWM mode
CTR_OVF
OVF
CTR [0−31]
PRD [0−31]
CMP [0−31]
TSCTR
(counter−32 bit)
RST
SYNCOut
PWM
compare
logic
Delta−mode
32
CTR=PRD
CTR=CMP
CTR [0−31]
32
PRD [0−31]
eCAPx
32
LD1
CAP1
(APRD active)
Polarity
select
LD
APRD
shadow
32
CMP [0−31]
32
32
LD2
Polarity
select
CAP2
(ACMP active)
LD
Event
qualifier
32
Event
Pre-scale
ACMP
shadow
Polarity
select
32
32
CAP3
(APRD shadow)
LD3
LD4
LD
CAP4
(ACMP shadow)
Polarity
select
LD
4
Capture events
4
CEVT[1:4]
Interrupt
Trigger
and
Flag
control
Continuous /
Oneshot
Capture Control
to Interrupt
Controller
CTR_OVF
CTR=PRD
CTR=CMP
Figure 5-42. eCAP Functional Block Diagram
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Table 5-72 is the list of the ECAP registers.
Table 5-72. ECAPx Configuration Registers
ECAP0
ECAP1
BYTE ADDRESS
ECAP2
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
Time-Stamp Counter
BYTE ADDRESS
0x01F0 6000
0x01F0 6004
0x01F0 6008
0x01F0 600C
0x01F0 6010
0x01F0 6014
0x01F0 6028
0x01F0 602A
0x01F0 602C
0x01F0 602E
0x01F0 6030
0x01F0 6032
0x01F0 605C
0x01F0 7000
0x01F0 7004
0x01F0 7008
0x01F0 700C
0x01F0 7010
0x01F0 7014
0x01F0 7028
0x01F0 702A
0x01F0 702C
0x01F0 702E
0x01F0 7030
0x01F0 7032
0x01F0 705C
0x01F0 8000
0x01F0 8004
0x01F0 8008
0x01F0 800C
0x01F0 8010
0x01F0 8014
0x01F0 8028
0x01F0 802A
0x01F0 802C
0x01F0 802E
0x01F0 8030
0x01F0 8032
0x01F0 805C
TSCTR
CTRPHS
CAP1
Counter Phase Offset Value Register
Capture 1 Register
CAP2
Capture 2 Register
CAP3
Capture 3 Register
CAP4
Capture 4 Register
ECCTL1
ECCTL2
ECEINT
ECFLG
ECCLR
ECFRC
REVID
Capture Control Register 1
Capture Control Register 2
Capture Interrupt Enable Register
Capture Interrupt Flag Register
Capture Interrupt Clear Register
Capture Interrupt Force Register
Revision ID
Table 5-73 shows the eCAP timing requirement and Table 5-74 shows the eCAP switching characteristics.
Table 5-73. Enhanced Capture (eCAP) Timing Requirement
PARAMETER
TEST CONDITIONS
Asynchronous
Synchronous
MIN
MAX
MAX
UNIT
cycles
cycles
tw(CAP)
Capture input pulse width
2tc(SCO)
2tc(SCO)
Table 5-74. eCAP Switching Characteristics
PARAMETER
Pulse duration, APWMx output high/low
TEST CONDITIONS
MIN
UNIT
tw(APWM)
20
ns
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5.20 Enhanced Quadrature Encoder (eQEP) Peripheral
The OMAP-L137 device contains up to two enhanced quadrature encoder (eQEP) modules. See the
OMAP-L137 Applications Processor DSP Peripherals Overview Reference Guide. (SPRUGA6) for more
details.
System
control registers
To CPU
EQEPxENCLK
SYSCLK2
QCPRD
QCAPCTL
16
QCTMR
16
16
Quadrature
capture unit
(QCAP)
QCTMRLAT
QCPRDLAT
QUTMR
QUPRD
QWDTMR
QWDPRD
Registers
used by
multiple units
32
16
QEPCTL
QEPSTS
QFLG
UTOUT
UTIME
QWDOG
QDECCTL
16
WDTOUT
EQEPxAIN
EQEPxBIN
EQEPxIIN
EQEPxINT
16
EQEPxA/XCLK
EQEPxB/XDIR
EQEPxI
QCLK
QDIR
QI
QS
Position counter/
control unit
(PCCU)
EQEPxIOUT
EQEPxIOE
EQEPxSIN
EQEPxSOUT
EQEPxSOE
Quadrature
decoder
(QDU)
GPIO
MUX
QPOSLAT
QPOSSLAT
QPOSILAT
PHE
PCSOUT
EQEPxS
32
32
16
QPOSCNT
QPOSINIT
QPOSMAX
QEINT
QFRC
QPOSCMP
QCLR
QPOSCTL
Enhanced QEP (eQEP) Peripheral
Figure 5-43. eQEP Functional Block Diagram
Table 5-75 is the list of the EQEP registers.
Table 5-76 shows the eQEP timing requirement and Table 5-77 shows the eQEP switching
characteristics.
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Table 5-75. EQEP Registers
EQEP0
EQEP1
BYTE ADDRESS
0x01F0 9000
0x01F0 9004
0x01F0 9008
0x01F0 900C
0x01F0 9010
0x01F0 9014
0x01F0 9018
0x01F0 901C
0x01F0 9020
0x01F0 9024
0x01F0 9026
0x01F0 9028
0x01F0 902A
0x01F0 902C
0x01F0 902E
0x01F0 9030
0x01F0 9032
0x01F0 9034
0x01F0 9036
0x01F0 9038
0x01F0 903A
0x01F0 903C
0x01F0 903E
0x01F0 9040
0x01F0 905C
BYTE ADDRESS
ACRONYM
QPOSCNT
QPOSINIT
QPOSMAX
QPOSCMP
QPOSILAT
QPOSSLAT
QPOSLAT
QUTMR
REGISTER DESCRIPTION
eQEP Position Counter
0x01F0 A000
0x01F0 A004
0x01F0 A008
0x01F0 A00C
0x01F0 A010
0x01F0 A014
0x01F0 A018
0x01F0 A01C
0x01F0 A020
0x01F0 A024
0x01F0 A026
0x01F0 A028
0x01F0 A02A
0x01F0 A02C
0x01F0 A02E
0x01F0 A030
0x01F0 A032
0x01F0 A034
0x01F0 A036
0x01F0 A038
0x01F0 A03A
0x01F0 A03C
0x01F0 A03E
0x01F0 A040
0x01F0 A05C
eQEP Initialization Position Count
eQEP Maximum Position Count
eQEP Position-compare
eQEP Index Position Latch
eQEP Strobe Position Latch
eQEP Position Latch
eQEP Unit Timer
QUPRD
eQEP Unit Period Register
eQEP Watchdog Timer
QWDTMR
QWDPRD
QDECCTL
QEPCTL
QCAPCTL
QPOSCTL
QEINT
eQEP Watchdog Period Register
eQEP Decoder Control Register
eQEP Control Register
eQEP Capture Control Register
eQEP Position-compare Control Register
eQEP Interrupt Enable Register
eQEP Interrupt Flag Register
eQEP Interrupt Clear Register
eQEP Interrupt Force Register
eQEP Status Register
QFLG
QCLR
QFRC
QEPSTS
QCTMR
eQEP Capture Timer
QCPRD
eQEP Capture Period Register
eQEP Capture Timer Latch
eQEP Capture Period Latch
eQEP Revision ID
QCTMRLAT
QCPRDLAT
REVID
Table 5-76. Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
PARAMETER
TEST CONDITIONS
Asynchronous/synchronous
Asynchronous/synchronous
Asynchronous/synchronous
Asynchronous/synchronous
Asynchronous/synchronous
MIN
MAX
UNIT
cycles
cycles
cycles
cycles
cycles
tw(QEPP)
QEP input period
2tc(SCO)
2tc(SCO)
2tc(SCO)
2tc(SCO)
2tc(SCO)
tw(INDEXH)
tw(INDEXL)
tw(STROBH)
tw(STROBL)
QEP Index Input High time
QEP Index Input Low time
QEP Strobe High time
QEP Strobe Input Low time
Table 5-77. eQEP Switching Characteristics
PARAMETER
MIN
MAX
UNIT
cycles
cycles
td(CNTR)xin
Delay time, external clock to counter increment
Delay time, QEP input edge to position compare sync output
4tc(SCO)
6tc(SCO)
td(PCS-OUT)QEP
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5.21 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
The OMAP-L137 device contains up to three enhanced PWM Modules (eHRPWM). Figure 5-44 shows a
block diagram of multiple eHRPWM modules. Figure 4-4 shows the signal interconnections with the
eHRPWM. See the OMAP-L137 Applications Processor DSP Peripherals Overview Reference Guide.
(SPRUGA6) for more details.
EPWMSYNCI
EPWM0SYNCI
EPWM0INT
EPWM0A
EPWM0B
eHRPWM0 module
EPWMTZ
EPWM0SYNCO
EPWM1SYNCI
Interrupt
Controllers
EPWM1INT
EPWM1A
EPWM1B
EPWMTZ
GPIO
MUX
eHRPWM1 module
EPWM1SYNCO
EPWM2SYNCI
EPWM2INT
EPWM2A
EPWM2B
eHRPWM2 module
EPWMTZ
EPWM2SYNCO
To eCAP0
module
(sync in)
EPWMSYNCO
Peripheral Bus
Figure 5-44. Multiple PWM Modules in a OMAP-L137 System
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Time−base (TB)
Sync
in/out
CTR=ZERO
CTR=CMPB
Disabled
TBPRD shadow (16)
TBPRD active (16)
EPWMSYNCO
control
Mux
CTR=PRD
TBCTL[SYNCOSEL]
TBCTL[CNTLDE]
EPWMSYNCI
TBCTL[SWFSYNC]
(software forced sync)
Counter
up/down
(16 bit)
CTR=ZERO
CTR_Dir
TBCNT
active (16)
TBPHSHR (8)
16
8
CTR = PRD
CTR = ZERO
Phase
control
Event
trigger
and
interrupt
(ET)
TBPHS active (24)
EPWMxINT
CTR = CMPA
CTR = CMPB
CTR_Dir
Counter compare (CC)
CTR=CMPA
CMPAHR (8)
Action
qualifier
(AQ)
16
8
HiRes PWM (HRPWM)
CMPA active (24)
EPWMA
EPWMB
EPWMxA
CMPA shadow (24)
CTR=CMPB
Dead
band
(DB)
PWM
chopper
(PC)
Trip
zone
(TZ)
16
EPWMxB
EPWMxTZINT
TZ
CMPB active (16)
CMPB shadow (16)
CTR = ZERO
Figure 5-45. eHRPWM Sub-Modules Showing Critical Internal Signal Interconnections
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Table 5-78. eHRPWM Module Control and Status Registers Grouped by Submodule
eHRPWM0
BYTE
ADDRESS
eHRPWM1
BYTE
ADDRESS
eHRPWM2
BYTE
ADDRESS
SIZE
(×16) SHADOW
ACRONYM
REGISTER DESCRIPTION
TIME-BASE SUBMODULE REGISTERS
0x01F0 0000 0x01F0 2000 0x01F0 4000
0x01F0 0002 0x01F0 2002 0x01F0 4002
0x01F0 0004 0x01F0 2004 0x01F0 4004
0x01F0 0006 0x01F0 2006 0x01F0 4006
0x01F0 0008 0x01F0 2008 0x01F0 4008
0x01F0 000A 0x01F0 200A 0x01F0 400A
TBCTL
TBSTS
1
1
1
1
1
1
No
No
No
No
No
Yes
Time-Base Control Register
Time-Base Status Register
Extension for HRPWM Phase Register
Time-Base Phase Register
Time-Base Counter Register
Time-Base Period Register
(1)
TBPHSHR
TBPHS
TBCNT
TBPRD
COUNTER-COMPARE SUBMODULE REGISTERS
0x01F0 000E 0x01F0 200E 0x01F0 400E
0x01F0 0010 0x01F0 2010 0x01F0 4010
0x01F0 0012 0x01F0 2012 0x01F0 4012
0x01F0 0014 0x01F0 2014 0x01F0 4014
CMPCTL
CMPAHR
CMPA
1
1
1
1
No
No
Counter-Compare Control Register
(1)
Extension for HRPWM Counter-Compare A Register
Counter-Compare A Register
Yes
Yes
CMPB
Counter-Compare B Register
ACTION-QUALIFIER SUBMODULE REGISTERS
0x01F0 0016 0x01F0 2016 0x01F0 4016
0x01F0 0018 0x01F0 2018 0x01F0 4018
AQCTLA
1
No
Action-Qualifier Control Register for Output A
(eHRPWMxA)
AQCTLB
1
No
Action-Qualifier Control Register for Output B
(eHRPWMxB)
0x01F0 001A 0x01F0 201A 0x01F0 401A
0x01F0 001C 0x01F0 201C 0x01F0 401C
AQSFRC
1
1
No
Action-Qualifier Software Force Register
AQCSFRC
Yes
Action-Qualifier Continuous S/W Force Register Set
DEAD-BAND GENERATOR SUBMODULE REGISTER
0x01F0 001E 0x01F0 201E 0x01F0 401E
0x01F0 0020 0x01F0 2020 0x01F0 4020
DBCTL
DBRED
1
1
No
No
Dead-Band Generator Control Register
Dead-Band Generator Rising Edge Delay Count
Register
0x01F0 0022 0x01F0 2022 0x01F0 4022
0x01F0 003C 0x01F0 203C 0x01F0 403C
DBFED
1
No
Dead-Band Generator Falling Edge Delay Count
Register
PWM-CHOPPER SUBMODULE REGISTERS
PCCTL No PWM-Chopper Control Register
TRIP-ZONE SUBMODULE REGISTERS
1
0x01F0 0024 0x01F0 2024 0x01F0 4024
0x01F0 0028 0x01F0 2028 0x01F0 4028
0x01F0 002A 0x01F0 202A 0x01F0 402A
0x01F0 002C 0x01F0 202C 0x01F0 402C
0x01F0 002E 0x01F0 202E 0x01F0 402E
0x01F0 0030 0x01F0 2030 0x01F0 4030
TZSEL
TZCTL
TZEINT
TZFLG
TZCLR
TZFRC
1
1
1
1
1
1
No
No
No
No
No
No
Trip-Zone Select Register
Trip-Zone Control Register
Trip-Zone Enable Interrupt Register
Trip-Zone Flag Register
Trip-Zone Clear Register
Trip-Zone Force Register
EVENT-TRIGGER SUBMODULE REGISTERS
0x01F0 0032 0x01F0 2032 0x01F0 4032
0x01F0 0034 0x01F0 2034 0x01F0 4034
0x01F0 0036 0x01F0 2036 0x01F0 4036
0x01F0 0038 0x01F0 2038 0x01F0 4038
0x01F0 003A 0x01F0 203A 0x01F0 403A
ETSEL
ETPS
1
1
1
1
1
No
No
No
No
No
Event-Trigger Selection Register
Event-Trigger Pre-Scale Register
Event-Trigger Flag Register
Event-Trigger Clear Register
Event-Trigger Force Register
ETFLG
ETCLR
ETFRC
HIGH-RESOLUTION PWM (HRPWM) SUBMODULE REGISTERS
(1)
0x01F0 1040 0x01F0 3040 0x01F0 5040
HRCNFG
1
No
HRPWM Configuration Register
(1) These registers are only available on eHRPWM instances that include the high-resolution PWM (HRPWM) extension; otherwise, these
locations are reserved.
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5.21.1 Enhanced Pulse Width Modulator (eHRPWM) Timing
PWM refers to PWM outputs on eHRPWM1-6. Table 5-79 shows the PWM timing requirements and
Table 5-80, switching characteristics.
Table 5-79. eHRPWM Timing Requirements
PARAMETER
TEST CONDITIONS
Asynchronous
MIN
MAX
UNIT
cycles
cycles
tw(SYNCIN)
Sync input pulse width
2tc(SCO)
2tc(SCO)
Synchronous
Table 5-80. eHRPWM Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
20
MAX
UNIT
ns
tw(PWM)
Pulse duration, PWMx output high/low
Sync output pulse width
tw(SYNCOUT)
td(PWM)TZA
8tc(SCO)
cycles
ns
Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low
no pin load;
no additional
programmable delay
25
20
td(TZ-PWM)HZ
Delay time, trip input active to PWM Hi-Z
no additional
ns
programmable delay
5.21.2 Trip-Zone Input Timing
t
w(TZ)
TZ
t
d(TZ_PWM)HZ
(A)
PWM
A. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM
recovery software.
Figure 5-46. PWM Hi-Z Characteristics
Table 5-81. Trip-Zone input Timing Requirements
PARAMETER
MIN
MAX
UNIT
cycles
cycles
tw(TZ)
Pulse duration, TZx input low
Asynchronous
Synchronous
1tc(SCO)
2tc(SCO)
Table 5-82 shows the high-resolution PWM switching characteristics.
Table 5-82. High Resolution PWM Characteristics at SYSCLKOUT = (60 - 100 MHz)
PARAMETER
MIN
TYP
MAX
UNIT
Micro Edge Positioning (MEP) step size(1)
200
ps
(1) MEP step size will increase with low voltage and high temperature and decrease with high voltage and cold temperature.
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5.22 LCD Controller
The LCD controller consists of two independent controllers, the Raster Controller and the LCD Interface
Display Driver (LIDD) controller. Each controller operates independently from the other and only one of
them is active at any given time.
•
The Raster Controller handles the synchronous LCD interface. It provides timing and data for constant
graphics refresh to a passive display. It supports a wide variety of monochrome and full-color display
types and sizes by use of programmable timing controls, a built-in palette, and a gray-scale/serializer.
Graphics data is processed and stored in frame buffers. A frame buffer is a contiguous memory block
in the system. A built-in DMA engine supplies the graphics data to the Raster engine which, in turn,
outputs to the external LCD device.
•
The LIDD Controller supports the asynchronous LCD interface. It provides full-timing programmability
of control signals (CS, WE, OE, ALE) and output data.
The maximum resolution for the LCD controller is 1024 x 1024 pixels. The maximum frame rate is
determined by the image size in combination with the pixel clock rate. OMAP-L1x/C674x/AM1x SOC
Architecture and Throughput Overview (SPRAB93).
Table 5-83 lists the LCD Controller registers
Table 5-83. LCD Controller (LCDC) Registers
BYTE ADDRESS
0x01E1 3000
0x01E1 3004
0x01E1 3008
0x01E1 300C
0x01E1 3010
0x01E1 3014
0x01E1 3018
0x01E1 301C
0x01E1 3020
0x01E1 3024
0x01E1 3028
0x01E1 302C
0x01E1 3030
0x01E1 3034
0x01E1 3038
0x01E1 3040
0x01E1 3044
0x01E1 3048
0x01E1 304C
0x01E1 3050
ACRONYM
REVID
REGISTER DESCRIPTION
LCD Revision Identification Register
LCD_CTRL
LCD Control Register
LCD_STAT
LCD Status Register
LIDD_CTRL
LCD LIDD Control Register
LIDD_CS0_CONF
LIDD_CS0_ADDR
LIDD_CS0_DATA
LIDD_CS1_CONF
LIDD_CS1_ADDR
LIDD_CS1_DATA
RASTER_CTRL
LCD LIDD CS0 Configuration Register
LCD LIDD CS0 Address Read/Write Register
LCD LIDD CS0 Data Read/Write Register
LCD LIDD CS1 Configuration Register
LCD LIDD CS1 Address Read/Write Register
LCD LIDD CS1 Data Read/Write Register
LCD Raster Control Register
RASTER_TIMING_0
RASTER_TIMING_1
RASTER_TIMING_2
RASTER_SUBPANEL
LCDDMA_CTRL
LCDDMA_FB0_BASE
LCDDMA_FB0_CEILING
LCDDMA_FB1_BASE
LCDDMA_FB1_CEILING
LCD Raster Timing 0 Register
LCD Raster Timing 1 Register
LCD Raster Timing 2 Register
LCD Raster Subpanel Display Register
LCD DMA Control Register
LCD DMA Frame Buffer 0 Base Address Register
LCD DMA Frame Buffer 0 Ceiling Address Register
LCD DMA Frame Buffer 1 Base Address Register
LCD DMA Frame Buffer 1 Ceiling Address Register
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5.22.1 LCD Interface Display Driver (LIDD Mode)
Table 5-84. LCD LIDD Mode Timing Requirements
No.
16
PARAMETER
MIN
7
MAX
UNIT
ns
tsu(LCD_D)
th(LCD_D)
Setup time, LCD_D[15:0] valid before LCD_MCLK high
Hold time, LCD_D[15:0] valid after LCD_MCLK high
17
0.5
ns
Table 5-85. LCD LIDD Mode Timing Characteristics
No.
4
PARAMETER
MIN
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
MAX
10
10
7
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td(LCD_D_V)
td(LCD_D_I)
td(LCD_E_A
td(LCD_E_I)
td(LCD_A_A)
td(LCD_A_I)
Delay time, LCD_MCLK high to LCD_D[15:0] valid (write)
Delay time, LCD_MCLK high to LCD_D[15:0] invalid (write)
Delay time, LCD_MCLK high to LCD_AC_ENB_CS low
Delay time, LCD_MCLK high to LCD_AC_ENB_CS high
Delay time, LCD_MCLK high to LCD_VSYNC low
Delay time, LCD_MCLK high to LCD_VSYNC high
Delay time, LCD_MCLK high to LCD_HSYNC low
Delay time, LCD_MCLK high to LCD_HSYNC high
Delay time, LCD_MCLK high to LCD_PCLK active
Delay time, LCD_MCLK high to LCD_PCLK inactive
Delay time, LCD_MCLK high to LCD_D[15:0] in 3-state
Delay time, LCD_MCLK high to LCD_D[15:0] (valid from 3-state)
5
6
)
7
7
8
8
9
8
10
11
12
13
14
15
td(LCD_W_A)
td(LCD_W_I)
td(LCD_STRB_A)
td(LCD_STRB_I)
td(LCD_D_Z)
td(Z_LCD_D)
8
8
12
12
12
12
CS_DELAY
R_SU
(0 to 31)
W_HOLD
(1 to 15)
1
2
R_HOLD
(1 to 15)
W_SU
(0 to 31)
W_STROBE
(1 to 63)
CS_DELAY
R_STROBE
(1 to 63)
3
LCD_MCLK
4
5
14
17
16
15
LCD_D[15:0]
LCD_PCLK
Write Data
Data[7:0]
Read Status
Not Used
8
9
LCD_VSYNC
LCD_HSYNC
RS
10
11
R/W
12
12
13
13
E0
E1
LCD_AC_ENB_CS
Figure 5-47. Character Display HD44780 Write
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W_HOLD
(1–15)
R_SU
(0–31)
R_STROBE R_HOLD CS_DELAY
(1–63) (1–5)
W_SU
(0–31)
W_STROBE
(1–63)
CS_DELAY
1
2
Not
3
Used
LCD_MCLK
LCD_D[7:0]
4
17
15
5
14
16
Data[7:0]
Write Instruction
Read
Data
LCD_PCLK
Not
Used
8
9
RS
LCD_VSYNC
LCD_HSYNC
10
11
R/W
12
13
13
12
E0
E1
LCD_AC_ENB_CS
Figure 5-48. Character Display HD44780 Read
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W_HOLD
(1−15)
W_HOLD
(1−15)
W_SU
(0−31)
W_STROBE
(1−63)
CS_DELAY
W_SU
(0−31)
W_STROBE
(1−63)
CS_DELAY
1
2
3
Clock
LCD_MCLK
4
6
5
7
5
4
LCD_D[15:0]
Write Address
Write Data
Data[15:0]
6
7
LCD_AC_ENB_CS
(async mode)
CS0
CS1
9
8
A0
R/W
E
LCD_VSYNC
10
11
10
11
LCD_HSYNC
LCD_PCLK
12
13
12
13
Figure 5-49. Micro-Interface Graphic Display 6800 Write
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W_HOLD
(1−15)
R_SU
(0−31)
W_SU
(0−31)
W_STROBE
(1−63)
CS_DELAY
R_STROBE R_HOLD CS_DELAY
(1−63
1
(1−15)
3
2
Clock
LCD_MCLK
4
14
5
16
15
Data[15:0]
17
LCD_D[15:0]
Write Address
Read
Data
6
6
7
7
LCD_AC_ENB_CS
(async mode)
CS0
CS1
9
8
LCD_VSYNC
LCD_HSYNC
LCD_PCLK
A0
R/W
E
11
10
13
12
13
12
Figure 5-50. Micro-Interface Graphic Display 6800 Read
162
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R_SU
(0−31)
R_SU
(0−31)
R_STROBE R_HOLD CS_DELAY
(1−63) (1−15)
R_HOLD CS_DELAY
(1−15)
R_STROBE
(1−63)
1
2
3
Clock
LCD_MCLK
17
17
14 16
14
15
7
16
15
LCD_D[15:0]
Data[15:0]
Read
Read
Data
Status
6
7
6
LCD_AC_ENB_CS
(async mode)
CS0
CS1
8
9
LCD_VSYNC
LCD_HSYNC
A0
R/W
E
13
12
12
13
LCD_PCLK
Figure 5-51. Micro-Interface Graphic Display 6800 Status
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W_HOLD
(1−15)
W_HOLD
(1−15)
W_SU
W_STROBE
CS_DELAY
W_SU
(0−31)
W_STROBE
(1−63)
CS_DELAY
1
2
(0−31)
3
(1−63)
Clock
LCD_MCLK
4
5
4
5
LCD_D[15:0]
Write Address
Write Data
7
6
6
7
LCD_AC_ENB_CS
(async mode)
CS0
CS1
8
9
LCD_VSYNC
LCD_HSYNC
LCD_PCLK
A0
WR
RD
11
10
10
11
Figure 5-52. Micro-Interface Graphic Display 8080 Write
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W_HOLD
(1−15)
R_SU
(0−31)
W_SU
(0−31)
W_STROBE
(1−63)
CS_DELAY
R_STROBE
(1−63)
R_HOLD CS_DELAY
(1−15)
1
Clock
2
3
LCD_MCLK
4
5
16
17
15
Data[15:0]
14
LCD_D[15:0]
Write Address
Read
Data
7
6
7
6
LCD_AC_ENB_CS
(async mode)
CS0
CS1
9
8
LCD_VSYNC
LCD_HSYNC
LCD_PCLK
A0
11
10
WR
12
13
RD
Figure 5-53. Micro-Interface Graphic Display 8080 Read
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R_SU
(0−31)
R_SU
(0−31)
R_STROBE R_HOLD CS_DELAY
R_STROBE R_HOLD
CS_DELAY
1
2
(1−15)
(1−63)
(1−63)
(1−15)
3
Clock
LCD_MCLK
17
16
17
15
Data[15:0]
14
6
16
15
14
LCD_D[15:0]
Read Data
Read Status
7
6
7
9
LCD_AC_ENB_CS
CS0
CS1
8
A0
WR
RD
LCD_VSYNC
LCD_HSYNC
12
13
13
12
LCD_PCLK
Figure 5-54. Micro-Interface Graphic Display 8080 Status
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5.22.2 LCD Raster Mode
Table 5-86. LCD Raster Mode Timing
See Figure 5-55 through Figure 5-59
No.
PARAMETER
Cycle time, pixel clock
MIN
26.6
MAX
UNIT
ns
1
2
tc(PIXEL_CLK)
tw(PIXEL_CLK_H)
tw(PIXEL_CLK_L)
td(LCD_D_V)
Pulse duration, pixel clock high
10
ns
3
Pulse duration, pixel clock low
10
ns
4
Delay time, LCD_PCLK high to LCD_D[15:0] valid (write)
Delay time, LCD_PCLK high to LCD_D[15:0] invalid (write)
Delay time, LCD_PCLK low to LCD_AC_ENB_CS high
Delay time, LCD_PCLK low to LCD_AC_ENB_CS low
Delay time, LCD_PCLK low to LCD_VSYNC high(2)
Delay time, LCD_PCLK low to LCD_VSYNC low(2)
Delay time, LCD_PCLK high to LCD_HSYNC high(2)
Delay time, LCD_PCLK high to LCD_HSYNC low(2)
-0.5
9
ns
5
td(LCD_D_IV)
-0.5
9
S2 + 9(1)
S2 + 9(1)
12
ns
6
td(LCD_AC_ENB_CS_A)
td(LCD_AC_ENB_CS_I)
td(LCD_VSYNC_A)
td(LCD_VSYNC_I)
td(LCD_HSYNC_A)
td(LCD_HSYNC_I)
S2 - 0.5(1)
S2 - 0.5(1)
-0.5
ns
7
ns
8
ns
9
-0.5
12
ns
10
11
-0.5
12
ns
-0.5
12
ns
(1) S2 = SYSCLK2 cycle time in ns
(2) The activation edge of the control signals LCD_VSYNC and LCD_HSYNC may be programmed to either the rising or falling edge of the
pixel clock through the LCD (RASTER_TIMING_2) register. In Figure 5-56 through Figure 5-59, all signal polarity and activation edges
are based on the default LCD (RASTER_TIMING_2) register settings.
Frame-to-frame timing is derived through the following parameters in the LCD (RASTER_TIMING_1)
register:
•
•
•
•
Vertical front porch (VFP)
Vertical sync pulse width (VSW)
Vertical back porch (VBP)
Lines per panel (LPP)
Line-to-line timing is derived through the following parameters in the LCD (RASTER_TIMING_0) register:
•
•
•
•
Horizontal front porch (HFP)
Horizontal sync pulse width (HSW)
Horizontal back porch (HBP)
Pixels per panel (PPL)
LCD_AC_ENB_CS timing is derived through the following parameter in the LCD (RASTER_TIMING_2)
register:
•
AC bias frequency (ACB)
The display format produced in raster mode is shown in Figure 5-55. An entire frame is delivered one line
at a time. The first line delivered starts at data pixel (1, 1) and ends at data pixel (P, 1). The last line
delivered starts at data pixel (1, L) and ends at data pixel (P, L). The beginning of each new frame is
denoted by the activation of I/O signal LCD_VSYNC. The beginning of each new line is denoted by the
activation of I/O signal LCD_HSYNC.
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Data Pixels (From 1 to P)
P−2,
1
P−1,
1
1, 1
1, 2
1, 3
2, 1
2, 2
3, 1
P, 1
P, 2
P, 3
P−1,
2
LCD
P,
1,
L−2
L−2
1,
2,
P,
P−1,
L−1
L−1
L−1
L−1
P−2,
L
P−1,
L
1, L
2, L
3, L
P, L
Figure 5-55. LCD Raster-Mode Display Format
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Frame Time ~ 70 Hz
Active TFT
VSW
VBP
LPP
(1 to 1024)
VFP
VSW
(1 to 64)
(0 to 255)
(1 to 64)
(0 to 255)
Line
Time
Hsync
LCD_HSYNC
LCD_VSYNC
Vsync
Data
LCD_D[15:0]
1, L-1
P, L-1
1, L
P, L
1, 2
P, 2
1, 1
P, 1
LCD_AC_ENB_CS
10
11
Hsync
LCD_HSYNC
CLK
LCD_PCLK
Data
LCD_D[15:0]
2, 1
1, 2
P, 2
P, 1
1, 1
2, 2
Enable
LCD_AC_ENB_CS
PLL
HFP
(1 to 256)
HSW
HBP
PLL
(1 to 256)
(1 to 64)
16 × (1 to 1024)
Line 1
16 × (1 to 1024)
Line 2
Figure 5-56. LCD Raster-Mode Active
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Frame Time ~ 70Hz
VBP = 0
VFP = 0
VBP = 0
VFP = 0
VSW = 1
VSW = 1
(1 to 64)
LPP
Passive STN
LCD_HSYNC
(1 to 64)
(1 to 1024)
Line
Time
LP
FP
LCD_VSYNC
1, L
Data
1, 2
P, 2
1, 1:
P, 1
1, 5:
P, 5
1, L
P, L
1, 1
P, 1
1, L:
P, L
1, 3: 1, 4:
P, 3 P, 4
1, 6:
P, 6
1, 2:
P, 2
LCD_D[7:0]
1, L−1
P, L−1
1, L−4 1, L−3
P, L−4 P, L−3
1, L−2
P, L−2
1, L−1
P, L−1
M
LCD_AC_ENB_CS
ACB
ACB
(0 to 255)
(0 to 255)
11
10
LP
LCD_HSYNC
LCD_PCLK
LCD_D[7:0]
CP
Data
1, 5
P, 6
1, 6
2, 6
2, 5
P, 5
PPL
HFP
HSW
(1 to 64)
HBP
PPL
16 (1 to 1024)
Line 5
(1 to 256)
(1 to 256)
16 (1 to 2024)
Line 6
Figure 5-57. LCD Raster-Mode Passive
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6
LCD_AC_ENB_CS
8
LCD_VSYNC
LCD_HSYNC
11
10
1
2
3
LCD_PCLK
(passive mode)
5
4
LCD_D[7:0]
2, L
2, 1
1, L
P, L
1, 1
P, 1
(passive mode)
1
3
2
LCD_PCLK
(active mode)
4
5
LCD_D[15:0]
(active mode)
1, L
P, L
2, L
VBP = 0
VFP = 0
VSW = 1
PPL
HSW
HBP
PPL
(1 to 1024)
×
HFP
(1 to 256
(1 to 1024)
(1 to 64)
(1 to 256)
×
16
16
Line L
Line 1 (Passive Only)
Figure 5-58. LCD Raster-Mode Control Signal Activation
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7
LCD_AC_ENB_CS
LCD_VSYNC
9
11
10
LCD_HSYNC
1
3
4
LCD_PCLK
(passive mode)
5
4
LCD_D[7:0]
2, 1
2, 2
1, 1
P, 1
1, 2
P, 2
(passive mode)
1
3
2
LCD_PCLK
(active mode)
4
5
LCD_D[15:0]
(active mode)
1, 1
P, 1
2, 1
VBP = 0
VFP = 0
VSW = 1
PPL
HSW
HBP
PPL
(1 to 1024)
×
HFP
(1 to 1024)
(1 to 256
(1 to 64)
(1 to 256)
×
16
16
Line 1 for passive
Line 1 for active
Line 2 for passive
Figure 5-59. LCD Raster-Mode Control Signal Deactivation
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SPRS563F –SEPTEMBER 2008–REVISED FEBRUARY 2013
5.23 Timers
The timers support the following features:
•
•
•
•
•
•
Configurable as single 64-bit timer or two 32-bit timers
Period timeouts generate interrupts, DMA events or external pin events
8 32-bit compare registers
Compare matches generate interrupt events
Capture capability
64-bit Watchdog capability (Timer64P1 only)
Table 5-87 lists the timer registers.
Table 5-87. Timer Registers
Timer64P 0
0x01C2 0000
0x01C2 0004
0x01C2 0008
0x01C2 000C
0x01C2 0010
0x01C2 0014
0x01C2 0018
0x01C2 001C
0x01C2 0020
0x01C2 0024
0x01C2 0028
0x01C2 0034
0x01C2 0038
0x01C2 003C
0x01C2 0040
0x01C2 0044
0x01C2 0060
0x01C2 0064
0x01C2 0068
0x01C2 006C
0x01C2 0070
0x01C2 0074
0x01C2 0078
0x01C2 007C
Timer64P 1
0x01C2 1000
0x01C2 1004
0x01C2 1008
0x01C2 100C
0x01C2 1010
0x01C2 1014
0x01C2 1018
0x01C2 101C
0x01C2 1020
0x01C2 1024
0x01C2 1028
0x01C2 1034
0x01C2 1038
0x01C2 103C
0x01C2 1040
0x01C2 1044
0x01C2 1060
0x01C2 1064
0x01C2 1068
0x01C2 106C
0x01C2 1070
0x01C2 1074
0x01C2 1078
0x01C2 107C
ACRONYM
REGISTER DESCRIPTION
REV
EMUMGT
GPINTGPEN
GPDATGPDIR
TIM12
Revision Register
Emulation Management Register
GPIO Interrupt and GPIO Enable Register
GPIO Data and GPIO Direction Register
Timer Counter Register 12
Timer Counter Register 34
Timer Period Register 12
Timer Period Register 34
Timer Control Register
TIM34
PRD12
PRD34
TCR
TGCR
Timer Global Control Register
Watchdog Timer Control Register
Timer Reload Register 12
Timer Reload Register 34
Timer Capture Register 12
Timer Capture Register 34
Timer Interrupt Control and Status Register
Compare Register 0
WDTCR
REL12
REL34
CAP12
CAP34
INTCTLSTAT
CMP0
CMP1
Compare Register 1
CMP2
Compare Register 2
CMP3
Compare Register 3
CMP4
Compare Register 4
CMP5
Compare Register 5
CMP6
Compare Register 6
CMP7
Compare Register 7
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5.23.1 Timer Electrical Data/Timing
Table 5-88. Timing Requirements for Timer Input(1) (2) (see Figure 5-60)
No.
1
PARAMETER
Cycle time, TM64Px_IN12
MIN
MAX
UNIT
tc(TM64Px_IN12)
tw(TINPH)
4P
ns
2
Pulse duration, TM64Px_IN12 high
Pulse duration, TM64Px_IN12 low
Transition time, TM64Px_IN12
0.45C
0.45C
0.55C
0.55C
0.25P or 10(3)
ns
ns
ns
3
tw(TINPL)
4
tt(TM64Px_IN12)
(1) P = OSCIN cycle time in ns.
(2) C = TM64P0_IN12 cycle time in ns. For example, when TM64Px_IN12 frequency is 27 MHz, use C = 37.037 ns
(3) Whichever is smaller. P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve
noise immunity on input signals.
1
2
3
4
4
TM64P0_IN12
Figure 5-60. Timer Timing
Table 5-89. Switching Characteristics Over Recommended Operating Conditions for Timer Output
(1)
No.
5
PARAMETER
Pulse duration, TM64P0_OUT12 high
Pulse duration, TM64P0_OUT12 low
MIN
4P
MAX
UNIT
ns
tw(TOUTH)
tw(TOUTL)
6
4P
ns
(1) P = OSCIN cycle time in ns. For example, when OSCIN frequency is 27 MHz, use P = 37.037 ns.
5
6
TM64P0_OUT12
Figure 5-61. Timer Timing
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SPRS563F –SEPTEMBER 2008–REVISED FEBRUARY 2013
5.24 Inter-Integrated Circuit Serial Ports (I2C0, I2C1)
5.24.1 I2C Device-Specific Information
Having two I2C modules on the OMAP-L137 simplifies system architecture, since one module may be
used by the DSP to control local peripherals ICs (DACs, ADCs, etc.) while the other may be used to
communicate with other controllers in a system or to implement a user interface. Figure 5-62 is block
diagram of the OMAP-L137 I2C Module.
Each I2C port supports:
•
•
•
•
•
•
•
Compatible with Philips® I2C Specification Revision 2.1 (January 2000)
Fast Mode up to 400 Kbps (no fail-safe I/O buffers)
Noise Filter to Remove Noise 50 ns or less
Seven- and Ten-Bit Device Addressing Modes
Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality
Events: DMA, Interrupt, or Polling
General-Purpose I/O Capability if not used as I2C
Clock Prescaler
I2CPSCx
Control
I2CCOARx
Prescaler
Register
Own Address
Register
Slave Address
Register
I2CSARx
Bit Clock Generator
I2CCLKHx
Noise
Filter
I2Cx_SCL
Clock Divide
High Register
I2CCMDRx
I2CEMDRx
I2CCNTx
I2CPID1
Mode Register
Extended Mode
Register
Clock Divide
Low Register
I2CCLKLx
Data Count
Register
Peripheral
Configuration
Bus
Transmit
Peripheral ID
Register 1
Transmit Shift
Register
I2CXSRx
Peripheral ID
Register 2
I2CPID2
I2CDXRx
Transmit Buffer
Noise
Filter
I2Cx_SDA
Interrupt/DMA
Interrupt Enable
Register
Receive
I2CIERx
Interrupt DMA
Requests
Receive Buffer
I2CDRRx
Interrupt Status
Register
I2CSTRx
I2CSRCx
Receive Shift
Register
Interrupt Source
Register
I2CRSRx
Control
Pin Function
Register
Pin Data Out
Register
I2CPDOUT
I2CPFUNC
Pin Direction
Register
Pin Data Set
Register
I2CPDIR
I2CPDIN
I2CPDSET
I2CPDCLR
Pin Data In
Register
Pin Data Clear
Register
Figure 5-62. I2C Module Block Diagram
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5.24.2 I2C Peripheral Registers Description(s)
Table 5-90 is the list of the I2C registers.
Table 5-90. Inter-Integrated Circuit (I2C) Registers
I2C0
BYTE ADDRESS
I2C1
ACRONYM
REGISTER DESCRIPTION
I2C Own Address Register
BYTE ADDRESS
0x01E2 8000
0x01E2 8004
0x01E2 8008
0x01E2 800C
0x01E2 8010
0x01E2 8014
0x01E2 8018
0x01E2 801C
0x01E2 8020
0x01E2 8024
0x01E2 8028
0x01E2 802C
0x01E2 8030
0x01E2 8034
0x01E2 8038
0x01E2 8048
0x01E2 804C
0x01E2 8050
0x01E2 8054
0x01E2 8058
0x01E2 805C
0x01C2 2000
0x01C2 2004
0x01C2 2008
0x01C2 200C
0x01C2 2010
0x01C2 2014
0x01C2 2018
0x01C2 201C
0x01C2 2020
0x01C2 2024
0x01C2 2028
0x01C2 202C
0x01C2 2030
0x01C2 2034
0x01C2 2038
0x01C2 2048
0x01C2 204C
0x01C2 2050
0x01C2 2054
0x01C2 2058
0x01C2 205C
ICOAR
ICIMR
I2C Interrupt Mask Register
I2C Interrupt Status Register
I2C Clock Low-Time Divider Register
I2C Clock High-Time Divider Register
I2C Data Count Register
ICSTR
ICCLKL
ICCLKH
ICCNT
ICDRR
I2C Data Receive Register
I2C Slave Address Register
I2C Data Transmit Register
I2C Mode Register
ICSAR
ICDXR
ICMDR
ICIVR
I2C Interrupt Vector Register
I2C Extended Mode Register
I2C Prescaler Register
ICEMDR
ICPSC
REVID1
REVID2
ICPFUNC
ICPDIR
ICPDIN
ICPDOUT
ICPDSET
ICPDCLR
I2C Revision Identification Register 1
I2C Revision Identification Register 2
I2C Pin Function Register
I2C Pin Direction Register
I2C Pin Data In Register
I2C Pin Data Out Register
I2C Pin Data Set Register
I2C Pin Data Clear Register
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5.24.3 I2C Electrical Data/Timing
5.24.3.1 Inter-Integrated Circuit (I2C) Timing
Table 5-91 and Table 5-92 assume testing over recommended operating conditions (see Figure 5-63 and
Figure 5-64).
Table 5-91. I2C Input Timing Requirements
No.
PARAMETER
MIN
MAX
UNIT
Standard Mode
Fast Mode
10
2.5
4.7
0.6
4
1
tc(SCL)
Cycle time, I2Cx_SCL
μs
Standard Mode
Fast Mode
2
3
4
5
6
7
8
9
tsu(SCLH-SDAL)
th(SCLL-SDAL)
tw(SCLL)
Setup time, I2Cx_SCL high before I2Cx_SDA low
Hold time, I2Cx_SCL low after I2Cx_SDA low
Pulse duration, I2Cx_SCL low
μs
μs
μs
μs
ns
μs
μs
ns
ns
ns
ns
μs
ns
pF
Standard Mode
Fast Mode
0.6
4.7
1.3
4
Standard Mode
Fast Mode
Standard Mode
Fast Mode
tw(SCLH)
Pulse duration, I2Cx_SCL high
0.6
250
100
0
Standard Mode
Fast Mode
tsu(SDA-SCLH)
th(SDA-SCLL)
tw(SDAH)
Setup time, I2Cx_SDA before I2Cx_SCL high
Hold time, I2Cx_SDA after I2Cx_SCL low
Pulse duration, I2Cx_SDA high
Standard Mode
Fast Mode
0
0.9
Standard Mode
Fast Mode
4.7
1.3
Standard Mode
Fast Mode
1000
300
1000
300
300
300
300
300
tr(SDA)
Rise time, I2Cx_SDA
20 + 0.1Cb
20 + 0.1Cb
20 + 0.1Cb
Standard Mode
Fast Mode
10 tr(SCL)
11 tf(SDA)
12 tf(SCL)
13 tsu(SCLH-SDAH)
14 tw(SP)
Rise time, I2Cx_SCL
Standard Mode
Fast Mode
Fall time, I2Cx_SDA
Standard Mode
Fast Mode
Fall time, I2Cx_SCL
20 + 0.1Cb
Standard Mode
Fast Mode
4
0.6
N/A
0
Setup time, I2Cx_SCL high before I2Cx_SDA high
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
Standard Mode
Fast Mode
50
400
400
Standard Mode
Fast Mode
15 Cb
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Table 5-92. I2C Switching Characteristics(1)
No.
PARAMETER
MIN
MAX
UNIT
Standard Mode
Fast Mode
10
2.5
4.7
0.6
4
16 tc(SCL)
Cycle time, I2Cx_SCL
μs
Standard Mode
Fast Mode
17 tsu(SCLH-SDAL)
18 th(SDAL-SCLL)
19 tw(SCLL)
Setup time, I2Cx_SCL high before I2Cx_SDA low
Hold time, I2Cx_SCL low after I2Cx_SDA low
Pulse duration, I2Cx_SCL low
μs
μs
μs
μs
ns
μs
μs
μs
Standard Mode
Fast Mode
0.6
4.7
1.3
4
Standard Mode
Fast Mode
Standard Mode
Fast Mode
20 tw(SCLH)
Pulse duration, I2Cx_SCL high
0.6
250
100
0
Standard Mode
Fast Mode
21 tsu(SDAV-SCLH)
22 th(SCLL-SDAV)
23 tw(SDAH)
Setup time, I2Cx_SDA valid before I2Cx_SCL high
Hold time, I2Cx_SDA valid after I2Cx_SCL low
Pulse duration, I2Cx_SDA high
Standard Mode
Fast Mode
0
0.9
Standard Mode
Fast Mode
4.7
1.3
4
Standard Mode
Fast Mode
28 tsu(SCLH-SDAH)
Setup time, I2Cx_SCL high before I2Cx_SDA high
0.6
(1) I2C must be configured correctly to meet the timings in Table 5-92.
11
9
I2Cx_SDA
6
8
14
4
13
5
10
I2Cx_SCL
1
12
3
2
7
3
Stop
Start
Repeated
Start
Stop
Figure 5-63. I2C Receive Timings
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26
24
I2Cx_SDA
21
23
19
28
20
25
I2Cx_SCL
16
27
18
17
22
18
Stop
Start
Repeated
Start
Stop
Figure 5-64. I2C Transmit Timings
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5.25 Universal Asynchronous Receiver/Transmitter (UART)
OMAP-L137 has three UART peripherals. Each UART has the following features:
•
•
•
•
•
•
•
•
•
•
16-byte storage space for both the transmitter and receiver FIFOs
Autoflow control signals (CTS, RTS) on UART0 only
1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA
DMA signaling capability for both received and transmitted data
Programmable auto-rts and auto-cts for autoflow control
Programmable Baud Rate up to 3MBaud
Programmable Oversampling Options of x13 and x16
Frequency pre-scale values from 1 to 65,535 to generate appropriate baud rates
Prioritized interrupts
Programmable serial data formats
–
–
–
5, 6, 7, or 8-bit characters
Even, odd, or no parity bit generation and detection
1, 1.5, or 2 stop bit generation
•
•
•
False start bit detection
Line break generation and detection
Internal diagnostic capabilities
–
–
Loopback controls for communications link fault isolation
Break, parity, overrun, and framing error simulation
The UART registers are listed in Section 5.25.1
5.25.1 UART Peripheral Registers Description(s)
Table 5-93 is the list of UART registers.
Table 5-93. UART Registers
UART0
UART1
UART2
ACRONYM
REGISTER DESCRIPTION
BYTE ADDRESS
BYTE ADDRESS
BYTE ADDRESS
0x01C4 2000
0x01C4 2000
0x01C4 2004
0x01C4 2008
0x01C4 2008
0x01C4 200C
0x01C4 2010
0x01C4 2014
0x01C4 2018
0x01C4 201C
0x01C4 2020
0x01C4 2024
0x01C4 2028
0x01C4 2030
0x01C4 2034
0x01D0 C000
0x01D0 C000
0x01D0 C004
0x01D0 C008
0x01D0 C008
0x01D0 C00C
0x01D0 C010
0x01D0 C014
0x01D0 C018
0x01D0 C01C
0x01D0 C020
0x01D0 C024
0x01D0 C028
0x01D0 C030
0x01D0 C034
0x01D0 D000
0x01D0 D000
0x01D0 D004
0x01D0 D008
0x01D0 D008
0x01D0 D00C
0x01D0 D010
0x01D0 D014
0x01D0 D018
0x01D0 D01C
0x01D0 D020
0x01D0 D024
0x01D0 D028
0x01D0 D030
0x01D0 D034
RBR
THR
IER
Receiver Buffer Register (read only)
Transmitter Holding Register (write only)
Interrupt Enable Register
Interrupt Identification Register (read only)
FIFO Control Register (write only)
Line Control Register
IIR
FCR
LCR
MCR
LSR
Modem Control Register
Line Status Register
MSR
SCR
DLL
Modem Status Register
Scratchpad Register
Divisor LSB Latch
DLH
REVID1
Divisor MSB Latch
Revision Identification Register 1
PWREMU_MGMT Power and Emulation Management Register
MDR
Mode Definition Register
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5.25.2 UART Electrical Data/Timing
Table 5-94. Timing Requirements for UARTx Receive(1) (see Figure 5-65)
No.
4
PARAMETER
Pulse duration, receive data bit (RXDn)
Pulse duration, receive start bit
MIN
MAX
1.05U
1.05U
UNIT
ns
tw(URXDB)
tw(URXSB)
0.96U
0.96U
5
ns
(1) U = UART baud time = 1/programmed baud rate.
Table 5-95. Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit(1)
(see Figure 5-65)
No.
1
PARAMETER
Maximum programmable baud rate
Pulse duration, transmit data bit (TXDn)
Pulse duration, transmit start bit
MIN
MAX
UNIT
MBaud(4)
ns
(2) (3)
f(baud)
D/E
2
tw(UTXDB)
tw(UTXSB)
U - 2
U - 2
U + 2
U + 2
3
ns
(1) U = UART baud time = 1/programmed baud rate.
(2) D = UART input clock in MHz. The UART(s) input clock source is PLL0_SYSCLK2.
(3) E = UART divisor x UART sampling rate. The UART divisor is set through the UART divisor latch registers (DLL and DLH). The UART
sampling rate is set through the over-sampling mode select bit (OSM_SEL) of the UART mode definition register (MDR).
(4) Baud rate is not indicative of data rate. Actual data rate will be limited by system factors such as EDMA loading, EMIF loading, system
frequency, etc.
3
2
Start
Bit
UART_TXDn
Data Bits
5
4
Start
Bit
UART_RXDn
Data Bits
Figure 5-65. UART Transmit/Receive Timing
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5.26 USB1 Host Controller Registers (USB1.1 OHCI)
All the device USB interfaces are compliant with Universal Serial Bus Specification, Revision 1.1.
Table 5-96 is the list of USB Host Controller registers.
Table 5-96. USB1 Host Controller Registers
BYTE ADDRESS
0x01E2 5000
0x01E2 5004
0x01E2 5008
0x01E2 500C
0x01E2 5010
0x01E2 5014
0x01E2 5018
0x01E2 501C
0x01E2 5020
0x01E2 5024
0x01E2 5028
0x01E2 502C
0x01E2 5030
0x01E2 5034
0x01E2 5038
0x01E2 503C
0x01E2 5040
0x01E2 5044
0x01E2 5048
0x01E2 504C
0x01E2 5050
0x01E2 5054
0x01E2 5058
ACRONYM
HCREVISION
REGISTER DESCRIPTION
OHCI Revision Number Register
HCCONTROL
HC Operating Mode Register
HC Command and Status Register
HC Interrupt and Status Register
HC Interrupt Enable Register
HC Interrupt Disable Register
HC HCAA Address Register(1)
HC Current Periodic Register(1)
HC Head Control Register(1)
HC Current Control Register(1)
HC Head Bulk Register(1)
HCCOMMANDSTATUS
HCINTERRUPTSTATUS
HCINTERRUPTENABLE
HCINTERRUPTDISABLE
HCHCCA
HCPERIODCURRENTED
HCCONTROLHEADED
HCCONTROLCURRENTED
HCBULKHEADED
HCBULKCURRENTED
HCDONEHEAD
HC Current Bulk Register(1)
HC Head Done Register(1)
HCFMINTERVAL
HC Frame Interval Register
HC Frame Remaining Register
HC Frame Number Register
HC Periodic Start Register
HCFMREMAINING
HCFMNUMBER
HCPERIODICSTART
HCLSTHRESHOLD
HCRHDESCRIPTORA
HCRHDESCRIPTORB
HCRHSTATUS
HC Low-Speed Threshold Register
HC Root Hub A Register
HC Root Hub B Register
HC Root Hub Status Register
HC Port 1 Status and Control Register(2)
HC Port 2 Status and Control Register(3)
HCRHPORTSTATUS1
HCRHPORTSTATUS2
(1) Restrictions apply to the physical addresses used in these registers.
(2) Connected to the integrated USB1.1 phy pins (USB1_DM, USB1_DP).
(3) Although the controller implements two ports, the second port cannot be used.
Table 5-97. Switching Characteristics Over Recommended Operating Conditions for USB1
LOW SPEED
FULL SPEED
No.
PARAMETER
UNIT
MIN
MAX
300(1)
300(1)
120(2)
2(1)
MIN
MAX
20(1)
20(1)
110(2)
2(1)
U1
U2
U3
U4
U5
U6
tr
Rise time, USB1_DP and USB1_DM signals(1)
Fall time, USB1_DP and USB1_DM signals(1)
Rise/Fall time matching(2)
Output signal cross-over voltage(1)
Differential propagation jitter(3)
75(1)
75(1)
80(2)
1.3(1)
-25(3)
4(1)
4(1)
90(2)
1.3(1)
-2(3)
ns
ns
tf
tRFM
VCRS
tj
%
V
25(3)
2(3)
ns
fop
Operating frequency(4)
1.5
12
MHz
(1) Low Speed: CL = 200 pF. High Speed: CL = 50pF
(2) tRFM =( tr/tf ) x 100
(3) t jr = t px(1) - tpx(0)
(4) fop = 1/tper
5.26.1 USB1 Unused Signal Configuration
If USB1 is unused, then the USB1 signals should be configured as shown in Section 5.4.
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5.27 USB0 OTG (USB2.0 OTG)
The OMAP-L137 USB2.0 peripheral supports the following features:
•
•
•
•
•
USB 2.0 peripheral at speeds high speed (HS: 480 Mb/s ) and full speed (FS: 12 Mb/s)
USB 2.0 host at speeds HS, FS, and low speed (LS: 1.5 Mb/s)
All transfer modes (control, bulk, interrupt, and isochronous)
4 Transmit (TX) and 4 Receive (RX) endpoints in addition to endpoint 0
FIFO RAM
–
–
4K endpoint
Programmable size
•
•
•
Integrated USB 2.0 High Speed PHY
Connects to a standard Charge Pump for VBUS 5 V generation
RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB
Important Notice: On the original device pinout (marked "A" in the lower right corner of the package),
pins USB0_VSSA33 (H4) and USB0_VSSA (F3) were connected to ground outside the package. For
more robust ESD performance, the USB0 ground references are now connected inside the package on
packages marked "B" and the package pins are unconnected. This change will require that any external
filter circuits previously referenced to ground at these pins will need to reference the board ground instead.
Important Notice: The USB0 controller module clock (PLL0_SYSCLK2) must be greater than 30 MHz for
proper operation of the USB controller. A clock rate of 60 MHz or greater is recommended to avoid data
throughput reduction.
Table 5-98 is the list of USB OTG registers.
Table 5-98. Universal Serial Bus OTG (USB0) Registers
BYTE ADDRESS
0x01E0 0000
0x01E0 0004
0x01E0 0008
0x01E0 000C
0x01E0 0010
0x01E0 0014
0x01E0 0018
0x01E0 001C
0x01E0 0020
0x01E0 0024
0x01E0 0028
0x01E0 002C
0x01E0 0030
0x01E0 0034
0x01E0 0038
0x01E0 003C
0x01E0 0040
0x01E0 0050
0x01E0 0054
0x01E0 0058
0x01E0 005C
0x01E0 0400
0x01E0 0401
0x01E0 0402
ACRONYM
REVID
REGISTER DESCRIPTION
Revision Register
Control Register
CTRLR
STATR
Status Register
EMUR
Emulation Register
Mode Register
MODE
AUTOREQ
SRPFIXTIME
TEARDOWN
INTSRCR
INTSETR
Autorequest Register
SRP Fix Time Register
Teardown Register
USB Interrupt Source Register
USB Interrupt Source Set Register
USB Interrupt Source Clear Register
USB Interrupt Mask Register
USB Interrupt Mask Set Register
USB Interrupt Mask Clear Register
USB Interrupt Source Masked Register
USB End of Interrupt Register
Reserved
INTCLRR
INTMSKR
INTMSKSETR
INTMSKCLRR
INTMASKEDR
EOIR
-
GENRNDISSZ1
GENRNDISSZ2
GENRNDISSZ3
GENRNDISSZ4
FADDR
Generic RNDIS Size EP1
Generic RNDIS Size EP2
Generic RNDIS Size EP3
Generic RNDIS Size EP4
Function Address Register
POWER
Power Management Register
Interrupt Register for Endpoint 0 plus Transmit Endpoints 1 to 4
INTRTX
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Table 5-98. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
0x01E0 0404
0x01E0 0406
0x01E0 0408
0x01E0 040A
0x01E0 040B
0x01E0 040C
0x01E0 040E
0x01E0 040F
ACRONYM
INTRRX
REGISTER DESCRIPTION
Interrupt Register for Receive Endpoints 1 to 4
Interrupt Enable Register for INTRTX
Interrupt Enable Register for INTRRX
Interrupt Register for Common USB Interrupts
Interrupt Enable Register for INTRUSB
Frame Number Register
INTRTXE
INTRRXE
INTRUSB
INTRUSBE
FRAME
INDEX
Index Register for Selecting the Endpoint Status and Control Registers
Register to Enable the USB 2.0 Test Modes
TESTMODE
INDEXED REGISTERS
These registers operate on the endpoint selected by the INDEX register
0x01E0 0410
0x01E0 0412
TXMAXP
PERI_CSR0
HOST_CSR0
PERI_TXCSR
HOST_TXCSR
RXMAXP
Maximum Packet Size for Peripheral/Host Transmit Endpoint
(Index register set to select Endpoints 1-4 only)
Control Status Register for Endpoint 0 in Peripheral Mode.
(Index register set to select Endpoint 0)
Control Status Register for Endpoint 0 in Host Mode.
(Index register set to select Endpoint 0)
Control Status Register for Peripheral Transmit Endpoint.
(Index register set to select Endpoints 1-4)
Control Status Register for Host Transmit Endpoint.
(Index register set to select Endpoints 1-4)
0x01E0 0414
0x01E0 0416
Maximum Packet Size for Peripheral/Host Receive Endpoint
(Index register set to select Endpoints 1-4 only)
PERI_RXCSR
HOST_RXCSR
COUNT0
Control Status Register for Peripheral Receive Endpoint.
(Index register set to select Endpoints 1-4)
Control Status Register for Host Receive Endpoint.
(Index register set to select Endpoints 1-4)
0x01E0 0418
0x01E0 041A
0x01E0 041B
Number of Received Bytes in Endpoint 0 FIFO.
(Index register set to select Endpoint 0)
RXCOUNT
Number of Bytes in Host Receive Endpoint FIFO.
(Index register set to select Endpoints 1- 4)
HOST_TYPE0
Defines the speed of Endpoint 0
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Transmit endpoint.
(Index register set to select Endpoints 1-4 only)
HOST_NAKLIMIT0
Sets the NAK response timeout on Endpoint 0.
(Index register set to select Endpoint 0)
HOST_TXINTERVAL
Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Transmit endpoint.
(Index register set to select Endpoints 1-4 only)
0x01E0 041C
0x01E0 041D
0x01E0 041F
HOST_RXTYPE
HOST_RXINTERVAL
CONFIGDATA
Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Receive endpoint.
(Index register set to select Endpoints 1-4 only)
Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Receive endpoint.
(Index register set to select Endpoints 1-4 only)
Returns details of core configuration.
(Index register set to select Endpoint 0)
FIFO
0x01E0 0420
0x01E0 0424
0x01E0 0428
0x01E0 042C
0x01E0 0430
FIFO0
FIFO1
FIFO2
FIFO3
FIFO4
Transmit and Receive FIFO Register for Endpoint 0
Transmit and Receive FIFO Register for Endpoint 1
Transmit and Receive FIFO Register for Endpoint 2
Transmit and Receive FIFO Register for Endpoint 3
Transmit and Receive FIFO Register for Endpoint 4
OTG DEVICE CONTROL
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Table 5-98. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
Device Control Register
DYNAMIC FIFO CONTROL
0x01E0 0460
DEVCTL
0x01E0 0462
0x01E0 0463
0x01E0 0464
0x01E0 0466
0x01E0 046C
TXFIFOSZ
RXFIFOSZ
Transmit Endpoint FIFO Size
(Index register set to select Endpoints 1-4 only)
Receive Endpoint FIFO Size
(Index register set to select Endpoints 1-4 only)
TXFIFOADDR
RXFIFOADDR
HWVERS
Transmit Endpoint FIFO Address
(Index register set to select Endpoints 1-4 only)
Receive Endpoint FIFO Address
(Index register set to select Endpoints 1-4 only)
Hardware Version Register
TARGET ENDPOINT 0 CONTROL REGISTERS, VALID ONLY IN HOST MODE
0x01E0 0480
0x01E0 0482
TXFUNCADDR
Address of the target function that has to be accessed through the
associated Transmit Endpoint.
TXHUBADDR
Address of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 0483
TXHUBPORT
Port of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 0484
0x01E0 0486
RXFUNCADDR
RXHUBADDR
Address of the target function that has to be accessed through the
associated Receive Endpoint.
Address of the hub that has to be accessed through the associated
Receive Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 0487
RXHUBPORT
Port of the hub that has to be accessed through the associated Receive
Endpoint. This is used only when full speed or low speed device is
connected via a USB2.0 high-speed hub.
TARGET ENDPOINT 1 CONTROL REGISTERS, VALID ONLY IN HOST MODE
0x01E0 0488
0x01E0 048A
TXFUNCADDR
Address of the target function that has to be accessed through the
associated Transmit Endpoint.
TXHUBADDR
Address of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 048B
TXHUBPORT
Port of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 048C
0x01E0 048E
RXFUNCADDR
RXHUBADDR
Address of the target function that has to be accessed through the
associated Receive Endpoint.
Address of the hub that has to be accessed through the associated
Receive Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 048F
RXHUBPORT
Port of the hub that has to be accessed through the associated Receive
Endpoint. This is used only when full speed or low speed device is
connected via a USB2.0 high-speed hub.
TARGET ENDPOINT 2 CONTROL REGISTERS, VALID ONLY IN HOST MODE
0x01E0 0490
0x01E0 0492
TXFUNCADDR
Address of the target function that has to be accessed through the
associated Transmit Endpoint.
TXHUBADDR
Address of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 0493
0x01E0 0494
TXHUBPORT
Port of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
RXFUNCADDR
Address of the target function that has to be accessed through the
associated Receive Endpoint.
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Table 5-98. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01E0 0496
RXHUBADDR
Address of the hub that has to be accessed through the associated
Receive Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 0497
RXHUBPORT
Port of the hub that has to be accessed through the associated Receive
Endpoint. This is used only when full speed or low speed device is
connected via a USB2.0 high-speed hub.
TARGET ENDPOINT 3 CONTROL REGISTERS, VALID ONLY IN HOST MODE
0x01E0 0498
0x01E0 049A
TXFUNCADDR
Address of the target function that has to be accessed through the
associated Transmit Endpoint.
TXHUBADDR
Address of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 049B
TXHUBPORT
Port of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 049C
0x01E0 049E
RXFUNCADDR
RXHUBADDR
Address of the target function that has to be accessed through the
associated Receive Endpoint.
Address of the hub that has to be accessed through the associated
Receive Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 049F
RXHUBPORT
Port of the hub that has to be accessed through the associated Receive
Endpoint. This is used only when full speed or low speed device is
connected via a USB2.0 high-speed hub.
TARGET ENDPOINT 4 CONTROL REGISTERS, VALID ONLY IN HOST MODE
0x01E0 04A0
0x01E0 04A2
TXFUNCADDR
Address of the target function that has to be accessed through the
associated Transmit Endpoint.
TXHUBADDR
Address of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 04A3
TXHUBPORT
Port of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 04A4
0x01E0 04A6
RXFUNCADDR
RXHUBADDR
Address of the target function that has to be accessed through the
associated Receive Endpoint.
Address of the hub that has to be accessed through the associated
Receive Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 04A7
RXHUBPORT
Port of the hub that has to be accessed through the associated Receive
Endpoint. This is used only when full speed or low speed device is
connected via a USB2.0 high-speed hub.
CONTROL AND STATUS REGISTER FOR ENDPOINT 0
0x01E0 0502
PERI_CSR0
HOST_CSR0
COUNT0
Control Status Register for Endpoint 0 in Peripheral Mode
Control Status Register for Endpoint 0 in Host Mode
Number of Received Bytes in Endpoint 0 FIFO
Defines the Speed of Endpoint 0
0x01E0 0508
0x01E0 050A
0x01E0 050B
0x01E0 050F
HOST_TYPE0
HOST_NAKLIMIT0
CONFIGDATA
Sets the NAK Response Timeout on Endpoint 0
Returns details of core configuration.
CONTROL AND STATUS REGISTER FOR ENDPOINT 1
0x01E0 0510
0x01E0 0512
TXMAXP
Maximum Packet Size for Peripheral/Host Transmit Endpoint
PERI_TXCSR
Control Status Register for Peripheral Transmit Endpoint
(peripheral mode)
HOST_TXCSR
RXMAXP
Control Status Register for Host Transmit Endpoint
(host mode)
0x01E0 0514
Maximum Packet Size for Peripheral/Host Receive Endpoint
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Table 5-98. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01E0 0516
PERI_RXCSR
Control Status Register for Peripheral Receive Endpoint
(peripheral mode)
HOST_RXCSR
Control Status Register for Host Receive Endpoint
(host mode)
0x01E0 0518
0x01E0 051A
RXCOUNT
Number of Bytes in Host Receive endpoint FIFO
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Transmit endpoint.
0x01E0 051B
0x01E0 051C
0x01E0 051D
HOST_TXINTERVAL
HOST_RXTYPE
Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Transmit endpoint.
Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Receive endpoint.
HOST_RXINTERVAL
Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Receive endpoint.
CONTROL AND STATUS REGISTER FOR ENDPOINT 2
0x01E0 0520
0x01E0 0522
TXMAXP
Maximum Packet Size for Peripheral/Host Transmit Endpoint
PERI_TXCSR
Control Status Register for Peripheral Transmit Endpoint
(peripheral mode)
HOST_TXCSR
Control Status Register for Host Transmit Endpoint
(host mode)
0x01E0 0524
0x01E0 0526
RXMAXP
Maximum Packet Size for Peripheral/Host Receive Endpoint
PERI_RXCSR
Control Status Register for Peripheral Receive Endpoint
(peripheral mode)
HOST_RXCSR
Control Status Register for Host Receive Endpoint
(host mode)
0x01E0 0528
0x01E0 052A
RXCOUNT
Number of Bytes in Host Receive endpoint FIFO
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Transmit endpoint.
0x01E0 052B
0x01E0 052C
0x01E0 052D
HOST_TXINTERVAL
HOST_RXTYPE
Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Transmit endpoint.
Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Receive endpoint.
HOST_RXINTERVAL
Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Receive endpoint.
CONTROL AND STATUS REGISTER FOR ENDPOINT 3
0x01E0 0530
0x01E0 0532
TXMAXP
Maximum Packet Size for Peripheral/Host Transmit Endpoint
PERI_TXCSR
Control Status Register for Peripheral Transmit Endpoint
(peripheral mode)
HOST_TXCSR
Control Status Register for Host Transmit Endpoint
(host mode)
0x01E0 0534
0x01E0 0536
RXMAXP
Maximum Packet Size for Peripheral/Host Receive Endpoint
PERI_RXCSR
Control Status Register for Peripheral Receive Endpoint
(peripheral mode)
HOST_RXCSR
Control Status Register for Host Receive Endpoint
(host mode)
0x01E0 0538
0x01E0 053A
RXCOUNT
Number of Bytes in Host Receive endpoint FIFO
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Transmit endpoint.
0x01E0 053B
0x01E0 053C
0x01E0 053D
HOST_TXINTERVAL
HOST_RXTYPE
Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Transmit endpoint.
Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Receive endpoint.
HOST_RXINTERVAL
Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Receive endpoint.
CONTROL AND STATUS REGISTER FOR ENDPOINT 4
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Table 5-98. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
0x01E0 0540
ACRONYM
TXMAXP
REGISTER DESCRIPTION
Maximum Packet Size for Peripheral/Host Transmit Endpoint
0x01E0 0542
PERI_TXCSR
Control Status Register for Peripheral Transmit Endpoint
(peripheral mode)
HOST_TXCSR
Control Status Register for Host Transmit Endpoint
(host mode)
0x01E0 0544
0x01E0 0546
RXMAXP
Maximum Packet Size for Peripheral/Host Receive Endpoint
PERI_RXCSR
Control Status Register for Peripheral Receive Endpoint (peripheral
mode)
HOST_RXCSR
Control Status Register for Host Receive Endpoint
(host mode)
0x01E0 0548
0x01E0 054A
RXCOUNT
Number of Bytes in Host Receive endpoint FIFO
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Transmit endpoint.
0x01E0 054B
0x01E0 054C
0x01E0 054D
HOST_TXINTERVAL
HOST_RXTYPE
Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Transmit endpoint.
Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Receive endpoint.
HOST_RXINTERVAL
Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Receive endpoint.
DMA REGISTERS
0x01E0 1000
0x01E0 1004
0x01E0 1008
0x01E0 1800
0x01E0 1808
0x01E0 180C
0x01E0 1810
0x01E0 1820
0x01E0 1828
0x01E0 182C
0x01E0 1830
0x01E0 1840
0x01E0 1848
0x01E0 184C
0x01E0 1850
0x01E0 1860
0x01E0 1868
0x01E0 186C
0x01E0 1870
0x01E0 2000
0x01E0 2800
0x01E0 2804
. . .
DMAREVID
TDFDQ
DMA Revision Register
DMA Teardown Free Descriptor Queue Control Register
DMA Emulation Control Register
DMAEMU
TXGCR[0]
Transmit Channel 0 Global Configuration Register
Receive Channel 0 Global Configuration Register
Receive Channel 0 Host Packet Configuration Register A
Receive Channel 0 Host Packet Configuration Register B
Transmit Channel 1 Global Configuration Register
Receive Channel 1 Global Configuration Register
Receive Channel 1 Host Packet Configuration Register A
Receive Channel 1 Host Packet Configuration Register B
Transmit Channel 2 Global Configuration Register
Receive Channel 2 Global Configuration Register
Receive Channel 2 Host Packet Configuration Register A
Receive Channel 2 Host Packet Configuration Register B
Transmit Channel 3 Global Configuration Register
Receive Channel 3 Global Configuration Register
Receive Channel 3 Host Packet Configuration Register A
Receive Channel 3 Host Packet Configuration Register B
DMA Scheduler Control Register
RXGCR[0]
RXHPCRA[0]
RXHPCRB[0]
TXGCR[1]
RXGCR[1]
RXHPCRA[1]
RXHPCRB[1]
TXGCR[2]
RXGCR[2]
RXHPCRA[2]
RXHPCRB[2]
TXGCR[3]
RXGCR[3]
RXHPCRA[3]
RXHPCRB[3]
DMA_SCHED_CTRL
WORD[0]
DMA Scheduler Table Word 0
WORD[1]
DMA Scheduler Table Word 1
. . .
. . .
0x01E0 28FC
WORD[63]
DMA Scheduler Table Word 63
QUEUE MANAGER REGISTERS
0x01E0 4000
0x01E0 4008
0x01E0 4020
0x01E0 4024
0x01E0 4028
QMGRREVID
DIVERSION
FDBSC0
Queue Manager Revision Register
Queue Diversion Register
Free Descriptor/Buffer Starvation Count Register 0
Free Descriptor/Buffer Starvation Count Register 1
Free Descriptor/Buffer Starvation Count Register 2
FDBSC1
FDBSC2
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Table 5-98. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
ACRONYM
FDBSC3
REGISTER DESCRIPTION
Free Descriptor/Buffer Starvation Count Register 3
Linking RAM Region 0 Base Address Register
Linking RAM Region 0 Size Register
Linking RAM Region 1 Base Address Register
Queue Pending Register 0
0x01E0 402C
0x01E0 4080
0x01E0 4084
0x01E0 4088
0x01E0 4090
0x01E0 4094
0x01E0 5000
0x01E0 5004
0x01E0 5010
0x01E0 5014
. . .
LRAM0BASE
LRAM0SIZE
LRAM1BASE
PEND0
PEND1
Queue Pending Register 1
QMEMRBASE[0]
QMEMRCTRL[0]
QMEMRBASE[1]
QMEMRCTRL[1]
. . .
Memory Region 0 Base Address Register
Memory Region 0 Control Register
Memory Region 1 Base Address Register
Memory Region 1 Control Register
. . .
0x01E0 50F0
0x01E0 50F4
0x01E0 600C
0x01E0 601C
. . .
QMEMRBASE[15]
QMEMRCTRL[15]
CTRLD[0]
Memory Region 15 Base Address Register
Memory Region 15 Control Register
Queue Manager Queue 0 Control Register D
Queue Manager Queue 1 Control Register D
. . .
CTRLD[1]
. . .
0x01E0 63FC
0x01E0 6800
0x01E0 6804
0x01E0 6808
0x01E0 6810
0x01E0 6814
0x01E0 6818
. . .
CTRLD[63]
QSTATA[0]
QSTATB[0]
QSTATC[0]
QSTATA[1]
QSTATB[1]
QSTATC[1]
. . .
Queue Manager Queue 63 Status Register D
Queue Manager Queue 0 Status Register A
Queue Manager Queue 0 Status Register B
Queue Manager Queue 0 Status Register C
Queue Manager Queue 1 Status Register A
Queue Manager Queue 1 Status Register B
Queue Manager Queue 1 Status Register C
. . .
0x01E0 6BF0
0x01E0 6BF4
0x01E0 6BF8
QSTATA[63]
QSTATB[63]
QSTATC[63]
Queue Manager Queue 63 Status Register A
Queue Manager Queue 63 Status Register B
Queue Manager Queue 63 Status Register C
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5.27.1 USB2.0 Electrical Data/Timing
The USB PHY PLL can support input clock of the following frequencies: 12.0 MHz, 13.0 MHz, 19.2 MHz,
20.0 MHz, 24.0 MHz, 26.0 MHz, 38.4 MHz, 40.0 MHz or 48.0 MHz. USB_REFCLKIN jitter tolerance is 50
ppm maximum.
Table 5-99. Switching Characteristics Over Recommended Operating Conditions for USB2.0 (see
Figure 5-66)
LOW SPEED
1.5 Mbps
FULL SPEED
12 Mbps
HIGH SPEED
480 Mbps
No.
PARAMETER
UNIT
MIN
75
MAX
300
300
120
2
MIN
4
MAX
20
20
111
2
MIN
0.5
0.5
–
MAX
1
2
3
4
5
tr(D)
Rise time, USB0_DP and USB0_DM signals(1)
Fall time, USB0_DP and USB0_DM signals(1)
Rise/Fall time, matching(2)
ns
ns
tf(D)
75
4
trfM
80
90
1.3
–
–
%
VCRS
Output signal cross-over voltage(1)
1.3
–
V
(3)ns
tjr(source)NT
tjr(FUNC)NT
tjr(source)PT
tjr(FUNC)PT
tw(EOPT)
tw(EOPR)
t(DRATE)
Source (Host) Driver jitter, next transition
Function Driver jitter, next transition
Source (Host) Driver jitter, paired transition(4)
Function Driver jitter, paired transition
2
2
(3)
(3)
(3)
25
2
ns
6
1
1
ns
10
1
ns
(5)
7
8
9
Pulse duration, EOP transmitter
1250
670
1500
160
82
175
–
–
–
ns
(5)
Pulse duration, EOP receiver
ns
Data Rate
1.5
–
12
480
49.5
-
Mb/s
Ω
10 ZDRV
11 ZINP
Driver Output Resistance
Receiver Input Impedance
–
40.5
49.5
40.5
-
100k
100k
Ω
(1) Low Speed: CL = 200 pF, Full Speed: CL = 50 pF, High Speed: CL = 50 pF
(2) tRFM = (tr/tf) x 100. [Excluding the first transaction from the Idle state.]
(3) For more detailed information, see the Universal Serial Bus Specification Revision 2.0, Chapter 7. Electrical.
(4) tjr = tpx(1) - tpx(0)
(5) Must accept as valid EOP
t
- t
per jr
USB0_DM
V
90% V
OH
CRS
10% V
OL
USB0_DP
t
f
t
r
Figure 5-66. USB0 Integrated Transceiver Interface Timing
5.27.2 USB0 Unused Signal Configuration
If USB0 is unused, then the USB0 signals should be configured as shown in Section 5.4.
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SPRS563F –SEPTEMBER 2008–REVISED FEBRUARY 2013
5.28 Host-Port Interface (UHPI)
5.28.1 HPI Device-Specific Information
The device includes a user-configurable 16-bit Host-port interface (HPI16). See the OMAP-L137
Applications Processor DSP Peripherals Overview Reference Guide. (SPRUGA6) for more details.
5.28.2 HPI Peripheral Register Description(s)
Table 5-100. HPI Control Registers
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
COMMENTS
0x01E1 0000
PID
Peripheral Identification Register
The CPU has read/write
access to the
0x01E1 0004
PWREMU_MGMT
HPI power and emulation management register
PWREMU_MGMT register.
0x01E1 0008
0x01E1 000C
0x01E1 0010
0x01E1 0014
0x01E1 0018
0x01E1 001C
0x01E1 0020
0x01E1 0024
01E1 0028
-
Reserved
GPIO_EN
GPIO_DIR1
GPIO_DAT1
GPIO_DIR2
GPIO_DAT2
GPIO_DIR3
GPIO_DAT3
-
General Purpose IO Enable Register
General Purpose IO Direction Register 1
General Purpose IO Data Register 1
General Purpose IO Direction Register 2
General Purpose IO Data Register 2
General Purpose IO Direction Register 3
General Purpose IO Data Register 3
Reserved
01E1 002C
-
Reserved
The Host and the CPU both
have read/write access to the
HPIC register.
01E1 0030
01E1 0034
HPIC
HPI control register
HPIA
HPI address register
(Write)
The Host has read/write
access to the HPIA registers.
The CPU has only read
(HPIAW)(1)
HPIA
HPI address register
(Read)
01E1 0038
(HPIAR)(1)
access to the HPIA registers.
01E1 000C - 01E1 07FF
-
Reserved
(1) There are two 32-bit HPIA registers: HPIAR for read operations and HPIAW for write operations. The HPI can be configured such that
HPIAR and HPIAW act as a single 32-bit HPIA (single-HPIA mode) or as two separate 32-bit HPIAs (dual-HPIA mode) from the
perspective of the Host. The CPU can access HPIAW and HPIAR independently.
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5.28.3 HPI Electrical Data/Timing
Table 5-101. Timing Requirements for Host-Port Interface Cycles(1) (2)
No.
1
PARAMETER
MIN MAX UNIT
tsu(SELV-HSTBL)
th(HSTBL-SELV)
tw(HSTBL)
Setup time, select signals(3) valid before UHPI_HSTROBE low
Hold time, select signals(3) valid after UHPI_HSTROBE low
Pulse duration, UHPI_HSTROBE active low
5
2
ns
ns
ns
ns
ns
ns
ns
ns
2
3
15
2M
5
4
tw(HSTBH)
Pulse duration, UHPI_HSTROBE inactive high between consecutive accesses
Setup time, selects signals valid before UHPI_HAS low
Hold time, select signals valid after UHPI_HAS low
Setup time, host data valid before UHPI_HSTROBE high
Hold time, host data valid after UHPI_HSTROBE high
9
tsu(SELV-HASL)
th(HASL-SELV)
tsu(HDV-HSTBH)
th(HSTBH-HDV)
10
11
12
2
5
2
Hold time, UHPI_HSTROBE high after UHPI_HRDY low. UHPI_HSTROBE should
not be inactivated until UHPI_HRDY is active (low); otherwise, HPI writes will not
complete properly.
13
th(HRDYL-HSTBH)
2
ns
16
17
tsu(HASL-HSTBL)
th(HSTBL-HASH)
Setup time, UHPI_HAS low before UHPI_HSTROBE low
Hold time, UHPI_HAS low after UHPI_HSTROBE low
2
2
ns
ns
(1) UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(UHPI_HDS1 XOR
UHPI_HDS2)] OR UHPI_HCS.
(2) M=SYSCLK2 period (CPU clock frequency)/2 in ns. For example, when running parts at 300 MHz, use M=6.67 ns.
(3) Select signals include: UHPI_HCNTL[1:0], UHPI_HRW and UHPI_HHWIL.
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Table 5-102. Switching Characteristics for Host-Port Interface Cycles(1) (2) (3)
PARAMETER
MIN MAX UNIT
For HPI Write, UHPI_HRDY can go high (not
ready) for these HPI Write conditions;
otherwise, UHPI_HRDY stays low (ready):
Case 1: Back-to-back HPIA writes (can be
either first or second half-word)
Case 2: HPIA write following a PREFETCH
command (can be either first or second half-
word)
Case 3: HPID write when FIFO is full or
flushing (can be either first or second half-
word)
Case 4: HPIA write and Write FIFO not empty
For HPI Read, UHPI_HRDY can go high (not
ready) for these HPI Read conditions:
Case 1: HPID read (with auto-increment) and
data not in Read FIFO (can only happen to
first half-word of HPID access)
Delay time,
UHPI_HSTROBE low to
UHPI_HRDY valid
5
td(HSTBL-HRDYV)
12
ns
Case 2: First half-word access of HPID Read
without auto-increment
For HPI Read, UHPI_HRDY stays low (ready)
for these HPI Read conditions:
Case 1: HPID read with auto-increment and
data is already in Read FIFO (applies to either
half-word of HPID access)
Case 2: HPID read without auto-increment
and data is already in Read FIFO (always
applies to second half-word of HPID access)
Case 3: HPIC or HPIA read (applies to either
half-word access)
5a
6
td(HASL-HRDYV)
ten(HSTBL-HDLZ)
td(HRDYL-HDV)
toh(HSTBH-HDV)
tdis(HSTBH-HDHZ)
Delay time, UHPI_HAS low to UHPI_HRDY valid
Enable time, HD driven from UHPI_HSTROBE low
Delay time, UHPI_HRDY low to HD valid
13
0
2
ns
ns
ns
ns
7
8
Output hold time, HD valid after UHPI_HSTROBE high
Disable time, HD high-impedance from UHPI_ HSTROBE high
1.5
14
12
For HPI Read. Applies to conditions where
data is already residing in HPID/FIFO:
Case 1: HPIC or HPIA read
Delay time,
UHPI_HSTROBE low to HD valid
Case 2: First half-word of HPID read with
auto-increment and data is already in Read
FIFO
15
td(HSTBL-HDV)
15
ns
Case 3: Second half-word of HPID read with
or without auto-increment
For HPI Write, UHPI_HRDY can go high (not
ready) for these HPI Write conditions;
otherwise, UHPI_HRDY stays low (ready):
Case 1: HPID write when Write FIFO is full
(can happen to either half-word)
Delay time,
UHPI_HSTROBE high to
UHPI_HRDY valid
18
td(HSTBH-HRDYV)
12
ns
Case 2: HPIA write (can happen to either half-
word)
Case 3: HPID write without auto-increment
(only happens to second half-word)
(1) M=SYSCLK2 period (CPU clock frequency)/2 in ns.
(2) UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(UHPI_HDS1 XOR
UHPI_HDS2)] OR UHPI_HCS.
(3) By design, whenever UHPI_HCS is driven inactive (high), HPI will drive UHPI_HRDY active (low).
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UHPI_HCS
(D)
UHPI_HAS
2
2
1
1
1
1
UHPI_HCNTL[1:0]
2
2
2
1
UHPI_HR/W
2
1
UHPI_HHWIL
4
3
3
(A)(C)
UHPI_HSTROBE
15
6
15
14
14
8
6
8
UHPI_HD[15:0]
(output)
13
7
1st Half-Word
2nd Half-Word
5
(B)
UHPI_HRDY
A. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2:
[NOT(UHPI_HDS1 XOR UHPI_HDS2)] OR UHPI_HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-
incrementing) and the state of the FIFO, transitions on UHPI_HRDY may or may not occur.
C. UHPI_HCS reflects typical UHPI_HCS behavior when UHPI_HSTROBE assertion is caused by UHPI_HDS1 or
UHPI_HDS2. UHPI_HCS timing requirements are reflected by parameters for UHPI_HSTROBE.
D. The diagram above assumes UHPI_HAS has been pulled high.
Figure 5-67. UHPI Read Timing (UHPI_HAS Not Used, Tied High)
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(A)
UHPI_HAS
17
17
10
9
10
9
UHPI_HCNTL[1:0]
UHPI_HR/W
10
10
10
9
9
9
10
9
UHPI_HHWIL
4
3
(B)
UHPI_HSTROBE
16
16
UHPI_HCS
14
14
6
8
15
8
UHPI_HD[15:0]
(output)
1st Half-Word
2nd Half-Word
5a
7
UHPI_HRDY
A. For correct operation, strobe the UHPI_HAS signal only once per UHPI_HSTROBE active cycle.
B. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2:
[NOT(UHPI_HDS1 XOR UHPI_HDS2)] OR UHPI_HCS.
Figure 5-68. UHPI Read Timing (UHPI_HAS Used)
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UHPI_HCS
(D)
UHPI_HAS
1
1
1
1
2
2
2
UHPI_HCNTL[1:0]
1
2
UHPI_HR/W
1
2
2
3
UHPI_HHWIL
3
4
(A)(C)
UHPI_HSTROBE
11
11
12
12
2nd Half-Word
18
UHPI_HD[15:0]
(input)
1st Half-Word
5
18
13
13
5
(B)
UHPI_HRDY
A. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2:
[NOT(UHPI_HDS1 XOR UHPI_HDS2)] OR UHPI_HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-
incrementing) and the state of the FIFO, transitions on UHPI_HRDY may or may not occur.
C. UHPI_HCS reflects typical UHPI_HCS behavior when UHPI_HSTROBE assertion is caused by UHPI_HDS1 or
UHPI_HDS2. UHPI_HCS timing requirements are reflected by parameters for UHPI_HSTROBE.
D. he diagram above assumes UHPI_HAS has been pulled high.
Figure 5-69. UHPI Write Timing (UHPI_HAS Not Used, Tied High)
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17
10
17
(A)
UHPI_HAS
10
9
9
9
9
UHPI_HCNTL[1:0]
UHPI_HR/W
10
10
10
9
10
9
UHPI_HHWIL
3
4
(B)
UHPI_HSTROBE
16
16
UHPI_HCS
11
11
12
12
UHPI_HD[15:0]
(input)
1st Half-Word
2nd Half-Word
5a
13
UHPI_HRDY
A. For correct operation, strobe the UHPI_HAS signal only once per UHPI_HSTROBE active cycle.
B. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2:
[NOT(UHPI_HDS1 XOR UHPI_HDS2)] OR UHPI_HCS.
Figure 5-70. UHPI Write Timing (UHPI_HAS Used)
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5.29 Power and Sleep Controller (PSC)
The Power and Sleep Controllers (PSC) are responsible for managing transitions of system power on/off,
clock on/off, resets (device level and module level). It is used primarily to provide granular power control
for on chip modules (peripherals and CPU). A PSC module consists of a Global PSC (GPSC) and a set of
Local PSCs (LPSCs). The GPSC contains memory mapped registers, PSC interrupts, a state machine for
each peripheral/module it controls. An LPSC is associated with every module that is controlled by the PSC
and provides clock and reset control.
The PSC includes the following features:
•
Provides a software interface to:
–
–
–
Control module clock enable/disable
Control module reset
Control CPU local reset
•
Supports ICEpick TAP Router power, clock and reset features. For details on ICEpick features see
http://tiexpressdsp.com/wiki/index.php?title=ICEPICK.
Table 5-103. Power and Sleep Controller (PSC) Registers
PSC0
PSC1
ACRONYM
REGISTER DESCRIPTION
BYTE ADDRESS
0x01C1 0000
0x01C1 0018
0x01C1 0040
BYTE ADDRESS
0x01E2 7000
0x01E2 7018
0x01E2 7040
REVID
INTEVAL
MERRPR0
Peripheral Revision and Class Information Register
Interrupt Evaluation Register
Module Error Pending Register 0 (module 0-15) (PSC0)
Module Error Pending Register 0 (module 0-31) (PSC1)
Module Error Clear Register 0 (module 0-15) (PSC0)
Module Error Clear Register 0 (module 0-31) (PSC1)
Power Error Pending Register
0x01C1 0050
0x01E2 7050
MERRCR0
0x01C1 0060
0x01C1 0068
0x01C1 0120
0x01C1 0128
0x01C1 0200
0x01C1 0204
0x01C1 0300
0x01C1 0304
0x01C1 0400
0x01C1 0404
0x01E2 7060
0x01E2 7068
0x01E2 7120
0x01E2 7128
0x01E2 7200
0x01E2 7204
0x01E2 7300
0x01E2 7304
0x01E2 7400
0x01E2 7404
PERRPR
PERRCR
Power Error Clear Register
PTCMD
Power Domain Transition Command Register
Power Domain Transition Status Register
Power Domain 0 Status Register
PTSTAT
PDSTAT0
PDSTAT1
Power Domain 1 Status Register
PDCTL0
Power Domain 0 Control Register
PDCTL1
Power Domain 1 Control Register
PDCFG0
Power Domain 0 Configuration Register
Power Domain 1 Configuration Register
Module Status n Register (modules 0-15) (PSC0)
Module Status n Register (modules 0-31) (PSC1)
Module Control n Register (modules 0-15) (PSC0)
Module Control n Register (modules 0-31) (PSC1)
PDCFG1
0x01C1 0800 -
0x01C1 083C
0x01E2 7800 -
0x01E2 787C
MDSTAT0-MDSTAT15
MDSTAT0-MDSTAT31
MDCTL0-MDCTL15
MDCTL0-MDCTL31
0x01C1 0A00 -
0x01C1 0A3C
0x01E2 7A00 -
0x01E2 7A7C
5.29.1 Power Domain and Module Topology
The SoC includes two PSC modules.
Each PSC module controls clock states for several of the on chip modules, controllers and interconnect
components. Table 5-104 and Table 5-105 lists the set of peripherals/modules that are controlled by the
PSC, the power domain they are associated with, the LPSC assignment and the default (power-on reset)
module states. The module states and terminology are defined in Section 5.29.1.2.
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Table 5-104. PSC0 Default Module Configuration
LPSC
Module Name
Power Domain
Default Module State
Auto Sleep/Wake Only
Number
0
EDMA3 Channel Controller
EDMA3 Transfer Controller 0
EDMA3 Transfer Controller 1
EMIFA (BR7)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
—
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
Enable
—
1
—
2
—
3
—
4
SPI 0
—
5
MMC/SD 0
—
6
ARM Interrupt Controller
ARM RAM/ROM
Not Used
—
7
Yes
—
8
—
9
UART 0
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
PD_DSP (PD1)
SwRstDisable
Enable
—
10
11
12
13
14
15
SCR0 (Br 0, Br 1, Br 2, Br 8)
SCR1 (Br 4)
Yes
Yes
Yes
—
Enable
SCR2 (Br 3, Br 5, Br 6)
PRUSS
Enable
SwRstDisable
SwRstDisable
Enable
ARM
—
DSP
—
Table 5-105. PSC1 Default Module Configuration
LPSC
Module Name
Power Domain
Default Module State
Auto Sleep/Wake Only
Number
0
Not Used
—
—
—
1
USB0 (USB2.0)
USB1 (USB1.1)
GPIO
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
—
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
—
—
2
—
3
—
4
UHPI
—
5
EMAC
—
6
EMIFB (Br 20)
McASP0 ( + McASP0 FIFO)
McASP1 ( + McASP1 FIFO)
McASP2( + McASP2 FIFO)
SPI 1
—
7
—
8
—
9
—
10
11
12
13
14-15
16
17
18-19
20
21
22-23
24
25
26
27-30
31
—
I2C 1
—
UART 1
—
UART 2
—
Not Used
—
LCDC
AlwaysON (PD0)
AlwaysON (PD0)
—
SwRstDisable
SwRstDisable
—
—
eHRPWM0/1/2
Not Used
—
—
ECAP0/1/2
AlwaysON (PD0)
AlwaysON (PD0)
—
SwRstDisable
SwRstDisable
—
—
EQEP0/1
—
Not Used
—
SCR8 (Br 15)
SCR7 (Br 12)
SCR12 (Br 18)
Not Used
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
—
Enable
Yes
Yes
Yes
—
Enable
Enable
—
Shared RAM (Br 13)
PD_SHRAM
Enable
Yes
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5.29.1.1 Power Domain States
A power domain can only be in one of the two states: ON or OFF, defined as follows:
•
•
ON: power to the domain is on
OFF: power to the domain is off
In the device, for both PSC0 and PSC1, the Always ON domain, or PD0 power domain, is always in the
ON state when the chip is powered-on. This domain is not programmable to OFF state.
•
•
On PSC0 PD1/PD_DSP Domain: Controls the sleep state for DSP L1 and L2 Memories
On PSC1 PD1/PD_SHRAM Domain: Controls the sleep state for the 128K Shared RAM
5.29.1.2 Module States
The PSC defines several possible states for a module. This states are essentially a combination of the
module reset asserted or de-asserted and module clock on/enabled or off/disabled. The module states are
defined in Table 5-106.
Table 5-106. Module States
Module State
Module Reset
Module Clock
Module State Definition
Enable
De-asserted
On
A module in the enable state has its module reset de-asserted and it has its
clock on. This is the normal operational state for a given module
Disable
De-asserted
Off
A module in the disabled state has its module reset de-asserted and it has its
module clock off. This state is typically used for disabling a module clock to
save power. The SoC is designed in full static CMOS, so when you stop a
module clock, it retains the module’s state. When the clock is restarted, the
module resumes operating from the stopping point.
SyncReset
Asserted
Asserted
On
Off
A module state in the SyncReset state has its module reset asserted and it has
its clock on. Generally, software is not expected to initiate this state
SwRstDisable
A module in the SwResetDisable state has its module reset asserted and it has
its clock disabled. After initial power-on, several modules come up in the
SwRstDisable state. Generally, software is not expected to initiate this state
Auto Sleep
De-asserted
Off
A module in the Auto Sleep state also has its module reset de-asserted and its
module clock disabled, similar to the Disable state. However this is a special
state, once a module is configured in this state by software, it can
“automatically” transition to “Enable” state whenever there is an internal
read/write request made to it, and after servicing the request it will
“automatically” transition into the sleep state (with module reset re de-asserted
and module clock disabled), without any software intervention. The transition
from sleep to enabled and back to sleep state has some cycle latency
associated with it. It is not envisioned to use this mode when peripherals are
fully operational and moving data.
Auto Wake
De-asserted
Off
A module in the Auto Wake state also has its module reset de-asserted and its
module clock disabled, similar to the Disable state. However this is a special
state, once a module is configured in this state by software, it will
“automatically” transition to “Enable” state whenever there is an internal
read/write request made to it, and will remain in the “Enabled” state from then
on (with module reset re de-asserted and module clock on), without any
software intervention. The transition from sleep to enabled state has some
cycle latency associated with it. It is not envisioned to use this mode when
peripherals are fully operational and moving data.
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5.30 Programmable Real-Time Unit Subsystem (PRUSS)
The Programmable Real-Time Unit Subsystem (PRUSS) consists of
•
•
Two Programmable Real-Time Units (PRU0 and PRU1) and their associated memories
An Interrupt Controller (INTC) for handling system interrupt events. The INTC also supports posting
events back to the device level host CPU.
•
A Switched Central Resource (SCR) for connecting the various internal and external masters to the
resources inside the PRUSS.
The two PRUs can operate completely independently or in coordination with each other. The PRUs can
also work in coordination with the device level host CPU. This is determined by the nature of the program
which is loaded into the PRUs instruction memory. Several different signaling mechanisms are available
between the two PRUs and the device level host CPU.
The PRUs are optimized for performing embedded tasks that require manipulation of packed memory
mapped data structures, handling of system events that have tight realtime constraints and interfacing with
systems external to the device.
The PRUSS comprises various distinct addressable regions. Externally the subsystem presents a single
64Kbyte range of addresses. The internal interconnect bus (also called switched central resource, or SCR)
of the PRUSS decodes accesses for each of the individual regions. The PRUSS memory map is
documented in Table 5-107 and in Table 5-108. Note that these two memory maps are implemented
inside the PRUSS and are local to the components of the PRUSS.
Table 5-107. Programmable Real-Time Unit Subsystem (PRUSS) Local Instruction Space Memory Map
BYTE ADDRESS
PRU0
PRU1
0x0000 0000 - 0x0000 0FFF
PRU0 Instruction RAM
PRU1 Instruction RAM
Table 5-108. Programmable Real-Time Unit Subsystem (PRUSS) Local Data Space Memory Map
BYTE ADDRESS
PRU0
Data RAM 0
Reserved
PRU1
Data RAM 1
Reserved
(1)
(1)
(1)
(1)
0x0000 0000 - 0x0000 01FF
0x0000 0200 - 0x0000 1FFF
0x0000 2000 - 0x0000 21FF
0x0000 2200 - 0x0000 3FFF
0x0000 4000 - 0x0000 6FFF
0x0000 7000 - 0x0000 73FF
0x0000 7400 - 0x0000 77FF
0x0000 7800 - 0x0000 7BFF
0x0000 7C00 - 0xFFFF FFFF
Data RAM 1
Reserved
Data RAM 0
Reserved
INTC Registers
PRU0 Control Registers
Reserved
INTC Registers
PRU0 Control Registers
Reserved
PRU1 Control Registers
Reserved
PRU1 Control Registers
Reserved
(1) Note that PRU0 accesses Data RAM0 at address 0x0000 0000, also PRU1 accesses Data RAM1 at address 0x0000 0000. Data RAM0
is intended to be the primary data memory for PRU0 and Data RAM1 is intended to be the primary data memory for PRU1. However for
passing information between PRUs, each PRU can access the data ram of the ‘other’ PRU through address 0x0000 2000.
The global view of the PRUSS internal memories and control ports is documented in Table 5-109. The
offset addresses of each region are implemented inside the PRUSS but the global device memory
mapping places the PRUSS slave port in the address range 0x01C3 0000-0x01C3 FFFF. The PRU0 and
PRU1 can use either the local or global addresses to access their internal memories, but using the local
addresses will provide access time several cycles faster than using the global addresses. This is because
when accessing via the global address the access needs to be routed through the switch fabric outside
PRUSS and back in through the PRUSS slave port.
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Table 5-109. Programmable Real-Time Unit Subsystem (PRUSS) Global Memory Map
BYTE ADDRESS
REGION
Data RAM 0
0x01C3 0000 - 0x01C3 01FF
0x01C3 0200 - 0x01C3 1FFF
0x01C3 2000 - 0x01C3 21FF
0x01C3 2200 - 0x01C3 3FFF
0x01C3 4000 - 0x01C3 6FFF
0x01C3 7000 - 0x01C3 73FF
0x01C3 7400 - 0x01C3 77FF
0x01C3 7800 - 0x01C3 7BFF
0x01C3 7C00 - 0x01C3 7FFF
0x01C3 8000 - 0x01C3 8FFF
0x01C3 9000 - 0x01C3 BFFF
0x01C3 C000 - 0x01C3 CFFF
0x01C3 D000 - 0x01C3 FFFF
Reserved
Data RAM 1
Reserved
INTC Registers
PRU0 Control Registers
PRU0 Debug Registers
PRU1 Control Registers
PRU1 Debug Registers
PRU0 Instruction RAM
Reserved
PRU1 Instruction RAM
Reserved
Each of the PRUs can access the rest of the device memory (including memory mapped peripheral and
configuration registers) using the global memory space addresses.
5.30.1 PRUSS Register Descriptions
Table 5-110. Programmable Real-Time Unit Subsystem (PRUSS) Control / Status Registers
PRU0 BYTE ADDRESS
0x01C3 7000
PRU1 BYTE ADDRESS
0x01C3 7800
ACRONYM
CONTROL
STATUS
REGISTER DESCRIPTION
PRU Control Register
PRU Status Register
0x01C3 7004
0x01C3 7804
0x01C3 7008
0x01C3 7808
WAKEUP
CYCLCNT
STALLCNT
PRU Wakeup Enable Register
PRU Cycle Count
0x01C3 700C
0x01C3 780C
0x01C3 7010
0x01C3 7810
PRU Stall Count
PRU Constant Table Block Index
Register 0
0x01C3 7020
0x01C3 7028
0x01C3 7820
0x01C3 7828
CONTABBLKIDX0
CONTABPROPTR0
PRU Constant Table Programmable
Pointer Register 0
PRU Constant Table Programmable
Pointer Register 1
0x01C3 702C
0x01C3 782C
CONTABPROPTR1
PRU Internal General Purpose
Register 0 (for Debug)
0x01C37400 - 0x01C3747C
0x01C37480 - 0x01C374FC
0x01C3 7C00 - 0x01C3 7C7C
0x01C3 7C80 - 0x01C3 7CFC
INTGPR0 – INTGPR31
INTCTER0 – INTCTER31
PRU Internal General Purpose
Register 0 (for Debug)
Table 5-111. Programmable Real-Time Unit Subsystem Interrupt Controller (PRUSS INTC) Registers
BYTE ADDRESS
0x01C3 4000
0x01C3 4004
0x01C3 4010
0x01C3 401C
0x01C3 4020
0x01C3 4024
0x01C3 4028
0x01C3 402C
0x01C3 4034
0x01C3 4038
ACRONYM
REVID
REGISTER DESCRIPTION
Revision ID Register
CONTROL
Control Register
GLBLEN
Global Enable Register
GLBLNSTLVL
STATIDXSET
STATIDXCLR
ENIDXSET
Global Nesting Level Register
System Interrupt Status Indexed Set Register
System Interrupt Status Indexed Clear Register
System Interrupt Enable Indexed Set Register
System Interrupt Enable Indexed Clear Register
Host Interrupt Enable Indexed Set Register
Host Interrupt Enable Indexed Clear Register
ENIDXCLR
HSTINTENIDXSET
HSTINTENIDXCLR
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Table 5-111. Programmable Real-Time Unit Subsystem Interrupt Controller (PRUSS INTC)
Registers (continued)
BYTE ADDRESS
0x01C3 4080
ACRONYM
GLBLPRIIDX
REGISTER DESCRIPTION
Global Prioritized Index Register
0x01C3 4200
STATSETINT0
System Interrupt Status Raw/Set Register 0
System Interrupt Status Raw/Set Register 1
System Interrupt Status Enabled/Clear Register 0
System Interrupt Status Enabled/Clear Register 1
System Interrupt Enable Set Register 0
System Interrupt Enable Set Register 1
System Interrupt Enable Clear Register 0
System Interrupt Enable Clear Register 1
Channel Map Registers 0-15
0x01C3 4204
STATSETINT1
0x01C3 4280
STATCLRINT0
0x01C3 4284
STATCLRINT1
0x01C3 4300
ENABLESET0
0x01C3 4304
ENABLESET1
0x01C3 4380
ENABLECLR0
0x01C3 4384
ENABLECLR1
0x01C3 4400 - 0x01C3 4440
0x01C3 4800 - 0x01C3 4808
CHANMAP0 - CHANMAP15
HOSTMAP0 - HOSTMAP2
Host Map Register 0-2
HOSTINTPRIIDX0 -
HOSTINTPRIIDX9
0x01C3 4900 - 0x01C3 4928
Host Interrupt Prioritized Index Registers 0-9
0x01C3 4D00
0x01C3 4D04
0x01C3 4D80
0x01C3 4D84
POLARITY0
POLARITY1
TYPE0
System Interrupt Polarity Register 0
System Interrupt Polarity Register 1
System Interrupt Type Register 0
System Interrupt Type Register 1
TYPE1
HOSTINTNSTLVL0-
HOSTINTNSTLVL9
0x01C3 5100 - 0x01C3 5128
0x01C3 5500
Host Interrupt Nesting Level Registers 0-9
Host Interrupt Enable Register
HOSTINTEN
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5.31 Emulation Logic
This section describes the steps to use a third party debugger. The debug capabilities and features for
DSP and ARM are as shown below.
For TI’s latest debug and emulation information see :
http://tiexpressdsp.com/wiki/index.php?title=Category:Emulation
DSP:
•
•
•
Basic Debug
–
–
Execution Control
System Visibility
Real-Time Debug
–
–
Interrupts serviced while halted
Low/non-intrusive system visibility while running
Advanced Debug
–
–
–
–
Global Start
Global Stop
Specify targeted memory level(s) during memory accesses
HSRTDX (High Speed Real Time Data eXchange)
•
•
Advanced System Control
–
–
–
Subsystem reset via debug
Peripheral notification of debug events
Cache-coherent debug accesses
Analysis Actions
–
–
–
–
–
–
Stop program execution
Generate debug interrupt
Benchmarking with counters
External trigger generation
Debug state machine state transition
Combinational and Sequential event generation
•
•
Analysis Events
–
–
–
–
–
Program event detection
Data event detection
External trigger Detection
System event detection (i.e. cache miss)
Debug state machine state detection
Analysis Configuration
–
–
Application access
Debugger access
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Table 5-112. DSP Debug Features
Hardware Feature
Availability
Unlimited
Software breakpoint
Up to 10 HWBPs, including:
4 precise(1) HWBPs inside DSP core and one of them is
associated with a counter.
2 imprecise(1) HWBPs from AET.
4 imprecise(1) HWBPs from AET which are shared for
watch point.
Basic Debug
Hardware breakpoint
Watch point
Up to 4 watch points, which are shared with HWBPs,
and can also be used as 2 watch points with data (32
bits)
Watch point with Data
Counters/timers
Up to 2, Which can also be used as 4 watch points.
Analysis
1x64-bits (cycle only) + 2x32-bits (watermark counters)
External Event Trigger In
External Event Trigger Out
1
1
(1) Precise hardware breakpoints will halt the processor immediately prior to the execution of the selected instruction. Imprecise breakpoints
will halt the processor some number of cycles after the selected instruction depending on device conditions.
ARM:
•
•
•
Basic Debug
–
–
Execution Control
System Visibility
Advanced Debug
–
–
Global Start
Global Stop
Advanced System Control
–
–
–
Subsystem reset via debug
Peripheral notification of debug events
Cache-coherent debug accesses
•
Program Trace
–
–
–
–
Program flow corruption
Code coverage
Path coverage
Thread/interrupt synchronization problems
•
•
•
Data Trace
–
Memory corruption
Timing Trace
–
Profiling
Analysis Actions
–
–
–
–
–
–
–
Stop program execution
Control trace streams
Generate debug interrupt
Benchmarking with counters
External trigger generation
Debug state machine state transition
Combinational and Sequential event generation
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•
Analysis Events
–
–
–
–
–
Program event detection
Data event detection
External trigger Detection
System event detection (i.e. cache miss)
Debug state machine state detection
•
Analysis Configuration
–
–
Application access
Debugger access
Table 5-113. ARM Debug Features
Category
Hardware Feature
Availability
Unlimited
Software breakpoint
Hardware breakpoint
Up to 14 HWBPs, including:
2 precise(1) HWBP inside ARM core which are shared
with watch points.
8 imprecise(1) HWBPs from ETM’s address comparators,
which are shared with trace function, and can be used
as watch point too.
Basic Debug
4 imprecise(1) HWBPs from ICECrusher.
Up to 6 watch points, including:
2 from ARM core which is shared with HWBPs and can
be associated with a data.
Watch point
8 from ETM’s address comparators, which are shared
with trace function, and HWBPs.
2 from ARM core which is shared with HWBPs.
Analysis
Watch point with Data
8 watch points from ETM can be associated with a data
comparator, and ETM has total 4 data comparators.
Counters/timers
3x32-bit (1 cycle ; 2 event)
External Event Trigger In
External Event Trigger Out
Internal Cross-Triggering Signals
Address range for trace
1
1
One between ARM and DSP
4
Data qualification for trace
System events for trace control
Counters/Timers for trace control
State Machines/Sequencers
Context/Thread ID Comparator
Independent trigger control units
Capture depth PC
2
20
Trace Control
2x16-bit
1x3-State State Machine
1
12
4k bytes ETB
4k bytes ETB
Y
On-chip Trace
Capture
Capture depth PC + Timing
Application accessible
(1) Precise hardware breakpoints will halt the processor immediately prior to the execution of the selected instruction. Imprecise breakpoints
will halt the processor some number of cycles after the selected instruction depending on device conditions.
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5.31.1 JTAG Port Description
The device target debug interface uses the five standard IEEE 1149.1(JTAG) signals (TRST, TCK, TMS,
TDI, and TDO), a return clock (RTCK) due to the clocking requirements of the ARM926EJ-S and EMU[0].
TRST holds the debug and boundary scan logic in reset (normal DSP operation) when pulled low (its
default state). Since TRST has an internal pull-down resistor, this ensures that at power up the device
functions in its normal (non-test) operation mode if TRST is not connected. Otherwise, TRST should be
driven inactive by the emulator or boundary scan controller. Boundary scan test cannot be performed
while the TRST pin is pulled low.
Table 5-114. JTAG Port Description
PIN
TYPE
NAME
DESCRIPTION
When asserted (active low) causes all test and debug logic in the device
to be reset along with the IEEE 1149.1 interface
TRST
I
Test Logic Reset
This is the test clock used to drive an IEEE 1149.1 TAP state machine
and logic. Depending on the emulator attached to , this is a free running
clock or a gated clock depending on RTCK monitoring.
TCK
I
Test Clock
Synchronized TCK. Depending on the emulator attached to, the JTAG
signals are clocked from RTCK or RTCK is monitored by the emulator to
gate TCK.
RTCK
O
Returned Test Clock
TMS
TDI
I
I
Test Mode Select
Test Data Input
Test Data Output
Emulation 0
Directs the next state of the IEEE 1149.1 test access port state machine
Scan data input to the device
TDO
O
I/O
Scan data output of the device
EMU[0]
Channel 0 trigger + HSRTDX
5.31.2 Scan Chain Configuration Parameters
Table 5-115 shows the TAP configuration details required to configure the router/emulator for this device.
Table 5-115. JTAG Port Description
Router Port ID
Default TAP
TAP Name
C674x
Tap IR Length
17
18
19
No
No
No
38
4
ARM926
ETB
4
The router is ICEpick revision C and has a 6-bit IR length.
5.31.3 Initial Scan Chain Configuration
The first level of debug interface that sees the scan controller is the TAP router module. The debugger
can configure the TAP router for serially linking up to 16 TAP controllers or individually scanning one of
the TAP controllers without disrupting the IR state of the other TAPs.
5.31.3.1 Adding TAPS to the Scan Chain
The TAP router must be programmed to add additional TAPs to the scan chain. The following JTAG scans
must be completed to add the ARM926EJ-S to the scan chain.
A Power-On Reset (POR) or the JTAG Test-Logic Reset state configures the TAP router to contain only
the router’s TAP.
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TDO
TDI
Router
CLK
TMS
Steps
Router
ARM926EJ-S/ETM
Figure 5-71. Adding ARM926EJ-S to the scan chain
Pre-amble: The device whose data reaches the emulator first is listed first in the board configuration file.
This device is a pre-amble for all the other devices. This device has the lowest device ID.
Post-amble: The device whose data reaches the emulator last is listed last in the board configuration file.
This device is a post-amble for all the other devices. This device has the highest device ID.
•
•
•
•
•
Function : Update the JTAG preamble and post-amble counts.
–
–
–
–
–
–
Parameter : The IR pre-amble count is '0'.
Parameter : The IR post-amble count is '0'.
Parameter : The DR pre-amble count is '0'.
Parameter : The DR post-amble count is '0'.
Parameter : The IR main count is '6'.
Parameter : The DR main count is '1'.
Function : Do a send-only JTAG IR/DR scan.
–
–
–
–
–
–
Parameter : The route to JTAG shift state is 'shortest transition'.
Parameter : The JTAG shift state is 'shift-ir'.
Parameter : The JTAG destination state is 'pause-ir'.
Parameter : The bit length of the command is '6'.
Parameter : The send data value is '0x00000007'.
Parameter : The actual receive data is 'discarded'.
Function : Do a send-only JTAG IR/DR scan.
–
–
–
–
–
–
Parameter : The route to JTAG shift state is 'shortest transition'.
Parameter : The JTAG shift state is 'shift-dr'.
Parameter : The JTAG destination state is 'pause-dr'.
Parameter : The bit length of the command is '8'.
Parameter : The send data value is '0x00000089'.
Parameter : The actual receive data is 'discarded'.
Function : Do a send-only JTAG IR/DR scan.
–
–
–
–
–
–
Parameter : The route to JTAG shift state is 'shortest transition'.
Parameter : The JTAG shift state is 'shift-ir'.
Parameter : The JTAG destination state is 'pause-ir'.
Parameter : The bit length of the command is '6'.
Parameter : The send data value is '0x00000002'.
Parameter : The actual receive data is 'discarded'.
Function : Embed the port address in next command.
–
–
Parameter : The port address field is '0x0f000000'.
Parameter : The port address value is '3'.
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•
Function : Do a send-only JTAG IR/DR scan.
–
–
–
–
–
–
Parameter : The route to JTAG shift state is 'shortest transition'.
Parameter : The JTAG shift state is 'shift-dr'.
Parameter : The JTAG destination state is 'pause-dr'.
Parameter : The bit length of the command is '32'.
Parameter : The send data value is '0xa2002108'.
Parameter : The actual receive data is 'discarded'.
•
Function : Do a send-only all-ones JTAG IR/DR scan.
–
–
–
–
–
Parameter : The JTAG shift state is 'shift-ir'.
Parameter : The JTAG destination state is 'run-test/idle'.
Parameter : The bit length of the command is '6'.
Parameter : The send data value is 'all-ones'.
Parameter : The actual receive data is 'discarded'.
•
•
Function : Wait for a minimum number of TCLK pulses.
Parameter : The count of TCLK pulses is '10'.
Function : Update the JTAG preamble and post-amble counts.
–
–
–
–
–
–
–
Parameter : The IR pre-amble count is '0'.
Parameter : The IR post-amble count is '6'.
Parameter : The DR pre-amble count is '0'.
Parameter : The DR post-amble count is '1'.
Parameter : The IR main count is '4'.
Parameter : The DR main count is '1'.
The initial scan chain contains only the TAP router module. The following steps must be completed in
order to add ETB TAP to the scan chain.
ARM926EJ-S/ETM
TDI
Router
TDO
CLK
TMS
Steps
ETB
ARM926EJ-S/ETM
Router
Figure 5-72. Adding ETB to the scan chain
Function : Do a send-only JTAG IR/DR scan.
•
–
–
–
–
–
–
Parameter : The route to JTAG shift state is 'shortest transition'.
Parameter : The JTAG shift state is 'shift-ir'.
Parameter : The JTAG destination state is 'pause-ir'.
Parameter : The bit length of the command is '6'.
Parameter : The send data value is '0x00000007'.
Parameter : The actual receive data is 'discarded'.
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•
Function : Do a send-only JTAG IR/DR scan.
–
–
–
–
–
–
Parameter : The route to JTAG shift state is 'shortest transition'.
Parameter : The JTAG shift state is 'shift-dr'.
Parameter : The JTAG destination state is 'pause-dr'.
Parameter : The bit length of the command is '8'.
Parameter : The send data value is '0x00000089'.
Parameter : The actual receive data is 'discarded'.
•
Function : Do a send-only JTAG IR/DR scan.
–
–
–
–
–
–
Parameter : The route to JTAG shift state is 'shortest transition'.
Parameter : The JTAG shift state is 'shift-ir'.
Parameter : The JTAG destination state is 'pause-ir'.
Parameter : The bit length of the command is '6'.
Parameter : The send data value is '0x00000002'.
Parameter : The actual receive data is 'discarded'.
•
•
Function : Embed the port address in next command.
–
–
Parameter : The port address field is '0x0f000000'.
Parameter : The port address value is '3'.
Function : Do a send-only JTAG IR/DR scan.
–
–
–
–
–
–
Parameter : The route to JTAG shift state is 'shortest transition'.
Parameter : The JTAG shift state is 'shift-dr'.
Parameter : The JTAG destination state is 'pause-dr'.
Parameter : The bit length of the command is '32'.
Parameter : The send data value is '0xa3302108'.
Parameter : The actual receive data is 'discarded'.
•
Function : Do a send-only all-ones JTAG IR/DR scan.
–
–
–
–
–
Parameter : The JTAG shift state is 'shift-ir'.
Parameter : The JTAG destination state is 'run-test/idle'.
Parameter : The bit length of the command is '6'.
Parameter : The send data value is 'all-ones'.
Parameter : The actual receive data is 'discarded'.
•
•
Function : Wait for a minimum number of TCLK pulses.
Parameter : The count of TCLK pulses is '10'.
Function : Update the JTAG preamble and post-amble counts.
–
–
–
–
–
–
–
Parameter : The IR pre-amble count is '0'.
Parameter : The IR post-amble count is '6 + 4'.
Parameter : The DR pre-amble count is '0'.
Parameter : The DR post-amble count is '1 + 1'.
Parameter : The IR main count is '4'.
Parameter : The DR main count is '1'.
5.31.4 JTAG 1149.1 Boundary Scan Considerations
To use boundary scan, the following sequence should be followed:
•
•
•
Execute a valid reset sequence and exit reset
Wait at least 6000 OSCIN clock cycles
Enter boundary scan mode using the JTAG pins
No specific value is required on the EMU[0] pin for boundary scan testing. If TRST is not driven by the
boundary scan tool or tester, TRST should be externally pulled high during boundary scan testing.
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5.32 IEEE 1149.1 JTAG
The JTAG (1) interface is used for BSDL testing and emulation of the device.
The device requires that both TRST and RESET be asserted upon power up to be properly initialized.
While RESET initializes the device, TRST initializes the device's emulation logic. Both resets are required
for proper operation.
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for
the device to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG
port interface and device's emulation logic in the reset state.
TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or
exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by
TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted.
RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE
correctly. Other boundary-scan instructions work correctly independent of current state of RESET.
For maximum reliability, the device includes an internal pulldown (IPD) on the TRST pin to ensure that
TRST will always be asserted upon power up and the device's internal emulation logic will always be
properly initialized.
JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG
controllers may not drive TRST high but expect the use of a pullup resistor on TRST.
When using this type of JTAG controller, assert TRST to initialize the device after powerup and externally
drive TRST high before attempting any emulation or boundary scan operations.
5.32.1 JTAG Peripheral Register Description(s) – JTAG ID Register (DEVIDR0)
Table 5-116. DEVIDR0 Register
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
JTAG Identification Register
COMMENTS
Read-only. Provides 32-bit
JTAG ID of the device.
0x01C1 4018
DEVIDR0
(1) IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the
device, the JTAG ID register resides at address location 0x01C1 4018. The register hex value for each
silicon revision is:
•
•
•
0x0B7D F02F for silicon revision 1.0
0x8B7D F02F for silicon revision 1.1
0x9B7D F02F for silicon revisions 3.0, 2.1, and 2.0
For the actual register bit names and their associated bit field descriptions, see Figure 5-73 and Table 5-
117.
31-28
VARIANT (4-Bit)
R-xxxx
27-12
11-1
0
PART NUMBER (16-Bit)
R-1011 0111 1101 1111
MANUFACTURER (11-Bit)
R-0000 0010 111
LSB
R-1
LEGEND: R = Read, W = Write, n = value at reset
Figure 5-73. JTAG ID (DEVIDR0) Register Description - Register Value
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Table 5-117. JTAG ID Register Selection Bit Descriptions
BIT
31:28
27:12
11-1
0
NAME
VARIANT
DESCRIPTION
Variant (4-Bit) value
PART NUMBER
Part Number (16-Bit) value
MANUFACTURER Manufacturer (11-Bit) value
LSB LSB. This bit is read as a "1".
5.32.2 JTAG Test-Port Electrical Data/Timing
Table 5-118. Timing Requirements for JTAG Test Port (see Figure 5-74)
No.
1
PARAMETER
MIN
MAX
UNIT
ns
tc(TCK)
Cycle time, TCK
40
16
16
40
16
16
4
2
tw(TCKH)
Pulse duration, TCK high
Pulse duration, TCK low
Cycle time, RTCK
ns
3
tw(TCKL)
ns
4
tc(RTCK)
ns
5
tw(RTCKH)
tw(RTCKL)
tsu(TDIV-RTCKH)
th(RTCKH-TDIV)
Pulse duration, RTCK high
ns
6
Pulse duration, RTCK low
ns
7
Setup time, TDI/TMS/TRST valid before RTCK high
Hold time, TDI/TMS/TRST valid after RTCK high
ns
8
4
ns
Table 5-119. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port
(see Figure 5-74)
No.
PARAMETER
Delay time, RTCK low to TDO valid
MIN
MAX
UNIT
9
td(RTCKL-TDOV)
15
ns
1
2
3
TCK
RTCK
TDO
4
5
6
9
8
7
TDI/TMS/TRST
Figure 5-74. JTAG Test-Port Timing
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5.33 Real Time Clock (RTC)
The RTC provides a time reference to an application running on the device. The current date and time is
tracked in a set of counter registers that update once per second. The time can be represented in 12-hour
or 24-hour mode. The calendar and time registers are buffered during reads and writes so that updates do
not interfere with the accuracy of the time and date.
Alarms are available to interrupt the CPU at a particular time, or at periodic time intervals, such as once
per minute or once per day. In addition, the RTC can interrupt the CPU every time the calendar and time
registers are updated, or at programmable periodic intervals.
The real-time clock (RTC) provides the following features:
•
•
•
•
•
•
•
•
•
100-year calendar (xx00 to xx99)
Counts seconds, minutes, hours, day of the week, date, month, and year with leap year compensation
Binary-coded-decimal (BCD) representation of time, calendar, and alarm
12-hour clock mode (with AM and PM) or 24-hour clock mode
Alarm interrupt
Periodic interrupt
Single interrupt to the CPU
Supports external 32.768-kHz crystal or external clock source of the same frequency
Separate isolated power supply
Figure 5-75 shows a block diagram of the RTC.
Oscillator
Compensation
Week
Days
Counter
32 kHz
RTC_XI
XTAL
Hours
Days
Years
Seconds
Minutes
Months
RTC_XO
Oscillator
Alarm
Interrupts
Alarm
Periodic
Interrupts
Timer
Figure 5-75. Real-Time Clock Block Diagram
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5.33.1 Clock Source
The clock reference for the RTC is an external 32.768-kHz crystal or an external clock source of the same
frequency. The RTC also has a separate power supply that is isolated from the rest of the system. When
the CPU and other peripherals are without power, the RTC can remain powered to preserve the current
time and calendar information.
The source for the RTC reference clock may be provided by a crystal or by an external clock source. The
RTC has an internal oscillator buffer to support direct operation with a crystal. The crystal is connected
between pins RTC_XI and RTC_XO. RTC_XI is the input to the on-chip oscillator and RTC_XO is the
output from the oscillator back to the crystal. A crystal with 70k-ohm max ESR is recommended. Typical
load capacitance values are 10-20 pF, where the load capacitance is the series combination of C1 and
C2.
An external 32.768-kHz clock source may be used instead of a crystal. In such a case, the clock source is
connected to RTC_XI, and RTC_XO is left unconnected.
If the RTC is not used, the RTC_XI pin should be static held high or low and RTC_XO should be left
unconnected.
RTC
Power
Source
Real Time Clock
RTC_CVDD
C2
RTC_XI
XTAL
32.768
kHz
Real
Time
Clock
(RTC)
Module
RTC_XO
32K
OSC
C1
RTC_VSS
Isolated RTC
Power Domain
Figure 5-76. Clock Source
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5.33.2 Real-Time Clock Registers
Table 5-120 lists the memory-mapped registers for the RTC.
Table 5-120. Real-Time Clock (RTC) Registers
BYTE ADDRESS
0x01C2 3000
0x01C2 3004
0x01C2 3008
0x01C2 300C
0x01C2 3010
0x01C2 3014
0x01C2 3018
0x01C2 3020
0x01C2 3024
0x01C2 3028
0x01C2 302C
0x01C2 3030
0x01C2 3034
0x01C2 3040
0x01C2 3044
0x01C2 3048
0x01C2 304C
0x01C2 3050
0x01C2 3054
0x01C2 3060
0x01C2 3064
0x01C2 3068
0x01C2 306C
0x01C2 3070
ACRONYM
SECOND
MINUTE
REGISTER DESCRIPTION
Seconds Register
Minutes Register
HOUR
Hours Register
DAY
Day of the Month Register
Month Register
MONTH
YEAR
Year Register
DOTW
Day of the Week Register
Alarm Seconds Register
Alarm Minutes Register
Alarm Hours Register
ALARMSECOND
ALARMMINUTE
ALARMHOUR
ALARMDAY
ALARMMONTH
ALARMYEAR
CTRL
Alarm Days Register
Alarm Months Register
Alarm Years Register
Control Register
STATUS
Status Register
INTERRUPT
COMPLSB
COMPMSB
OSC
Interrupt Enable Register
Compensation (LSB) Register
Compensation (MSB) Register
Oscillator Register
SCRATCH0
SCRATCH1
SCRATCH2
KICK0
Scratch 0 (General-Purpose) Register
Scratch 1 (General-Purpose) Register
Scratch 2 (General-Purpose) Register
Kick 0 (Write Protect) Register
Kick 1 (Write Protect) Register
KICK1
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6 Device and Documentation Support
6.1 Device Support
6.1.1 Development Support
TI offers an extensive line of development tools for the OMAP-L13x platform, including tools to evaluate
the performance of the processors, generate code, develop algorithm implementations, and fully integrate
and debug software and hardware modules. The tool's support documentation is electronically available
within the Code Composer Studio™ Integrated Development Environment (IDE).
The following products support development of OMAP-L13x applications:
Software Development Tools:
Code Composer Studio™ Integrated Development Environment (IDE): including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target
software needed to support any application.
Hardware Development Tools:
Extended Development System (XDS™) Emulator
For a complete listing of development-support tools for OMAP-L13x, visit the Texas Instruments web
site on the Worldwide Web at www.ti.com uniform resource locator (URL). For information on pricing
and availability, contact the nearest TI field sales office or authorized distributor.
6.1.2 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
DSP devices and support tools. Each DSP commercial family member has one of three prefixes: X, P, or
NULL (e.g., XOMAPL137). Texas Instruments recommends two of three possible prefix designators for its
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development
from engineering prototypes (X/TMDX) through fully qualified production devices/tools (NULL/TMDS).
Device development evolutionary flow:
X
Experimental device that is not necessarily representative of the final device's electrical
specifications.
P
Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification.
NULL
Fully-qualified production device.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
NULL devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
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TI nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, ZKB), the temperature range (for example, "Blank" is the commercial temperature range),
and the device speed range in megahertz (for example, "Blank" is the default).
Figure 6-1 provides a legend for reading the complete device name for any OMAPL13x member.
( )
( )
X
OMAPL137
ZKB
3
DEVICE SPEED RANGE
3 = 300 Mhz (Revision A)
3 = 375 Mhz (Revision B)
4 = 456 Mhz (Revision B)
PREFIX
X = Experimental Device
P = Prototype Device
Blank = Production Device
TEMPERATURE RANGE (JUNCTION)
DEVICE
Blank = 0°C to 90°C (Commercial Grade)
D = –40°C to 90°C (Industrial Grade)
A = –40°C to 105°C (Extended Grade)
T = –40°C to 125°C (Automotive Grade)
OMAPL137
SILICON REVISION
Blank = Silicon Revision 1.0
A = Silicon Revision 1.1
B = Silicon Revision 2.0
C = Silicon Revision 2.1
D = Silicon Revision 3.0
PACKAGE TYPE
ZKB = 256 Pin Plastic BGA, with Pb-free
Soldered Balls [Green]
Figure 6-1. Device Nomenclature
6.2 Documentation Support
The following documents describe the OMAP-L13x Low-power applications processor. Copies of these
documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box
provided at www.ti.com.
DSP Reference Guides
SPRUFE8
TMS320C674x DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C674x digital signal
processors (DSPs). The C674x DSP is an enhancement of the C64x+ and C67x+ DSPs with
added functionality and an expanded instruction set.
SPRUFK5
TMS320C674x DSP Megamodule Reference Guide. Describes the TMS320C674x digital
signal processor (DSP) megamodule. Included is a discussion on the internal direct memory
access (IDMA) controller, the interrupt controller, the power-down controller, memory
protection, bandwidth management, and the memory and cache.
SPRUH92 OMAP-L1x DSP+ARM Processor Technical Reference Manual. Describes the System-on-
Chip (SoC) and each peripheral in the device.
User's Guides
SPRU186
SPRU187
SPRUG82
TMS320C6000 Assembly Language Tools User's Guide.Describes the assembly
language tools (assembler, linker, and other tools used to develop assembly language code),
assembler directives, macros, common object file format, and symbolic debugging directives
for the TMS320C6000 platform of devices (including the C64x+, C67x+, and C674x
generations).
TMS320C6000 Optimizing Compiler User's Guide. Describes the TMS320C6000 C
compiler and the assembly optimizer. This C compiler accepts ANSI standard C source code
and produces assembly language source code for the TMS320C6000 platform of devices
(including the C64x+, C67x+, and C674x generations). The assembly optimizer helps you
optimize your assembly code.
TMS320C674x DSP Cache User's Guide. Explains the fundamentals of memory caches
and describes how the two-level cache-based internal memory architecture in the
TMS320C674x digital signal processor (DSP) can be efficiently used in DSP applications.
Copyright © 2008–2013, Texas Instruments Incorporated
Device and Documentation Support
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OMAP-L137
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Shows how to maintain coherence with external memory, how to use DMA to reduce
memory latencies, and how to optimize your code to improve cache efficiency. The internal
memory architecture in the C674x DSP is organized in a two-level hierarchy consisting of a
dedicated program cache (L1P) and a dedicated data cache (L1D) on the first level.
Accesses by the CPU to the these first level caches can complete without CPU pipeline
stalls. If the data requested by the CPU is not contained in cache, it is fetched from the next
lower memory level, L2 or external memory.
6.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and
help solve problems with fellow engineers.
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help
developers get started with Embedded Processors from Texas Instruments and to foster
innovation and growth of general knowledge about the hardware and software surrounding
these devices.
218
Device and Documentation Support
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SPRS563F –SEPTEMBER 2008–REVISED FEBRUARY 2013
7 Mechanical Packaging and Orderable Information
This section describes the OMAP-L137 orderable part numbers, packaging options, materials, thermal and
mechanical parameters.
This section contains mechanical drawings for the ZKB Plastic Ball Grid Array package .
7.1 Thermal Data for ZKB
The following table(s) show the thermal resistance characteristics for the PBGA–ZKB mechanical
package.
Table 7-1. Thermal Resistance Characteristics (PBGA Package) [ZKB]
No.
°C/W(1)
°C/W(2)
AIR FLOW
(m/s)(3)
1
2
RΘJC
RΘJB
RΘJA
Junction-to-case
Junction-to-board
Junction-to-free air
12.8
15.1
24.5
21.9
21.1
20.4
19.6
0.6
13.5
19.7
33.8
30
N/A
N/A
3
0.00
0.50
1.00
2.00
4.00
0.00
0.50
1.00
2.00
4.00
0.00
0.50
1.00
2.00
4.00
4
5
28.7
27.4
26
RΘJMA
Junction-to-moving air
6
7
8
0.8
9
0.8
1
10
11
12
13
14
15
16
17
PsiJT
Junction-to-package top
0.9
1.2
1.1
1.4
1.3
1.8
14.9
14.4
14.4
14.3
14.1
19.1
18.2
18
PsiJB
Junction-to-board
17.7
17.4
(1) These measurements were conducted in a JEDEC defined 2S2P system and will change based on environment as well as application.
For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment
Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount
Packages. Power dissipation of 1W and ambient temp of 70C assumed. PCB with 2oz (70um) top and bottom copper thickness and
1.5oz (50um) inner copper thickness
(2) Simulation data, using the same model but with 1oz (35um) top and bottom copper thickness and 0.5oz (18um) inner copper thickness.
Power dissipation of 1W and ambient temp of 70C assumed.
(3) m/s = meters per second
7.2 Packaging Information
The following packaging information and addendum reflect the most current data available for the
designated device(s). This data is subject to change without notice and without revision of this document.
Copyright © 2008–2013, Texas Instruments Incorporated
Mechanical Packaging and Orderable Information
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219
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2013
PACKAGING INFORMATION
Orderable Device
OMAPL137BZKB3
OMAPL137BZKB4
OMAPL137BZKBA3
OMAPL137BZKBD4
OMAPL137BZKBT3
OMAPL137DZKB3
OMAPL137DZKB4
OMAPL137DZKBA3
OMAPL137DZKBD4
OMAPL137DZKBT3
XOMAPL137DZKBA3
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 90
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
OBSOLETE
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
ZKB
256
256
256
256
256
256
256
256
256
256
256
Green (RoHS
& no Sb/Br)
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
Call TI
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Call TI
OMAP
L137BZKB3
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
ACTIVE
ZKB
ZKB
ZKB
ZKB
ZKB
ZKB
ZKB
ZKB
ZKB
ZKB
Green (RoHS
& no Sb/Br)
0 to 90
OMAP
L137BZKB4
Green (RoHS
& no Sb/Br)
-40 to 105
-40 to 90
-40 to 125
OMAP
L137BZKBA3
Green (RoHS
& no Sb/Br)
OMAP
L137BZKBD4
Green (RoHS
& no Sb/Br)
OMAPL137BZKBT3
90
1
Green (RoHS
& no Sb/Br)
OMAP
L137DZKB3
ACTIVE
Green (RoHS
& no Sb/Br)
OMAP
L137DZKB4
ACTIVE
90
90
90
1
Green (RoHS
& no Sb/Br)
OMAP
L137DZKBA3
ACTIVE
TBD
OMAP
L137DZKBD4
ACTIVE
Green (RoHS
& no Sb/Br)
SNAGCU
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
OMAPL137DZKBT3
ACTIVE
Green (RoHS
& no Sb/Br)
XOMAP
L137DZKBA3
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2013
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
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