OMAPL137ZKB3 [TI]
Low-Power Applications Processor; 低功耗应用处理器
| 型号： | OMAPL137ZKB3 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Low-Power Applications Processor |
| 文件： | 总219页 (文件大小：1837K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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1 OMAP-L137 Low-Power Applications Processor
1.1 Features
–
Six ALU (32-/40-Bit) Functional Units
•
Applications
•
•
•
Supports 32-Bit Integer, SP (IEEE Single
Precision/32-Bit) and DP (IEEE Double
Precision/64-Bit) Floating Point
Supports up to Four SP Additions Per
Clock, Four DP Additions Every 2
Clocks
Supports up to Two Floating Point (SP
or DP) Approximate Reciprocal or
Square Root Operations Per Cycle
–
–
–
–
Industrial Control
USB, Networking
High-Speed Encoding
Professional Audio
•
•
•
Software Support
–
–
TI DSP/BIOS™
Chip Support Library and DSP Library
Dual Core SoC
–
–
–
Two Multiply Functional Units
•
300-MHz ARM926EJ-S™ RISC MPU
300-MHz C674x™ VLIW DSP
Mixed-Precision IEEE Floating Point
Multiply Supported up to:
ARM926EJ-S Core
–
–
–
–
2 SP x SP -> SP Per Clock
–
–
–
–
–
32-Bit and 16-Bit (Thumb®) Instructions
DSP Instruction Extensions
Single Cycle MAC
ARM® Jazelle® Technology
EmbeddedICE-RT™ for Real-Time Debug
2 SP x SP -> DP Every Two Clocks
2 SP x DP -> DP Every Three Clocks
2 DP x DP -> DP Every Four Clocks
•
Fixed Point Multiply Supports Two 32 x
32-Bit Multiplies, Four 16 x 16-Bit
Multiplies, or Eight 8 x 8-Bit Multiplies
per Clock Cycle, and Complex Multiples
•
•
ARM9 Memory Architecture
C674x Instruction Set Features
–
–
–
Instruction Packing Reduces Code Size
All Instructions Conditional
Hardware Support for Modulo Loop
Operation
Protected Mode Operation
Exceptions Support for Error Detection and
Program Redirection
–
–
–
–
–
–
–
Superset of the C67x+™ and C64x+™ ISAs
2400/1800 C674x MIPS/MFLOPS
Byte-Addressable (8-/16-/32-/64-Bit Data)
8-Bit Overflow Protection
Bit-Field Extract, Set, Clear
Normalization, Saturation, Bit-Counting
Compact 16-Bit Instructions
–
–
•
•
128K-Byte RAM Shared Memory
Two External Memory Interfaces:
–
•
•
•
C674x Two Level Cache Memory Architecture
–
–
–
–
–
32K-Byte L1P Program RAM/Cache
32K-Byte L1D Data RAM/Cache
256K-Byte L2 Unified Mapped RAM/Cache
Flexible RAM/Cache Partition (L1 and L2)
1024K-Byte L2 ROM
EMIFA
•
•
•
NOR (8-/16-Bit-Wide Data)
NAND (8-/16-Bit-Wide Data)
16-Bit SDRAM With 128MB Address
Space
Enhanced Direct-Memory-Access Controller 3
(EDMA3):
–
–
–
–
–
EMIFB
32-Bit or 16-Bit SDRAM With 256MB
Address Space
Three Configurable 16550 type UART Modules:
•
2 Transfer Controllers
32 Independent DMA Channels
8 Quick DMA Channels
•
–
–
–
UART0 With Modem Control Signals
16-byte FIFO
16x or 13x Oversampling Option
Programmable Transfer Burst Size
TMS320C674x™ Floating Point VLIW DSP Core
–
Load-Store Architecture With Non-Aligned
Support
64 General-Purpose Registers (32 Bit)
•
•
LCD Controller
Two Serial Peripheral Interfaces (SPI) Each
–
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
C674x, TMS320C6000, C6000 are trademarks of Texas Instruments.
ARM926EJ-S is a trademark of ARM Limited.
All other trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2008–2008, Texas Instruments Incorporated
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With One Chip-Select
Separate Power Rail
•
•
•
•
Multimedia Card (MMC)/Secure Digital (SD)
Card Interface with Secure Data I/O (SDIO)
Two Master/Slave Inter-Integrated Circuit (I2C
Bus™)
•
•
•
One 64-Bit General-Purpose Timer
(Configurable as Two 32-Bit Timers)
One 64-Bit General-Purpose Timer (Watch
Dog)
USB 1.1 OHCI (Host) With Integrated PHY
(USB1)
Three Enhanced Pulse Width Modulators
(eHRPWM):
–
Dedicated 16-Bit Time-Base Counter With
Period And Frequency Control
USB 2.0 OTG Port With Integrated PHY (USB0)
–
–
–
–
USB 2.0 High-/Full-Speed Client
USB 2.0 High-/Full-/Low-Speed Host
End Point 0 (Control)
End Points 1,2,3,4 (Control, Bulk, Interrupt
or ISOC) Rx and Tx
–
6 Single Edge, 6 Dual Edge Symmetric or 3
Dual Edge Asymmetric Outputs
–
–
–
Dead-Band Generation
PWM Chopping by High-Frequency Carrier
Trip Zone Input
•
•
Three Multichannel Audio Serial Ports:
•
Three 32-Bit Enhanced Capture Modules
(eCAP):
–
–
–
–
–
Transmit/Receive Clocks up to 50 MHz
Six Clock Zones and 28 Serial Data Pins
Supports TDM, I2S, and Similar Formats
DIT-Capable (McASP2)
–
Configurable as 3 Capture Inputs or 3
Auxiliary Pulse Width Modulator (APWM)
outputs
FIFO buffers for Transmit and Receive
–
Single Shot Capture of up to Four Event
Time-Stamps
10/100 Mb/s Ethernet MAC (EMAC):
–
–
–
IEEE 802.3 Compliant (3.3-V I/O Only)
RMII Media Independent Interface
Management Data I/O (MDIO) Module
•
•
•
Two 32-Bit Enhanced Quadrature Encoder
Pulse Modules (eQEP)
256-Ball Pb-Free Plastic Ball Grid Array
(PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
•
•
One Host-Port Interface (HPI) With 16-Bit-Wide
Muxed Address/Data Bus For High Bandwidth
Commercial or Extended Temperature
Real-Time Clock With 32 KHz Oscillator and
2
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1.2 Trademarks
DSP/BIOS, TMS320C6000, C6000, TMS320, TMS320C62x, and TMS320C67x are trademarks of Texas
Instruments.
All trademarks are the property of their respective owners.
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1.3 Description
The OMAP-L137 is a Low-power applications processor based on an ARM926EJ-S™ and a C674x™
DSP core. It provides significantly lower power than other members of the TMS320C6000™ platform of
DSPs.
The OMAP-L137 enables OEMs and ODMs to quickly bring to market devices featuring robust operating
systems support, rich user interfaces, and high processing performance life through the maximum
flexibility of a fully integrated mixed processor solution.
The dual-core architecture of the OMAP-L137 provides benefits of both DSP and Reduced Instruction Set
Computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an
ARM926EJ-S core.
The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and
processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and
memory system can operate continuously.
The ARM core has a coprocessor 15 (CP15), protection module, and Data and program Memory
Management Units (MMUs) with table look-aside buffers. It has separate 16K-byte instruction and
16K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core
also has a 8KB RAM (Vector Table) and 64KB ROM.
The OMAP-L137 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P)
is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache.
The Level 2 program cache (L2P) consists of a 256KB memory space that is shared between program
and data space. L2 also has a 1024KB ROM. L2 memory can be configured as mapped memory, cache,
or combinations of the two. Although the DSP L2 is accessible by ARM and other hosts in the system, an
additional 128KB RAM shared memory is available for use by other hosts without affecting DSP
performance.
The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output
(MDIO) module; two inter-integrated circuit (I2C) Bus interfaces; 3 multichannel audio serial port (McASP)
with 16/12/4 serializers and FIFO buffers; 2 64-bit general-purpose timers each configurable (one
configurable as watchdog); a configurable 16-bit host port interface (HPI); up to 8 banks of 16 pins of
general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed
with other peripherals; 3 UART interfaces (one with RTS and CTS); 3 enhanced high-resolution pulse
width modulator (eHRPWM) peripherals; 3 32-bit enhanced capture (eCAP) module peripherals which can
be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; 2 32-bit enhanced
quadrature pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM
external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory
interface (EMIFB) for SDRAM.
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the OMAP-L137
and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and
100 Mbps in either half- or full-duplex mode. Additionally an Management Data Input/Output (MDIO)
interface is available for PHY configuration.
The HPI, I2C, SPI, USB1.1 and USB2.0 ports allow the OMAP-L137 to easily control peripheral devices
and/or communicate with host processors.
The rich peripheral set provides the ability to control external peripheral devices and communicate with
external processors. For details on each of the peripherals, see the related sections later in this document
and the associated peripheral reference guides.
The OMAP-L137 has a complete set of development tools for both the ARM and DSP. These include C
compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™
debugger interface for visibility into source code execution.
4
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1.4 Functional Block Diagram
ARM Subsystem
DSP Subsystem
JTAG Interface
System Control
ARM926EJ-S CPU
With MMU
C674x™
DSP CPU
PLL/Clock
Input
Generator
Clock(s)
w/OSC
4 KB ETB
AET
General-
Purpose
Timer
16 KB
I-Cache
32 KB
L1 Pgm
16 KB
D-Cache
32 KB
L1 RAM
Power/Sleep
Controller
General-
Purpose
Timer
8 KB RAM
(Vector Table)
256 KB L2 RAM
1024 KB L2 ROM
RTC/
32-KHz
OSC
Pin
Multiplexing
64 KB ROM
(Watchdog)
Switched Central Resource (SCR)
Peripherals
Display
Internal Memory
DMA
Audio Ports
Serial Interfaces
McASP
w/FIFO
(3)
2
SPI
(2)
UART
(3)
I C
(2)
LCD
Ctlr
128 KB
RAM
EDMA3
Connectivity
(10/100)
External Memory Interfaces
Control Timers
EMIFB
SDRAM Only
(16b/32b)
USB2.0
OTG Ctlr OHCI Ctlr
PHY PHY
USB1.1
EMIFA(8b/16B)
NAND/Flash
16b SDRAM
ePWM
(3)
eCAP
(3)
eQEP
(2)
MMC/SD
(8b)
EMAC
(RMII)
MDIO
HPI
Note: Not all peripherals are available at the same time due to multiplexing.
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Contents
6.2
Recommended Clock and Control Signal Transition
Behavior ............................................. 79
1
OMAP-L137 Low-Power Applications Processor . 1
1.1 Features .............................................. 1
1.2 Trademarks ........................................... 3
1.3 Description............................................ 4
1.4 Functional Block Diagram ............................ 5
Revision History ......................................... 7
Device Overview ......................................... 8
3.1 Device Characteristics................................ 8
3.2 Device Compatibility .................................. 9
3.3 ARM Subsystem...................................... 9
3.4 DSP Subsystem..................................... 12
3.5 Memory Map Summary ............................. 18
3.6 Pin Assignments .................................... 21
3.7 Terminal Functions.................................. 22
Device Configuration .................................. 38
4.1 SYSCFG Module .................................... 38
4.2 Pin Multiplexing Control Registers .................. 39
4.3 Bus Master Priority Configuration ................... 60
6.3 Power Supplies...................................... 80
6.4 Reset ................................................ 80
6.5
Crystal Oscillator or External Clock Input ........... 81
6.6 Clock PLLs .......................................... 82
6.7 Interrupts ............................................ 85
6.8 General-Purpose Input/Output (GPIO).............. 96
6.9 EDMA ............................................... 99
6.10 External Memory Interface A (EMIFA)............. 104
6.11 EMIFB Peripheral Registers Description(s)........ 114
6.12 MMC / SD / SDIO (MMCSD)....................... 119
6.13 Ethernet Media Access Controller (EMAC) ........ 122
6.14 Management Data Input/Output (MDIO)........... 128
6.15 Multichannel Audio Serial Ports (McASP0, McASP1,
and McASP2) ...................................... 130
6.16 Serial Peripheral Interface Ports (SPI0, SPI1)..... 146
6.17 ECAP Peripheral Registers Description(s) ........ 164
6.18 EQEP Peripheral Registers Description(s) ........ 167
6.19 eHRPWM .......................................... 169
6.22 LCD Controller ..................................... 173
6.23 Timers.............................................. 188
6.24 Inter-Integrated Circuit Serial Ports (I2C0, I2C1) .. 190
6.25 Universal Asynchronous Receiver/Transmitter
(UART) ............................................. 194
6.26 USB1 Host Controller Registers (USB1.1 OHCI).. 196
6.27 USB0 OTG (USB2.0 OTG) ........................ 197
6.32 Power and Sleep Controller (PSC) ................ 204
6.34 Emulation Logic.................................... 207
6.35 Real Time Clock (RTC) ............................ 213
2
3
4
4.4
Chip Configuration Registers (CFGCHIP and
SUSPSRC) .......................................... 64
4.5 ARM/DSP Communication Registers ............... 71
4.6 Device Support ...................................... 72
4.7 Documentation Support ............................. 73
Device Operating Conditions ........................ 75
5
6
5.1
Absolute Maximum Ratings Over Operating Case
Temperature Range
(Unless Otherwise Noted) .......................... 75
5.2 Recommended Operating Conditions............... 76
5.3
Electrical Characteristics Over Recommended
Ranges of Supply Voltage and Operating Case
Temperature (Unless Otherwise Noted) ............ 77
7
Mechanical Packaging and Orderable
Information............................................. 216
7.1 Thermal Data for ZKB.............................. 216
7.2 Mechanical Drawings .............................. 216
Peripheral Information and Electrical
Specifications ........................................... 78
6.1 Parameter Information .............................. 78
6
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2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This data manual revision history highlights the changes made to the SPRS563 device-specific data
manual to make it an SPRS563A revision.
Table 2-1. Revision History
SEE
ADDITIONS/MODIFICATIONS/DELETIONS
Section 1.4, Functional Block Diagram
Updated the Functional Block Diagram.
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3 Device Overview
3.1 Device Characteristics
Table 3-1 provides an overview of the OMAP-L137 Low power applications processor. The table shows
significant features of the device, including the capacity of on-chip RAM, peripherals, and the package
type with pin count.
Table 3-1. Characteristics of the OMAP-L137 Processor
HARDWARE FEATURES
OMAP-L137
EMIFB
EMIFA
SDRAM only, 16/32-bit bus width
Asynchronous (8/16-bit bus width) RAM, Flash, 16-bit SDRAM, NOR, NAND
MMC and SD cards supported.
Flash Card Interface
EDMA3
32 independent channels, 8 QDMA channels, 2 Transfer controllers
2 64-Bit General Purpose (configurable as 2 separate 32-bit timers, 1 configurable as
Watch Dog)
Timers
UART
SPI
I2C
3 (one with RTS and CTS flow control)
2 (Each with one hardware chip select)
2 (both Master/Slave)
Peripherals
Multichannel Audio
Serial Port [McASP]
3 (each with transmit/receive, FIFO buffer, 16/12/4 serializers)
Not all peripherals pins
are available at the
same time (for more
detail, see the Device
Configurations section).
10/100 Ethernet MAC
with Management Data
I/O
1 (RMII Interface)
eHRPWM
eCAP
6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
3 32-bit capture inputs or 3 32-bit auxiliary PWM outputs
2 32-bit QEP channels with 4 inputs/channel
eQEP
UHPI
1 (16-bit multiplexed address/data)
USB 2.0 (USB0)
USB 1.1 (USB1)
High-Speed OTG Controller with on-chip OTG PHY
Full-Speed OHCI (as host) with on-chip PHY
General-Purpose
Input/Output Port
8 banks of 16-bit
LCD Controller
Size (Bytes)
1
488KB RAM, 1088KB ROM
DSP
32KB L1 Program (L1P)/Cache (up to 32KB)
32KB L1 Data (L1D)/Cache (up to 32KB)
256KB Unified Mapped RAM/Cache (L2)
1024KB ROM (L2)
DSP Memories can be made accessible to ARM, EDMA3, and other peripherals.
On-Chip Memory
Organization
ARM
16KB I-Cache
16KB D-Cache
8KB RAM (Vector Table)
64KB ROM
ADDITIONAL SHARED MEMORY
128KB RAM
C674x CPU ID + CPU Control Status Register
0x1400
0x0000
Rev ID
(CSR.[31:16])
C674x Megamodule
Revision
Revision ID Register
(MM_REVID[15:0])
JTAG BSDL_ID
JTAGID Register
0x0B7D_F02F
674x DSP 300 MHz
ARM926 300 MHz
CPU Frequency
MHz
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Table 3-1. Characteristics of the OMAP-L137 Processor (continued)
HARDWARE FEATURES
OMAP-L137
674x DSP 3.33 ns
Cycle Time
ns
ARM926 3.33 ns
Core (V)
I/O (V)
1.2 V
Voltage
3.3 V
Package
17 mm x 17 mm, 256-Ball 1 mm pitch, PBGA (ZKB)
Product Preview (PP),
Advance Information
(AI),
Product Status
PP
or Production Data
(PD)
3.2 Device Compatibility
The ARM926EJ-S RISC CPU is compatible with other ARM9 CPUs from ARM Holdings plc.
The C674x DSP core is code-compatible with the C6000™ DSP platform and supports features of both
the C64x+ and C67x+ DSP families.
3.3 ARM Subsystem
The ARM Subsystem includes the following features:
•
•
•
•
•
•
•
•
•
•
ARM926EJ-S RISC processor
ARMv5TEJ (32/16-bit) instruction set
Little endian
System Control Co-Processor 15 (CP15)
MMU
16KB Instruction cache
16KB Data cache
Write Buffer
Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)
ARM Interrupt controller
3.3.1 ARM926EJ-S RISC CPU
The ARM Subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of
ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications
where full memory management, high performance, low die size, and low power are all important. The
ARM926EJ-S processor supports the 32-bit ARM and 16 bit THUMB instruction sets, enabling the user to
trade off between high performance and high code density. Specifically, the ARM926EJ-S processor
supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes,
providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code
overhead.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both
hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a
complete high performance subsystem, including:
•
•
•
•
•
•
ARM926EJ -S integer core
CP15 system control coprocessor
Memory Management Unit (MMU)
Separate instruction and data caches
Write buffer
Separate instruction and data (internal RAM) interfaces
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•
•
Separate instruction and data AHB bus interfaces
Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)
For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available
at http://www.arm.com
3.3.2 CP15
The ARM926EJ-S system control coprocessor (CP15) is used to configure and control instruction and
data caches, Memory Management Unit (MMU), and other ARM subsystem functions. The CP15 registers
are programmed using the MRC and MCR ARM instructions, when the ARM in a privileged mode such as
supervisor or system mode.
3.3.3 MMU
A single set of two level page tables stored in main memory is used to control the address translation,
permission checks and memory region attributes for both data and instruction accesses. The MMU uses a
single unified Translation Lookaside Buffer (TLB) to cache the information held in the page tables. The
MMU features are:
•
•
Standard ARM architecture v4 and v5 MMU mapping sizes, domains and access protection scheme.
Mapping sizes are:
–
–
–
–
1MB (sections)
64KB (large pages)
4KB (small pages)
1KB (tiny pages)
•
Access permissions for large pages and small pages can be specified separately for each quarter of
the page (subpage permissions)
•
•
•
•
Hardware page table walks
Invalidate entire TLB, using CP15 register 8
Invalidate TLB entry, selected by MVA, using CP15 register 8
Lockdown of TLB entries, using CP15 register 10
3.3.4 Caches and Write Buffer
The size of the Instruction cache is 16KB, Data cache is 16KB. Additionally, the caches have the following
features:
•
•
Virtual index, virtual tag, and addressed using the Modified Virtual Address (MVA)
Four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with
two dirty bits in the Dcache
•
Dcache supports write-through and write-back (or copy back) cache operation, selected by memory
region using the C and B bits in the MMU translation tables
•
•
Critical-word first cache refilling
Cache lockdown registers enable control over which cache ways are used for allocation on a line fill,
providing a mechanism for both lockdown, and controlling cache corruption
•
Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the TAG
RAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the
TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the
possibility of TLB misses related to the write-back address.
•
Cache maintenance operations provide efficient invalidation of, the entire Dcache or Icache, regions of
the Dcache or Icache, and regions of virtual memory.
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The write buffer is used for all writes to a noncachable bufferable region, write-through region and write
misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for
cache line evictions or cleaning of dirty cache lines. The main write buffer has 16-word data buffer and a
four-address buffer. The Dcache write-back has eight data word entries and a single address entry.
3.3.5 Advanced High-Performance Bus (AHB)
The ARM Subsystem uses the AHB port of the ARM926EJ-S to connect the ARM to the Config bus and
the external memories. Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB by the
Config Bus and the external memories bus.
3.3.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an
Embedded Trace Macrocell (ETM). The ARM926ES-J Subsystem in the OMAP-L137 also includes the
Embedded Trace Buffer (ETB). The ETM consists of two parts:
•
•
Trace Port provides real-time trace capability for the ARM9.
Triggering facilities provide trigger resources, which include address and data comparators, counter,
and sequencers.
The OMAP-L137 trace port is not pinned out and is instead only connected to the Embedded Trace Buffer.
The ETB has a 4KB buffer memory. ETB enabled debug tools are required to read/interpret the captured
trace data.
3.3.7 ARM Memory Mapping
By default the ARM has access to most on and off chip memory areas, including the DSP Internal
memories, EMIFA, EMIFB, and the additional 128K byte on chip shared SRAM. Likewise almost all of the
on chip peripherals are accessible to the ARM by default.
To improve security and/or robustness the OMAP-L137 has extensive memory and peripheral protection
units which can be configured to limit access rights to the various on / off chip resources to specific hosts;
including the ARM as well as other master peripherals. This allows the system tasks to be partitioned
between the ARM and DSP as best suites the particular application; while enhancing the overall
robustness of the solution.
See Table 3-3 for a detailed top level OMAP-L137 memory map that includes the ARM memory space.
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3.4 DSP Subsystem
The DSP Subsystem includes the following features:
•
•
•
•
•
•
C674x DSP CPU
32KB L1 Program (L1P)/Cache (up to 32KB)
32KB L1 Data (L1D)/Cache (up to 32KB)
256KB Unified Mapped RAM/Cache (L2)
1MB Mask-programmable ROM
Little endian
32K Bytes
L1P RAM/
Cache
256K Bytes
L2 RAM
1M Byte
L2 ROM
256
256
256
256
Cache Control
Memory Protect
Bandwidth Mgmt
Cache Control
Memory Protect
Bandwidth Mgmt
L1P
L2
256
256
Power Down
256
256
Instruction Fetch
C674x
Fixed/Floating Point CPU
Interrupt
Controller
IDMA
256
Register
File A
Register
File B
64
64
CFG
Bandwidth Mgmt
Memory Protect
Cache Control
EMC
Configuration
Peripherals
Bus
32
L1D
MDMA
SDMA
8 x 32
64
64
64
64
32K Bytes
L1D RAM/
Cache
High
Performance
Switch Fabric
Figure 3-1. C674x Megamodule Block Diagram
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3.4.1 C674x DSP CPU Description
The C674x Central Processing Unit (CPU) consists of eight functional units, two register files, and two
data paths as shown in Figure 3-2. The two general-purpose register files (A and B) each contain
32 32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be
data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit
data, 40-bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are
stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or
32 MSBs in the next upper register (which is always an odd-numbered register).
The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one
instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units
perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from
memory to the register file and store results from the register file into memory.
The C674x CPU combines the performance of the C64x+ core with the floating-point capabilities of the
C67x core.
Each C674x .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x
32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with
add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four
16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for
Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and
modems require complex multiplication. The complex multiply (CMPY) instruction takes for 16-bit inputs
and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding
capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The
32 x 32 bit multiply instructions provide the extended precision necessary for high-precision algorithms on
a variety of signed and unsigned 32-bit data types.
The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a
pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data
performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.
The C674x core enhances the .S unit in several ways. On the previous cores, dual 16-bit MIN2 and MAX2
comparisons were only available on the .L units. On the C674x core they are also available on the .S unit
which increases the performance of algorithms that do searching and sorting. Finally, to increase data
packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit
and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack
instructions return parallel results to output precision including saturation support.
Other new features include:
•
SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where
multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size
associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.
•
Compact Instructions - The native instruction size for the C6000 devices is 32 bits. Many common
instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C674x
compiler can restrict the code to use certain registers in the register file. This compression is
performed by the code generation tools.
•
•
•
Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit
multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field
multiplication.
Exceptions Handling - Intended to aid the programmer in isolating bugs. The C674x CPU is able to
detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and
from system events (such as a watchdog time expiration).
Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a
basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with
read, write, and execute permissions.
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•
Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a
free-running time-stamp counter is implemented in the CPU which is not sensitive to system stalls.
For more details on the C674x CPU and its enhancements over the C64x architecture, see the following
documents:
•
•
TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732)
TMS320C64x Technical Overview (literature number SPRU395)
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Even
register
file A
(A0, A2,
A4...A30)
src1
src2
Odd
register
file A
(A1, A3,
A5...A31)
.L1
odd dst
even dst
long src
(D)
8
32 MSB
32 LSB
ST1b
ST1a
8
long src
even dst
odd dst
src1
(D)
Data path A
.S1
src2
32
32
(A)
(B)
dst2
dst1
src1
.M1
src2
(C)
32 MSB
32 LSB
LD1b
LD1a
dst
src1
src2
.D1
.D2
DA1
2x
1x
Even
register
file B
(B0, B2,
B4...B30)
Odd
register
file B
(B1, B3,
B5...B31)
src2
DA2
src1
dst
32 LSB
LD2a
LD2b
32 MSB
src2
(C)
.M2
src1
dst2
32
32
(B)
(A)
dst1
src2
src1
.S2
odd dst
even dst
long src
(D)
Data path B
8
8
32 MSB
32 LSB
ST2a
ST2b
long src
even dst
(D)
odd dst
.L2
src2
src1
Control Register
A. On .M unit, dst2 is 32 MSB.
B. On .M unit, dst1 is 32 LSB.
C. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits.
D. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files.
Figure 3-2. TMS320C674x™ CPU (DSP Core) Data Paths
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3.4.2 DSP Memory Mapping
The DSP memory map is shown in Section 3.5.
By default the DSP also has access to most on and off chip memory areas, with the exception of the ARM
RAM, ROM, and AINTC interrupt controller. The DSP also boots first, and must release the ARM from
reset before the ARM can execute any code. This allows the DSP (the secure host) to configure the
memory and IO protection and ensure security first, before the ARM can even attempt to access any of
the device resources.
Additionally, the DSP megamodule includes the capability to limit access to its internal memories through
its SDMA port; without needing an external MPU unit.
3.4.2.1 ARM Internal Memories
The DSP does not have access to the ARM internal memory.
3.4.2.2 External Memories
The DSP has access to the following External memories:
•
•
Asynchronous EMIF / SDRAM / NAND / NOR Flash (EMIFA)
SDRAM (EMIFB)
3.4.2.3 DSP Internal Memories
The DSP has access to the following DSP memories:
•
•
•
L2 RAM
L1P RAM
L1D RAM
3.4.2.4 C674x CPU
The C674x core uses a two-level cache-based architecture. The Level 1 Program cache (L1P) is 32 KB
direct mapped cache and the Level 1 Data cache (L1D) is 32 KB 2-way set associated cache. The Level 2
memory/cache (L2) consists of a 256 KB memory space that is shared between program and data space.
L2 memory can be configured as mapped memory, cache, or a combination of both.
Table 3-2 shows a memory map of the C674x CPU cache registers for the device.
Table 3-2. C674x Cache Registers
HEX ADDRESS RANGE
0x0184 0000
REGISTER ACRONYM
L2CFG
DESCRIPTION
L2 Cache configuration register
0x0184 0020
L1PCFG
L1PCC
L1P Size Cache configuration register
L1P Freeze Mode Cache configuration register
L1D Size Cache configuration register
L1D Freeze Mode Cache configuration register
Reserved
0x0184 0024
0x0184 0040
L1DCFG
L1DCC
0x0184 0044
0x0184 0048 - 0x0184 0FFC
0x0184 1000
-
EDMAWEIGHT
-
L2 EDMA access control register
Reserved
0x0184 1004 - 0x0184 1FFC
0x0184 2000
L2ALLOC0
L2ALLOC1
L2ALLOC2
L2ALLOC3
-
L2 allocation register 0
0x0184 2004
L2 allocation register 1
0x0184 2008
L2 allocation register 2
0x0184 200C
L2 allocation register 3
0x0184 2010 - 0x0184 3FFF
0x0184 4000
Reserved
L2WBAR
L2WWC
L2WIBAR
L2WIWC
L2 writeback base address register
L2 writeback word count register
L2 writeback invalidate base address register
L2 writeback invalidate word count register
0x0184 4004
0x0184 4010
0x0184 4014
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Table 3-2. C674x Cache Registers (continued)
HEX ADDRESS RANGE
REGISTER ACRONYM
L2IBAR
L2IWC
DESCRIPTION
L2 invalidate base address register
0x0184 4018
0x0184 401C
L2 invalidate word count register
L1P invalidate base address register
L1P invalidate word count register
L1D writeback invalidate base address register
L1D writeback invalidate word count register
Reserved
0x0184 4020
L1PIBAR
L1PIWC
L1DWIBAR
L1DWIWC
-
0x0184 4024
0x0184 4030
0x0184 4034
0x0184 4038
0x0184 4040
L1DWBAR
L1DWWC
L1DIBAR
L1DIWC
-
L1D Block Writeback
0x0184 4044
L1D Block Writeback
0x0184 4048
L1D invalidate base address register
L1D invalidate word count register
Reserved
0x0184 404C
0x0184 4050 - 0x0184 4FFF
0x0184 5000
L2WB
L2 writeback all register
0x0184 5004
L2WBINV
L2INV
L2 writeback invalidate all register
L2 Global Invalidate without writeback
Reserved
0x0184 5008
0x0184 500C - 0x0184 5027
0x0184 5028
-
L1PINV
-
L1P Global Invalidate
0x0184 502C - 0x0184 5039
0x0184 5040
Reserved
L1DWB
L1DWBINV
L1DINV
MAR0 - MAR63
L1D Global Writeback
0x0184 5044
L1D Global Writeback with Invalidate
L1D Global Invalidate without writeback
Reserved 0x0000 0000 – 0x3FFF FFFF
0x0184 5048
0x0184 8000 – 0x0184 80FF
Memory Attribute Registers for EMIFA SDRAM Data (CS0) 0x4000 0000 –
0x5FFF FFFF
0x0184 8100 – 0x0184 817F
0x0184 8180 – 0x0184 8187
0x0184 8188 – 0x0184 818F
0x0184 8190 – 0x0184 8197
MAR64 – MAR95
MAR96 - MAR97
MAR98 – MAR99
MAR100 – MAR101
Memory Attribute Registers for EMIFA Async Data (CS2) 0x6000 0000 –
0x61FF FFFF
Memory Attribute Registers for EMIFA Async Data (CS3) 0x6200 0000 –
0x63FF FFFF
Memory Attribute Registers for EMIFA Async Data (CS4) 0x6400 0000 –
0x65FF FFFF
Memory Attribute Registers for EMIFA Async Data (CS5) 0x6600 0000 –
0x67FF FFFF
0x0184 8198 – 0x0184 819F
0x0184 81A0 – 0x0184 81FF
MAR102 – MAR103
MAR104 – MAR127
Reserved 0x6800 0000 – 0x7FFF FFFF
Memory Attribute Register for Shared RAM 0x8000 0000 – 0x8001 FFFF
Reserved 0x8002 0000 – 0x81FF FFFF
0x0184 8200
MAR128
0x0184 8204 – 0x0184 82FF
0x0184 8300 – 0x0184 837F
0x0184 8380 – 0x0184 83FF
MAR129 – MAR191
MAR192 – MAR223
MAR224 – MAR255
Reserved 0x8200 0000 – 0xBFFF FFFF
Memory Attribute Registers for EMIFB SDRAM Data (CS2) 0xC000 0000 –
0xDFFF FFFF
Reserved 0xE000 0000 – 0xFFFF FFFF
See Table 3-3 for a detailed top level OMAP-L137 memory map that includes the DSP memory space.
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3.5 Memory Map Summary
Table 3-3. OMAP-L137 Top Level Memory Map
Start Address
End Address
Size
ARM Mem
Map
DSP Mem Map
EDMA Mem Map
Master
Peripheral
Mem Map
LCDC
Mem
Map
0x0000 0000
0x006F FFFF
6M +
-
1024K
0x0070 0000
0x0080 0000
0x0084 0000
0x007F FFFF
0x0083 FFFF
0x00DF FFFF
1024K
256K
-
-
DSP L2 ROM
DSP L2 RAM
-
-
5M +
768K
-
0x00E0 0000
0x00E0 8000
0x00F0 0000
0x00F0 8000
0x00E0 7FFF
0x00EF FFFF
0x00F0 7FFF
0x017F FFFF
32K
992K
32K
-
-
DSP L1P RAM
DSP L1D RAM
-
-
-
-
8M +
992K
0x0180 0000
0x0181 0000
0x0180 FFFF
0x0181 0FFF
64K
-
-
DSP Interrupt
Controller
-
-
4K
DSP Powerdown
Controller
0x0181 1000
0x0181 2000
0x0181 3000
0x0182 0000
0x0183 0000
0x0181 1FFF
0x0181 2FFF
0x0181 FFFF
0x0182 FFFF
0x0183 FFFF
4K
4K
-
-
-
-
-
DSP Security ID
DSP Revision ID
-
-
-
-
-
-
52K
64K
64K
DSP EMC
DSP Internal
Reserved
0x0184 0000
0x0185 0000
0x01BC 0000
0x0184 FFFF
0x01BB FFFF
0x01BC 0FFF
64K
-
DSP Memory
System
-
3M +
600K
-
4K
ARM ETB
memory
-
0x01BC 1000
0x01BC 1800
0x01BC 17FF
0x01BC 18FF
2K
ARM ETB reg
-
-
256
ARM Ice
Crusher
0x01BC 1900
0x01C0 0000
0x01C0 8000
0x01C0 8400
0x01C0 8800
0x01C1 0000
0x01C1 1000
0x01C1 2000
0x01C1 4000
0x01C1 5000
0x01C1 6000
0x01C1 7000
0x01C1 8000
0x01C2 0000
0x01C2 1000
0x01C2 2000
0x01C2 3000
0x01BF FFFF
0x01C0 7FFF
0x01C0 83FF
0x01C0 87FF
0x01C0 FFFF
0x01C1 0FFF
0x01C1 1FFF
0x01C1 3FFF
0x01C1 4FFF
0x01C1 5FFF
0x01C1 6FFF
0x01C1 7FFF
0x01C1 FFFF
0x01C2 0FFF
0x01C2 1FFF
0x01C2 2FFF
0x01C2 3FFF
260K
32K
1024
1024
30K
4K
-
EDMA3 CC
-
-
-
EDMA3 TC0
EDMA3 TC1
-
PSC 0
-
-
4K
PLL Controller
8K
-
4K
BootConfig
-
4K
-
4K
-
-
-
4K
-
32K
4K
-
Timer64P 0
Timer64P 1
I2C 0
-
-
-
-
4K
4K
4K
RTC
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Table 3-3. OMAP-L137 Top Level Memory Map (continued)
Start Address
End Address
Size
ARM Mem
Map
DSP Mem Map
EDMA Mem Map
Master
Peripheral
Mem Map
LCDC
Mem
Map
0x01C2 4000
0x01C2 5000
0x01C4 0000
0x01C4 1000
0x01C4 2000
0x01C4 3000
0x01D0 0000
0x01D0 1000
0x01D0 2000
0x01D0 3000
0x01D0 4000
0x01D0 5000
0x01D0 6000
0x01D0 7000
0x01D0 8000
0x01D0 9000
0x01D0 A000
0x01D0 B000
0x01D0 C000
0x01D0 D000
0x01D0 E000
0x01D0 F000
0x01E0 0000
0x01E1 0000
0x01E1 1000
0x01E1 2000
0x01E1 3000
0x01E1 4000
0x01E1 5000
0x01E1 6000
0x01E2 0000
0x01E2 2000
0x01E2 3000
0x01E2 4000
0x01E2 5000
0x01E2 6000
0x01E2 7000
0x01E2 8000
0x01E2 9000
0x01E2 A000
0x01F0 0000
0x01F0 1000
0x01F0 2000
0x01F0 3000
0x01F0 4000
0x01F0 5000
0x01C2 4FFF
0x01C3 FFFF
0x01C4 0FFF
0x01C4 1FFF
0x01C4 2FFF
0x01CF FFFF
0x01D0 0FFF
0x01D0 1FFF
0x01D0 2FFF
0x01D0 3FFF
0x01D0 4FFF
0x01D0 5FFF
0x01D0 6FFF
0x01D0 7FFF
0x01D0 8FFF
0x01D0 9FFF
0x01D0 AFFF
0x01D0 BFFF
0x01D0 CFFF
0x01D0 DFFF
0x01D0 EFFF
0x01DF FFFF
0x01E0 FFFF
0x01E1 0FFF
0x01E1 1FFF
0x01E1 2FFF
0x01E1 3FFF
0x01E1 4FFF
0x01E1 5FFF
0x01E1 FFFF
0x01E2 1FFF
0x01E2 2FFF
0x01E2 3FFF
0x01E2 4FFF
0x01E2 5FFF
0x01E2 6FFF
0x01E2 7FFF
0x01E2 8FFF
0x01E2 9FFF
0x01EF FFFF
0x01F0 0FFF
0x01F0 1FFF
0x01F0 2FFF
0x01F0 3FFF
0x01F0 4FFF
0x01F0 5FFF
4K
110K
4K
-
-
-
MMC/SD 0
SPI 0
-
-
-
4K
4K
UART 0
-
774K
4K
McASP 0 Control
-
-
-
4K
McASP 0 AFIFO Ctrl
4K
McASP 0 Data
4K
-
4K
McASP 1 Control
-
-
-
4K
McASP 1 AFIFO Ctrl
4K
McASP 1 Data
4K
-
4K
McASP 2 Control
-
-
-
4K
McASP 2 AFIFO Ctrl
4K
McASP 2 Data
4K
-
4K
UART 1
-
-
-
4K
UART 2
4K
-
964K
64K
4K
-
USB0
-
-
UHPI
4K
-
4K
SPI 1
-
-
-
-
4K
LCD Controller
4K
-
4K
-
40K
8K
-
EMAC Control Module RAM
-
-
-
-
-
-
-
-
-
4K
EMAC Control Module Registers
4K
EMAC Control Registers
EMAC MDIO port
USB1
4K
4K
4K
GPIO
4K
PSC 1
4K
I2C 1
4K
-
856K
4K
-
eHRPWM 0
HRPWM 0
eHRPWM 1
HRPWM 1
eHRPWM 2
HRPWM 2
-
-
-
-
-
-
4K
4K
4K
4K
4K
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Table 3-3. OMAP-L137 Top Level Memory Map (continued)
Start Address
End Address
Size
ARM Mem
Map
DSP Mem Map
EDMA Mem Map
Master
Peripheral
Mem Map
LCDC
Mem
Map
0x01F0 6000
0x01F0 7000
0x01F0 8000
0x01F0 9000
0x01F0 A000
0x01F0 B000
0x01F0 C000
0x01F0 6FFF
0x01F0 7FFF
0x01F0 8FFF
0x01F0 9FFF
0x01F0 AFFF
0x01F0 BFFF
0x116F FFFF
4K
4K
4K
4K
4K
4K
ECAP 0
-
-
-
-
-
-
ECAP 1
ECAP 2
EQEP 0
EQEP 1
-
247M +
976K
-
0x1170 0000
0x1180 0000
0x1184 0000
0x117F FFFF
0x1183 FFFF
0x11DF FFFF
1024K
256K
DSP L2 ROM
-
-
DSP L2 RAM
-
5M +
768K
0x11E0 0000
0x11E0 8000
0x11F0 0000
0x11F0 8000
0x11E0 7FFF
0x11EF FFFF
0x11F0 7FFF
0x3FFF FFFF
32K
992K
32K
DSP L1P RAM
-
-
-
DSP L1D RAM
-
736M +
992K
0x4000 0000
0x6000 0000
0x6200 0000
0x6400 0000
0x6600 0000
0x6800 0000
0x6800 8000
0x5FFF FFFF
0x61FF FFFF
0x63FF FFFF
0x65FF FFFF
0x67FF FFFF
0x6800 7FFF
0x7FFF FFFF
512M
32M
32M
32M
32M
32K
EMIFA SDRAM data (CS0)
EMIFA async data (CS2)
EMIFA async data (CS3)
EMIFA async data (CS4)
EMIFA async data (CS5)
EMIFA Control Regs
-
-
-
-
-
-
-
383M +
992K
0x8000 0000
0x8002 0000
0x8001 FFFF
128K
Shared RAM
-
-
0xAFFF FFFF 767M +
896K
0xB000 0000
0xB000 8000
0xB000 7FFF
32K
EMIFB Control Regs
-
0xBFFF FFFF 255M +
992K
0xC000 0000
0xE000 0000
0xDFFF FFFF
512M
EMIFB SDRAM Data
-
0xFFFC FFFF 511M +
832K
0xFFFD 0000
0xFFFD FFFF
64K
ARM local
ROM
-
0xFFFE 0000
0xFFFE E000
0xFFFE DFFF
0xFFFE FFFF
56K
8K
-
ARM Interrupt
Controller
-
-
0xFFFF 0000
0xFFFF 2000
0xFFFF 1FFF
0xFFFF FFFF
8K
ARM local
RAM
56K
-
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SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
3.6 Pin Assignments
Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in
the smallest possible package. Pin multiplexing is controlled using a combination of hardware
configuration at device reset and software programmable register settings.
3.6.1 Pin Map (Bottom View)
Figure 3-3 shows the pin assignments for the BGA package.Note that micro-vias are not required. Contact
your TI representative for routing recommendations.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
EMA_D[0]/
MMCSD_DAT[0]/
UHPI_HD[0]/
GP0[0]/
SPI0_CLK/
EQEP1I/
GP5[2]/
SPI1_CLK/
EQEP1S/
GP5[7]/
EMA_D[9]/
UHPI_HD[9]/
LCD_D[9]/
GP0[9]
EMA_CS[3]/ EMA_CS[0]/
AMUTE2/
GP2[6]
EMA_A[0]/
LCD_D[7]/
GP1[0]
EMA_A[4]/
LCD_D[3]/
GP1[4]
EMA_A[8]/
LCD_PCLK/
GP1[8]
AXR1[0]/
GP4[0]
AXR1[11]/
GP5[11]
EMA_SDCKE/
GP2[0]
T
R
P
N
M
L
T
R
P
N
M
L
VSS
VSS
UHPI_HAS/
GP2[4]
VSS
VSS
BOOT[2]
BOOT[7]
BOOT[12]
UART0_RXD/
I2C0_SDA/
TM64P0_IN12/ UART2_RXD/
GP5[8]/
BOOT[8]
SPI0_ENA/
UART0_CTS/
EQEP0A/
GP5[3]/
SPIO_SOMI[0]/
EQEPOI/
GP5[0]/
EMA_A[1]/
MMCSD_CLK/
UHPI_HCNTL0/
GP1[1]
EMA_CLK/
OBSCLK/
AHCLKR2/
GP1[15]
EDMA_D[2]/
EMA_D[10]/
EMA_D[1]/
EMA_OE/
UHPI_HDS1/
AXR0[13]/
GP2[7]
SPI1_ENA/
EMA_BA[0]/
LCD_D[4]/
GP1[14]
EMA_A[5]/ EMA_A[9]/
LCD_D[2]/ LCD_HSYNC/
GP1[5]
AXR1[1]/
GP4[1]
MMCSD_DAT[2]/ UHPI_HD[10]/ MMCSD_DAT[1]/
UHPI_HD[2]/
GP0[2]
DVDD
DVDD
LCD_D[10]/
GP0[10]
UHPI_HD[1]/
GP0[1]
GP5[12]
GP1[9]
BOOT[0]
BOOT[3]
UART0_TXD/
I2C0_SCL/
TM64P0_OUT12/ UART2_TXD/
GP5[9]/
BOOT[9]
EMA_WE_
DQM[1]/
UHPI_HDS2/
AXR0[14]/
GP2[8]
SPI1_SOMI[0]/ SPI0_SIMO[0]/
I2C1_SCL/
GP5[5]/
EMA_BA[1]/
LCD_D[5]/ MMCSD_CMD/
UHPI_HHWIL/ UHPI_HCNTL1/
EMA_A[2]/
EMA_A[11]/
LCD_AC_
ENB_CS/
GP1[11]
EMA_D[4]/
EMA_D[12]/
EMA_D[3]/
EMA_D[11]/
EMA_CS[2]/
UHPI_HCS/
GP2[5]/
AXR1[3]/
EQEP1A/
GP4[3]
SPI1_SCS[0]/
EMA_A[6]/
LCD_D[1]/
GP1[6]
AXR1[2]/
GP4[2]
EQEP0S/
GP5[1]/
BOOT[1]
MMCSD_DAT[4]/ UHPI_HD[12]/ MMCSD_DAT[3]/ UHPI_HD[11]/
UHPI_HD[4]/
GP0[4]
LCD_D[12]/
GP0[12]
UHPI_HD[3]/
GP0[3]
LCD_D[11]
GP0[11]
GP5[13]
BOOT[5]
GP1[13]
GP1[2]
BOOT[15]
SPI0_SCS[0]/
UART0_RTS/
SPI1_SIMO[0]/
I2C1_SDA/
GP5[6]/
EMA_D[8]/
EMA_D[6]/
EMA_D[14]/
EMA_D[5]/
EMA_D[13]/
AXR1[5]/
EPWM2B/
GP4[5]
AXR1[4]/
EQEP1B/
GP4[4]
EMA_WAIT[0]/ EMA_RAS/ EMA_A[10]/ EMA_A[3]/
UHPI_HRDY/ EMA_CS[5]/ LCD_VSYNC/ LCD_D[6]/
GP2[10]
EMA_A[7]/
LCD_D[0]/
GP1[7]
EMA_A[12]/
LCD_MCLK/
GP1[12]
AXR1[10]/
UHPI_HD[8]/ MMCSD_DAT[6]/ UHPI_HD[14]/ MMCSD_DAT[5]/ UHPI_HD[13]/
EQEP0B/
GP5[10]
LCD_D[8]/
GP0[8]
UHPI_HD[6]/
GP0[6]
LCD_D[14]/
GP0[14]
UHPI_HD[5]/
GP0[5]
LCD_D[13]/
GP0[13]
GP5[4]/
BOOT[4]
GP2[2]
GP1[10]
GP1[3]
BOOT[6]
EMA_D[7]/
MMCSD_DAT[7]/
UHPI_HD[7]/
GP0[7]/
EMA_WE/
UHPI_HRW/
AXR0[12]/
GP2[3]/
EMA_WE_
DQM[0]/
UHPI_HINT/
AXR0[15]/
GP2[9]
EMA_D[15]/
UHPI_HD[15]/
LCD_D[15]/
GP0[15]
AXR1[8]/
EPWM1A/
GP4[8]
AXR1[7]/
EPWM1B/
GP4[7]
AXR1[6]/
EPWM2A/
GP4[6]
AXR1[9]/
GP4[9]
DVDD
DVDD
DVDD
VSS
VSS
DVDD
DVDD
VSS
VSS
DVDD
DVDD
DVDD
CVDD
CVDD
DVDD
DVDD
BOOT[14]]
BOOT[13]
ACLKR1/
ECAP2/
APWM2/
GP4[12]
EMA_CAS/
EMB_D[23] EMA_CS[4]/
GP2[1]
AHCLKR1/
GP4[11]
AFSR1/
GP4[13]
AMUTE0/
RESETOUT
CVDD
CVDD
CVDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DVDD
CVDD
CVDD
CVDD
CVDD
DVDD
VSS
EMB_CAS
EMB_D[20]
EMB_D[22]
AFSX1/
EPWMSYNCI/
EPWMSYNCO/
GP4[10]
AHCLKX1/
EPWM0B/
GP3[14]
ACLKX1/
EPWM0A/
GP3[15]
EMB_WE_
DQM[0]/
GP5[15]
RTCK/
GP7[14]
K
J
K
J
CVDD
CVDD
CVDD
CVDD
RSV1
CVDD
CVDD
CVDD
CVDD
VSS
EMB_WE
EMB_D[21]
EMU0/
GP7[15]
EMB_D[5]/
GP6[5]
EMB_D[6]/
GP6[6]
EMB_D[7]/
GP6[7]
TMS
TDI
TDO
TCK
TRST
EMB_D[19]
EMB_D[17]
EMB_D[31]
EMB_D[29]
EMB_D[27]
EMB_D[3]/
GP6[3]
EMB_D[4]/
GP6[4]
USB0_
VSSA33
USB0_
VDDA33
H
G
F
H
G
F
RTC_XI
RTC_XO
RTC_VSS
OSCIN
CV
DD
CV
DD
CV
DD
EMB_D[18]
EMB_D[16]
EMB_D[30]
EMB_D[28]
EMB_D[1]/
GP6[1]
EMB_D[2]/
GP6[2]
RTC_CVDD
OSCOUT
PLL0_VSSA
PLL0_VDDA
RESET
USB0_DM
DV
DD
DV
DD
DV
DD
EMB_D[15]/
GP6[15]
EMB_D[0]/
GP6[0]
USB0_VSSA USB0_DP
USB0_
DRVVBUS/
EMB_D[13]/
GP6[13]
EMB_D[14]/
GP6[14]
USB0_
VDDA18
GP4[15]
E
D
C
B
A
E
D
C
B
A
OSCVSS
USB0_ID
VSS
VSS
DV
DD
DV
DD
VSS
DV
DD
AXR0[6]/ AXR0[2]/
RMII_RXER/ RMII_TXEN/
AMUTE1/
USB0_VBUS EHRPWMTZ/
GP4[14]
AFSX0/
GP2[13]/
BOOT[10]
UART1_TXD/
AXR0[10]/
GP3[10]
EMB_A[0]/
GP7[2]
EMB_A[4]/
GP7[6]
EMB_A[8]/
GP7[10]
EMB_D[9]/
GP6[9]
EMB_D[10]/ EMB_D[11]/ EMB_D[12]/
GP6[11]
EMB_CS[0]
ACLKR2/
GP3[6]
AXR2[3]/
GP3[2]
GP6[10]
GP6[12]
ACLKX0/
ECAP0/
APWM0/
GP2[12]
AXR0[5]/ AXR0[1]/
RMII_RXD[1]/ RMII_TXD[1]/ EMB_BA[0]/
UART1_RXD/
AXR0[9]/
GP3[9]
EMB_WE_
DQM[1]/
GP5[14]
EMB_A[1]/
GP7[3]
EMB_A[5]/
GP7[7]
EMB_A[9]/
GP7[11]
EMB_D[8]/
GP6[8]
USB1_
VDDA33
USB1_
VDDA18
USB0_
VDDA12
AFSR0/
GP3[12]
EMB_SDCKE EMB_CLK
AFSX2/
GP3[5]
ACLKX2/
GP3[1]
GP7[1]
AHLKX0/
AHCLKX2/
USB_
REFCLKIN/
GP2[11]
ACLKR0/
ECAP1/
APWM1/
GP2[15]
AXR0[4]/ AXR0[0]/
RMII_RXD[0]/ RMII_TXD[0]/ EMB_BA[1]/
AXR0[8]/
MDIO_D/
GP3[8]
EMB_A[2]/
GP7[4]
EMB_A[6]/
GP7[8]
EMB_A[11]/
GP7[13]
EMB_A[12]/
GP3[13]
EMB_WE_
EMB_D[25]
DQM[2]
RSV2
VSS
USB1_DM
DVDD
AXR2[1]/
GP3[4]
AFSR2/
GP3[0]
GP7[0]
AHCLKR0/
RMII_MHZ_ AXR0[11]/
AXR0[3]/
RMII_CRS_DV/
AXR2[2]/
AXR0[7]/
MDIO_CLK/
GP3[7]
EMB_A[10]/
GP7[12]
EMB_A[3]/
GP7[5]
EMB_A[7]/
GP7[9]
EMB_WE_
DQM[3]
VSS
VSS
USB1_DP
3
50_CLK/
GP2[14]/
BOOT[11]
AXR2[0]/
GP3[11]
EMB_RAS
8
EMB_D[24]
13
EMB_D[26]
14
VSS
VSS
GP3[3]
1
2
4
5
6
7
9
10
11
12
15
16
Figure 3-3. Pin Map (BGA)
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3.7 Terminal Functions
Table 3-4 to Table 3-24 identify the external signal names, the associated pin/ball numbers along with the
mechanical package designator, the pin type (I, O, IO, OZ, or PWR), whether the pin/ball has any internal
pullup/pulldown resistors, whether the pin/ball is configurable as an IO in GPIO mode, and a functional pin
description.
3.7.1 Device Reset and JTAG
Table 3-4. Reset and JTAG Terminal Functions
PIN NO
SIGNAL NAME
TYPE(1)
PULL(2)
DESCRIPTION
ZKB
RESET
Device reset input
Reset output. Multiplexed with McASP0 mute output.
JTAG
RESET
G3
L4
I
AMUTE0/RESETOUT
O(3)
IPD
TMS
J1
J2
J3
H3
J4
J5
K1
I
I
IPU
IPU
IPU
IPU
IPD
IPU
IPU
JTAG test mode select
JTAG test data input
JTAG test data output
JTAG test clock
TDI
TDO
O
I
TCK
TRST
I
JTAG test reset
EMU[0]/GP7[15]
RSVD/GP7[14]
I/O
I/O
Miscellaneous emulation pin.
Reserved
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
(3) Open drain mode for RESETOUT function.
3.7.2 High-Frequency Oscillator and PLL
Table 3-5. High-Frequency Oscillator and PLL Terminal Functions
PIN NO
SIGNAL NAME
TYPE(1)
PULL(2)
DESCRIPTION
ZKB
1.2-V OSCILLATOR
OSCIN
F2
F1
E2
I
Oscillator input
Oscillator output
Oscillator ground (for filter only)
1.2-V PLL
OSCOUT
OSCVSS
O
GND
PLL0_VDDA
PLL0_VSSA
D1
E1
PWR
GND
PLL analog VDD (1.2-V filtered supply)
PLL analog VSS (for filter)
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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3.7.3 Real-Time Clock and 32-kHz Oscillator
Table 3-6. Real-Time Clock (RTC) and 1.2-V, 32-kHz Oscillator Terminal Functions
PIN NO
SIGNAL NAME
TYPE(1)
PULL(2)
DESCRIPTION
ZKB
G1
H1
RTC_CVDD
PWR
I
RTC module core power ( isolated from rest of chip CVDD)
RTC_XI
RTC_XO
RTC_Vss
Low-frequency (32-kHz) oscillator receiver for real-time clock
Low-frequency (32-kHz) oscillator driver for real-time clock
Oscillator ground (for filter)
H2
O
G2
GND
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
3.7.4 External Memory Interface A (ASYNC, SDRAM)
Table 3-7. External Memory Interface A (EMIFA) Terminal Functions
PIN
NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
ZKB
M16
N14
N16
P14
P16
R14
T14
N12
EMA_D[15]/UHPI_HD[15]/LCD_D[15]/GP0[15]
EMA_D[14]/UHPI_HD[14]/LCD_D[14]/GP0[14]
EMA_D[13]/UHPI_HD[13]/LCD_D[13]/GP0[13]
EMA_D[12]/UHPI_HD[12]/LCD_D[12]/GP0[12]
EMA_D[11]/UHPI_HD[11]/LCD_D[11]/GP0[11]
EMA_D[10]/UHPI_HD[10]/LCD_D[10]/GP0[10]
EMA_D[9]/UHPI_HD[9]/LCD_D[9]/GP0[9]
EMA_D[8]/UHPI_HD[8]/LCD_D[8]/GP0[8]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
UHPI, LCD,
GPIO
MMC/SD, UHPI,
GPIO, BOOT
EMIFA data bus
EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/BOOT[13]
M15
I/O
IPU
EMA_D[6]/MMCSD_DAT[6]/UHPI_HD[6]/GP0[6]
EMA_D[5]/MMCSD_DAT[5]/UHPI_HD[5]/GP0[5]
EMA_D[4]/MMCSD_DAT[4]/UHPI_HD[4]/GP0[4]
EMA_D[3]/MMCSD_DAT[3]/UHPI_HD[3]/GP0[3]
EMA_D[2]/MMCSD_DAT[2]/UHPI_HD[2]/GP0[2]
EMA_D[1]/MMCSD_DAT[1]/UHPI_HD[1]/GP0[1]
N13
N15
P13
P15
R13
R15
I/O
I/O
I/O
I/O
I/O
I/O
IPU
IPU
IPU
IPU
IPU
IPU
MMC/SD, UHPI,
GPIO
MMC/SD, UHPI,
GPIO, BOOT
EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/BOOT[12]
T13
I/O
IPU
EMA_A[12]/LCD_MCLK/GP1[12]
EMA_A[11]/LCD_AC_ENB_CS/GP1[11]
EMA_A[10]/LCD_VSYNC/GP1[10]
EMA_A[9]/LCD_HSYNC/GP1[9]
EMA_A[8]/LCD_PCLK/GP1[8]
EMA_A[7]/LCD_D[0]/GP1[7]
EMA_A[6]/LCD_D[1]/GP1[6]
EMA_A[5]/LCD_D[2]/GP1[5]
EMA_A[4]/LCD_D[3]/GP1[4]
EMA_A[3]/LCD_D[6]/GP1[3]
N11
P11
N8
O
O
O
O
O
O
O
O
O
O
IPU
IPU
IPU
IPU
IPU
IPD
IPD
IPD
IPD
IPD
R11
T11
N10
P10
R10
T10
N9
LCD, GPIO
EMIFA address bus
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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Table 3-7. External Memory Interface A (EMIFA) Terminal Functions (continued)
PIN
NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
ZKB
P9
EMA_A[2]/MMCSD_CMD/UHPI_HCNTL1/GP1[2]
EMA_A[1]/MMCSD_CLK/UHPI_HCNTL0/GP1[1]
EMA_A[0]/LCD_D[7]/GP1[0]
O
O
O
IPU
IPU
IPD
MMCSD, UHPI,
GPIO
R9
EMIFA address bus.
EMIFA bank address
T9
LCD, GPIO
LCD, UHPI,
GPIO
EMA_BA[1]/LCD_D[5]/UHPI_HHWIL/GP1[13]
P8
O
IPU
EMA_BA[0]/LCD_D[4]/GP1[14]
EMA_CLK/AHCLKR2/GP1[15]
R8
O
O
IPU
IPU
LCD, GPIO
R12
McASP2, GPIO EMIFA clock.
EMIFA SDRAM clock
enable.
EMA_SDCKE/GP2[0]
T12
N7
O
O
O
IPU
IPU
IPU
GPIO
EMIFA SDRAM row
address strobe.
EMA_RAS/EMA_CS[5]/GP2[2]
EMA_CAS/EMA_CS[4]/GP2[1]
EMIF A chip
select, GPIO
EMIFA SDRAM column
address strobe.
L16
EMA_RAS/EMA_CS[5]/GP2[2]
EMA_CAS/EMA_CS[4]/GP2[1]
EMA_CS[3]/AMUTE2/GP2[6]
N7
L16
T7
O
O
O
IPU
IPU
IPU
EMIF A
SDRAM, GPIO
McASP2, GPIO EMIFA Async Chip
Select
UHPI, GPIO,
BOOT
EMA_CS[2]/UHPI_HCS/GP2[5]/BOOT[15]
EMA_CS[0]/UHPI_HAS/GP2[4]
P7
T8
O
O
O
IPU
IPU
IPU
UHPI, GPIO
UHPI, MCASP0, EMIFA SDRAM write
EMA_WE/UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14]
M13
GPIO, BOOT
enable.
EMIFA write
EMA_WE_DQM[1]/UHPI_HDS2/AXR0[14]/GP2[8]
EMA_WE_DQM[0]/UHPI_HINT/AXR0[15]/GP2[9]
P12
M14
O
O
IPU
IPU
enable/data mask for
EMA_D[15:8]
UHPI, McASP,
GPIO
EMIFA write
enable/data mask for
EMA_D[7:0].
UHPI, McASP0,
GPIO
EMA_OE/UHPI_HDS1/AXR0[13]/GP2[7]
EMA_WAIT[0]/UHPI_HRDY/GP2[10]
R7
N6
O
I
IPU
IPU
EMIFA output enable.
EMIFA wait
input/interrupt.
UHPI, GPIO
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3.7.5 External Memory Interface B (only SDRAM )
Table 3-8. External Memory Interface B (EMIFB) Terminal Functions
PIN NO
ZKB
G14
F15
F14
E15
E14
A14
B14
A13
L15
L14
K16
K13
J14
SIGNAL NAME
TYPE(1)
PULL(2)
MUXED
DESCRIPTION
EMB_D[31]
EMB_D[30]
EMB_D[29]
EMB_D[28]
EMB_D[27]
EMB_D[26]
EMB_D[25]
EMB_D[24]
EMB_D[23]
EMB_D[22]
EMB_D[21]
EMB_D[20]
EMB_D[19]
EMB_D[18]
EMB_D[17]
EMB_D[16]
O
O
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
O
O
O
O
O
O
O
O
O
O
O
H15
H14
G15
F13
E16
E13
D16
D15
D14
D13
C16
J16
O
O
O
EMIFB SDRAM data bus.
EMB_D[15]/GP6[15]
EMB_D[14]/GP6[14]
EMB_D[13]/GP6[13]
EMB_D[12]/GP6[12]
EMB_D[11]/GP6[11]
EMB_D[10]/GP6[10]
EMB_D[9]/GP6[9]
EMB_D[8]/GP6[8]
EMB_D[7]/GP6[7]
EMB_D[6]/GP6[6]
EMB_D[5]/GP6[5]
EMB_D[4]/GP6[4]
EMB_D[3]/GP6[3]
EMB_D[2]/GP6[2]
EMB_D[1]/GP6[1]
EMB_D[0]/GP6[0]
EMB_A[12]/GP3[13]
EMB_A[11]/GP7[13]
EMB_A[10]/GP7[12]
EMB_A[9]/GP7[11]
EMB_A[8]/GP7[10]
EMB_A[7]/GP7[9]
EMB_A[6]/GP7[8]
EMB_A[5]/GP7[7]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
GPIO
J15
J13
H16
H13
G16
G13
F16
B15
B12
A9
O
O
C12
D12
A11
B11
C11
O
EMIFB SDRAM row/column
address bus.
GPIO
O
O
O
O
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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Table 3-8. External Memory Interface B (EMIFB) Terminal Functions (continued)
PIN NO
ZKB
D11
A10
B10
C10
D10
B9
SIGNAL NAME
TYPE(1)
PULL(2)
MUXED
DESCRIPTION
EMB_A[4]/GP7[6]
EMB_A[3]/GP7[5]
EMB_A[2]/GP7[4]
EMB_A[1]/GP7[3]
EMB_A[0]/GP7[2]
EMB_BA[1]/GP7[0]
EMB_BA[0]/GP7[1]
EMB_CLK
O
O
IPD
IPD
IPD
IPD
IPD
IPU
IPU
IPU
IPU
IPU
EMIFB SDRAM row/column
address.
O
O
GPIO
O
O
EMIFB SDRAM bank address.
C9
O
C14
C13
K15
O
EMIF SDRAM clock.
EMB_SDCKE
I/O
O
EMIFB SDRAM clock enable.
EMIFB write enable
EMB_WE
EMIFB SDRAM row address
strobe.
EMB_RAS
A8
O
IPU
EMB_CAS
L13
D9
O
O
O
O
O
O
IPU
IPU
IPU
IPU
IPU
IPU
EMIFB column address strobe.
EMIFB SDRAM chip select 0.
EMB_CS[0]
EMB_WE_DQM[3]
EMB_WE_DQM[2]
A12
B13
C15
K14
EMIFB write enable/data mask
for EMB_D.
EMB_WE_DQM[1]/GP5[14]
EMB_WE_DQM[0]/GP5[15]
GPIO
3.7.6 Serial Peripheral Interface Modules (SPI0, SPI1)
Table 3-9. Serial Peripheral Interface (SPI) Terminal Functions
PIN
NO
SIGNAL NAME
TYPE(1)
SPI0
PULL(2)
MUXED
DESCRIPTION
ZKB
UART0, EQEP0B,
GPIO, BOOT
SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4]
N4
I/O
IPU
SPI0 chip select.
SPI0 enable.
UART0, EQEP0A,
GPIO, BOOT
SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3]
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2]
R5
T5
P6
I/O
I/O
I/O
IPU
IPD
IPD
eQEP1, GPIO, BOOT SPI0 clock.
SPI0 data
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1]
slave-in-master-out.
eQEP0, GPIO, BOOT
SPI0 data
slave-out-master-in.
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0]
R6
I/O
IPD
SPI1
SPI1_SCS[0]/UART2_TXD/GP5[13]
SPI1_ENA/UART2_RXD/GP5[12]
SPI1_CLK/EQEP1S/GP5[7]/BOOT[7]
P4
R4
T6
I/O
I/O
I/O
IPU
IPU
IPD
SPI1 chip select.
SPI1 enable.
UART2, GPIO
eQEP1, GPIO, BOOT SPI1 clock.
SPI1 data
slave-in-master-out.
SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6]
SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5]
N5
P5
I/O
I/O
IPU
IPU
I2C1, GPIO, BOOT
SPI1 data
slave-out-master-in.
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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3.7.7 Enhanced Capture/Auxiliary PWM Modules (eCAP0, eCAP1, eCAP2)
The eCAP Module pins function as either input captures or auxilary PWM 32-bit outputs, depending upon
how the eCAP module is programmed.
Table 3-10. Enhanced Capture Module (eCAP) Terminal Functions
PIN
NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
ZKB
eCAP0
eCAP1
eCAP2
enhanced capture
0 input or
auxiliary PWM 0
output.
ACLKX0/ECAP0/APWM0/GP2[12]
C5
I/O
I/O
I/O
IPD
IPD
IPD
McASP0, GPIO
enhanced capture
1 input or
auxiliary PWM 1
output.
ACLKR0/ECAP1/APWM1/GP2[15]
ACLKR1/ECAP2/APWM2/GP4[12]
B4
L2
McASP0, GPIO
McASP1, GPIO
enhanced capture
2 input or
auxiliary PWM 2
output.
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
3.7.8 Enhanced Pulse Width Modulators (eHRPWM0, eHRPWM1, eHRPWM2)
Table 3-11. Enhanced Pulse Width Modulator (eHRPWM) Terminal Functions
PIN
NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
ZKB
eHRPWM0
eHRPWM0 A output
(with high-resolution).
ACLKX1/EPWM0A/GP3[15]
K3
K2
D4
I/O
IPD
IPD
IPD
McASP1, GPIO
AHCLKX1/EPWM0B/GP3[14]
AMUTE1/EPWMTZ/GP4[14]
I/O
I/O
eHRPWM0 B output.
McASP1, eHRPWM1, eHRPWM0 trip zone
GPIO, eHRPWM2
input.
Sync input to
McASP1, eHRPWM0, eHRPWM0 module or
AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10]
K4
I/O
IPD
GPIO
sync output to
external PWM.
eHRPWM1
eHRPWM1 A output
(with high-resolution).
AXR1[8]/EPWM1A/GP4[8]
AXR1[7]/EPWM1B/GP4[7]
AMUTE1/EPWMTZ/GP4[14]
M2
M3
D4
I/O
IPD
IPD
IPD
McASP1, GPIO
I/O
I/O
eHRPWM1 B output.
McASP1, eHRPWM1, eHRPWM1 trip zone
GPIO, eHRPWM2 input.
eHRPWM2
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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Table 3-11. Enhanced Pulse Width Modulator (eHRPWM) Terminal Functions (continued)
PIN
NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
ZKB
M4
N1
eHRPWM2 A output
(with high-resolution).
AXR1[6]/EPWM2A/GP4[6]
I/O
I/O
I/O
IPD
IPD
IPD
McASP1, GPIO
AXR1[5]/EPWM2B/GP4[5]
AMUTE1/EPWMTZ/GP4[14]
eHRPWM2 B output.
McASP1, eHRPWM1, eHRPWM2 trip zone
GPIO, eHRPWM2 input.
D4
3.7.9 Enhanced Quadrature Encoder Pulse Module (eQEP)
Table 3-12. Enhanced Quadrature Encoder Pulse Module (eQEP) Terminal Functions
PIN
NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
ZKB
eQEP0
EQEP0A quadrature
input.
SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3]
SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4]
R5
N4
I
I
IPU
IPU
SPIO, UART0, GPIO,
BOOT
EQEP0B quadrature
input.
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0]
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1]
R6
P6
I
I
IPD
IPD
eQEP0 index.
eQEP0 strobe.
SPI1, GPIO, BOOT
eQEP1
eQEP1 quadrature
input.
AXR1[3]/EQEP1A/GP4[3]
AXR1[4]/EQEP1B/GP4[4]
P1
N2
I
I
IPD
IPD
McASP1, GPIO
McASP1, GPIO
eQEP1 quadrature
input.
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2]
SPI1_CLK/EQEP1S/GP5[7]/BOOT[7]
T5
T6
I
I
IPD
IPD
eQEP1 index.
eQEP1 strobe.
SPI1, GPIO, BOOT
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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3.7.10 Boot
Table 3-13. Boot Mode Selection Terminal Functions(1)
PIN NO
ZKB
P7
SIGNAL NAME
TYPE(2)
PULL(3)
MUXED
DESCRIPTION
EMA_CS[2]/UHPI_HCS/GP2[5]/BOOT[15]
I
I
IPU
IPU
EMIFA, UHPI, GPIO
EMIFA, UHPI,
McASP0, GPIO
EMA_WE/UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14]
M13
EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/BOOT[13]
EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/BOOT[12]
M15
T13
I
I
IPU
IPU
EMIFA, MMC/SD,
UHPI, GPIO
McASP0, EMAC,
GPIO
AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11]
AFSX0/GP2[13]/BOOT[10]
A4
D5
P3
I
I
I
IPD
IPD
IPU
McASP0, GPIO
UART0, I2C0, Timer0,
GPIO
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]
UART0, I2C0, Timer0,
GPIO
Boot Mode
Selection Pins
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8]
R3
I
IPU
SPI1_CLK/EQEP1S/GP5[7]/BOOT[7]
SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6]
SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5]
T6
N5
P5
I
I
I
IPD
IPU
IPU
SPI1, eQEP1, GPIO
SPI1, I2C1, GPIO
SPI0, UART0,
eQEP0, GPIO
SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4]
SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3]
N4
R5
I
I
IPU
IPU
SPI0, UART0,
eQEP0, GPIO
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2]
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1]
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0]
T5
P6
R6
I
I
I
IPD
IPD
IPD
SPIO, eQEP1, GPIO
SPI0, eQEP0, GPIO
(1) Boot decoding will be defined in the ROM datasheet.
(2) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(3) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
3.7.11 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)
Table 3-14. Universal Asynchronous Receiver/Transmitter (UART) Terminal Functions
PIN
NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
ZKB
UART0
I2C0, BOOT,
Timer0, GPIO,
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8]
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]
SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4]
SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3]
R3
P3
N4
R5
I
IPU
IPU
IPU
IPU
UART0 receive data.
I2C0, Timer0, GPIO, UART0 transmit
BOOT
O
O
I
data.
UART0
ready-to-send output
SPIO, eQEP0,
GPIO, BOOT
UART0
clear-to-send input
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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Table 3-14. Universal Asynchronous Receiver/Transmitter (UART) Terminal Functions (continued)
PIN
NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
McASP0, GPIO
SPI1, GPIO
DESCRIPTION
ZKB
UART1
C6
UART1_RXD/AXR0[9]/GP3[9]
I
IPD
IPD
UART1 receive data.
UART1 transmit
data.
UART1_TXD/AXR0[10]/GP3[10]
D6
O
UART2
SPI1_ENA/UART2_RXD/GP5[12]
SPI1_SCS[0]/UART2_TXD/GP5[13]
R4
I
IPU
IPU
UART2 receive data.
UART2 transmit
data.
P4
O
3.7.12 Inter-Integrated Circuit Modules(I2C0, I2C1)
Table 3-15. Inter-Integrated Circuit (I2C) Terminal Functions
PIN
NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
ZKB
I2C0
UART0, Timer0,
GPIO, BOOT
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8]
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]
R3
P3
I/O
I/O
IPU
IPU
I2C0 serial data.
I2C0 serial clock.
UART0, Timer0,
GPIO, BOOT
I2C1
N5
SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6]
SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5]
I/O
I/O
IPU
IPU
I2C1 serial data.
I2C1 serial clock.
SPI1, GPIO, BOOT
P5
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
3.7.13 Timers
Table 3-16. Timers Terminal Functions
PIN
NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
ZKB
TIMER0
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8]
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]
R3
I
IPU
IPU
Timer0 lower input.
UART0, I2C0,
GPIO, BOOT
Timer0 lower
output
P3
O
TIMER1 (Watchdog )
No external pins. The Timer1 peripheral signals are not pinned out as external pins.
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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3.7.14 Universal Host-Port Interface (UHPI)
Table 3-17. Universal Host-Port Interface (UHPI) Terminal Functions
PIN
NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
ZKB
M16
N14
N16
P14
P16
R14
T14
N12
EMA_D[15]/UHPI_HD[15]/LCD_D[15]/GP0[15]
EMA_D[14]/UHPI_HD[14]/LCD_D[14]/GP0[14]
EMA_D[13]/UHPI_HD[13]/LCD_D[13]/GP0[13]
EMA_D[12]/UHPI_HD[12]/LCD_D[12]/GP0[12]
EMA_D[11]/UHPI_HD[11]/LCD_D[11]/GP0[11]
EMA_D[10]/UHPI_HD[10]/LCD_D[10]/GP0[10]
EMA_D[9]/UHPI_HD[9]/LCD_D[9]/GP0[9]
EMA_D[8]/UHPI_HD[8]/LCD_D[8]/GP0[8]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
EMIFA, LCD, GPIO
EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/
BOOT[13]
EMIFA, MMC/SD,
GPIO, BOOT
UHPI data bus.
M15
I/O
IPU
EMA_D[6]/MMCSD_DAT[6]/UHPI_HD[6]/GP0[6]
EMA_D[5]/MMCSD_DAT[5]/UHPI_HD[5]/GP0[5]
EMA_D[4]/MMCSD_DAT[4]/UHPI_HD[4]/GP0[4]
EMA_D[3]/MMCSD_DAT[3]/UHPI_HD[3]/GP0[3]
EMA_D[2]/MMCSD_DAT[2]/UHPI_HD[2]/GP0[2]
EMA_D[1]/MMCSD_DAT[1]/UHPI_HD[1]/GP0[1]
N13
N15
P13
P15
R13
R15
I/O
I/O
I/O
I/O
I/O
I/O
IPU
IPU
IPU
IPU
IPU
IPU
EMIFA, MMC/SD,
GPIO
EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/
BOOT[12]
EMIFA, MMC/SD,
GPIO, BOOT
T13
I/O
IPU
EMA_A[2]/MMCSD_CMD/UHPI_HCNTL1/GP1[2]
EMA_A[1]/MMCSD_CLK/UHPI_HCNTL0/GP1[1]
P9
R9
I/O
I/O
IPU
IPU
EMIFA,
MMCSD_CMD,
GPIO
UHPI access control.
UHPI half-word
identification control.
EMA_BA[1]/LCD_D[5]/UHPI_HHWIL/GP1[13]
EMA_WE/UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14]
EMA_CS[2]/UHPI_HCS/GP2[5]/BOOT[15]
P8
M13
P7
I/O
I/O
I/O
IPU
IPU
IPU
EMIFA, LCD, GPIO
EMIFA, McASP,
GPIO, BOOT
UHPI read/write.
UHPI chip select.
EMIFA, GPIO,
BOOT
EMA_WE_DQM[1]/UHPI_HDS2/AXR0[14]/GP2[8]
EMA_OE/UHPI_HDS1/AXR0[13]/GP2[7]
EMA_WE_DQM[0]/UHPI_HINT/AXR0[15]/GP2[9]
EMA_WAIT[0]/UHPI_HRDY/GP2[10]
P12
R7
I/O
I/O
I/O
I/O
IPU
IPU
IPU
IPU
UHPI data strobe.
EMIFA, McASP0,
GPIO
M14
N6
UHPI host interrupt.
UHPI ready.
EMIFA, GPIO
UHPI address
strobe.
EMA_CS[0]/UHPI_HAS/GP2[4]
T8
I/O
IPU
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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3.7.15 Multichannel Audio Serial Ports (McASP0, McASP1, McASP2)
Table 3-18. Multichannel Audio Serial Ports (McASPs) Terminal Functions
PIN
NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
ZKB
McASP0
EMA_WE_DQM[0]/UHPI_HINT/AXR0[15]/GP2[9]
EMA_WE_DQM[1]/UHPI_HDS2/AXR0[14]/GP2[8]
EMA_OE/UHPI_HDS1/AXR0[13]/GP2[7]
M14
P12
R7
I/O
I/O
I/O
IPU
IPU
IPU
EMIFA, UHPI,
GPIO
EMIFA, UHPI,
GPIO, BOOT
EMA_WE/UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14]
M13
I/O
IPU
AXR0[11]/AXR2[0]/GP3[11]
A5
D6
C6
B6
A6
D7
C7
B7
A7
D8
C8
B8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IPD
IPD
IPD
IPU
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
McASP2, GPIO
GPIO
AXR0[10]/GP3[10]
AXR0[9]/GP3[9]
GPIO
McASP0 serial
data.
AXR0[8]/MDIO_D/GP3[8]
MDIO, GPIO
AXR0[7]/MDIO_CLK/GP3[7]
AXR0[6]/RMII_RXER/ACLKR2/GP3[6]
AXR0[5]/RMII_RXD[1]/AFSX2/GP3[5]
AXR0[4]/RMII_RXD[0]/AXR2[1]/GP3[4]
AXR0[3]/RMII_CRS_DV/AXR2[2]/GP3[3]
AXR0[2]/RMII_TXEN/AXR2[3]/GP3[2]
AXR0[1]/RMII_TXD[1]/ACLKX2/GP3[1]
AXR0[0]/RMII_TXD[0]/AFSR2/GP3[0]
EMAC,
McASP2, GPIO
McASP2, USB, McASP1 transmit
AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11]
ACLKX0/ECAP0/APWM0/GP2[12]
AFSX0/GP2[13]/BOOT[10]
B5
C5
D5
A4
B4
C4
L4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IPD
IPD
IPD
IPD
IPD
IPD
IPD
GPIO
master clock.
McASP0 transmit
bit clock.
eCAP0, GPIO
McASP0 transmit
frame sync.
GPIO, BOOT
EMAC, GPIO,
BOOT
McASP0 receive
master clock.
AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11]
ACLKR0/ECAP1/APWM1/GP2[15]
AFSR0/GP3[12]
McASP0 receive
bit clock.
eCAP1, GPIO
GPIO
McASP0 receive
frame sync.
McASP0 mute
output.
AMUTE0/RESETOUT
RESETOUT
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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Table 3-18. Multichannel Audio Serial Ports (McASPs) Terminal Functions (continued)
PIN
NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
ZKB
McASP1
AXR1[11]/GP5[11]
AXR1[10]/GP5[10]
AXR1[9]/GP4[9]
T4
N3
M1
I/O
I/O
I/O
IPU
IPU
IPD
GPIO
eHRPWM1 A,
GPIO
AXR1[8]/EPWM1A/GP4[8]
AXR1[7]/EPWM1B/GP4[7]
AXR1[6]/EPWM2A/GP4[6]
AXR1[5]/EPWM2B/GP4[5]
M2
M3
M4
N1
I/O
I/O
I/O
I/O
IPD
IPD
IPD
IPD
eHRPWM1 B,
GPIO
eHRPWM2 A,
GPIO
McASP1 serial
data.
eHRPWM2 B,
GPIO
AXR1[4]/EQEP1B/GP4[4]
AXR1[3]/EQEP1A/GP4[3]
AXR1[2]/GP4[2]
N2
P1
P2
R2
T3
I/O
I/O
I/O
I/O
I/O
IPD
IPD
IPD
IPD
IPD
eQEP1, GPIO
AXR1[1]/GP4[1]
GPIO
AXR1[0]/GP4[0]
eHRPWM0,
GPIO
McASP1 transmit
master clock.
AHCLKX1/EPWM0B/GP3[14]
ACLKX1/EPWM0A/GP3[15]
AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10]
AHCLKR1/GP4[11]
K2
K3
K4
L1
L2
L3
I/O
I/O
I/O
I/O
I/O
I/O
IPD
IPD
IPD
IPD
IPD
IPD
eHRPWM0,
GPIO
McASP1 transmit
bit clock.
eHRPWM0,
GPIO
McASP1 transmit
frame sync.
McASP1 receive
master clock.
GPIO
McASP1 receive
bit clock.
ACLKR1/ECAP2/APWM2/GP4[12]
AFSR1/GP4[13]
eCAP2, GPIO
GPIO
McASP1 receive
frame sync.
eHRPWM0,
eHRPWM1,
GPIO,
McASP1 mute
output.
AMUTE1/EPWMTZ/GP4[14]
D4
I/O
IPD
eHRPWM2
McASP2
AXR0[2]/RMII_TXEN/AXR2[3]/GP3[2]
AXR0[3]/RMII_CRS_DV/AXR2[2]/GP3[3]
AXR0[4]/RMII_RXD[0]/AXR2[1]/GP3[4]
D8
A7
B7
I/O
I/O
I/O
IPD
IPD
IPD
McASP0,
EMAC, GPIO
McASP2 serial
data.
UART1,
McASP0, GPIO
UART1_TXD/AXR2[0]AXR0[11]/GP3[11]
AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11]
AXR0[1]/RMII_TXD[1]/ACLKX2/GP3[1]
AXR0[5]/RMII_RXD[1]/AFSX2/GP3[5]
EMA_CLK/OBSCLK/AHCLKR2/GP1[15]
AXR0[6]/RMII_RXER/ACLKR2/GP3[6]
EMA_CS[3]/AMUTE2/GP2[6]
A5
B5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IPD
IPD
IPD
IPD
IPU
IPD
IPU
McASP2 transmit
master clock.
McASP0, USB,
GPIO
McASP2 transmit
bit clock.
C8
C7
R12
D7
T7
McASP0,
EMAC, GPIO
McASP2 transmit
frame sync.
McASP2 receive
master clock.
EMIFA, GPIO
McASP0,
EMAC, GPIO
McASP2 receive
bit clock.
McASP2 mute
output.
EMIFA, GPIO
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3.7.16 Universal Serial Bus Modules (USB0, USB1)
Table 3-19. Universal Serial Bus (USB) Terminal Functions
PIN
NO
SIGNAL NAME
TYPE(1) PULL(2) MUXED
DESCRIPTION
ZKB
USB0 2.0 OTG (USB0)
USB0_DM
G4
F4
H5
H4
E3
C3
F3
D2
D3
A
NA
NA
NA
NA
NA
NA
NA
NA
NA
USB0 PHY data minus
USB0_DP
A
USB0 PHY data plus
USB0_VDDA33
USB0_VSSA33
USB0_VDDA18
USB0_VDDA12
USB0_VSSA
USB0_ID
PWR
PWR
PWR
PWR
PWR
A
USB0 PHY 3.3-V supply
USB0 PHY 3.3-V supply reference
USB0 PHY 1.8-V supply input
USB0 PHY 1.2-V LDO output for bypass cap
USB0 PHY 1.8-V and 1.2-V supply reference
USB0 PHY identification (mini-A or mini-B plug)
USB0 bus voltage
USB0_VBUS
A
USB0 controller VBUS control output. Multiplexed
with GPIO bank 4 pin 15.
USB0_DRVVBUS/GP4[15]
E4
B5
0
I
IPD
IPD
GPIO
AHCLKX0/AHCLKX2/USB_REFCLKIN/
GP2[11]
USB_REFCLKIN. Optional clock input.
USB1 1.1 OHCI (USB1)
USB1_DM
B3
A3
C1
C2
A
NA
USB1 PHY data minus
USB1 PHY data plus
USB1_DP
A
NA
NA
NA
USB1_VDDA33
USB1_VDDA18
PWR
PWR
USB1 PHY 3.3-V supply
USB1 PHY 1.8-V supply
AHCLKX0/AHCLKX2/USB_REFCLKIN/
GP2[11]
B5
I
IPD
NA
USB_REFCLKIN. Optional clock input.
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
3.7.17 Ethernet Media Access Controller (EMAC)
Table 3-20. Ethernet Media Access Controller (EMAC) Terminal Functions
PIN
NO
SIGNAL NAME
TYPE(1) PULL(2)
RMII
MUXED
DESCRIPTION
ZKB
EMAC 50-MHz
clock input or
output.
AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11]
A4
I/O
IPD
McASP0, GPIO, BOOT
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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Table 3-20. Ethernet Media Access Controller (EMAC) Terminal Functions (continued)
PIN
NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
ZKB
EMAC RMII receiver
error.
AXR0[6]/RMII_RXER/ACLKR2/GP3[6]
D7
I
IPD
AXR0[5]/RMII_RXD[1]/AFSX2/GP3[5]
AXR0[4]/RMII_RXD[0]/AXR2[1]/GP3[4]
C7
B7
I
I
IPD
IPD
EMAC RMII receive
data.
EMAC RMII carrier
sense data valid.
AXR0[3]/RMII_CRS_DV/AXR2[2]/GP3[3]
AXR0[2]/RMII_TXEN/AXR2[3]/GP3[2]
A7
D8
I
IPD
IPD
McASP0, McASP2, GPIO
EMAC RMII transmit
enable.
O
AXR0[1]/RMII_TXD[1]/ACLKX2/GP3[1]
AXR0[0]/RMII_TXD[0]/AFSR2/GP3[0]
C8
B8
O
O
IPD
IPD
EMAC RMII trasmit
data.
MDIO
I/O
AXR0[8]/MDIO_D/GP3[8]
B6
A6
IPU
IPD
MDIO serial data.
MDIO clock
McASP0, GPIO
AXR0[7]/MDIO_CLK/GP3[7]
O
3.7.18 Multimedia Card/Secure Digital (MMC/SD)
Table 3-21. Multimedia Card/Secure Digital (MMC/SD) Terminal Functions
PIN
NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
ZKB
R9
EMA_A[1]/MMCSD_CLK/UHPI_HCNTL0/GP1[1]
EMA_A[2]/MMCSD_CMD/UHPI_HCNTL1/GP1[2]
O
IPU
IPU
MMCSD Clock.
EMIFA, UHPI, GPIO
P9
I/O
MMCSD Command.
EMIFA, UHPI, GPIO,
BOOT
EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/BOOT[13]
M15
I/O
IPU
EMA_D[6]/MMCSD_DAT[6]/UHPI_HD[6]/GP0[6]
EMA_D[5]/MMCSD_DAT[5]/UHPI_HD[5]/GP0[5]
EMA_D[4]/MMCSD_DAT[4]/UHPI_HD[4]/GP0[4]
EMA_D[3]/MMCSD_DAT[3]/UHPI_HD[3]/GP0[3]
EMA_D[2]/MMCSD_DAT[2]/UHPI_HD[2]/GP0[2]
EMA_D[1]/MMCSD_DAT[1]/UHPI_HD[1]/GP0[1]
N13
N15
P13
P15
R13
R15
I/O
I/O
I/O
I/O
I/O
I/O
IPU
IPU
IPU
IPU
IPU
IPU
EMIFA, UHPI, GPIO
MMC/SD data.
EMIFA, UHPI, GPIO,
BOOT
EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/BOOT[12]
T13
I/O
IPU
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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3.7.19 Liquid Crystal Display Controller(LCD)
Table 3-22. Liquid Crystal Display Controller (LCD) Terminal Functions
PIN NO
ZKB
M16
N14
N16
P14
P16
R14
T14
N12
T9
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
EMA_D[15]/UHPI_HD[15]/LCD_D[15]/GP0[15]
EMA_D[14]/UHPI_HD[14]/LCD_D[14]/GP0[14]
EMA_D[13]/UHPI_HD[13]/LCD_D[13]/GP0[13]
EMA_D[12]/UHPI_HD[12]/LCD_D[12]/GP0[12]
EMA_D[11]/UHPI_HD[11]/LCD_D[11]/GP0[11]
EMA_D[10]/UHPI_HD[10]/LCD_D[10]/GP0[10]
EMA_D[9]/UHPI_HD[9]/LCD_D[9]/GP0[9]
EMA_D[8]/UHPI_HD[8]/LCD_D[8]/GP0[8]
EMA_A[0]/LCD_D[7]/GP1[0]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
EMIFA, UHPI,
GPIO
LCD data bus.
EMIFA, GPIO
EMA_A[3]/LCD_D[6]/GP1[3]
N9
EMIFA, UHPI,
GPIO
EMA_BA[1]/LCD_D[5]/UHPI_HHWIL/GP1[13]
P8
I/O
IPU
EMA_BA[0]/LCD_D[4]/GP1[14]
EMA_A[4]/LCD_D[3]/GP1[4]
EMA_A[5]/LCD_D[2]/GP1[5]
EMA_A[6]/LCD_D[1]/GP1[6]
EMA_A[7]/LCD_D[0]/GP1[7]
EMA_A[8]/LCD_PCLK/GP1[8]
EMA_A[9]/LCD_HSYNC/GP1[9]
EMA_A[10]/LCD_VSYNC/GP1[10]
R8
T10
R10
P10
N10
T11
R11
N8
I/O
I/O
I/O
I/O
I/O
O
IPU
IPD
IPD
IPD
IPD
IPU
IPU
IPU
LCD data bus.
EMIFA, GPIO
LCD pixel clock.
O
LCD horizontal sync.
LCD vertical sync.
O
LCD AC bias enable
chip select.
EMA_A[11]/LCD_AC_ENB_CS/GP1[11]
EMA_A[12]/LCD_MCLK/GP1[12]
P11
N11
O
O
IPU
IPU
LCD memory clock.
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
3.7.20 Reserved
Table 3-23. Reserved Terminal Functions
PIN NO
SIGNAL NAME
TYPE(1)
DESCRIPTION
ZKB
RSV1
RSV2
F7
PWR
PWR
Reserved. (Leave unconnected, do not connect to power or ground.)
Reserved. For proper device operation, this pin must be tied directly to
B1
CVDD
.
(1) PWR = Supply voltage.
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3.7.21 Supply and Ground
Table 3-24. Supply and Ground Terminal Functions
PIN NO
ZKB
SIGNAL NAME
TYPE(1)
DESCRIPTION
F6,G6, G7,
G10, G11,H6,
H7, H10, H11,
H12,J6, J7,
J10, J11, J12,
K6, K7, K10,
K11,L6
CVDD (Core supply)
PWR
1.2-V core supply voltage pins
B16, E5, E8,
E9, E12, F5,
F11, F12, G5,
G12, K5, K12,
L5, L11, L12,
M5, M8, M9,
M12, R1, R16
DVDD (I/O supply)
PWR
3.3-V I/O supply voltage pins.
A1, A2, A15,
A16,
B2,
E6, E7, E10,
E11,
F8, F9, F10,
G8, G9,
H8, H9,
J8, J9,
VSS (Ground)
GND
Ground pins.
K8, K9,
L7, L8, L9,
L10,
M6, M7, M10,
M11,
T1, T2, T15,
T16
(1) PWR = Supply voltage, GND - Ground.
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4 Device Configuration
4.1 SYSCFG Module
The following system level features of the chip are controlled by the SYSCFG peripheral:
•
•
•
•
•
Readable Device, Die, and Chip Revision ID
Control of Pin Multiplexing
Priority of bus accesses different bus masters in the system
Capture at power on reset the chip BOOT[15:0] pin values and make them available to software
Special case settings for peripherals:
–
–
–
–
–
Locking of PLL controller settings
Default burst sizes for EDMA3 TC0 and TC1
Selection of the source for the eCAP module input capture (including on chip sources)
McASP AMUTEIN selection and clearing of AMUTE status for the three McASP peripherals
Control of the reference clock source and other side-band signals for both of the integrated USB
PHYs
–
Clock source selection for EMIFA and EMIFB
•
•
Source of emulation suspend signal (from either ARM or DSP) of peripherals supporting this function
Control of on-chip inter-processor interrupts for signaling between ARM and DSP
Since the SYSCFG peripheral controls global operation of the device, its registers are protected against
erroneous accesses by several mechanisms:
•
A special key sequence must be written to KICK0, KICK1 registers before any other registers are
writeable.
–
–
–
–
Unlock sequence: write 0x83e70b13 to KICK0, then write 0x95A4F1E0 to KICK1
SYSCFG remains unlocked after the unlock sequence until locked again.
Any number of accesses may be performed while the module is unlocked
Locking the module is accomplished by writing any other value to either KICK0 or KICK1
•
Additionally, many registers are accessible only by a host (ARM or DSP) when it is operating in its
privileged mode. (ex. from the kernel, but not from user space code).
Table 4-1. System Configuration (SYSCFG) Module Register Access
Offset
Acronym
Register Description
Access
—
0x01C1 4000
REVID
Revision Identification Register
Device Identification Register 0 - 3
0x01C14008 –
0x01C1 4014
DIEIDR0-DIEDR3
—
0x01C1 4020
0x01C1 4038
0x01C1 403C
0x01C1 4040
0x01C1 4044
0x01C1 40E0
0x01C1 40E4
0x01C1 40E8
0x01C1 40EC
0x01C1 40F0
0x01C1 40F4
0x01C1 40F8
BOOTCFG
KICK0R
Boot Configuration Register
Kick 0 Register
Privileged mode
Privileged mode
Privileged mode
—
KICK1R
Kick 1 Register
HOST0CFG
HOST1CFG
IRAWSTAT
IENSTAT
IENSET
Host 0 Configuration Register
Host 1 Configuration Register
Interrupt Raw Status/Set Register
Interrupt Enable Status/Clear Register
Interrupt Enable Register
Interrupt Enable Clear Register
End of Interrupt Register
Fault Address Register
—
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
—
IENCLR
EOI
FLTADDRR
FLTSTAT
MSTPRI0-MSTPRI2
Fault Status Register
0x01C1
Master Priority 0-2 Registers
Privileged mode
4110-0x01C1 4118
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Table 4-1. System Configuration (SYSCFG) Module Register Access (continued)
Offset
Acronym
Register Description
Access
0x01C1
PINMUX0-PINMUX19
Pin Multiplexing Control 0-19 Registers
Privileged mode
4120-0x01C1 416C
0x01C1 4170
0x01C1 4174
0x01C1 4178
SUSPSRC
Suspend Source Register
Chip Signal Register
Privileged mode
CHIPSIG
—
—
CHIPSIG_CLR
CFGCHIP0-CFGCHIP4
Chip Signal Clear Register
Chip Configuration 0-4 Registers
0x01C1
417C-0x01C1
418C
Privileged mode
4.2 Pin Multiplexing Control Registers
Device level pin multiplexing is controlled by registers PINMUX0 - PINMUX19 in the SYSCFG module.
For the OMAP-L13x device family, pin multiplexing can be controlled on a pin-by-pin basis. Each pin that
is multiplexed with several different functions has a corresponding 4-bit field in one of the PINMUX
registers.
Pin multiplexing selects which of several peripheral pin functions controls the pin's IO buffer output data
and output enable values only. The default pin multiplexing control for almost every pin is to select 'none'
of the peripheral functions in which case the pin's IO buffer is held tri-stated.
Note that the input from each pin is always routed to all of the peripherals that share the pin; the PINMUX
registers have no effect on input from
a
pin. This feature allows
a
pin such as
AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11] to be used as both the McASP0 AHCLKX0 (output) pin,
and the McASP2 AHCLKX2 master clock (output) pin simultaneously.
Section 4.2.1 through Section 4.2.20 contain the specific bit field definitions for the PINMUX registers on
the OMAP-L137 devices.
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4.2.1 PINMUX0 Register Definition (Address 0x01C1 4120 )
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
17
16
PINMUX0[31:28]
R/W-0
PINMUX0[27:24]
R/W-0
PINMUX0[23:20]
R/W-0
PINMUX0[19:16]
R/W-0
15
14
13
12
11
10
9
8
7
6
5
2
1
0
PINMUX0[15:12]
R/W-0
PINMUX0[11:8]
R/W-0
PINMUX0[7:4]
R/W-0
PINMUX0[3:0]
R/W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 4-1. PINMUX0 Register Bit Layout
Table 4-2. Field Descriptions for PINMUX0
Bits Field
ZKB Description
Ball
31:28 PINMUX0[31:28]
K15 EMB_WE Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_WE
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Reserved - Behavior is Undefined
other = Reserved - Behavior is Undefined.
27:24 PINMUX0[27:24]
23:20 PINMUX0[23:20]
19:16 PINMUX0[19:16]
15:12 PINMUX0[15:12]
11:8 PINMUX0[11:8]
A8
EMB_RAS Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_RAS
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Reserved - Behavior is Undefined
other = Reserved - Behavior is Undefined.
L13 EMB_CAS Control
0000 [Default] = Pin is tri-stated.
0100 = Reserved - Behavior is Undefined
1000 = Reserved - Behavior is Undefined
other = Reserved - Behavior is Undefined.
0001 = Selects Output Function EMB_CAS
0010 = Reserved - Behavior is Undefined
D9
EMB_CS[0] Control
0000 = Pin is tri-stated.
0001 = Selects Output Function EMB_CS[0]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Reserved - Behavior is Undefined
other = Reserved - Behavior is Undefined.
C14 EMB_CLK Control
0000 [Default] = Pin is tri-stated.
0001 = Reserved - Behavior is Undefined
0010 = Selects Output Function EMB_CLK
0100 = Reserved - Behavior is Undefined
1000 = Reserved - Behavior is Undefined
other = Reserved - Behavior is Undefined.
C13 EMB_SDCKE Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_SDCKE
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Reserved - Behavior is Undefined
other = Reserved - Behavior is Undefined.
7:4
3:0
PINMUX0[7:4]
PINMUX0[3:0]
J5
EMU[0] / GP7[15] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function GP7[15]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function EMU[0]
other = Reserved - Behavior is Undefined.
K1
RTCK / GP7[14] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function GP7[14]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function RTCK
other = Reserved - Behavior is Undefined.
40
Device Configuration
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SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
4.2.2 PINMUX1 Register Definition (Address 0x01C1 4124 )
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
17
16
0
PINMUX1[31:28]
R/W-0
PINMUX1[27:24]
R/W-0
PINMUX1[23:20]
R/W-0
PINMUX1[19:16]
R/W-0
15
14
13
12
11
10
9
8
7
6
5
2
1
PINMUX1[15:12]
R/W-0
PINMUX1[11:8]
R/W-0
PINMUX1[7:4]
R/W-0
PINMUX1[3:0]
R/W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 4-2. PINMUX1 Register Bit Layout
Table 4-3. Field Descriptions for PINMUX1
Bits Field
ZKB Description
Ball
31:28 PINMUX1[31:28]
C11 EMB_A[5] / GP7[7] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_A[5]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP7[7]
other = Reserved - Behavior is Undefined.
27:24 PINMUX1[27:24]
23:20 PINMUX1[23:20]
19:16 PINMUX1[19:16]
15:12 PINMUX1[15:12]
11:8 PINMUX1[11:8]
D11 EMB_A[4] / GP7[6] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_A[4]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP7[6]
other = Reserved - Behavior is Undefined.
A10 EMB_A[3] / GP7[5] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_A[3]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP7[5]
other = Reserved - Behavior is Undefined.
B10 EMB_A[2] / GP7[4] Control
0000 = Pin is tri-stated.
0001 = Selects Output Function EMB_A[2]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP7[4]
other = Reserved - Behavior is Undefined.
C10 EMB_A[1] / GP7[3] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_A[1]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP7[3]
other = Reserved - Behavior is Undefined.
D10 EMB_A[0] / GP7[2] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_A[0]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP7[2]
other = Reserved - Behavior is Undefined.
7:4
3:0
PINMUX1[7:4]
PINMUX1[3:0]
C9
B9
EMB_BA[0] / GP7[1] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_BA[0]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP7[1]
other = Reserved - Behavior is Undefined.
EMB_BA[1] / GP7[0] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_BA[1]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP7[0]
other = Reserved - Behavior is Undefined.
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41
OMAP-L137 Low-Power Applications Processor
SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
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4.2.3 PINMUX2 Register Definition (Address 0x01C1 4128 )
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
17
16
PINMUX2[31:28]
R/W-0
PINMUX2[27:24]
R/W-0
PINMUX2[23:20]
R/W-0
PINMUX2[19:16]
R/W-0
15
14
13
12
11
10
9
8
7
6
5
2
1
0
PINMUX2[15:12]
R/W-0
PINMUX2[11:8]
R/W-0
PINMUX2[7:4]
R/W-0
PINMUX2[3:0]
R/W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 4-3. PINMUX2 Register Bit Layout
Table 4-4. Field Descriptions for PINMUX2
Bits Field
ZKB Description
Ball
31:28 PINMUX2[31:28]
G14 EMB_D[31] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_D[31]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Reserved - Behavior is Undefined
other = Reserved - Behavior is Undefined.
27:24 PINMUX2[27:24]
23:20 PINMUX2[23:20]
19:16 PINMUX2[19:16]
15:12 PINMUX2[15:12]
11:8 PINMUX2[11:8]
B15 EMB_A[12] / GP3[13] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_A[12]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP3[13]
other = Reserved - Behavior is Undefined.
B12 EMB_A[11] / GP7[13] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_A[11]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP7[13]
other = Reserved - Behavior is Undefined.
A9
EMB_A[10]/GP7[12] Control
0000 = Pin is tri-stated.
0001 = Selects Output Function EMB_A[10]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP7[12]
other = Reserved - Behavior is Undefined.
C12 EMB_A[9] / GP7[11] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_A[9]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP7[11]
other = Reserved - Behavior is Undefined.
D12 EMB_A[8] / GP7[10] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_A[8]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP7[10]
other = Reserved - Behavior is Undefined.
7:4
3:0
PINMUX2[7:4]
PINMUX2[3:0]
A11 EMB_A[7] / GP7[9] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_A[7]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP7[9]
other = Reserved - Behavior is Undefined.
B11 EMB_A[6] / GP7[8] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_A[6]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP7[8]
other = Reserved - Behavior is Undefined.
42
Device Configuration
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4.2.4 PINMUX3 Register Definition (Address 0x01C1 412C )
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
17
16
0
PINMUX3[31:28]
R/W-0
PINMUX3[27:24]
R/W-0
PINMUX3[23:20]
R/W-0
PINMUX3[19:16]
R/W-0
15
14
13
12
11
10
9
8
7
6
5
2
1
PINMUX3[15:12]
R/W-0
PINMUX3[11:8]
R/W-0
PINMUX3[7:4]
R/W-0
PINMUX3[3:0]
R/W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 4-4. PINMUX3 Register Bit Layout
Table 4-5. Field Descriptions for PINMUX3
Bits Field
ZKB Description
Ball
31:28 PINMUX3[31:28]
L15 EMB_D[23] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_D[23]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Reserved - Behavior is Undefined
other = Reserved - Behavior is Undefined.
27:24 PINMUX3[27:24]
23:20 PINMUX3[23:20]
19:16 PINMUX3[19:16]
15:12 PINMUX3[15:12]
11:8 PINMUX3[11:8]
A13 EMB_D[24] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_D[24]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Reserved - Behavior is Undefined
other = Reserved - Behavior is Undefined.
B14 EMB_D[25] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_D[25]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Reserved - Behavior is Undefined
other = Reserved - Behavior is Undefined.
A14 EMB_D[26] Control
0000 = Pin is tri-stated.
0001 = Selects Output Function EMB_D[26]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Reserved - Behavior is Undefined
other = Reserved - Behavior is Undefined.
E14 EMB_D[27] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_D[27]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Reserved - Behavior is Undefined
other = Reserved - Behavior is Undefined.
E15 EMB_D[28] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_D[28]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Reserved - Behavior is Undefined
other = Reserved - Behavior is Undefined.
7:4
3:0
PINMUX3[7:4]
PINMUX3[3:0]
F14 EMB_D[29] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_D[29]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Reserved - Behavior is Undefined
other = Reserved - Behavior is Undefined.
F15 EMB_D[30] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_D[30]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Reserved - Behavior is Undefined
other = Reserved - Behavior is Undefined.
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43
OMAP-L137 Low-Power Applications Processor
SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
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4.2.5 PINMUX4 Register Definition (Address 0x01C1 4130 )
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
17
16
PINMUX4[31:28]
R/W-0
PINMUX4[27:24]
R/W-0
PINMUX4[23:20]
R/W-0
PINMUX4[19:16]
R/W-0
15
14
13
12
11
10
9
8
7
6
5
2
1
0
PINMUX4[15:12]
R/W-0
PINMUX4[11:8]
R/W-0
PINMUX4[7:4]
R/W-0
PINMUX4[3:0]
R/W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 4-5. PINMUX4 Register Bit Layout
Table 4-6. Field Descriptions for PINMUX4
Bits Field
ZKB Description
Ball
31:28 PINMUX4[31:28]
A12 EMB_WE_DQM[3] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function
EMB_WE_DQM[3]
0100 = Reserved - Behavior is Undefined
1000 = Reserved - Behavior is Undefined
other = Reserved - Behavior is Undefined.
0010 = Reserved - Behavior is Undefined
27:24 PINMUX4[27:24]
23:20 PINMUX4[23:20]
19:16 PINMUX4[19:16]
15:12 PINMUX4[15:12]
11:8 PINMUX4[11:8]
G15 EMB_D[16] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_D[16]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Reserved - Behavior is Undefined
other = Reserved - Behavior is Undefined.
H14 EMB_D[17] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_D[17]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Reserved - Behavior is Undefined
other = Reserved - Behavior is Undefined.
H15 EMB_D[18] Control
0000 = Pin is tri-stated.
0001 = Selects Output Function EMB_D[18]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Reserved - Behavior is Undefined
other = Reserved - Behavior is Undefined.
J14
EMB_D[19] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_D[19]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Reserved - Behavior is Undefined
other = Reserved - Behavior is Undefined.
K13 EMB_D[20] Control
0000 [Default] = Pin is tri-stated.
0100 = Reserved - Behavior is Undefined
1000 = Reserved - Behavior is Undefined
other = Reserved - Behavior is Undefined.
0001 = Selects Output Function EMB_D[20]
0010 = Reserved - Behavior is Undefined
7:4
3:0
PINMUX4[7:4]
PINMUX4[3:0]
K16 EMB_D[21] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_D[21]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Reserved - Behavior is Undefined
other = Reserved - Behavior is Undefined.
L14 EMB_D[22] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_D[22]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Reserved - Behavior is Undefined
other = Reserved - Behavior is Undefined.
44
Device Configuration
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SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
4.2.6 PINMUX5 Register Definition (Address 0x01C1 4134 )
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
17
16
0
PINMUX5[31:28]
R/W-0
PINMUX5[27:24]
R/W-0
PINMUX5[23:20]
R/W-0
PINMUX5[19:16]
R/W-0
15
14
13
12
11
10
9
8
7
6
5
2
1
PINMUX5[15:12]
R/W-0
PINMUX5[11:8]
R/W-0
PINMUX5[7:4]
R/W-0
PINMUX5[3:0]
R/W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 4-6. PINMUX5 Register Bit Layout
Table 4-7. Field Descriptions for PINMUX5
Bits Field
ZKB Description
Ball
31:28 PINMUX5[31:28]
J15
EMB_D[6] / GP6[6] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_D[6]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP6[6]
other = Reserved - Behavior is Undefined.
27:24 PINMUX5[27:24]
23:20 PINMUX5[23:20]
19:16 PINMUX5[19:16]
15:12 PINMUX5[15:12]
11:8 PINMUX5[11:8]
J13
EMB_D[5] / GP6[5] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_D[5]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP6[5]
other = Reserved - Behavior is Undefined.
H16 EMB_D[4] / GP6[4] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_D[4]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP6[4]
other = Reserved - Behavior is Undefined.
H13 EMB_D[3] / GP6[3] Control
0000 = Pin is tri-stated.
0001 = Selects Output Function EMB_D[3]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP6[3]
other = Reserved - Behavior is Undefined.
G16 EMB_D[2] / GP6[2] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_D[2]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP6[2]
other = Reserved - Behavior is Undefined.
G13 EMB_D[1] / GP6[1] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_D[1]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP6[1]
other = Reserved - Behavior is Undefined.
7:4
3:0
PINMUX5[7:4]
PINMUX5[3:0]
F16 EMB_D[0] / GP6[0] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_D[0]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP6[0]
other = Reserved - Behavior is Undefined.
B13 EMB_WE_DQM[2] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function
EMB_WE_DQM[2]
0100 = Reserved - Behavior is Undefined
1000 = Reserved - Behavior is Undefined
other = Reserved - Behavior is Undefined.
0010 = Reserved - Behavior is Undefined
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OMAP-L137 Low-Power Applications Processor
SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
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4.2.7 PINMUX6 Register Definition (Address 0x01C1 4138 )
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
17
16
PINMUX6[31:28]
R/W-0
PINMUX6[27:24]
R/W-0
PINMUX6[23:20]
R/W-0
PINMUX6[19:16]
R/W-0
15
14
13
12
11
10
9
8
7
6
5
2
1
0
PINMUX6[15:12]
R/W-0
PINMUX6[11:8]
R/W-0
PINMUX6[7:4]
R/W-0
PINMUX6[3:0]
R/W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 4-7. PINMUX6 Register Bit Layout
Table 4-8. Field Descriptions for PINMUX6
Bits Field
ZKB Description
Ball
31:28 PINMUX6[31:28]
E16 EMB_D[14] / GP6[14] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_D[14]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP6[14]
other = Reserved - Behavior is Undefined.
27:24 PINMUX6[27:24]
23:20 PINMUX6[23:20]
19:16 PINMUX6[19:16]
15:12 PINMUX6[15:12]
11:8 PINMUX6[11:8]
E13 EMB_D[13] / GP6[13] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_D[13]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP6[13]
other = Reserved - Behavior is Undefined.
D16 EMB_D[12] / GP6[12] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_D[12]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP6[12]
other = Reserved - Behavior is Undefined.
D15 EMB_D[11] / GP6[11] Control
0000 = Pin is tri-stated.
0001 = Selects Output Function EMB_D[11]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP6[11]
other = Reserved - Behavior is Undefined.
D14 EMB_D[10] / GP6[10] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_D[10]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP6[10]
other = Reserved - Behavior is Undefined.
D13 EMB_D[9] / GP6[9] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_D[9]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP6[9]
other = Reserved - Behavior is Undefined.
7:4
3:0
PINMUX6[7:4]
PINMUX6[3:0]
C16 EMB_D[8] / GP6[8] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_D[8]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP6[8]
other = Reserved - Behavior is Undefined.
J16
EMB_D[7] / GP6[7] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_D[7]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP6[7]
other = Reserved - Behavior is Undefined.
46
Device Configuration
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SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
4.2.8 PINMUX7 Register Definition (Address 0x01C1 413C )
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
17
16
0
PINMUX7[31:28]
R/W-0
PINMUX7[27:24]
R/W-0
PINMUX7[23:20]
R/W-0
PINMUX7[19:16]
R/W-0
15
14
13
12
11
10
9
8
7
6
5
2
1
PINMUX7[15:12]
R/W-0
PINMUX7[11:8]
R/W-0
PINMUX7[7:4]
R/W-0
PINMUX7[3:0]
R/W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 4-8. PINMUX7 Register Bit Layout
Table 4-9. Field Descriptions for PINMUX7
Bits Field
ZKB Description
Ball
31:28 PINMUX7[31:28]
N4
SPI0_SCS[0] / UART0_RTS / EQEP0B / GP5[4] / BOOT[4] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function SPI0_SCS[0]
0010 = Selects Output Function UART0_RTS
0100 = Selects Output Function EQEP0B
1000 = Selects Output Function GP5[4]
other = Reserved - Behavior is Undefined.
27:24 PINMUX7[27:24]
23:20 PINMUX7[23:20]
19:16 PINMUX7[19:16]
15:12 PINMUX7[15:12]
11:8 PINMUX7[11:8]
R5
T5
P6
R6
SPI0_ENA / UART0_CTS / EQEP0A / GP5[3] / BOOT[3] Control
0000 [Default] = Pin is tri-stated.
0100 = Selects Output Function EQEP0A
0001 = Selects Output Function SPI0_ENA
0010 = Selects Output Function UART0_CTS
1000 = Selects Output Function GP5[3]
other = Reserved - Behavior is Undefined.
SPI0_CLK / EQEP1I / GP5[2] / BOOT[2] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function SPI0_CLK
0010 = Selects Output Function EQEP1I
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP5[2]
other = Reserved - Behavior is Undefined.
SPIO_SOMI[0] / EQEP0S / GP5[1] Control
0000 = Pin is tri-stated.
0001 = Selects Output Function SPIO_SOMI[0]
0010 = Selects Output Function EQEP0S
0100 = Reserved - Behavior is Undefined.
1000 = Selects Output Function GP5[1]
other = Reserved - Behavior is Undefined.
SPI0_SOMI[0] / EQEP0I / GP5[0] / BOOT[0] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function SPI0_SOMI[0]
0010 = Selects Output Function EQEP0I
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP5[0]
other = Reserved - Behavior is Undefined.
K14 EMB_WE_DQM[0] / GP5[15] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function
EMB_WE_DQM[0]
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP5[15]
other = Reserved - Behavior is Undefined.
0010 = Reserved - Behavior is Undefined
7:4
3:0
PINMUX7[7:4]
PINMUX7[3:0]
C15 EMB_WE_DQM[1] / GP5[14] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function
EMB_WE_DQM[1]
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP5[14]
other = Reserved - Behavior is Undefined.
0010 = Reserved - Behavior is Undefined
F13 EMB_D[15] / GP6[15] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMB_D[15]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP6[15]
other = Reserved - Behavior is Undefined.
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Device Configuration
47
OMAP-L137 Low-Power Applications Processor
SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
www.ti.com
4.2.9 PINMUX8 Register Definition (Address 0x01C1 4140 )
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
17
16
PINMUX8[31:28]
R/W-0
PINMUX8[27:24]
R/W-0
PINMUX8[23:20]
R/W-0
PINMUX8[19:16]
R/W-0
15
14
13
12
11
10
9
8
7
6
5
2
1
0
PINMUX8[15:12]
R/W-0
PINMUX8[11:8]
R/W-0
PINMUX8[7:4]
R/W-0
PINMUX8[3:0]
R/W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 4-9. PINMUX8 Register Bit Layout
Table 4-10. Field Descriptions for PINMUX8
Bits Field
ZKB Description
Ball
31:28 PINMUX8[31:28]
R4
SPI1_ENA / UART2_RXD / GP5[12] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function SPI1_ENA
0010 = Selects Output Function UART2_RXD
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP5[12]
other = Reserved - Behavior is Undefined.
27:24 PINMUX8[27:24]
23:20 PINMUX8[23:20]
19:16 PINMUX8[19:16]
15:12 PINMUX8[15:12]
11:8 PINMUX8[11:8]
T4
N3
P3
R3
T6
N5
P5
AXR1[11] / GP5[11] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function AXR1[11]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP5[11]
other = Reserved - Behavior is Undefined.
AXR1[10] / GP5[10] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function AXR1[10]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP5[10]
other = Reserved - Behavior is Undefined.
UART0_TXD / I2C0_SCL / TM64P0_OUT12 / GP5[9] Control
0000 = Pin is tri-stated.
0001 = Selects Output Function UART0_TXD
0010 = Selects Output Function I2C0_SCL
0100 = Selects Output Function TM64P0_OUT12
1000 = Selects Output Function GP5[9]
other = Reserved - Behavior is Undefined.
UART0_RXD / I2C0_SDA / TM64P0_IN12 / GP5[8] / BOOT[8] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function UART0_RXD
0010 = Selects Output Function I2C0_SDA
0100 = Selects Output Function TM64P0_IN12
1000 = Selects Output Function GP5[8]
other = Reserved - Behavior is Undefined.
SPI1_CLK / EQEP1S / GP5[7] / BOOT[7] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function SPI1_CLK
0010 = Selects Output Function EQEP1S
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP5[7]
other = Reserved - Behavior is Undefined.
7:4
3:0
PINMUX8[7:4]
PINMUX8[3:0]
SPI1_SIMO[0] / I2C1_SDA / GP5[6] / BOOT[6] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function SPI1_SIMO[0]
0010 = Selects Output Function I2C1_SDA
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP5[6]
other = Reserved - Behavior is Undefined.
SPI1_SOMI[0] / I2C1_SCL / GP5[5] / BOOT[5] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function SPI1_SOMI[0]
0010 = Selects Output Function I2C1_SCL
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP5[5]
other = Reserved - Behavior is Undefined.
48
Device Configuration
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OMAP-L137 Low-Power Applications Processor
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SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
4.2.10 PINMUX9 Register Definition (Address 0x01C1 4144 )
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
17
16
0
PINMUX9[31:28]
R/W-0
PINMUX9[27:24]
R/W-0
PINMUX9[23:20]
R/W-0
PINMUX9[19:16]
R/W-0
15
14
13
12
11
10
9
8
7
6
5
2
1
PINMUX9[15:12]
R/W-0
PINMUX9[11:8]
R/W-0
PINMUX9[7:4]
R/W-0
PINMUX9[3:0]
R/W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 4-10. PINMUX9 Register Bit Layout
Table 4-11. Field Descriptions for PINMUX9
Bits Field
ZKB Description
Ball
31:28 PINMUX9[31:28]
C4
AFSR0 / GP3[12] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function AFSR0
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP3[12]
other = Reserved - Behavior is Undefined.
27:24 PINMUX9[27:24]
23:20 PINMUX9[23:20]
B4
A4
ACLKR0 / ECAP1 / APWM1 / GP2[15] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function ACLKR0
0010 = Selects Output Function ECAP1 / APWM1 other = Reserved - Behavior is Undefined.
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP2[15]
AHCLKR0 / RMII_MHZ_50_CLK / GP2[14] / BOOT[11] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function AHCLKR0
0010 = Selects Output Function
RMII_MHZ_50_CLK
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP2[14]
other = Reserved - Behavior is Undefined.
19:16 PINMUX9[19:16]
15:12 PINMUX9[15:12]
11:8 PINMUX9[11:8]
D5
C5
B5
E4
P4
AFSX0 / GP2[13] Control
0000 = Pin is tri-stated.
0001 = Selects Output Function AFSX0
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP2[13]
other = Reserved - Behavior is Undefined.
ACLKX0 / ECAP0 / APWM0 / GP2[12] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function ACLKX0
0010 = Selects Output Function ECAP0 / APWM0 other = Reserved - Behavior is Undefined.
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP2[12]
AHCLKX0 / AHCLKX2 / USB_REFCLKIN / GP2[11] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function AHCLKX0
0010 = Selects Output Function AHCLKX2
0100 = Selects Output Function USB_REFCLKIN
1000 = Selects Output Function GP2[11]
other = Reserved - Behavior is Undefined.
7:4
3:0
PINMUX9[7:4]
PINMUX9[3:0]
USB0_DRVVBUS / GP4[15] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function USB0_DRVVBUS 1000 = Selects Output Function GP4[15]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
other = Reserved - Behavior is Undefined.
SPI1_SCS[0] / UART2_TXD / GP5[13] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function SPI1_SCS[0]
0010 = Selects Output Function UART2_TXD
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP5[13]
other = Reserved - Behavior is Undefined.
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Device Configuration
49
OMAP-L137 Low-Power Applications Processor
SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
www.ti.com
4.2.11 PINMUX10 Register Definition (Address 0x01C1 4148 )
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
17
16
PINMUX10[31:28]
R/W-0
PINMUX10[27:24]
R/W-0
PINMUX10[23:20]
R/W-0
PINMUX10[19:16]
R/W-0
15
14
13
12
11
10
9
8
7
6
5
2
1
0
PINMUX10[15:12]
R/W-0
PINMUX10[11:8]
R/W-0
PINMUX10[7:4]
R/W-0
PINMUX10[3:0]
R/W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 4-11. PINMUX10 Register Bit Layout
Table 4-12. Field Descriptions for PINMUX10
Bits Field
ZKB Description
Ball
31:28 PINMUX10[31:28] D7
27:24 PINMUX10[27:24] C7
23:20 PINMUX10[23:20] B7
19:16 PINMUX10[19:16] A7
15:12 PINMUX10[15:12] D8
AXR0[6] / RMII_RXER / ACLKR2 / GP3[6] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function AXR0[6]
0010 = Selects Output Function RMII_RXER
0100 = Selects Output Function ACLKR2
1000 = Selects Output Function GP3[6]
other = Reserved - Behavior is Undefined.
AXR0[5] / RMII_RXD[1] / AFSX2 / GP3[5] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function AXR0[5]
0010 = Selects Output Function RMII_RXD[1]
0100 = Selects Output Function AFSX2
1000 = Selects Output Function GP3[5]
other = Reserved - Behavior is Undefined.
AXR0[4] / RMII_RXD[0] / AXR2[1] / GP3[4] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function AXR0[4]
0010 = Selects Output Function RMII_RXD[0]
0100 = Selects Output Function AXR2[1]
1000 = Selects Output Function GP3[4]
other = Reserved - Behavior is Undefined.
AXR0[3] / RMII_CRS_DV / AXR2[2] / GP3[3] Control
0000 = Pin is tri-stated.
0001 = Selects Output Function AXR0[3]
0010 = Selects Output Function RMII_CRS_DV
0100 = Selects Output Function AXR2[2]
1000 = Selects Output Function GP3[3]
other = Reserved - Behavior is Undefined.
AXR0[2] / RMII_TXEN / AXR2[3] / GP3[2] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function AXR0[2]
0010 = Selects Output Function RMII_TXEN
0100 = Selects Output Function AXR2[3]
1000 = Selects Output Function GP3[2]
other = Reserved - Behavior is Undefined.
11:8 PINMUX10[11:8]
C8
B8
L4
AXR0[1] / RMII_TXD[1] / ACLKX2 / GP3[1] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function AXR0[1]
0010 = Selects Output Function RMII_TXD[1]
0100 = Selects Output Function ACLKX2
1000 = Selects Output Function GP3[1]
other = Reserved - Behavior is Undefined.
7:4
3:0
PINMUX10[7:4]
PINMUX10[3:0]
AXR0[0] / RMII_TXD[0] / AFSR2 / GP3[0] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function AXR0[0]
0010 = Selects Output Function RMII_TXD[0]
0100 = Selects Output Function AFSR2
1000 = Selects Output Function GP3[0]
other = Reserved - Behavior is Undefined.
AMUTE0 / RESETOUT Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function AMUTE0
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function RESETOUT
other = Reserved - Behavior is Undefined.
50
Device Configuration
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SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
4.2.12 PINMUX11 Register Definition (Address 0x01C1 414C )
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
17
16
0
PINMUX11[31:28]
R/W-0
PINMUX11[27:24]
R/W-0
PINMUX11[23:20]
R/W-0
PINMUX11[19:16]
R/W-0
15
14
13
12
11
10
9
8
7
6
5
2
1
PINMUX11[15:12]
R/W-0
PINMUX11[11:8]
R/W-0
PINMUX11[7:4]
R/W-0
PINMUX11[3:0]
R/W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 4-12. PINMUX11 Register Bit Layout
Table 4-13. Field Descriptions for PINMUX11
Bits Field
ZKB Description
Ball
31:28 PINMUX11[31:28] K4
27:24 PINMUX11[27:24] K3
23:20 PINMUX11[23:20] K2
19:16 PINMUX11[19:16] A5
15:12 PINMUX11[15:12] D6
AFSX1 / EPWMSYNCI / EPWMSYNC0 / GP4[10] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function AFSX1
0010 = Selects Output Function EPWMSYNCI
0100 = Selects Output Function EPWMSYNC0
1000 = Selects Output Function GP4[10]
other = Reserved - Behavior is Undefined.
ACLKX1 / EPWM0A / GP3[15] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function ACLKX1
0010 = Selects Output Function EPWM0A
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP3[15]
other = Reserved - Behavior is Undefined.
AHCLKX1 / EPWM0B / GP3[14] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function AHCLKX1
0010 = Selects Output Function EPWM0B
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP3[14]
other = Reserved - Behavior is Undefined.
AXR0[11] / AXR2[0] / GP3[11] Control
0000 = Pin is tri-stated.
0001 = Selects Output Function AXR0[11]
0010 = Reserved - Behavior is Undefined.
0100 = Selects Output Function AXR2[0]
1000 = Selects Output Function GP3[11]
other = Reserved - Behavior is Undefined.
UART1_TXD / AXR0[10] / GP3[10] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function UART1_TXD
0010 = Selects Output Function AXR0[10]
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP3[10]
other = Reserved - Behavior is Undefined.
11:8 PINMUX11[11:8]
C6
B6
A6
UART1_RXD / AXR0[9] / GP3[9] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function UART1_RXD
0010 = Selects Output Function AXR0[9]
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP3[9]
other = Reserved - Behavior is Undefined.
7:4
3:0
PINMUX11[7:4]
PINMUX11[3:0]
AXR0[8] / MDIO_D / GP3[8] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function AXR0[8]
0010 = Selects Output Function MDIO_D
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP3[8]
other = Reserved - Behavior is Undefined.
AXR0[7] / MDIO_CLK / GP3[7] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function AXR0[7]
0010 = Selects Output Function MDIO_CLK
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP3[7]
other = Reserved - Behavior is Undefined.
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Device Configuration
51
OMAP-L137 Low-Power Applications Processor
SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
www.ti.com
4.2.13 PINMUX12 Register Definition (Address 0x01C1 4150 )
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
17
16
PINMUX12[31:28]
R/W-0
PINMUX12[27:24]
R/W-0
PINMUX12[23:20]
R/W-0
PINMUX12[19:16]
R/W-0
15
14
13
12
11
10
9
8
7
6
5
2
1
0
PINMUX12[15:12]
R/W-0
PINMUX12[11:8]
R/W-0
PINMUX12[7:4]
R/W-0
PINMUX12[3:0]
R/W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 4-13. PINMUX12 Register Bit Layout
Table 4-14. Field Descriptions for PINMUX12
Bits Field
ZKB Description
Ball
31:28 PINMUX12[31:28] P1
27:24 PINMUX12[27:24] P2
23:20 PINMUX12[23:20] R2
19:16 PINMUX12[19:16] T3
15:12 PINMUX12[15:12] D4
AXR1[3] / EQEP1A / GP4[3] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function AXR1[3]
0010 = Selects Output Function EQEP1A
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP4[3]
other = Reserved - Behavior is Undefined.
AXR1[2] / GP4[2] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function AXR1[2]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP4[2]
other = Reserved - Behavior is Undefined.
AXR1[1] / GP4[1] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function AXR1[1]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP4[1]
other = Reserved - Behavior is Undefined.
AXR1[0] / GP4[0] Control
0000 = Pin is tri-stated.
0001 = Selects Output Function AXR1[0]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined.
1000 = Selects Output Function GP4[0]
other = Reserved - Behavior is Undefined.
AMUTE1 / EHRPWMTZ / GP4[14] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function AMUTE1
0010 = Selects Output Function EHRPWMTZ
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP4[14]
other = Reserved - Behavior is Undefined.
11:8 PINMUX12[11:8]
L3
L2
L1
AFSR1 / GP4[13] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function AFSR1
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP4[13]
other = Reserved - Behavior is Undefined.
7:4
3:0
PINMUX12[7:4]
PINMUX12[3:0]
ACLKR1 / ECAP2 / APWM2 / GP4[12] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function ACLKR1
0010 = Selects Output Function ECAP2 / APWM2 other = Reserved - Behavior is Undefined.
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP4[12]
AHCLKR1 / GP4[11] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function AHCLKR1
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP4[11]
other = Reserved - Behavior is Undefined.
52
Device Configuration
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SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
4.2.14 PINMUX13 Register Definition (Address 0x01C1 4154 )
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
17
16
0
PINMUX13[31:28]
R/W-0
PINMUX13[27:24]
R/W-0
PINMUX13[23:20]
R/W-0
PINMUX13[19:16]
R/W-0
15
14
13
12
11
10
9
8
7
6
5
2
1
PINMUX13[15:12]
R/W-0
PINMUX13[11:8]
R/W-0
PINMUX13[7:4]
R/W-0
PINMUX13[3:0]
R/W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 4-14. PINMUX13 Register Bit Layout
Table 4-15. Field Descriptions for PINMUX13
Bits Field
ZKB Description
Ball
31:28 PINMUX13[31:28] R15 EMA_D[1] / MMCSD_DAT[1] / UHPI_HD[1] / GP0[1] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMA_D[1]
0100 = Selects Output Function UHPI_HD[1]
1000 = Selects Output Function GP0[1]
0010 = Selects Output Function MMCSD_DAT[1] other = Reserved - Behavior is Undefined.
27:24 PINMUX13[27:24] T13 EMA_D[0] / MMCSD_DAT[0] / UHPI_HD[0] / GP0[0] / BOOT[12] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMA_D[0]
0100 = Selects Output Function UHPI_HD[0]
1000 = Selects Output Function GP0[0]
0010 = Selects Output Function MMCSD_DAT[0] other = Reserved - Behavior is Undefined.
23:20 PINMUX13[23:20] M1
19:16 PINMUX13[19:16] M2
15:12 PINMUX13[15:12] M3
AXR1[9] / GP4[9] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function AXR1[9]
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP4[9]
other = Reserved - Behavior is Undefined.
AXR1[8] / EPWM1A / GP4[8]
0000 = Pin is tri-stated.
0001 = Selects Output Function AXR1[8]
0010 = Reserved - Behavior is Undefined.
0100 = Selects Output Function EPWM1A
1000 = Selects Output Function GP4[8]
other = Reserved - Behavior is Undefined.
AXR1[7] / EPWM1B / GP4[7] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function AXR1[7]
0010 = Selects Output Function EPWM1B
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP4[7]
other = Reserved - Behavior is Undefined.
11:8 PINMUX13[11:8]
M4
N1
N2
AXR1[6] / EPWM2A / GP4[6] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function AXR1[6]
0010 = Selects Output Function EPWM2A
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP4[6]
other = Reserved - Behavior is Undefined.
7:4
3:0
PINMUX13[7:4]
PINMUX13[3:0]
AXR1[5] / EPWM2B / GP4[5] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function AXR1[5]
0010 = Selects Output Function EPWM2B
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP4[5]
other = Reserved - Behavior is Undefined.
AXR1[4] / EQEP1B / GP4[4] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function AXR1[4]
0010 = Selects Output Function EQEP1B
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP4[4]
other = Reserved - Behavior is Undefined.
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Device Configuration
53
OMAP-L137 Low-Power Applications Processor
SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
www.ti.com
4.2.15 PINMUX14 Register Definition (Address 0x01C1 4158 )
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
17
16
PINMUX14[31:28]
R/W-0
PINMUX14[27:24]
R/W-0
PINMUX14[23:20]
R/W-0
PINMUX14[19:16]
R/W-0
15
14
13
12
11
10
9
8
7
6
5
2
1
0
PINMUX14[15:12]
R/W-0
PINMUX14[11:8]
R/W-0
PINMUX14[7:4]
R/W-0
PINMUX14[3:0]
R/W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 4-15. PINMUX14 Register Bit Layout
Table 4-16. Field Descriptions for PINMUX14
Bits Field
ZKB Description
Ball
31:28 PINMUX14[31:28] T14 EMA_D[9] / UHPI_HD[9] / LCD_D[9] / GP0[9] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMA_D[9]
0010 = Selects Output Function UHPI_HD[9]
0100 = Selects Output Function LCD_D[9]
1000 = Selects Output Function GP0[9]
other = Reserved - Behavior is Undefined.
27:24 PINMUX14[27:24] N12 EMA_D[8] / UHPI_HD[8] / LCD_D[8] / GP0[8] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMA_D[8]
0010 = Selects Output Function UHPI_HD[8]
0100 = Selects Output Function LCD_D[8]
1000 = Selects Output Function GP0[8]
other = Reserved - Behavior is Undefined.
23:20 PINMUX14[23:20] M15 EMA_D[7] / MMCSD_DAT[7] / UHPI_HD[7] / GP0[7] / BOOT[13] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMA_D[7]
0100 = Selects Output Function UHPI_HD[7]
1000 = Selects Output Function GP0[7]
0010 = Selects Output Function MMCSD_DAT[7] other = Reserved - Behavior is Undefined.
19:16 PINMUX14[19:16] N13 EMA_D[6] / MMCSD_DAT[6] / UHPI_HD[6] / GP0[6]
0000 = Pin is tri-stated.
0001 = Selects Output Function EMA_D[6]
0100 = Selects Output Function UHPI_HD[6]
1000 = Selects Output Function GP0[6]
0010 = Selects Output Function MMCSD_DAT[6] other = Reserved - Behavior is Undefined.
15:12 PINMUX14[15:12] N15 EMA_D[5] / MMCSD_DAT[5] / UHPI_HD[5] / GP0[5] Control
0000 [Default] = Pin is tri-stated. 0100 = Selects Output Function UHPI_HD[5]
0001 = Selects Output Function EMA_D[5] 1000 = Selects Output Function GP0[5]
0010 = Selects Output Function MMCSD_DAT[5] other = Reserved - Behavior is Undefined.
11:8 PINMUX14[11:8]
P13 EMA_D[4] / MMCSD_DAT[4] / UHPI_HD[4] / GP0[4] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMA_D[4]
0100 = Selects Output Function UHPI_HD[4]
1000 = Selects Output Function GP0[4]
0010 = Selects Output Function MMCSD_DAT[4] other = Reserved - Behavior is Undefined.
7:4
3:0
PINMUX14[7:4]
PINMUX14[3:0]
P15 EMA_D[3] / MMCSD_DAT[3] / UHPI_HD[3] / GP0[3] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMA_D[3]
0100 = Selects Output Function UHPI_HD[3]
1000 = Selects Output Function GP0[3]
0010 = Selects Output Function MMCSD_DAT[3] other = Reserved - Behavior is Undefined.
R13 EMA_D[2] / MMCSD_DAT[2] / UHPI_HD[2] / GP0[2] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMA_D[2]
0100 = Selects Output Function UHPI_HD[2]
1000 = Selects Output Function GP0[2]
0010 = Selects Output Function MMCSD_DAT[2] other = Reserved - Behavior is Undefined.
54
Device Configuration
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SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
4.2.16 PINMUX15 Register Definition (Address 0x01C1 415C )
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
17
16
0
PINMUX15[31:28]
R/W-0
PINMUX15[27:24]
R/W-0
PINMUX15[23:20]
R/W-0
PINMUX15[19:16]
R/W-0
15
14
13
12
11
10
9
8
7
6
5
2
1
PINMUX15[15:12]
R/W-0
PINMUX15[11:8]
R/W-0
PINMUX15[7:4]
R/W-0
PINMUX15[3:0]
R/W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 4-16. PINMUX15 Register Bit Layout
Table 4-17. Field Descriptions for PINMUX15
Bits Field
ZKB Description
Ball
31:28 PINMUX15[31:28] R9
EMA_A[1] / MMCSD_CLK / UHPI_HCNTL0 / GP1[1] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMA_A[1]
0010 = Selects Output Function MMCSD_CLK
0100 = Selects Output Function UHPI_HCNTL0
1000 = Selects Output Function GP1[1]
other = Reserved - Behavior is Undefined.
27:24 PINMUX15[27:24] T9
EMA_A[0] / LCD_D[7] / GP1[0] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMA_A[0]
0010 = Selects Output Function LCD_D[7]
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP1[0]
other = Reserved - Behavior is Undefined.
23:20 PINMUX15[23:20] M16 EMA_D[15] / UHPI_HD[15] / LCD_D[15] / GP0[15] Control
0000 [Default] = Pin is tri-stated.
0100 = Selects Output Function LCD_D[15]
0001 = Selects Output Function EMA_D[15]
0010 = Selects Output Function UHPI_HD[15]
1000 = Selects Output Function GP0[15]
other = Reserved - Behavior is Undefined.
19:16 PINMUX15[19:16] N14 EMA_D[14] / UHPI_HD[14] / LCD_D[14] / GP0[14] Control
0000 = Pin is tri-stated.
0100 = Selects Output Function LCD_D[14]
0001 = Selects Output Function EMA_D[14]
0010 = Selects Output Function UHPI_HD[14]
1000 = Selects Output Function GP0[14]
other = Reserved - Behavior is Undefined.
15:12 PINMUX15[15:12] N16 EMA_D[13] / UHPI_HD[13] / LCD_D[13] / GP0[13] Control
0000 [Default] = Pin is tri-stated.
0100 = Selects Output Function LCD_D[13]
0001 = Selects Output Function EMA_D[13]
0010 = Selects Output Function UHPI_HD[13]
1000 = Selects Output Function GP0[13]
other = Reserved - Behavior is Undefined.
11:8 PINMUX15[11:8]
P14 EMA_D[12] / UHPI_HD[12] / LCD_D[12] / GP0[12] Control
0000 [Default] = Pin is tri-stated.
0100 = Selects Output Function LCD_D[12]
0001 = Selects Output Function EMA_D[12]
0010 = Selects Output Function UHPI_HD[12]
1000 = Selects Output Function GP0[12]
other = Reserved - Behavior is Undefined.
7:4
3:0
PINMUX15[7:4]
PINMUX15[3:0]
P16 EMA_D[11] / UHPI_HD[11] / LCD_D[11] / GP0[11] Control
0000 [Default] = Pin is tri-stated.
0100 = Selects Output Function LCD_D[11]
0001 = Selects Output Function EMA_D[11]
0010 = Selects Output Function UHPI_HD[11]
1000 = Selects Output Function GP0[11]
other = Reserved - Behavior is Undefined.
R14 EMA_D[10] / UHPI_HD[10] / LCD_D[10] / GP0[10] Control
0000 [Default] = Pin is tri-stated.
0100 = Selects Output Function LCD_D[10]
0001 = Selects Output Function EMA_D[10]
0010 = Selects Output Function UHPI_HD[10]
1000 = Selects Output Function GP0[10]
other = Reserved - Behavior is Undefined.
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Device Configuration
55
OMAP-L137 Low-Power Applications Processor
SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
www.ti.com
4.2.17 PINMUX16 Register Definition (Address 0x01C1 4160 )
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
17
16
PINMUX16[31:28]
R/W-0
PINMUX16[27:24]
R/W-0
PINMUX16[23:20]
R/W-0
PINMUX16[19:16]
R/W-0
15
14
13
12
11
10
9
8
7
6
5
2
1
0
PINMUX16[15:12]
R/W-0
PINMUX16[11:8]
R/W-0
PINMUX16[7:4]
R/W-0
PINMUX16[3:0]
R/W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 4-17. PINMUX16 Register Bit Layout
Table 4-18. Field Descriptions for PINMUX16
Bits Field
ZKB Description
Ball
31:28 PINMUX16[31:28] R11 EMA_A[9] / LCD_HSYNC / GP1[9] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMA_A[9]
0010 = Selects Output Function LCD_HSYNC
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP1[9]
other = Reserved - Behavior is Undefined.
27:24 PINMUX16[27:24] T11 EMA_A[8] / LCD_PCLK / GP1[8] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMA_A[8]
0010 = Selects Output Function LCD_PCLK
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP1[8]
other = Reserved - Behavior is Undefined.
23:20 PINMUX16[23:20] N10 EMA_A[7] / LCD_D[0] / GP1[7] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMA_A[7]
0010 = Selects Output Function LCD_D[0]
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP1[7]
other = Reserved - Behavior is Undefined.
19:16 PINMUX16[19:16] P10 EMA_A[6] / LCD_D[1] / GP1[6] Control
0000 = Pin is tri-stated.
0001 = Selects Output Function EMA_A[6]
0010 = Selects Output Function LCD_D[1]
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP1[6]
other = Reserved - Behavior is Undefined.
15:12 PINMUX16[15:12] R10 EMA_A[5] / LCD_D[2] / GP1[5] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMA_A[5]
0010 = Selects Output Function LCD_D[2]
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP1[5]
other = Reserved - Behavior is Undefined.
11:8 PINMUX16[11:8]
T10 EMA_A[4] / LCD_D[3] / GP1[4] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMA_A[4]
0010 = Selects Output Function LCD_D[3]
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP1[4]
other = Reserved - Behavior is Undefined.
7:4
3:0
PINMUX16[7:4]
PINMUX16[3:0]
N9
P9
EMA_A[3] / LCD_D[6] / GP1[3] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMA_A[3]
0010 = Selects Output Function LCD_D[6]
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP1[3]
other = Reserved - Behavior is Undefined.
EMA_A[2] / MMCSD_CMD / UHPI_HCNTL1 / GP1[2] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMA_A[2]
0010 = Selects Output Function MMCSD_CMD
0100 = Selects Output Function UHPI_HCNTL1
1000 = Selects Output Function GP1[2]
other = Reserved - Behavior is Undefined.
56
Device Configuration
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SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
4.2.18 PINMUX17 Register Definition (Address 0x01C1 4164 )
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
17
16
0
PINMUX17[31:28]
R/W-0
PINMUX17[27:24]
R/W-0
PINMUX17[23:20]
R/W-0
PINMUX17[19:16]
R/W-0
15
14
13
12
11
10
9
8
7
6
5
2
1
PINMUX17[15:12]
R/W-0
PINMUX17[11:8]
R/W-0
PINMUX17[7:4]
R/W-0
PINMUX17[3:0]
R/W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 4-18. PINMUX17 Register Bit Layout
Table 4-19. Field Descriptions for PINMUX17
Bits Field
ZKB Description
Ball
31:28 PINMUX17[31:28] L16 EMA_CAS / EMA_CS[4] / GP2[1] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMA_CAS
0010 = Selects Output Function EMA_CS[4]
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP2[1]
other = Reserved - Behavior is Undefined.
27:24 PINMUX17[27:24] T12 EMA_SDCKE / GP2[0] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMA_SDCKE
0010 = Reserved - Behavior is Undefined
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP2[0]
other = Reserved - Behavior is Undefined.
23:20 PINMUX17[23:20] R12 EMA_CLK / OBSCLK / AHCLKR2 / GP1[15] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMA_CLK
0010 = Selects Output Function OBSCLK
0100 = Selects Output Function AHCLKR2
1000 = Selects Output Function GP1[15]
other = Reserved - Behavior is Undefined.
19:16 PINMUX17[19:16] R8
15:12 PINMUX17[15:12] P8
EMA_BA[0] / LCD_D[4] / GP1[14] Control
0000 = Pin is tri-stated.
0001 = Selects Output Function EMA_BA[0]
0010 = Selects Output Functio LCD_D[4]
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP1[14]
other = Reserved - Behavior is Undefined.
EMA_BA[1] / LCD_D[5] / UHPI_HHWIL / GP1[13] Control
0000 [Default] = Pin is tri-stated.
0100 = Selects Output Function UHPI_HHWIL
0001 = Selects Output Function EMA_BA[1]
0010 = Selects Output Function LCD_D[5]
1000 = Selects Output Function GP1[13]
other = Reserved - Behavior is Undefined.
11:8 PINMUX17[11:8]
N11 EMA_A[12] / LCD_MCLK / GP1[12] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMA_A[12]
0010 = Selects Output Function LCD_MCLK
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP1[12]
other = Reserved - Behavior is Undefined.
7:4
3:0
PINMUX17[7:4]
PINMUX17[3:0]
P11 EMA_A[11] / LCD_AC_ENB_CS / GP1[11] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMA_A[11]
0010 = Selects Output Function
LCD_AC_ENB_CS
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP1[11]
other = Reserved - Behavior is Undefined.
N8
EMA_A[10] / LCD_VSYNC / GP1[10] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMA_A[10]
0010 = Selects Output Function LCD_VSYNC
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP1[10]
other = Reserved - Behavior is Undefined.
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57
OMAP-L137 Low-Power Applications Processor
SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
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4.2.19 PINMUX18 Register Definition (Address 0x01C1 4168 )
31
30
29
28
27
26
25
24
23
22
21
20
4
19
3
18
17
16
PINMUX18[31:28]
R/W-0
PINMUX18[27:24]
R/W-0
PINMUX18[23:20]
R/W-0
PINMUX18[19:16]
R/W-0
15
14
13
12
11
10
9
8
7
6
5
2
1
0
PINMUX18[15:12]
R/W-0
PINMUX18[11:8]
R/W-0
PINMUX18[7:4]
R/W-0
PINMUX18[3:0]
R/W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 4-19. PINMUX18 Register Bit Layout
Table 4-20. Field Descriptions for PINMUX18
Bits Field
ZKB Description
Ball
31:28 PINMUX18[31:28] M14 EMA_WE_DQM[0] / UHPI_HINT / AXR0[15] / GP2[9] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function
EMA_WE_DQM[0]
0100 = Selects Output Function AXR0[15]
1000 = Selects Output Function GP2[9]
other = Reserved - Behavior is Undefined.
0010 = Selects Output Function UHPI_HINT
27:24 PINMUX18[27:24] P12 EMA_WE_DQM[1] / UHPI_HDS2 / AXR0[14] / GP2[8] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function
EMA_WE_DQM[1]
0100 = Selects Output Function AXR0[14]
1000 = Selects Output Function GP2[8]
other = Reserved - Behavior is Undefined.
0010 = Selects Output Function UHPI_HDS2
23:20 PINMUX18[23:20] R7
19:16 PINMUX18[19:16] T7
15:12 PINMUX18[15:12] P7
EMA_OE / UHPI_HDS1 / AXR0[13] / GP2[7] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMA_OE
0010 = Selects Output Function UHPI_HDS1
0100 = Selects Output Function AXR0[13]
1000 = Selects Output Function GP2[7]
other = Reserved - Behavior is Undefined.
EMA_CS[3] / AMUTE2 / GP2[6]
0000 = Pin is tri-stated.
0001 = Selects Output Function EMA_CS[3]
0010 = Reserved - Behavior is Undefined.
0100 = Selects Output Function AMUTE2
1000 = Selects Output Function GP2[6]
other = Reserved - Behavior is Undefined.
EMA_CS[2] / UHPI_HCS / GP2[5] / BOOT[15] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMA_CS[2]
0010 = Selects Output Function UHPI_HCS
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP2[5]
other = Reserved - Behavior is Undefined.
11:8 PINMUX18[11:8]
T8
EMA_CS[0] / UHPI_HAS / GP2[4] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMA_CS[0]
0010 = Selects Output Function UHPI_HAS
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP2[4]
other = Reserved - Behavior is Undefined.
7:4
3:0
PINMUX18[7:4]
PINMUX18[3:0]
M13 EMA_WE / UHPI_HRW / AXR0[12] / GP2[3] / BOOT[14] Control
0000 [Default] = Pin is tri-stated.
0100 = Selects Output Function AXR0[12]
0001 = Selects Output Function EMA_WE
0010 = Selects Output Function UHPI_HRW
1000 = Selects Output Function GP2[3]
other = Reserved - Behavior is Undefined.
N7
EMA_RAS / EMA_CS[5] / GP2[2] Control
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMA_RAS
0010 = Selects Output Function EMA_CS[5]
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP2[2]
other = Reserved - Behavior is Undefined.
58
Device Configuration
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SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
4.2.20 PINMUX19 Register Definition (Address 0x01C1 416C )
31
30
29
28
27
26
25
24
Reserved
R/W-0
23
22
21
5
20
4
19
3
18
17
16
0
15
14
13
12
11
10
9
8
7
6
2
1
Reserved
R/W-0
LEGEND: R = Read, W = Write, n = value at reset
PINMUX19[3:0]
R/W-0
Figure 4-20. PINMUX19 Register Bit Layout
Table 4-21. Field Descriptions for PINMUX19
Bits Field
ZKB Description
Ball
31:4 Reserved
Reserved - Write '0' to this register field when modifying this register.
EMA_WAIT[0] / UHPI_HRDY / GP2[10] Control
3:0
PINMUX19[3:0]
N6
0000 [Default] = Pin is tri-stated.
0001 = Selects Output Function EMA_WAIT[0]
0010 = Selects Output Function UHPI_HRDY
0100 = Reserved - Behavior is Undefined
1000 = Selects Output Function GP2[10]
other = Reserved - Behavior is Undefined.
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59
OMAP-L137 Low-Power Applications Processor
SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
www.ti.com
4.3 Bus Master Priority Configuration
The on chip switch fabric performs priority based arbitration among the various bus masters on the SOC .
The priority of each master is controlled by the MSTPRI0, MSTPRI1, and MSTPRI2 registers and may be
adjusted as required to suite a particular application. Section 4.3.1 through Section 4.3.3 give provide a
detailed description of these registers.
60
Device Configuration
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4.3.1 MSTPRI0 Register Definition (0x01C1 4110)
31
30
29
28
27
26
25
24
23
22
6
21
20
4
19
18
2
17
16
0
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
R/W-0
R/W-100
R/W-0
R/W-100
R/W-0
R/W-100
R/W-0
R/W-100
15
14
13
12
11
10
9
8
7
5
3
1
RSV
DSP_CFG
R/W-010
RSV
DSP_MDMA
R/W-010
RSV
ARM_D
RSV
ARM_I
R/W-0
R/W-0
R/W-0
R/W-010
R/W-0
R/W-010
LEGEND: R = Read, W = Write, n = value at reset
Figure 4-21. MSTPRI0 Bit Description
Table 4-22. MSTPRI0 Field Descriptions
Bit
Field
Description
Reserved - Write 0 to this Field when modifying this register.
Reserved For Future Use - Write Default Value to Maintain Compatibility - Default Value is 100
31
RSV
30:28 RSV
000 = Priority 0 (Highest)
001 = Priority 1
010 = Priority 2
011 = Priority 3
100 = Priority 4
101 = Priority 5
110 = Priority 6
111 = Priority 7 (lowest)
27
RSV
Reserved - Write 0 to this Field when modifying this register.
Reserved For Future Use - Write Default Value to Maintain Compatibility - Default Value is 100
26:24 RSV
000 = Priority 0 (Highest)
001 = Priority 1
010 = Priority 2
011 = Priority 3
100 = Priority 4
101 = Priority 5
110 = Priority 6
111 = Priority 7 (lowest)
23
RSV
Reserved - Write 0 to this Field when modifying this register.
Reserved For Future Use - Write Default Value to Maintain Compatibility - Default Value is 100
22:20 RSV
000 = Priority 0 (Highest)
001 = Priority 1
010 = Priority 2
011 = Priority 3
100 = Priority 4
101 = Priority 5
110 = Priority 6
111 = Priority 7 (lowest)
19
RSV
Reserved - Write 0 to this Field when modifying this register.
Reserved For Future Use - Write Default Value to Maintain Compatibility - Default Value is 100
18:16 RSV
000 = Priority 0 (Highest)
001 = Priority 1
010 = Priority 2
011 = Priority 3
100 = Priority 4
101 = Priority 5
110 = Priority 6
111 = Priority 7 (lowest)
15
RSV
Reserved - Write 0 to this Field when modifying this register.
Bus Priority for Bus Master DSP - Configuration Bus - Default Value is 010
14:12 DSP_CFG
000 = Priority 0 (Highest)
001 = Priority 1
010 = Priority 2
011 = Priority 3
100 = Priority 4
101 = Priority 5
110 = Priority 6
111 = Priority 7 (lowest)
11
RSV
Reserved - Write 0 to this Field when modifying this register.
Bus Priority for Bus Master DSP - DMA Bus - Default Value is 010
10:8 DSP_MDMA
000 = Priority 0 (Highest)
001 = Priority 1
010 = Priority 2
011 = Priority 3
100 = Priority 4
101 = Priority 5
110 = Priority 6
111 = Priority 7 (lowest)
7
RSV
Reserved - Write 0 to this Field when modifying this register.
Bus Priority for Bus Master ARM - Data Fetch - Default Value is 010
6:4
ARM_D
000 = Priority 0 (Highest)
001 = Priority 1
010 = Priority 2
011 = Priority 3
100 = Priority 4
101 = Priority 5
110 = Priority 6
111 = Priority 7 (lowest)
3
RSV
Reserved - Write 0 to this Field when
modifying this register.
2:0
ARM_I
Bus Priority for Bus Master ARM - Instruction Fetch - Default Value is 010
000 = Priority 0 (Highest)
001 = Priority 1
010 = Priority 2
011 = Priority 3
100 = Priority 4
101 = Priority 5
110 = Priority 6
111 = Priority 7 (lowest)
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4.3.2 MSTPRI1 Register Definition (0x01C1 4114)
31
30
29
28
27
26
25
24
23
22
6
21
20
4
19
18
2
17
16
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
R/W-0
R/W-100
R/W-0
R/W-100
R/W-0
R/W-100
R/W-0
R/W-100
1
15
14
13
12
11
10
9
8
7
5
3
0
RSV
TC1
RSV
TC0
RSV
RSV
RSV
RSV
R/W-0
R/W-000
R/W-0
R/W-000
R/W-0
R/W-000
R/W-0
R/W-000
LEGEND: R = Read, W = Write, n = value at reset
Figure 4-22. MSTPRI1 Bit Description
Table 4-23. MSTPRI1 Field Descriptions
Bit
Field
Description
Reserved - Write 0 to this Field when modifying this register.
Reserved For Future Use - Write Default Value to Maintain Compatibility - Default Value is 100
31
RSV
30:28 RSV
000 = Priority 0 (Highest)
001 = Priority 1
010 = Priority 2
011 = Priority 3
100 = Priority 4
101 = Priority 5
110 = Priority 6
111 = Priority 7 (lowest)
27
RSV
Reserved - Write 0 to this Field when modifying this register.
Reserved For Future Use - Write Default Value to Maintain Compatibility - Default Value is 100
26:24 RSV
000 = Priority 0 (Highest)
001 = Priority 1
010 = Priority 2
011 = Priority 3
100 = Priority 4
101 = Priority 5
110 = Priority 6
111 = Priority 7 (lowest)
23
RSV
Reserved - Write 0 to this Field when modifying this register.
Reserved For Future Use - Write Default Value to Maintain Compatibility - Default Value is 100
22:20 RSV
000 = Priority 0 (Highest)
001 = Priority 1
010 = Priority 2
011 = Priority 3
100 = Priority 4
101 = Priority 5
110 = Priority 6
111 = Priority 7 (lowest)
19
RSV
Reserved - Write 0 to this Field when modifying this register.
Reserved For Future Use - Write Default Value to Maintain Compatibility - Default Value is 100
18:16 RSV
000 = Priority 0 (Highest)
001 = Priority 1
010 = Priority 2
011 = Priority 3
100 = Priority 4
101 = Priority 5
110 = Priority 6
111 = Priority 7 (lowest)
15
RSV
Reserved - Write 0 to this Field when modifying this register.
Bus Priority for Bus Master EDMA3 TC1 - Default Value is 000
14:12 TC1
000 = Priority 0 (Highest)
001 = Priority 1
010 = Priority 2
011 = Priority 3
100 = Priority 4
101 = Priority 5
110 = Priority 6
111 = Priority 7 (lowest)
11
RSV
Reserved - Write 0 to this Field when modifying this register.
Bus Priority for Bus Master EDMA3 TC0 - Default Value is 000
10:8 TC0
000 = Priority 0 (Highest)
001 = Priority 1
010 = Priority 2
011 = Priority 3
100 = Priority 4
101 = Priority 5
110 = Priority 6
111 = Priority 7 (lowest)
7:0
RSV
Reserved - Write 0 to this Field when modifying this register.
62
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4.3.3 MSTPRI2 Register Definition (0x01C1 4118)
31
30
29
28
27
26
25
24
23
22
6
21
20
4
19
18
2
17
16
0
RSV
LCDC
RSV
USB1
RSV
UHPI
RSV
RSV
R/W-0
R/W-101
R/W-0
R/W-100
R/W-0
R/W-110
R/W-0
R/W-000
15
14
13
12
11
10
9
8
7
5
3
1
RSV
USB0
RSV
USB0
RSV
RSV
RSV
EMAC
R/W-0
R/W-100
R/W-0
R/W-100
R/W-0
R/W-000
R/W-0
R/W-100
LEGEND: R = Read, W = Write, n = value at reset. In a loaded system, the LCDC default priority value of 5 might not be a good default and
may need to be changed.
Figure 4-23. MSTPRI2 Bit Description
Table 4-24. MSTPRI2 Field Descriptions
Bit
Field
Description
31
RSV
Reserved - Write 0 to this Field when modifying this register.
Bus Priority for Bus Master LCDC - Default Value is 101
30:28 LCDC
000 = Priority 0 (Highest)
001 = Priority 1
010 = Priority 2
011 = Priority 3
100 = Priority 4
101 = Priority 5
110 = Priority 6
111 = Priority 7 (lowest)
27
RSV
Reserved - Write 0 to this Field when modifying this register.
Bus Priority for Bus Master USB1 - Default Value is 100
26:24 USB1
000 = Priority 0 (Highest)
001 = Priority 1
010 = Priority 2
011 = Priority 3
100 = Priority 4
101 = Priority 5
110 = Priority 6
111 = Priority 7 (lowest)
23
RSV
Reserved - Write 0 to this Field when modifying this register.
Bus Priority for Bus Master UHPI - Default Value is 110
22:20 UHPI
000 = Priority 0 (Highest)
001 = Priority 1
010 = Priority 2
011 = Priority 3
100 = Priority 4
101 = Priority 5
110 = Priority 6
111 = Priority 7 (lowest)
19
RSV
Reserved - Write 0 to this Field when modifying this register.
Reserved For Future Use - Write Default Value to Maintain Compatibility - Default Value is 000
18:16 RSV
000 = Priority 0 (Highest)
001 = Priority 1
010 = Priority 2
011 = Priority 3
100 = Priority 4
101 = Priority 5
110 = Priority 6
111 = Priority 7 (lowest)
15
RSV
Reserved - Write 0 to this Field when modifying this register.
Bus Priority for Bus Master USB0 - Default Value is 100
14:12 USB0
000 = Priority 0 (Highest)
001 = Priority 1
010 = Priority 2
011 = Priority 3
100 = Priority 4
101 = Priority 5
110 = Priority 6
111 = Priority 7 (lowest)
11
RSV
Reserved - Write 0 to this Field when modifying this register.
Bus Priority for Bus Master USB0 - Default Value is 100
10:8 USB0
000 = Priority 0 (Highest)
001 = Priority 1
010 = Priority 2
011 = Priority 3
100 = Priority 4
101 = Priority 5
110 = Priority 6
111 = Priority 7 (lowest)
7
RSV
RSV
Reserved - Write 0 to this Field when modifying this register.
Reserved For Future Use - Write Default Value to Maintain Compatibility - Default Value is 000
6:4
000 = Priority 0 (Highest)
001 = Priority 1
010 = Priority 2
011 = Priority 3
100 = Priority 4
101 = Priority 5
110 = Priority 6
111 = Priority 7 (lowest)
3
RSV
Reserved - Write 0 to this Field when modifying this register.
Bus Priority for Bus Master EMAC - Default Value is 100
2:0
EMAC
000 = Priority 0 (Highest)
001 = Priority 1
010 = Priority 2
011 = Priority 3
100 = Priority 4
101 = Priority 5
110 = Priority 6
111 = Priority 7 (lowest)
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4.4 Chip Configuration Registers (CFGCHIP and SUSPSRC)
These registers control EDMA3 default transfer burst sizes, clock muxing, McASP AMUTE and eCAP
sources, UHPI enable and configuration, and USB PHY settings
4.4.1 CFGCHIP0
31
30
29
28
27
26
25
24
Reserved
R-n/a
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
R-n/a
Reserved
R/W-000
PLLMASTERLOCK
R/W-0
TC1DBS
R/W-00
TC0DBS
R/W-00
R/W-1
LEGEND: R = Read, W = Write, n = value at reset
Figure 4-24. CFGCHIP0 Register Bit Layout
Table 4-25. CFGCHIP0 Field Description
Bit
31:5
4
Field
Description
Reserved
Reserved
PLL_MASTER_LOCK
This bit is used to lock the PLL MMRs
0 = PLLCTRL MMR registers are freely accessible.
1 = PLLCTRL MMR registers are locked.
3:2
1:0
TC1DBS
TC0DBS
EDMA3 TC1 Default Burst Size
00 = 16 byte
01 = 32 byte
10 = 64 byte
11 = Reserved
EDMA3 TC1 Default Burst Size
00 = 16 byte
01 = 32 byte
10 = 64 byte
11 = Reserved
64
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4.4.2 CFGCHIP1
31
30
29
28
27
26
25
24
23
9
22
8
21
20
19
18
17
16
CAP2SRC
R/W-0
CAP1SRC
CAP0SRC
HPIBYTEAD
R/W-0
R/W-0
R/W-0
4
15
HPIENA
R/W-0
14
13
12
TBCLKSYNC
11
10
7
6
5
3
2
1
0
Rsvd
AMUTESEL2
AMUTESEL1
R/W-0
AMUTESEL0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 4-25. CFGCHIP1 Register Bit Layout
Table 4-26. CFGCHIP1 Field Description
Bit
Field
Description
31:27 CAP2SRC
26:22 CAP1SRC
21:17 CAP0SRC
eCAP2 Module Event Input Select
eCAP1 Module Event Input Select
eCAP0 Module Event Input Select
For each eCAPx (x=0,1,2):
00000 = eCAPx Pin Input
00001 = McASP0 TX DMA Event
00010 = McASP0 RX DMA Event
00011 = McASP1 TX DMA Event
00100 = McASP1 RX DMA Event
00101 = McASP2 TX DMA Event
00110 = McASP2 RX DMA Event
00111 = EMAC C0 RX Threshold Pulse Interrupt
01000 = EMAC C0 RX Pulse Interrupt
01001 = EMAC C0 TX Pulse Interrupt
01010 = EMAC C0 Misc Interrupt01011 = EMAC C1 RX Threshold Pulse Interrupt
01100 = EMAC C1 RX Pulse Interrupt
01101 = EMAC C1 TX Pulse Interrupt
01110 = EMAC C1 Misc Interrupt
01111 = EMAC C2 RX Threshold Pulse Interrupt
10000 = EMAC C2 RX Pulse Interrupt
10001 = EMAC C2 TX Pulse Interrupt
10010 = EMAC C2 Misc Interrupt
10011 - 11111 = Reserved
16
15
HPIBYTEAD
HPIENA
HPI Module Byte / Word Address Mode
0 = Host Address is a word address
HPI Enable Bit
1 = Host Address is a byte address
1 = HPI Enabled
0 = HPI Disabled
14:13 Reserved
Reserved
12
TBCLKSYNC
eHRPWM Module Time Base Clock Sync
0 (default) = The TBCLK (Time Base
Clock) within each enabled
eHRPWM is stopped.
1 = All enabled eHRPWM module
clocks are started with the first
rising edge of TBCLK aligned.
11:8
7:4
AMUTESEL2
AMUTESEL1
AMUTESEL0
Selects the source of the McASP2 AMUTEIN signal
Selects the source of the McASP1 AMUTEIN signal
Selects the source of the McASP0 AMUTEIN signal
3:0
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Table 4-26. CFGCHIP1 Field Description (continued)
Bit
Field
Description
For each McASPx (x=0,1,2)
0000 = Drive McASPx AMUTEIN Low
0001 = McASPx AMUTEIN source is GPIO Interrupt from Bank 0
0010 = McASPx AMUTEIN source is GPIO Interrupt from Bank 1
0011 = McASPx AMUTEIN source is GPIO Interrupt from Bank 2
0100 = McASPx AMUTEIN source is GPIO Interrupt from Bank 3
0101 = McASPx AMUTEIN source is GPIO Interrupt from Bank 4
0110 = McASPx AMUTEIN source is GPIO Interrupt from Bank 5
0111 =McASPx AMUTEIN source is GPIO Interrupt from Bank 6
1000 = McASPx AMUTEIN source is GPIO Interrupt from Bank 7
1001 - 1111 are reserved
66
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4.4.3 CFGCHIP2
31
30
29
28
27
26
25
24
RESERVED
R-n/a
23
22
21
20
19
18
17
USB0PHYCLKGD
16
USB0VBUSSENSE
RESERVED
R-n/a
15
14
13
12
11
10
9
8
RESET
USB0OTGMODE
USB1PHYCLKMUX
USB0PHYCLKMUX USB0PHYPWDN USB0OTGPWRDN USB0DATPO
L
R/W-1
R/W-11
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
7
6
5
4
3
2
1
0
USB1SUSPENDM
R/W-0
USB0PHY_PLLON USB0SESNDEN USB0VBDTCTEN
R/W-0 R/W-0 R/W-0
USB0REF-FREQ[3:0]
R/W-0000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 4-26. CFGCHIP2 Register Bit Layout
Table 4-27. CFGCHIP2 Field Description
Bit
Field
Description
31:8
17
Reserved
Reserved
USB0PHYCLKGD
USB0VBUSSENSE
Reset
Indicates clock is present, power is good and phy PLL is locked.
Indicates status of VBUS detection.
16
15
When '1' drives 'phy_reset' active to put the phy UTMI+ interface in reset.
14:13
USB0OTGMODE
OTGMODE = 00. Do not override phy values. Let PHY drive signals to controller based
on its comparators for the VBUS and ID pins.
OTGMODE = 01. Override phy values to force USB Host Operation.
Force VBUSVALID = 1, SESSVALID = 1, SESSEND = 0, IDDIG = 0
OTGMODE = 10. Override phy values to force USB Device Operation.
Force VBUSVALID = 1, SESSVALID = 1, SESSEND = 0, IDDIG = 1
OTGMODE = 11. Override phy values to force USB Host Operation with VBUS low.
Force VBUSVALID = 0, SESSVALID = 0, SESSEND = 1, IDDIG = 0
12
11
USB1PHYCLKMUX
USB0PHYCLKMUX
USB1 PHY Clock Source.
1 = USB1 Phy Clock (48 MHz) is sourced by an external pin.
0 = USB1 Phy Clock (48 MHz) is sourced by the 48 MHz output of the USB0 PHY.
USB0 PHY Clock Source.
1 = USB0 Phy reference clock internally generated.
0 = USB0 Phy reference clock comes from pin.
10
9
USB0PHYPWDN
Phy Powerdown 0=Phy is powered up, 1=Phy is powered down.
USB0OTGPWRDN
OTG Analog Module Powerdown 0=OTG Analog Module is powered up, 1=OTG Analog
Module is powered down.
8
7
6
USB0DATPOL
USB0 Data Polarity, 0 = Reversed DP/DM polarity, 1 = Normal DP/DM polarity.
USB1SUSPENDM
USB0PHY_PLLON
USB1 Phy Suspend, Program to '0' if USB1 is not used, Program to '1' if USB1 is used.
USB0 Phy PLL On, 0 = Normal USB Behavior, 1 = Override USB SUSPEND behavior
and release PLL from SUSPEND state.
5
4
USB0SESNDEN
USB0VBDTCTEN
Turns on session end comparator.
Turns on all VBUS line comparators.
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Table 4-27. CFGCHIP2 Field Description (continued)
Bit
Field
Description
3:0
USB0REF-FREQ[3:0]
USB0 Phy Clock Input Select.
0000 = Reserved
0001 = 12 MHz
0010 = 24 MHz
0011 = 48 MHz
0100 = 19.2 MHz
0101 = 38.4 MHz
0110 = 13 MHz
0111 = 26 MHz
1000 = 20 MHz
1001 = 40 MHz
1010 = Reserved
1011 = Reserved
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = Reserved
4.4.4 CFGCHIP3
31
30
29
28
12
27
11
26
10
25
24
23
22
21
20
19
18
17
16
0
Reserved
R-n/a
7
15
14
13
9
8
6
5
4
3
2
1
Reserved
Reserved
DIV4P5EN EMA_CL EMB_C
A
KSRC
LKSRC
R/W-1
LEGEND: R = Read, W = Write, n = value at reset
R/W-0
R/W-0
R/W-0
R/W-0
Figure 4-27. CFGCHIP3 Register Bit Layout
Table 4-28. CFGCHIP3 Field Description
Bit
Field
Description
31:16
15:8
7:3
Reserved
Reserved
Reserved
DIV4P5ENA
Reserved
Reserved
Reserved
2
Fixed 4.5 divider Enable.
0 = Divide by 4.5 is Disabled. 1 = Divide by 4.5 is Enabled.
1
0
EMA_CLKSRC
EMB_CLKSRC
EMIF A Memory Clock Source Select.
0 = EMIFA clock domain is driven by the PLLCTRL SYSCLK3 output.
1 = EMIFA clock domain is driven by the fixed / 4.5 PLL output.
EMIF B Memory Clock Source Select.
0 = EMIFB SDRAM clock domain is driven by the PLLCTRL SYSCLK5 output.
1 = EMIFB SDRAM clock domain is driven by the fixed / 4.5 PLL output.
68
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4.4.5 CFGCHIP4
31
30
29
28
12
27
11
26
10
25
9
24
Reserved
R-n/a
23
22
6
21
20
4
19
3
18
17
16
15
14
13
8
7
5
2
1
0
Reserved
Reserved
AMUT AMUT AMUT
ECLR ECLR ECLR
2
1
0
R/W-1
LEGEND: R = Read, W = Write, n = value at reset
R/W-0
R/W-0 R/W-0 R/W-0
Figure 4-28. CFGCHIP4 Register Bit Layout
Table 4-29. CFGCHIP4 Field Description
Bit
Field
Description
31:16
15:8
7:3
Reserved
Reserved
Reserved
AMUTECLR2
Reserved
Reserved
Reserved
2
Write 1 causes a single pulse that clears the 'latched' GPIO interrupt for AMUTEIN of McASP2
when '1'. Always reads back '0'.
1
0
AMUTECLR1
AMUTECLR0
Write 1 causes a single pulse that clears the 'latched' GPIO interrupt for AMUTEIN of McASP1
when '1'. Always reads back '0'.
Write 1 causes a single pulse that clears the 'latched' GPIO interrupt for AMUTEIN of McASP1
when '1'. Always reads back '0'.
4.4.6 SUSPSRC
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
TIMER TIMER GPIOS ePWM ePWM ePWM SPI1
SPI0 UART UART UART
I2C1
SRC
I2C0
SRC
64P1
12
64P0
RC
2SRC 1SRC 0SRC
R/W-1
SRC
SRC
5
2SRC 1 SRC 0SRC
15
14
13
11
10
9
8
7
6
4
3
2
1
0
MMC /
SD /
Reserved
HPI
SRC
RSV
USB1 USB0
SRC SRC
Reserved
RSV EMAC eQEP eQEP eCAP2 eCAP1 eCAP0
SRC 1 SRC 0 SRC SRC
SRC
SRC
SRC
R/W-1
LEGEND: R = Read, W = Write, n = value at reset
Figure 4-29. SUSPSRC Register Bit Layout
Table 4-30. SUSPSRC Field Descriptions
Bit Field
Description
31: RSV
29
Reserved
28 TIMER64P1
27 TIMER64P0
26 GPIOSRC
TIMER64P1 Suspend Source
0 = ARM emulation suspend, 1 = DSP emulation suspend
TIMER64P0 Suspend Source
0 = ARM emulation suspend, 1 = DSP emulation suspend
GPIO Module Suspend Source
0 = ARM emulation suspend, 1 = DSP emulation suspend
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Table 4-30. SUSPSRC Field Descriptions (continued)
Bit Field
Description
25 ePWM2SRC
ePWM2 Suspend Source
0 = ARM emulation suspend, 1 = DSP emulation suspend
ePWM1 Suspend Source
24 ePWM1SRC
23 ePWM0SRC
22 SPI1 SRC
21 SPI0 SRC
20 UART2 SRC
19 UART1 SRC
18 UART0 SRC
17 I2C1 SRC
16 I2C0 SRC
0 = ARM emulation suspend, 1 = DSP emulation suspend
ePWM0 Suspend Source
0 = ARM emulation suspend, 1 = DSP emulation suspend
SPI1 Suspend Source
0 = ARM emulation suspend, 1 = DSP emulation suspend
SPI0 Suspend Source
0 = ARM emulation suspend, 1 = DSP emulation suspend
UART2 SRC Suspend Source
0 = ARM emulation suspend, 1 = DSP emulation suspend
UART1 Suspend Source
0 = ARM emulation suspend, 1 = DSP emulation suspend
UART0 Suspend Source
0 = ARM emulation suspend, 1 = DSP emulation suspend
I2C1 Suspend Source
0 = ARM emulation suspend, 1 = DSP emulation suspend
I2C0 Suspend Source
0 = ARM emulation suspend, 1 = DSP emulation suspend
15 MMC/SD SRC MMC /SD Suspend Source
0 = ARM emulation suspend, 1 = DSP emulation suspend
Reserved
14: Reserved
13
12 HPI SRC
HPI Suspend Source
0 = ARM emulation suspend, 1 = DSP emulation suspend
Reserved
11 Reserved
10 USB1 SRC
USB1 Suspend Source
0 = ARM emulation suspend, 1 = DSP emulation suspend
USB0 Suspend Source
9
USB0 SRC
0 = ARM emulation suspend, 1 = DSP emulation suspend
Reserved
8:6 Reserved
5
4
3
2
1
0
EMACSRC
eQEP1SRC
eQEP0SRC
eCAP2SRC
eCAP1SRC
eCAP0SRC
EMAC Suspend Source
0 = ARM emulation suspend, 1 = DSP emulation suspend
eQEP1 Suspend Source
0 = ARM emulation suspend, 1 = DSP emulation suspend
eQEP0 Suspend Source
0 = ARM emulation suspend, 1 = DSP emulation suspend
eCAP2 Suspend Source
0 = ARM emulation suspend, 1 = DSP emulation suspend
eCAP1 Suspend Source
0 = ARM emulation suspend, 1 = DSP emulation suspend
eCAP0 Suspend Source
0 = ARM emulation suspend, 1 = DSP emulation suspend
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4.5 ARM/DSP Communication Registers
4.5.1 CHIPSIG
The CHIPSIG register provides a signaling mechanism between the ARM and DSP. Writing a '1' to a bit
causes the corresponding interrupt to be asserted. Writing a '0' has no effect. Reads return the value of
the bit.
31
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Rsvd
R-0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Rsvd
R-0
CHIPSIG[4:0]
W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 4-30. CHIPSIG Register Bit Layout
Table 4-31. CHIPSIG Field Description
Bit
31:5
4
Field
Description
Reserved
CHIPSIG[4]
CHIPSIG[3]
CHIPSIG[2]
CHIPSIG[1]
CHIPSIG[0]
Reserved
Asserts DSP NMI Interrupt.
Asserts DSP Interrupt CHIPSIG[3].
Asserts DSP Interrupt CHIPSIG[2].
Asserts ARM Interrupt CHIPSIG[1].
Asserts ARM Interrupt CHIPSIG[0].
3
2
1
0
4.5.2 CHIPSIG_CLR
The CHIPSIG_CLR register clears interrupts that have been initiated using the CHIPSIG register. Writing
a '1' to a bit clears the corresponding interrupt. Writing a '0' has no effect. Reads return the value of the
bit.
31
15
30
14
29
13
28
12
27
26
25
24
23
22
21
20
19
18
17
16
Rsvd
R-0
11
10
9
8
7
6
5
4
3
2
1
0
Rsvd
R-0
CHIPSIG[4:0]
W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 4-31. CHIPSIG_CLR Register Bit Layout
Table 4-32. CHIPSIG_CLR Field Description
Bit
31:5
4
Field
Description
Reserved
CHIPSIG[4]
CHIPSIG[3]
CHIPSIG[2]
CHIPSIG[1]
CHIPSIG[0]
Reserved
Clears DSP NMI Interrupt.
Clears DSP Interrupt CHIPSIG[3].
Clears DSP Interrupt CHIPSIG[2].
Clears ARM Interrupt CHIPSIG[1].
Clears ARM Interrupt CHIPSIG[0].
3
2
1
0
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4.6 Device Support
4.6.1 Development Support
TI offers an extensive line of development tools for the OMAP-L13x platform, including tools to evaluate
the performance of the processors, generate code, develop algorithm implementations, and fully integrate
and debug software and hardware modules. The tool's support documentation is electronically available
within the Code Composer Studio™ Integrated Development Environment (IDE).
The following products support development of OMAP-L13x applications:
Software Development Tools:
Code Composer Studio™ Integrated Development Environment (IDE): including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target
software needed to support any application.
Hardware Development Tools:
Extended Development System (XDS™) Emulator
For a complete listing of development-support tools for OMAP-L13x, visit the Texas Instruments web
site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For information on
pricing and availability, contact the nearest TI field sales office or authorized distributor.
4.6.2 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX,
TMP, or TMS (e.g., TMS320C6745). Texas Instruments recommends two of three possible prefix
designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of
product development from engineering prototypes (TMX/TMDX) through fully qualified production
devices/tools (TMS/TMDS).
Device development evolutionary flow:
X
Experimental device that is not necessarily representative of the final device's electrical
specifications.
P
Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification.
NULL
Fully-qualified production device.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully qualified development-support product.
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
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TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ZWT), the temperature range (for example, "Blank" is the commercial
temperature range), and the device speed range in megahertz (for example, "Blank" is the default).
Figure 4-32 provides a legend for reading the complete device name for any TMS320C674x member.
( )
( )
X
OMAPL137/L127
ZKB
3
PREFIX
3 = 300 MHz
2 = 200 MHz
X = Experimental Device
P = Prototype Device
Blank = Production Device
Blank = 0°C to 85°C (Commercial Grade)
= –40°C to 105°C (Automotive Grade)
T
DEVICE
PACKAGE TYPE
SILICON REVISION
ZKB = 256 Pin Plastic BGA, with Pb-free
Soldered Balls [Green]
Blank = Silicon Revision 1.0
A. BGA = Ball Grid Array
B. The device speed range symbolization indicates the maximum CPU frequency when the core voltage CVDD is set to
1.2 V.
Figure 4-32. Device Nomenclature
4.7 Documentation Support
4.7.1 Related Documentation From Texas Instruments
The following documents describe the OMAP-L13x Low-power Applications Processor. Copies of these
documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box
provided at www.ti.com.
C64x+ Reference Guides
SPRU186
TMS320C6000 Assembly Language Tools v 6.1 User's Guide. Describes the assembly
language tools (assembler, linker, and other tools used to develop assembly language code),
assembler directives, macros, common object file format, and symbolic debugging directives
for the TMS320C6000 platform of devices (including the C64x+ and C67x+ generations).
SPRU187
TMS320C6000 Optimizing Compiler v 6.1 User's Guide. Describes the TMS320C6000 C
compiler and the assembly optimizer. This C compiler accepts ANSI standard C source code
and produces assembly language source code for the TMS320C6000 platform of devices
(including the C64x+ and C67x+ generations). The assembly optimizer helps you optimize
your assembly code.
SPRU198
SPRU862
TMS320C6000 Programmer's Guide. Reference for programming the TMS320C6000 digital
signal processors (DSPs). Before you use this manual, you should install your code
generation and debugging tools. Includes a brief description of the C6000 DSP architecture
and code development flow, includes C code examples and discusses optimization methods
for the C code, describes the structure of assembly code and includes examples and
discusses optimizations for the assembly code, and describes programming considerations
for the C64x DSP.
TMS320C64x+ DSP Cache User's Guide. Explains the fundamentals of memory caches
and describes how the two-level cache-based internal memory architecture in the
TMS320C64x+ digital signal processor (DSP) of the TMS320C6000 DSP family can be
efficiently used in DSP applications. Shows how to maintain coherence with external
memory, how to use DMA to reduce memory latencies, and how to optimize your code to
improve cache efficiency. The internal memory architecture in the C64x+ DSP is organized
in a two-level hierarchy consisting of a dedicated program cache (L1P) and a dedicated data
cache (L1D) on the first level. Accesses by the CPU to the these first level caches can
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complete without CPU pipeline stalls. If the data requested by the CPU is not contained in
cache, it is fetched from the next lower memory level, L2 or external memory.
SPRU871
TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital
signal processor (DSP) megamodule. Included is a discussion on the internal direct memory
access (IDMA) controller, the interrupt controller, the power-down controller, memory
protection, bandwidth management, and the memory and cache.
Primus DSP Reference Guides
SPRUG82
TMS320C674x DSP Cache User's Guide. Explains the fundamentals of memory caches
and describes how the two-level cache-based internal memory architecture in the
TMS320C674x digital signal processor (DSP) can be efficiently used in DSP applications.
Shows how to maintain coherence with external memory, how to use DMA to reduce
memory latencies, and how to optimize your code to improve cache efficiency. The internal
memory architecture in the C674x DSP is organized in a two-level hierarchy consisting of a
dedicated program cache (L1P) and a dedicated data cache (L1D) on the first level.
Accesses by the CPU to the these first level caches can complete without CPU pipeline
stalls. If the data requested by the CPU is not contained in cache, it is fetched from the next
lower memory level, L2 or external memory.
SPRUFE8
SPRUG84
SPRUFK5
SPRUGA6
TMS320C674x DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C674x digital signal
processors (DSPs). The C674x DSP is an enhancement of the C64x+ and C67x+ DSPs with
added functionality and an expanded instruction set.
OMAP-L137 Applications Processor System Reference Guide. Describes the
System-on-Chip (SoC) including the ARM subsystem, DSP subsystem, system memory,
device clocking, phase-locked loop controller (PLLC), power and sleep controller (PSC),
power management, ARM interrupt controller (AINTC), and system configuration module.
TMS320C674x DSP Megamodule Reference Guide. Describes the TMS320C674x digital
signal processor (DSP) megamodule. Included is a discussion on the internal direct memory
access (IDMA) controller, the interrupt controller, the power-down controller, memory
protection, bandwidth management, and the memory and cache.
OMAP-L137 Applications Processor Peripherals Overview Reference Guide. Provides
an overview and briefly describes the peripherals available on the OMAP-L137 Applications
Processor.
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5 Device Operating Conditions
5.1 Absolute Maximum Ratings Over Operating Case Temperature Range
(1)
(Unless Otherwise Noted)
Core
-0.5 V to 1.4 V
-0.5 V to 2 V
(3)
(CVDD, RTC_CVDD, PLL0_VDDA , USB0_VDDA12(2), )
I/O, 1.8V
(USB0_VDDA18, USB1_VDDA18)
Supply voltage ranges
(3)
I/O, 3.3V
-0.5 V to 3.8V
(3)
(DVDD, USB0_VDDA33, USB1_VDDA33)
VI I/O, 1.2V
(OSCIN, RTC_XI)
-0.3 V to CVDD + 0.3V
-0.3V to DVDD + 0.3V
VI I/O, 3.3V
(Steady State)
VI I/O, 3.3V
DVDD + 20%
up to 20% of Signal
Period
Input voltage ranges
(Transient)
VI I/O, USB 5V Tolerant Pins:
5.25V(4)
(USB0_DM, USB0_DP, USB0_ID, USB1_DM, USB1_DP)
VI I/O, USB0 VBUS
5.50V(4)
VO I/O, 3.3V
-0.5 V to DVDD + 0.3V
(Steady State)
Output voltage ranges
Clamp Current
VO I/O, 3.3V
(Transient)
DVDD + 20%
up to 20% of Signal
Period
Input or Output Voltages 0.3V above or below their respective power
rails. Limit clamp current that flows through the I/O's internal diode
protection cells.
±20mA
(default)
0°C to 105°C
-40°C to 125°C
-55°C to 150°C
Operating Junction Temperature ranges,
TJ
(T version)
(default)
Storage temperature range, Tstg
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) This pin is an internal LDO output and connected via 0.22 µF capacitor to USB0_VDDA12.
(3) All voltage values are with respect to VSS, USB0_VSSA33, USB0_VSSA, PLL0_VSSA, OSCVSS, RTC_VSS
(4) Up to a max of 24 hours.
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5.2 Recommended Operating Conditions
MIN
NOM
MAX UNIT
Supply voltage, Core
CVDD
1.14
1.2 or 1.26
1.32
1.89
3.45
V
V
V
(2)
(CVDD, RTC_CVDD, PLL0_VDDA , USB0_VDDA12(1)
)
Supply voltage, I/O, 1.8V
(USB0_VDDA18, USB1_VDDA18)
1.71
3.15
1.8
3.3
DVDD
Supply voltage, I/O, 3.3V
(DVDD, USB0_VDDA33, USB1_VDDA33)
Supply ground
VSS
VIH
(VSS, USB0_VSSA33, USB0_VSSA, PLL0_VSSA, OSCVSS(3)
,
0
0
0
V
RTC_VSS(3)
)
High-level input voltage, I/O, 3.3V
High-level input voltage, OSCIN, RTC_XI
Low-level input voltage, I/O, 3.3V
2
V
V
TBD
0.8
TBD
10
V
VIL
tt
Low-level input voltage, OSCIN, RTC_XI
Transition time, 10%-90%, All Inputs
V
ns
°C
Default
0
-40
0
70
TA
Operating ambient temperature range
Automotive (T
suffix)
105
300
300
°C
Default
MHz
MHz
DSP and ARM Operating Frequency
(SYSCLK1,6)
FSYSCLK1,6
Automotive (T
suffix)
0
(1) This pin is an internal LDO output and connected via 0.22 µF capacitor to USB0_VDDA12.
(2) Future variants of TI SOC devices may operate at voltages ranging from 1.0 V to 1.32 V to provide a range of system power/
performance options. TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.0 V,
1.1 V, 1.2, 1.26 V with ±5% tolerances) by implementing simple board changes such as reference resistor values or input pin
configuration modifications. Not incorporating a flexible supply may limit the system's ability to easily adapt to future versions of TI SOC
devices.
(3) Oscillator (OSC_VSS, RTC_VSS) ground must be kept separate from other grounds and connected directly to the crystal load capacitor
ground. These pins are shorted to VSS on the device itself and should not be connected to VSS on the circuit board.
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5.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating
Case Temperature (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Low/full speed:
USB0_DM and USB0_DP
2.8
USB0_VDDA33
V
mV
V
High speed:
USB_DM and USB_DP
360
2.8
440
VOH
Low/full speed:
USB1_DM and USB1_DP
USB1_VDDA33
DVDD = 3.15V, IOH = -4 mA
2.4
V
V
High-level output voltage (3.3V I/O)
DVDD = 3.15V, IOH = -100 µA
2.95
Low/full speed:
USB_DM and USB_DP
0.0
-10
0.3
10
V
High speed:
USB_DM and USB_DP
mV
VOL
DVDD = 3.15V, IOL = 4mA
0.4
0.2
V
V
Low-level output voltage (3.3V I/O)
DVDD = 3.15V, IOL = -100 µA
VI = VSS to DVDD without opposing
internal resistor
±35
200
µA
µA
µA
VI = VSS to DVDD with opposing
(1)
II
Input current
30
(2)
internal pullup resistor
VI = VSS to DVDD with opposing
-50
-250
(2)
internal pulldown resistor
IOH
IOL
High-level output current
Low-level output current
All peripherals
All peripherals
-4 mA
mA
4
(1) II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II
indicates the input leakage current and off-state (Hi-Z) output leakage current.
(2) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
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6 Peripheral Information and Electrical Specifications
6.1 Parameter Information
6.1.1 Parameter Information Device-Specific Information
Tester Pin Electronics
Data Sheet Timing Reference Point
42 Ω
3.5 nH
Output
Under
Test
Transmission Line
Z0 = 50 Ω
(see note)
Device Pin
(see note)
4.0 pF
1.85 pF
A. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add or subtract the transmission line delay (2 ns or longer) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the
device pin.
Figure 6-1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
6.1.1.1 Signal Transition Levels
All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. For 3.3 V I/O,
Vref = 1.65 V. For 1.8 V I/O, Vref = 0.9 V.
V
ref
Figure 6-2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks,
VOLMAX and VOH MIN for output clocks.
V
ref
= V MIN (or V MIN)
IH OH
V
ref
= V MAX (or V MAX)
IL OL
Figure 6-3. Rise and Fall Transition Time Voltage Reference Levels
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6.2 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
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6.3 Power Supplies
6.3.1 Power-on Sequence
OMAP-L13x devices include on chip logic that ensures I/O pins are tri-stated during the power on ramp,
as long as the RESET\ pin is asserted. This is true even if the core voltage (CVDD) has not yet ramped.
Normally, the only requirement during the power on ramp is that both the RESET\ and TRST\ pins remain
asserted (low) until after the power supply rails have fully ramped.
However, if the on chip USB modules are used; then to limit any noise on the USB0_DM, USB0_DP,
USB1_DM, and USB1_DP pins to less than 200mV during the power on ramp, the sequence illustrated in
Figure 6-4 must be followed. The requirement is that the core supply (CVDD) must ramp to at least 0.9V
(1) before the IO supply (DVDD) reaches the 1.65V point in its ramp (2). And as is always the case,
RESET\ and TRST\ must remain asserted during the power on ramp and released only after CVDD and
DVDD are within their specified ranges.
(2)
1.65 V
DVDD
(3)
(1)
CVDD
900 mV
RESET, TRST
VIL
USB0_DM, USB0_DP
USB1_DM, USB1_DP
200 mV
Figure 6-4. Power Sequence
6.4 Reset
TBD
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6.5 Crystal Oscillator or External Clock Input
The OMAP-L137 device includes two choices to provide an external clock input, which is fed to the
on-chip PLL to generate high-frequency system clocks. These options are illustrated in Figure 6-5 and
Figure 6-6.
•
•
Figure 6-5 illustrates the option that uses on-chip 1.2V oscillator with external crystal circuit.
Figure 6-6 illustrates the option that uses an external 1.2V clock input.
C2
OSCIN
Clock Input
to PLL
X1
OSCOUT
C1
OSCVSS
Figure 6-5. On-Chip 1.2V Oscillator
Clock
Input
to PLL
OSCIN
OSCOUT
NC
OSCVSS
Figure 6-6. External 1.2V Clock Source
Table 6-1. CLKIN Timing Requirements
MIN
12
MAX
30
UNIT
MHz
MHz
ns
fosc
Oscillator frequency range (OSCIN/OSCOUT)
fPLL
Freuency range of PLL input , external clock source only
Cycle time, external clock driven on OSCIN
12
50
tc(CLKIN)
20
tw(CLKINH) Pulse width high, external clock on OSCIN
0.4
ns
tc(CLKIN)
tw(CLKINL) Pulse width low, external clock on OSCIN
0.4
tc(CLKIN)
ns
ns
tt(CLKIN)
Transition time, CLKIN
5
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6.6 Clock PLLs
The OMAP-L137 has one PLL controller that provides clock to different parts of the system. PLL0 provides
clocks (though various dividers) to most of the components of the device.
The PLL controller provides the following:
•
•
•
•
Glitch-Free Transitions (on changing clock settings)
Domain Clocks Alignment
Clock Gating
PLL power down
The various clock outputs given by the controller are as follows:
•
•
Domain Clocks: SYSCLK [1:n]
Auxiliary Clock from reference clock source: AUXCLK
Various dividers that can be used are as follows:
•
•
Post-PLL Divider: POSTDIV
SYSCLK Divider: D1, , Dn
Various other controls supported are as follows:
•
•
PLL Multiplier Control: PLLM
Software programmable PLL Bypass: PLLEN
6.6.1 PLL Device-Specific Information
The OMAP-L137 DSP generates the high-frequency internal clocks it requires through an on-chip PLL.
The PLL requires some external filtering components to reduce power supply noise as shown in
Figure 6-7.
CVDD
50R
PLL0_VDDA
0.1
µF
0.01
µF
VSS
50R
PLL0_VSSA
Ferrite Bead: Murata BLMG1P500SPT or Equivalent
Figure 6-7. PLL External Filtering Components
The input to the PLL is either from the on-chip oscillator (OSCIN pin) or from an external clock on the
CLKIN pin. The PLL outputs nine clocks that have programmable divider options. Figure 6-8 illustrates the
PLL Topology.
The PLL is disabled by default after a device reset. It must be configured by software according to the
allowable operating conditions listed in Table 6-2 before enabling the DSP to run from the PLL by setting
PLLEN = 1.
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DIV4p5
(/4.5)
Clock Input
from CLKIN
or OSCIN
PLLOUT
PLLREF
PREDIV
(/1 to /32)
PLLM
(x4 to x32)
POSTDIV
1
(/2 to /32)
PLLDIV1
(/1, 1.5, /2,
/2.5 ... /32.5)
SYSCLK1
SYSCLK2
SYSCLK3
SYSCLK4
0
PLLDIV2
(/1, 1.5, /2,
/2.5 ... /32.5)
PLLEN
(PLL_CSR[0])
PLLDIV3
(/1, 1.5, /2,
/2.5 ... /32.5)
PLLDIV4
(/1, 1.5, /2,
/2.5 ... /32.5)
PLLDIV9
(/1, 1.5, /2,
/2.5 ... /32.5)
SYSCLK9
AUXCLK
Figure 6-8. PLL Topology
Table 6-2. Allowed PLL Operating Conditions
NO
PARAMETER
MIN
MAX
N/A
2000 N
UNIT
1
PLLRST: Assertion time during initialization
125
ns
Max PLL Lock Time =
Lock time: The time that the application has to wait for the
PLL to acquire locks before setting PLLEN, after changing
PREDIV, PLLM, or OSCIN
m
2
N/A
ns
where N = Pre-Divider Ratio
M = PLL Multiplier
PLL input frequency
( PLLREF after D0)
PLL multiplier values (PLLM)(1)
3
4
5
12
x4
50
x32
MHz
MHz
PLL output frequency. ( PLLOUT before dividers D1, D2, D3,
....)
400
600(2)
(1) The multiplier values must be chosen such that the PLL output frequency (at PLLOUT) is between 400 and 1000 MHz, but the
frequency going into the SYSCLK dividers (after the post divider) cannot exceed 410 MHz. If the PLLOUT exceeds 410 MHz the post
divider must be used to divide it down. The Post Divider and SYSCLK divider values must be chosen such that the CPU clocks do not
exceed 300 MHz.
(2) PLL post divider / 2 must be used. The /4.5 clock path can be used to generate an EMIF clock from the undivided (i.e. 600 MHz) PLL
output clock.
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6.6.2 Device Clock Generation
PLL0 is controlled by PLL Controller 0. The PLLC0 manages the clock ratios, alignment, and gating for the
system clocks to the chip. The PLLC is responsible for controlling all modes of the PLL through software,
in terms of pre-division of the clock inputs, multiply factor within the PLL, and post-division for each of the
chip-level clocks from the PLL output. The PLLC also controls reset propagation through the chip, clock
alignment, and test points.
PLLC0 generates several clocks from the PLL0 output clock for use by the various processors and
modules. These are summarized in Table 6-3. The clock ratios between SYSCLK1, SYSCLK2, SYSCLK4
and SYSCLK6 must always be maintained as shown in the table.
Table 6-3. System PLLC0 Output Clocks
Output
Clock
Used by
Default Ratio (relative to
SYSCLK1)
Notes
SYSCLK1
SYSCLK2
DSP
/1
/2
No Required Ratio
SYSCLK1 / 2
ARM RAM, ARM ROM, EDMA, DSP ports, EMIFB (ports to switch
fabric), ECAP 0/1/2, EPWM 0/1/2, EQEP 0/1, Shared RAM, LCDC,
McASP/FIFO 0/1/2, SPI 1, UHPI, USB2.0 (logic), UART 1/2,
HRPWM 0/1/2
SYSCLK3
EMIFA
/3
/4
No Required Ratio
SYSCLK1 / 4
SYSCLK4 SYSCFG, Interrupt Controller, PLLC0, PSC 0, EMAC/MDIO, GPIO,
I2C 1, PSC 1, USB1.1
SYSCLK5
SYSCLK6
SYSCLK7
EMIFB
/3
/1
/6
No Required Ratio
SYSCLK1 / 1
ARM Subsystem
RMII clock to EMAC
No Required Ratio ;
Should be set to 50 MHz
AUXCLK
USB48
McASP AuxClk,RTC,Timer64P0,Timer64P1
USB2.0 Phy, USB1.1 logic
N/A
N/A
No Required Ratio
No Required Ratio; Should
be set to 48 MHz
USB12
USB2.0 Phy, USB1.1 logic
N/A
No Required Ratio; 12
MHz, generated by the
USB1 Module by dividing
USB48 by 4.
DIV4p5
133MHz clock source for EMIFB
PLL output/4.5
No Required Ratio
•
The divide values in the PLL Controller 0 for SYSCLK1/SYSCLK6, SYSCLK2 and SYSCLK4 are not
fixed so that user can change the divide values for power saving reasons. But users are responsible to
guarantee that the divide ratios between these clock domains must be fixed to 1:2:4.
•
•
Although the PLL is capable of running at 600 MHz, the SYSCLK dividers in the PLLC0 are not
(maximum 410 MHz). For this reason, the post-divider in the PLLC0 should be configured for /2 to
provide 300 MHz to each of the SYSCLK dividers.
The DIV4p5 (/4.5) hardware clock divider is provided to generate 133 MHz from the 600 MHz PLL
clock for use as clocks to the EMIFs.
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6.7 Interrupts
The OMAP-L137 devices have a large number of interrupts to service the needs of its many peripherals
and subsystems. Both the ARM and C674x CPUs are capable of servicing these interrupts equally. The
interrupts can be selectively enabled or disabled in either of the controllers. Also, the ARM and DSP can
communicate with each other through interrupts controlled by registers in the SYSCFG module.
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6.7.1 ARM CPU Interrupts
The ARM9 CPU core supports 2 direct interrupts: FIQ and IRQ. The ARM Interrupt Controller on the
OMAP-L13x extends the number of interrupts to 100, and provides features like programmable masking,
priority, hardware nesting support, and interrupt vector generation. The OMAP-L13x ARM Interrupt
controller is enhanced from previous devices like the DM6446 and DM355.
6.7.1.1 ARM Interrupt Controller (AINTC) Interrupt Signal Hierarchy
On OMAP-L13x, the ARM Interrupt controller organizes interrupts into the following hierarchy:
•
Peripheral Interrupt Requests
Individual Interrupt Sources from Peripherals
100 System Interrupts
–
•
–
One or more Peripheral Interrupt Requests are combined (fixed configuration) to generate a
System Interrupt.
–
After prioritization, the AINTC will provide an interrupt vector based unique to each System Interrupt
•
32 Interrupt Channels
–
–
Each System Interrupt is mapped to one of the 32 Interrupt Channels
Channel Number determines the first level of prioritization, Channel 0 is highest priority and 31
lowest.
–
If more than one system interrupt is mapped to a channel, priority within the channel is determined
by system interrupt number (0 highest priority)
•
•
Host Interrupts (FIQ and IRQ)
–
–
Interrupt Channels 0 and 1 generate the ARM FIQ interrupt
Interrupt Channels 2 through 31 Generate the ARM IRQ interrupt
Debug Interrupts
–
–
Two Debug Interrupts are supported and can be used to trigger events in the debug subsystem
Sources can be selected from any of the System Interrupts or Host Interrupts
6.7.1.2 AINTC Hardware Vector Generation
The AINTC also generates an interrupt vector in hardware for both IRQ and FIQ host interrupts. This may
be used to accelerate interrupt dispatch. A unique vector is generated for each of the 100 system
interrupts. The vector is computed in hardware as:
VECTOR = BASE + (SYSTEM INTERRUPT NUMBER × SIZE)
Where BASE and SIZE are programmable. The computed vector is a 32-bit address which may
dispatched to using a single instruction of type LDR PC, [PC, #-<offset_12>] at the FIQ and IRQ vector
locations (0xFFFF0018 and 0xFFFF001C respectively).
6.7.1.3 AINTC Hardware Interrupt Nesting Support
Interrupt nesting occurs when an interrupt service routine re-enables interrupts, to allow the CPU to
interrupt the ISR if a higher priority event occurs. The AINTC provides hardware support to facilitate
interrupt nesting. It supports both global and per host interrupt (FIQ and IRQ in this case) automatic
nesting. If enabled, the AINTC will automatically update an internal nesting register that temporarily masks
interrupts at and below the priority of the current interrupt channel. Then if the ISR re-enables interrupts;
only higher priority channels will be able to interrupt it. The nesting level is restored by the ISR by writing
to the nesting level register on completion. Support for nesting can be enabled/disabled by software, with
the option of automatic nesting on a global or per host interrupt basis; or manual nesting.
6.7.1.4 AINTC System Interrupt Assignments on OMAP-L137
System Interrupt assignments for the OMAP-L137 are listed in Table 6-4
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Table 6-4. AINTC System Interrupt Assignments
System Interrupt
Interrupt Name
COMMTX
Source
0
ARM
1
COMMRX
ARM
2
NINT
ARM
3
-
Reserved
4
-
Reserved
5
-
Reserved
6
-
Reserved
7
-
Reserved
8
-
Reserved
9
-
Reserved
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
-
Reserved
EDMA3_CC0_CCINT
EDMA3_CC0_CCERRINT
EDMA3_TC0_TCERRINT
EMIFA_INT
EDMA CC Region 0
EDMA CC
EDMA TC0
EMIFA
IIC0_INT
I2C0
MMCSD_INT0
MMCSD_INT1
PSC0_ALLINT
RTC_IRQS[1:0]
SPI0_INT
MMCSD
MMCSD
PSC0
RTC
SPI0
T64P0_TINT12
T64P0_TINT34
T64P1_TINT12
T64P1_TINT34
UART0_INT
-
Timer64P0 Interrupt 12
Timer64P0 Interrupt 34
Timer64P1 Interrupt 12
Timer64P1 Interrupt 34
UART0
Reserved
PROTERR
SYSCFG Protection Shared Interrupt
SYSCFG CHIPSIG Register
SYSCFG CHIPSIG Register
SYSCFG CHIPSIG Register
SYSCFG CHIPSIG Register
EDMA TC1
SYSCFG_CHIPINT0
SYSCFG_CHIPINT1
SYSCFG_CHIPINT2
SYSCFG_CHIPINT3
EDMA3_TC1_TCERRINT
EMAC_C0RXTHRESH
EMAC_C0RX
EMAC_C0TX
EMAC_C0MISC
EMAC_C1RXTHRESH
EMAC_C1RX
EMAC_C1TX
EMAC_C1MISC
EMIF_MEMERR
GPIO_B0INT
GPIO_B1INT
GPIO_B2INT
GPIO_B3INT
GPIO_B4INT
EMAC - Core 0 Receive Threshold Interrupt
EMAC - Core 0 Receive Interrupt
EMAC - Core 0 Transmit Interrupt
EMAC - Core 0 Miscellaneous Interrupt
EMAC - Core 1 Receive Threshold Interrupt
EMAC - Core 1 Receive Interrupt
EMAC - Core 1 Transmit Interrupt
EMAC - Core 1 Miscellaneous Interrupt
EMIFB
GPIO Bank 0 Interrupt
GPIO Bank 1 Interrupt
GPIO Bank 2 Interrupt
GPIO Bank 3 Interrupt
GPIO Bank 4 Interrupt
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Table 6-4. AINTC System Interrupt Assignments (continued)
System Interrupt
Interrupt Name
GPIO_B5INT
GPIO_B6INT
GPIO_B7INT
-
Source
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
GPIO Bank 5 Interrupt
GPIO Bank 6 Interrupt
GPIO Bank 7 Interrupt
Reserved
IIC1_INT
I2C1
LCDC_INT
LCD Controller
UART_INT1
MCASP_INT
PSC1_ALLINT
SPI1_INT
UART1
McASP0, 1, 2 Combined RX / TX Interrupts
PSC1
SPI1
UHPI_ARMINT
USB0_INT
HPI Arm Interrupt
USB0 Interrupt
USB1_HCINT
USB1_RWAKEUP
UART2_INT
-
USB1 OHCI Host Controller Interrupt
USB1 Remote Wakeup Interrupt
UART2
Reserved
EHRPWM0
HiResTimer / PWM0 Interrupt
HiResTimer / PWM0 Trip Zone Interrupt
HiResTimer / PWM1 Interrupt
HiResTimer / PWM1 Trip Zone Interrupt
HiResTimer / PWM2 Interrupt
HiResTimer / PWM2 Trip Zone Interrupt
ECAP0
EHRPWM0TZ
EHRPWM1
EHRPWM1TZ
EHRPWM2
EHRPWM2TZ
ECAP0
ECAP1
ECAP1
ECAP2
ECAP2
EQEP0
EQEP0
EQEP1
EQEP1
T64P0_CMPINT0
T64P0_CMPINT1
T64P0_CMPINT2
T64P0_CMPINT3
T64P0_CMPINT4
T64P0_CMPINT5
T64P0_CMPINT6
T64P0_CMPINT7
T64P1_CMPINT0
T64P1_CMPINT1
T64P1_CMPINT2
T64P1_CMPINT3
T64P1_CMPINT4
T64P1_CMPINT5
T64P1_CMPINT6
T64P1_CMPINT7
ARMCLKSTOPREQ
-
Timer64P0 - Compare 0
Timer64P0 - Compare 1
Timer64P0 - Compare 2
Timer64P0 - Compare 3
Timer64P0 - Compare 4
Timer64P0 - Compare 5
Timer64P0 - Compare 6
Timer64P0 - Compare 7
Timer64P1 - Compare 0
Timer64P1 - Compare 1
Timer64P1 - Compare 2
Timer64P1 - Compare 3
Timer64P1 - Compare 4
Timer64P1 - Compare 5
Timer64P1 - Compare 6
Timer64P1 - Compare 7
PSC0
Reserved
-
Reserved
-
Reserved
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Table 6-4. AINTC System Interrupt Assignments (continued)
System Interrupt
Interrupt Name
Source
94
95
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
96
97
98
99
100
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6.7.1.5 AINTC Memory Map
Table 6-5. AINTC Memory Map
BYTE ADDRESS
0xFFFE E000
REGISTER NAME
DESCRIPTION
Revision Register
REV
0xFFFE E004
CR
Control Register
0xFFFE E008 - 0xFFFE E00F
0xFFFE E010
-
Reserved
GER
Global Enable Register
0xFFFE E014 - 0xFFFE E01B
0xFFFE E01C
-
Reserved
GNLR
Global Nesting Level Register
System Interrupt Status Indexed Set Register
System Interrupt Status Indexed Clear Register
System Interrupt Enable Indexed Set Register
System Interrupt Enable Indexed Clear Register
Reserved
0xFFFE E020
SISR
0xFFFE E024
SICR
0xFFFE E028
EISR
0xFFFE E02C
EICR
0xFFFE E030
-
0xFFFE E034
HIEISR
Host Interrupt Enable Indexed Set Register
Host Interrupt Enable Indexed Clear Register
Reserved
0xFFFE E038
HIDISR
0xFFFE E03C - 0xFFFE E04F
0xFFFE E050
-
VBR
Vector Base Register
0xFFFE E054
VSR
Vector Size Register
0xFFFE E058
VNR
Vector Null Register
0xFFFE E05C - 0xFFFE E07F
0xFFFE E080
-
Reserved
GPIR
Global Prioritized Index Register
Global Prioritized Vector Register
Reserved
0xFFFE E084
GPVR
0xFFFE E088 - 0xFFFE E1FF
0xFFFE E200 - 0xFFFE E20F
0xFFFE E210- 0xFFFE E27F
0xFFFE E280 - 0xFFFE E28B
0xFFFE E28C - 0xFFFE E2FF
0xFFFE E300 - 0xFFFE E30F
0xFFFE E310 - 0xFFFE E37F
0xFFFE E380 - 0xFFFE E38B
0xFFFE E38C - 0xFFFE E3FF
0xFFFE E400 - 0xFFFE E45B
0xFFFE E45C - 0xFFFE E8FF
0xFFFE E800 - 0xFFFE E81F
0xFFFE E820 - 0xFFFE E8FF
0xFFFE E900 - 0xFFFE E904
0xFFFE E908 - 0xFFFE EEFF
0xFFFE EF00 - 0xFFFE EF04
0xFFFE EF08 - 0xFFFE F0FF
0xFFFE F100 - 0xFFFE F104
0xFFFE F108 - 0xFFFE F4FF
0xFFFE F500
-
SRSR[0] - SRSR[3]
System Interrupt Status Raw / Set Registers
Reserved
-
SECR[0] - SECR[3]
System Interrupt Status Enabled / Clear Registers
-
Reserved
System Interrupt Enable Set Registers
Reserved
ESR[0] - ESR[3]
-
ECR[0] - ECR[3]
System Interrupt Enable Clear Registers
Reserved
-
CMR[0] - CMR[31]
Channel Map Registers (Byte Wide Registers)
Reserved
-
-
Reserved
-
Reserved
HIPIR[0] - HIPIR[1]
Host Interrupt Prioritized Index Registers
Reserved
-
DSR[0] - DSR[1]
Debug Select Registers
Reserved
-
HINLR[0] - HINLR[1]
Host Interrupt Nesting Level Registers
Reserved
-
HIER[0]
Host Interrupt Enable Register
Reserved
0xFFFE F504 - 0xFFFE F5FF
0xFFFE F600
-
HIPVR[0] - HIPVR[1]
-
Host Interrupt Prioritized Vector Registers
Reserved
0xFFFE F608 - 0xFFFE FFFF
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6.7.2 DSP Interrupts
The C674x DSP interrupt controller combines device events into 12 prioritized interrupts. The source for
each of the 12 CPU interrupts is user programmable and is listed in Table 6-6. Also, the interrupt
controller controls the generation of the CPU exception, NMI, and emulation interrupts. Table 6-7
summarizes the C674x interrupt controller registers and memory locations.
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Table 6-6. OMAP-L137 DSP Interrupts
EVT#
0
Interrupt Name
EVT0
Source
C674x Int Ctl 0
1
EVT1
C674x Int Ctl 1
2
EVT2
C674x Int Ctl 2
3
EVT3
C674x Int Ctl 3
4
T64P0_TINT12
SYSCFG_CHIPINT2
-
Timer64P0 - TINT12
SYSCFG_CHIPSIG Register
Reserved
5
6
7
EHRPWM0
TPCC0_INT1
EMU-DTDMA
EHRPWM0TZ
EMU-RTDXRX
EMU-RTDXTX
IDMAINT0
HiResTimer/PWM0 Interrupt
TPCC0 Region 1 Interrupt
C674x-ECM
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
HiResTimer/PWM0 Trip Zone Interrupt
C674x-RTDX
C674x-RTDX
C674x-EMC
IDMAINT1
C674x-EMC
MMCSD_INT0
MMCSD_INT1
-
MMCSD MMC/SD Interrupt
MMCSD SDIO Interrupt
Reserved
EHRPWM1
USB0_INT
USB1_HCINT
USB1_RWAKEUP
-
HiResTimer/PWM1 Interrupt
USB0 Interrupt
USB1 OHCI Host Controller Interrupt
USB1 Remote Wakeup Interrupt
Reserved
EHRPWM1TZ
EHRPWM2
EHRPWM2TZ
EMAC_C0RXTHRESH
EMAC_C0RX
EMAC_C0TX
EMAC_C0MISC
EMAC_C1RXTHRESH
EMAC_C1RX
EMAC_C1TX
EMAC_C1MISC
UHPI_DSPINT
-
HiResTimer/PWM1 Trip Zone Interrupt
HiResTimer/PWM2 Interrupt
HiResTimer/PWM2 Trip Zone Interrupt
EMAC - Core 0 Receive Threshold Interrupt
EMAC - Core 0 Receive Interrupt
EMAC - Core 0 Transmit Interrupt
EMAC - Core 0 Miscellaneous Interrupt
EMAC - Core 1 Receive Threshold Interrupt
EMAC - Core 1 Receive Interrupt
EMAC - Core 1 Transmit Interrupt
EMAC - Core 1 Miscellaneous Interrupt
UHPI DSP Interrupt
Reserved
IIC0_INT
I2C0
SP0_INT
SPI0
UART0_INT
-
UART0
Reserved
T64P1_TINT12
GPIO_B1INT
IIC1_INT
Timer64P1 Interrupt 12
GPIO Bank 1 Interrupt
I2C1
SPI1_INT
SPI1
-
Reserved
ECAP0
ECAP0
UART_INT1
UART1
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Table 6-6. OMAP-L137 DSP Interrupts (continued)
EVT#
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
Interrupt Name
ECAP1
Source
ECAP1
T64P1_TINT34
GPIO_B2INT
-
Timer64P1 Interrupt 34
GPIO Bank 2 Interrupt
Reserved
ECAP2
ECAP2
GPIO_B3INT
EQEP1
GPIO Bank 3 Interrupt
EQEP1
GPIO_B4INT
EMIFA_INT
GPIO Bank 4 Interrupt
EMIFA
EDMA3_CC0_ERRINT
EDMA3_TC0_ERRINT
EDMA3_TC1_ERRINT
GPIO_B5INT
EMIFB_INT
EDMA3 Channel Controller 0
EDMA3 Transfer Controller 0
EDMA3 Transfer Controller 1
GPIO Bank 5 Interrupt
EMIFB Memory Error Interrupt
McASP0,1,2 Combined RX/TX Interrupts
GPIO Bank 6 Interrupt
RTC Combined
MCASP_INT
GPIO_B6INT
RTC_IRQS
T64P0_TINT34
GPIO_B0INT
-
Timer64P0 Interrupt 34
GPIO Bank 0 Interrupt
Reserved
SYSCFG_CHIPINT3
EQEP0
SYSCFG_CHIPSIG Register
EQEP0
UART2_INT
UART2
PSC0_ALLINT
PSC1_ALLINT
GPIO_B7INT
LCDC_INT
PSC0
PSC1
GPIO Bank 7 Interrupt
LDC Controller
PROTERR
SYSCFG Protection Shared Interrupt
Reserved
-
-
Reserved
-
Reserved
T64P0_CMPINT0
T64P0_CMPINT1
T64P0_CMPINT2
T64P0_CMPINT3
T64P0_CMPINT4
T64P0_CMPINT5
T64P0_CMPINT6
T64P0_CMPINT7
T64P1_CMPINT0
T64P1_CMPINT1
T64P1_CMPINT2
T64P1_CMPINT3
T64P1_CMPINT4
T64P1_CMPINT5
T64P1_CMPINT6
T64P1_CMPINT7
Timer64P0 - Compare 0
Timer64P0 - Compare 1
Timer64P0 - Compare 2
Timer64P0 - Compare 3
Timer64P0 - Compare 4
Timer64P0 - Compare 5
Timer64P0 - Compare 6
Timer64P0 - Compare 7
Timer64P1 - Compare 0
Timer64P1 - Compare 1
Timer64P1 - Compare 2
Timer64P1 - Compare 3
Timer64P1 - Compare 4
Timer64P1 - Compare 5
Timer64P1 - Compare 6
Timer64P1 - Compare 7
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Table 6-6. OMAP-L137 DSP Interrupts (continued)
EVT#
94
Interrupt Name
Source
-
Reserved
95
-
Reserved
96
INTERR
C674x-Int Ctl
C674x-EMC
Reserved
97
EMC_IDMAERR
98
-
99
-
Reserved
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
-
Reserved
Reserved
-
Reserved
-
Reserved
-
Reserved
PMC_ED
-
C674x-PMC
Reserved
-
Reserved
UMC_ED1
UMC_ED2
PDC_INT
SYS_CMPA
PMC_CMPA
PMC_CMPA
DMC_CMPA
DMC_CMPA
UMC_CMPA
UMC_CMPA
EMC_CMPA
EMC_BUSERR
C674x-UMC
C674x-UMC
C674x-PDC
C674x-SYS
C674x-PMC
C674x-PMC
C674x-DMC
C674x-DMC
C674x-UMC
C674x-UMC
C674x-EMC
C674x-EMC
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Table 6-7. C674x DSP Interrupt Controller Registers
BYTE ADDRESS
0x0180 0000
0x0180 0004
0x0180 0008
0x0180 000C
0x0180 0020
0x0180 0024
0x0180 0028
0x0180 002C
0x0180 0040
0x0180 0044
0x0180 0048
0x0180 004C
0x0180 0080
0x0180 0084
0x0180 0088
0x0180 008C
0x0180 00A0
0x0180 00A4
0x0180 00A8
0x0180 00AC
0x0180 00C0
0x0180 00C4
0x0180 00C8
0x0180 00CC
0x0180 00E0
0x0180 00E4
0x0180 00E8
0x0180 00EC
0x0180 0104
0x0180 0108
0x0180 010C
0x0180 0140 - 0x0180 0144
0x0180 0180
0x0180 0184
0x0180 0188
0x0180 01C0
REGISTER NAME
EVTFLAG0
EVTFLAG1
EVTFLAG2
EVTFLAG3
EVTSET0
DESCRIPTION
Event flag register 0
Event flag register 1
Event flag register 2
Event flag register 3
Event set register 0
EVTSET1
Event set register 1
EVTSET2
Event set register 2
EVTSET3
Event set register 3
EVTCLR0
Event clear register 0
EVTCLR1
Event clear register 1
EVTCLR2
Event clear register 2
EVTCLR3
Event clear register 3
EVTMASK0
EVTMASK1
EVTMASK2
EVTMASK3
MEVTFLAG0
MEVTFLAG1
MEVTFLAG2
MEVTFLAG3
EXPMASK0
EXPMASK1
EXPMASK2
EXPMASK3
MEXPFLAG0
MEXPFLAG1
MEXPFLAG2
MEXPFLAG3
INTMUX1
Event mask register 0
Event mask register 1
Event mask register 2
Event mask register 3
Masked event flag register 0
Masked event flag register 1
Masked event flag register 2
Masked event flag register 3
Exception mask register 0
Exception mask register 1
Exception mask register 2
Exception mask register 3
Masked exception flag register 0
Masked exception flag register 1
Masked exception flag register 2
Masked exception flag register 3
Interrupt mux register 1
Interrupt mux register 2
Interrupt mux register 3
Reserved
INTMUX2
INTMUX3
-
INTXSTAT
INTXCLR
Interrupt exception status
Interrupt exception clear
Dropped interrupt mask register
Event assert register
INTDMASK
EVTASRT
6.7.3 ARM/DSP Communications Interrupts
Communications Interrupts between the ARM and DSP are part of the SYSCFG module on the
OMAP-L13x family of devices.( Section 4.5.1 CHIPSIG, Section 4.5.2 CHIPSIG_CLR)
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6.8 General-Purpose Input/Output (GPIO)
The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.
When configured as an output, a write to an internal register can control the state driven on the output pin.
When configured as an input, the state of the input is detectable by reading the state of an internal
register. In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different
interrupt/event generation modes. The GPIO peripheral provides generic connections to external devices.
The GPIO pins are grouped into banks of 16 pins per bank (i.e., bank 0 consists of GPIO [0:15]).
The OMAP-L137 GPIO peripheral supports the following:
•
•
Up to 128 Pins on ZKB package configurable as GPIO
External Interrupt and DMA request Capability
–
–
–
–
–
–
Every GPIO pin may be configured to generate an interrupt request on detection of rising and/or
falling edges on the pin.
The interrupt requests within each bank are combined (logical or) to create eight unique bank level
interrupt requests.
The bank level interrupt service routine may poll the INTSTATx register for its bank to determine
which pin(s) have triggered the interrupt.
GPIO Banks 0, 1, 2, 3, 4, 5, 6, and 7 Interrupts assigned to ARM INTC Interrupt Requests 42, 43,
44, 45, 46, 47, 48, and 49 respectively
GPIO Banks 0, 1, 2, 3, 4, 5, 6, and 7 Interrupts assigned to DSP Events 65, 41, 49, 52, 54, 59, 62
and 72 respectively
Additionally, GPIO Banks 0, 1, 2, 3, 4, and 5 Interrupts assigned to EDMA events 6, 7, 22, 23, 28,
and 29 respectively.
•
Set/clear functionality: Firmware writes 1 to corresponding bit position(s) to set or to clear GPIO
signal(s). This allows multiple firmware processes to toggle GPIO output signals without critical section
protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to
anther process during GPIO programming).
•
•
Separate Input/Output registers
Output register in addition to set/clear so that, if preferred by firmware, some GPIO output signals can
be toggled by direct write to the output register(s).
•
Output register, when read, reflects output drive status. This, in addition to the input register reflecting
pin status and open-drain I/O cell, allows wired logic be implemented.
The memory map for the GPIO registers is shown in Table 6-8. See the OMAP-L137 Applications
Processor DSP Peripherals Overview Reference Guide. – Literature Number SPRUGA6 for more details.
6.8.1 GPIO Register Description(s)
Table 6-8. GPIO Registers
GPIO
Acronym
Register Description
BYTE ADDRESS
0x01E2 6000
0x01E2 6004
0x01E2 6008
REV
Peripheral Revision Register
RESERVED
BINTEN
Reserved
GPIO Interrupt Per-Bank Enable Register
GPIO Banks 0 and 1
0x01E2 6010
0x01E2 6014
0x01E2 6018
0x01E2 601C
0x01E2 6020
0x01E2 6024
DIR01
GPIO Banks 0 and 1 Direction Register
GPIO Banks 0 and 1 Output Data Register
GPIO Banks 0 and 1 Set Data Register
GPIO Banks 0 and 1 Clear Data Register
GPIO Banks 0 and 1 Input Data Register
GPIO Banks 0 and 1 Set Rising Edge Interrupt Register
OUT_DATA01
SET_DATA01
CLR_DATA01
IN_DATA01
SET_RIS_TRIG01
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Table 6-8. GPIO Registers (continued)
GPIO
Acronym
Register Description
BYTE ADDRESS
0x01E2 6028
0x01E2 602C
0x01E2 6030
0x01E2 6034
CLR_RIS_TRIG01
SET_FAL_TRIG01
CLR_FAL_TRIG01
INTSTAT01
GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register
GPIO Banks 0 and 1 Set Falling Edge Interrupt Register
GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register
GPIO Banks 0 and 1 Interrupt Status Register
GPIO Banks 2 and 3
0x01E2 6038
0x01E2 603C
0x01E2 6040
0x01E2 6044
0x01E2 6048
0x01E2 604C
0x01E2 6050
0x01E2 6054
0x01E2 6058
0x01E2 605C
DIR23
GPIO Banks 2 and 3 Direction Register
OUT_DATA23
SET_DATA23
CLR_DATA23
IN_DATA23
GPIO Banks 2 and 3 Output Data Register
GPIO Banks 2 and 3 Set Data Register
GPIO Banks 2 and 3 Clear Data Register
GPIO Banks 2 and 3 Input Data Register
SET_RIS_TRIG23
CLR_RIS_TRIG23
SET_FAL_TRIG23
CLR_FAL_TRIG23
INTSTAT23
GPIO Banks 2 and 3 Set Rising Edge Interrupt Register
GPIO Banks 2 and 3 Clear Rising Edge Interrupt Register
GPIO Banks 2 and 3 Set Falling Edge Interrupt Register
GPIO Banks 2 and 3 Clear Falling Edge Interrupt Register
GPIO Banks 2 and 3 Interrupt Status Register
GPIO Banks 4 and 5
0x01E2 6060
0x01E2 6064
0x01E2 6068
0x01E2 606C
0x01E2 6070
0x01E2 6074
0x01E2 6078
0x01E2 607C
0x01E2 6080
0x01E2 6084
DIR45
GPIO Banks 4 and 5 Direction Register
OUT_DATA45
SET_DATA45
CLR_DATA45
IN_DATA45
GPIO Banks 4 and 5 Output Data Register
GPIO Banks 4 and 5 Set Data Register
GPIO Banks 4 and 5 Clear Data Register
GPIO Banks 4 and 5 Input Data Register
SET_RIS_TRIG45
CLR_RIS_TRIG45
SET_FAL_TRIG45
CLR_FAL_TRIG45
INTSTAT45
GPIO Banks 4 and 5 Set Rising Edge Interrupt Register
GPIO Banks 4 and 5 Clear Rising Edge Interrupt Register
GPIO Banks 4 and 5 Set Falling Edge Interrupt Register
GPIO Banks 4 and 5 Clear Falling Edge Interrupt Register
GPIO Banks 4 and 5 Interrupt Status Register
GPIO Banks 6 and 7
0x01E2 6088
0x01E2 608C
0x01E2 6090
0x01E2 6094
0x01E2 6098
0x01E2 609C
0x01E2 60A0
0x01E2 60A4
0x01E2 60A8
0x01E2 60AC
DIR67
GPIO Banks 6 and 7 Direction Register
OUT_DATA67
SET_DATA67
CLR_DATA67
IN_DATA67
GPIO Banks 6 and 7 Output Data Register
GPIO Banks 6 and 7 Set Data Register
GPIO Banks 6 and 7 Clear Data Register
GPIO Banks 6 and 7 Input Data Register
SET_RIS_TRIG67
CLR_RIS_TRIG67
SET_FAL_TRIG67
CLR_FAL_TRIG67
INTSTAT67
GPIO Banks 6 and 7 Set Rising Edge Interrupt Register
GPIO Banks 6 and 7 Clear Rising Edge Interrupt Register
GPIO Banks 6 and 7 Set Falling Edge Interrupt Register
GPIO Banks 6 and 7 Clear Falling Edge Interrupt Register
GPIO Banks 6 and 7 Interrupt Status Register
6.8.2 GPIO Peripheral Input/Output Electrical Data/Timing
Table 6-9. Timing Requirements for GPIO Inputs(1) (see Figure 6-9)
NO.
UNIT
MIN MAX
2C(1)(2)
1
tw(GPIH)
Pulse duration, GPIx high
ns
(1) The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have OMAP-L137
recognize the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to allow OMAP-L137
enough time to access the GPIO register through the internal bus.
(2) C=SYSCLK4 period in ns. For example, when running parts at 300 MHz, C=13.33 ns
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Table 6-9. Timing Requirements for GPIO Inputs (see Figure 6-9) (continued)
NO.
UNIT
MIN MAX
2C(1)(2)
2
tw(GPIL)
Pulse duration, GPIx low
ns
Table 6-10. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see Figure 6-9)
NO.
PARAMETER
Pulse duration, GPOx high
Pulse duration, GPOx low
UNIT
MIN
2C(1) (2)
2C(1)(2)
MAX
3
4
tw(GPOH)
tw(GPOL)
ns
ns
(1) This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the
GPIO is dependent upon internal bus activity.
(2) C=SYSCLK4 period in ns. For example, when running parts at 300 MHz, C=13.33 ns
2
1
GPIx
4
3
GPOx
Figure 6-9. GPIO Port Timing
6.8.3 GPIO Peripheral External Interrupts Electrical Data/Timing
Table 6-11. Timing Requirements for External Interrupts(1) (see Figure 6-10)
NO.
UNIT
MIN
MAX
1
2
tw(ILOW)
tw(IHIGH)
Width of the external interrupt pulse low
Width of the external interrupt pulse high
2C(1)(2)
ns
ns
(1)(2)
2C
(1) The pulse width given is sufficient to generate an interrupt or an EDMA event. However, if a user wants to have OMAP-L137 recognize
the GPIO changes through software polling of the GPIO register, the GPIO duration must be extended to allow OMAP-L137 enough
time to access the GPIO register through the internal bus.
(2) C=SYSCLK4 period in ns. For example, when running parts at 300 MHz, C=13.33 ns
2
1
EXT_INTx
Figure 6-10. GPIO External Interrupt Timing
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6.9 EDMA
Table 6-12 is the list of EDMA3 Channel Contoller Registers and Table 6-13 is the list of EDMA3 Transfer
Controller registers.
Table 6-12. EDMA3 Channel Controller (EDMA3CC) Registers
BYTE ADDRESS
0x01C0 0000
Acronym
PID
Register Description
Peripheral Identification Register
EDMA3CC Configuration Register
0x01C0 0004
CCCFG
Global Registers
0x01C0 0200
0x01C0 0204
0x01C0 0208
0x01C0 020C
0x01C0 0210
0x01C0 0214
0x01C0 0218
0x01C0 021C
0x01C0 0240
0x01C0 0244
0x01C0 0248
0x01C0 024C
0x01C0 0260
0x01C0 0284
0x01C0 0300
0x01C0 0308
0x01C0 0310
0x01C0 0314
0x01C0 0318
0x01C0 031C
0x01C0 0320
0x01C0 0340
0x01C0 0348
0x01C0 0350
0x01C0 0358
0x01C0 0380
0x01C0 0384
0x01C0 0388
0x01C0 038C
0x01C0 0400 - 0x01C0 043C
0x01C0 0440 - 0x01C0 047C
0x01C0 0600
0x01C0 0604
0x01C0 0620
0x01C0 0640
QCHMAP0
QCHMAP1
QCHMAP2
QCHMAP3
QCHMAP4
QCHMAP5
QCHMAP6
QCHMAP7
DMAQNUM0
DMAQNUM1
DMAQNUM2
DMAQNUM3
QDMAQNUM
QUEPRI
QDMA Channel 0 Mapping Register
QDMA Channel 1 Mapping Register
QDMA Channel 2 Mapping Register
QDMA Channel 3 Mapping Register
QDMA Channel 4 Mapping Register
QDMA Channel 5 Mapping Register
QDMA Channel 6 Mapping Register
QDMA Channel 7 Mapping Register
DMA Channel Queue Number Register 0
DMA Channel Queue Number Register 1
DMA Channel Queue Number Register 2
DMA Channel Queue Number Register 3
QDMA Channel Queue Number Register
Queue Priority Register(1)
EMR
Event Missed Register
EMCR
Event Missed Clear Register
QEMR
QDMA Event Missed Register
QEMCR
QDMA Event Missed Clear Register
EDMA3CC Error Register
CCERR
CCERRCLR
EEVAL
EDMA3CC Error Clear Register
Error Evaluate Register
DRAE0
DMA Region Access Enable Register for Region 0
DMA Region Access Enable Register for Region 1
DMA Region Access Enable Register for Region 2
DMA Region Access Enable Register for Region 3
QDMA Region Access Enable Register for Region 0
QDMA Region Access Enable Register for Region 1
QDMA Region Access Enable Register for Region 2
QDMA Region Access Enable Register for Region 3
Event Queue Entry Registers Q0E0-Q0E15
Event Queue Entry Registers Q1E0-Q1E15
Queue 0 Status Register
DRAE1
DRAE2
DRAE3
QRAE0
QRAE1
QRAE2
QRAE3
Q0E0-Q0E15
Q1E0-Q1E15
QSTAT0
QSTAT1
Queue 1 Status Register
QWMTHRA
CCSTAT
Queue Watermark Threshold A Register
EDMA3CC Status Register
Global Channel Registers
0x01C0 1000
0x01C0 1008
ER
Event Register
ECR
Event Clear Register
(1) On previous architectures, the EDMA3TC priority was controlled by the queue priority register (QUEPRI) in the EDMA3CC
memory-map. However for this device, the priority control for the transfer controllers is controlled by the chip-level registers in the
System Configuration Module. You should use the chip-level registers and not QUEPRI to configure the TC priority.
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Table 6-12. EDMA3 Channel Controller (EDMA3CC) Registers (continued)
BYTE ADDRESS
0x01C0 1010
0x01C0 1018
0x01C0 1020
0x01C0 1028
0x01C0 1030
0x01C0 1038
0x01C0 1040
0x01C0 1050
0x01C0 1058
0x01C0 1060
0x01C0 1068
0x01C0 1070
0x01C0 1078
0x01C0 1080
0x01C0 1084
0x01C0 1088
0x01C0 108C
0x01C0 1090
0x01C0 1094
Acronym
ESR
Register Description
Event Set Register
CER
Chained Event Register
EER
Event Enable Register
EECR
EESR
SER
Event Enable Clear Register
Event Enable Set Register
Secondary Event Register
Secondary Event Clear Register
Interrupt Enable Register
SECR
IER
IECR
IESR
Interrupt Enable Clear Register
Interrupt Enable Set Register
Interrupt Pending Register
Interrupt Clear Register
IPR
ICR
IEVAL
QER
Interrupt Evaluate Register
QDMA Event Register
QEER
QEECR
QEESR
QSER
QSECR
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Shadow Region 0 Channel Registers
0x01C0 2000
0x01C0 2008
0x01C0 2010
0x01C0 2018
0x01C0 2020
0x01C0 2028
0x01C0 2030
0x01C0 2038
0x01C0 2040
0x01C0 2050
0x01C0 2058
0x01C0 2060
0x01C0 2068
0x01C0 2070
0x01C0 2078
0x01C0 2080
0x01C0 2084
0x01C0 2088
0x01C0 208C
0x01C0 2090
0x01C0 2094
ER
ECR
Event Register
Event Clear Register
ESR
Event Set Register
CER
Chained Event Register
EER
Event Enable Register
EECR
EESR
SER
Event Enable Clear Register
Event Enable Set Register
Secondary Event Register
Secondary Event Clear Register
Interrupt Enable Register
SECR
IER
IECR
IESR
IPR
Interrupt Enable Clear Register
Interrupt Enable Set Register
Interrupt Pending Register
Interrupt Clear Register
ICR
IEVAL
QER
Interrupt Evaluate Register
QDMA Event Register
QEER
QEECR
QEESR
QSER
QSECR
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Shadow Region 1 Channel Registers
0x01C0 2200
0x01C0 2208
0x01C0 2210
0x01C0 2218
0x01C0 2220
ER
Event Register
Event Clear Register
Event Set Register
ECR
ESR
CER
EER
Chained Event Register
Event Enable Register
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Table 6-12. EDMA3 Channel Controller (EDMA3CC) Registers (continued)
BYTE ADDRESS
Acronym
EECR
EESR
SER
Register Description
Event Enable Clear Register
Event Enable Set Register
0x01C0 2228
0x01C0 2230
0x01C0 2238
Secondary Event Register
0x01C0 2240
SECR
IER
Secondary Event Clear Register
Interrupt Enable Register
0x01C0 2250
0x01C0 2258
IECR
IESR
Interrupt Enable Clear Register
Interrupt Enable Set Register
Interrupt Pending Register
0x01C0 2260
0x01C0 2268
IPR
0x01C0 2270
ICR
Interrupt Clear Register
0x01C0 2278
IEVAL
QER
Interrupt Evaluate Register
QDMA Event Register
0x01C0 2280
0x01C0 2284
QEER
QEECR
QEESR
QSER
QSECR
—
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Parameter RAM (PaRAM)
0x01C0 2288
0x01C0 228C
0x01C0 2290
0x01C0 2294
0x01C0 4000 - 0x01C0 4FFF
Table 6-13. EDMA3 Transfer Controller (EDMA3TC) Registers
Offset
Transfer Controller Transfer Controller
Acronym
Register Description
0
1
BYTE ADDRESS
BYTE ADDRESS
0h
0x01C0 8000
0x01C0 8004
0x01C0 8100
0x01C0 8120
0x01C0 8124
0x01C0 8128
0x01C0 812C
0x01C0 8130
0x01C0 8140
0x01C0 8240
0x01C0 8244
0x01C0 8248
0x01C0 824C
0x01C0 8250
0x01C0 8254
0x01C0 8258
0x01C0 825C
0x01C0 8260
0x01C0 8280
0x01C0 8284
0x01C0 8288
0x01C0 8400
0x01C0 8404
0x01C0 8500
0x01C0 8520
0x01C0 8524
0x01C0 8528
0x01C0 852C
0x01C0 8530
0x01C0 8540
0x01C0 8640
0x01C0 8644
0x01C0 8648
0x01C0 864C
0x01C0 8650
0x01C0 8654
0x01C0 8658
0x01C0 865C
0x01C0 8660
0x01C0 8680
0x01C0 8684
0x01C0 8688
PID
Peripheral Identification Register
4h
TCCFG
EDMA3TC Configuration Register
EDMA3TC Channel Status Register
Error Status Register
100h
120h
124h
128h
12Ch
130h
140h
240h
244h
248h
24Ch
250h
254h
258h
25Ch
260h
280h
284h
288h
TCSTAT
ERRSTAT
ERREN
Error Enable Register
ERRCLR
ERRDET
ERRCMD
RDRATE
SAOPT
Error Clear Register
Error Details Register
Error Interrupt Command Register
Read Command Rate Register
Source Active Options Register
SASRC
Source Active Source Address Register
Source Active Count Register
SACNT
SADST
Source Active Destination Address Register
Source Active B-Index Register
SABIDX
SAMPPRXY
SACNTRLD
SASRCBREF
SADSTBREF
DFCNTRLD
DFSRCBREF
DFDSTBREF
Source Active Memory Protection Proxy Register
Source Active Count Reload Register
Source Active Source Address B-Reference Register
Source Active Destination Address B-Reference Register
Destination FIFO Set Count Reload Register
Destination FIFO Set Source Address B-Reference Register
Destination FIFO Set Destination Address B-Reference
Register
300h
304h
308h
30Ch
0x01C0 8300
0x01C0 8304
0x01C0 8308
0x01C0 830C
0x01C0 8700
0x01C0 8704
0x01C0 8708
0x01C0 870C
DFOPT0
DFSRC0
DFCNT0
DFDST0
Destination FIFO Options Register 0
Destination FIFO Source Address Register 0
Destination FIFO Count Register 0
Destination FIFO Destination Address Register 0
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Table 6-13. EDMA3 Transfer Controller (EDMA3TC) Registers (continued)
Offset
Transfer Controller Transfer Controller
Acronym
Register Description
0
1
BYTE ADDRESS
BYTE ADDRESS
310h
314h
340h
344h
348h
34Ch
350h
354h
380h
384h
388h
38Ch
390h
394h
3C0h
3C4h
3C8h
3CCh
3D0h
3D4h
0x01C0 8310
0x01C0 8314
0x01C0 8340
0x01C0 8344
0x01C0 8348
0x01C0 834C
0x01C0 8350
0x01C0 8354
0x01C0 8380
0x01C0 8384
0x01C0 8388
0x01C0 838C
0x01C0 8390
0x01C0 8394
0x01C0 83C0
0x01C0 83C4
0x01C0 83C8
0x01C0 83CC
0x01C0 83D0
0x01C0 83D4
0x01C0 8710
0x01C0 8714
0x01C0 8740
0x01C0 8744
0x01C0 8748
0x01C0 874C
0x01C0 8750
0x01C0 8754
0x01C0 8780
0x01C0 8784
0x01C0 8788
0x01C0 878C
0x01C0 8790
0x01C0 8794
0x01C0 87C0
0x01C0 87C4
0x01C0 87C8
0x01C0 87CC
0x01C0 87D0
0x01C0 87D4
DFBIDX0
DFMPPRXY0
DFOPT1
Destination FIFO B-Index Register 0
Destination FIFO Memory Protection Proxy Register 0
Destination FIFO Options Register 1
DFSRC1
Destination FIFO Source Address Register 1
Destination FIFO Count Register 1
DFCNT1
DFDST1
Destination FIFO Destination Address Register 1
Destination FIFO B-Index Register 1
DFBIDX1
DFMPPRXY1
DFOPT2
Destination FIFO Memory Protection Proxy Register 1
Destination FIFO Options Register 2
DFSRC2
Destination FIFO Source Address Register 2
Destination FIFO Count Register 2
DFCNT2
DFDST2
Destination FIFO Destination Address Register 2
Destination FIFO B-Index Register 2
DFBIDX2
DFMPPRXY2
DFOPT3
Destination FIFO Memory Protection Proxy Register 2
Destination FIFO Options Register 3
DFSRC3
Destination FIFO Source Address Register 3
Destination FIFO Count Register 3
DFCNT3
DFDST3
Destination FIFO Destination Address Register 3
Destination FIFO B-Index Register 3
DFBIDX3
DFMPPRXY3
Destination FIFO Memory Protection Proxy Register 3
Table 6-14 shows an abbreviation of the set of registers which make up the parameter set for each of 128
EDMA events. Each of the parameter register sets consist of 8 32-bit word entries. Table 6-15 shows the
parameter set entry registers with relative memory address locations within each of the parameter sets.
Table 6-14. EDMA Parameter Set RAM
HEX ADDRESS RANGE
0x01C0 4000 - 0x01C0 401F
0x01C0 4020 - 0x01C0 403F
0x01C0 4040 - 0x01cC0 405F
0x01C0 4060 - 0x01C0 407F
0x01C0 4080 - 0x01C0 409F
0x01C0 40A0 - 0x01C0 40BF
...
DESCRIPTION
Parameters Set 0 (8 32-bit words)
Parameters Set 1 (8 32-bit words)
Parameters Set 2 (8 32-bit words)
Parameters Set 3 (8 32-bit words)
Parameters Set 4 (8 32-bit words)
Parameters Set 5 (8 32-bit words)
...
0x01C0 4FC0 - 0x01C0 4FDF
0x01C0 4FE0 - 0x01C0 4FFF
Parameters Set 126 (8 32-bit words)
Parameters Set 127 (8 32-bit words)
Table 6-15. Parameter Set Entries
HEX OFFSET ADDRESS
WITHIN THE PARAMETER SET
ACRONYM
PARAMETER ENTRY
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
OPT
SRC
Option
Source Address
A_B_CNT
DST
A Count, B Count
Destination Address
SRC_DST_BIDX
LINK_BCNTRLD
Source B Index, Destination B Index
Link Address, B Count Reload
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Table 6-15. Parameter Set Entries (continued)
HEX OFFSET ADDRESS
WITHIN THE PARAMETER SET
ACRONYM
PARAMETER ENTRY
0x0018
0x001C
SRC_DST_CIDX
CCNT
Source C Index, Destination C Index
C Count
Table 6-16. EDMA Events
Event
Event Name / Source
Event
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Event Name / Source
MMCSD Receive
MMCSD Transmit
SPI1 Receive
0
1
McASP0 Receive
McASP0 Transmit
McASP1 Receive
McASP1 Transmit
McASP2 Receive
McASP2 Transmit
GPIO Bank 0 Interrupt
GPIO Bank 1 Interrupt
UART0 Receive
2
3
SPI1 Transmit
4
Reserved
5
Reserved
6
GPIO Bank 2 Interrupt
GPIO Bank 3 Interrupt
I2C0 Receive
7
8
9
UART0 Transmit
I2C0 Transmit
10
11
12
13
14
15
Timer64P0 Event Out 12
Timer64P0 Event Out 34
UART1 Receive
I2C1 Receive
I2C1 Transmit
GPIO Bank 4 Interrupt
GPIO Bank 5 Interrupt
UART2 Receive
UART2 Transmit
UART1 Transmit
SPI0 Receive
SPI0 Transmit
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6.10 External Memory Interface A (EMIFA)
EMIFA is one of two external memory interfaces supported on the OMAP-L137 . It is primarily intended to
support asynchronous memory types, such as NAND and NOR flash and Asynchronous SRAM. However
on OMAP-L137 EMIFA also provides a secondary interface to SDRAM.
6.10.1 EMIFA Asynchronous Memory Support
EMIFA supports asynchronous:
•
•
•
SRAM memories
NAND Flash memories
NOR Flash memories
The EMIFA data bus width is up to 16-bits on the ZKB package .The device supports up to fifteen address
lines and an external wait/interrupt input. Up to four asynchronous chip selects are supported by EMIFA
(EMA_CS[5:2]) . All four chip selects are available on the ZKB package.
Each chip select has the following individually programmable attributes:
•
•
•
•
•
•
•
Data Bus Width
Read cycle timings: setup, hold, strobe
Write cycle timings: setup, hold, strobe
Bus turn around time
Extended Wait Option With Programmable Timeout
Select Strobe Option
NAND flash controller supports 1-bit and 4-bit ECC calculation on blocks of 512 bytes.
6.10.2 EMIFA Synchronous DRAM Memory Support
The OMAP-L137 ZKB package supports 16-bit SDRAM in addition to the asynchronous memories listed in
Section 6.10.1. It has a single SDRAM chip select (EMA_CS[0]). SDRAM configurations that are
supported are:
•
•
•
•
•
One, Two, and Four Bank SDRAM devices
Devices with Eight, Nine, Ten, and Eleven Column Address
CAS Latency of two or three clock cycles
Sixteen Bit Data Bus Width
3.3V LVCMOS Interface
Additionally, the SDRAM interface of EMIFA supports placing the SDRAM in Self Refresh and Powerdown
Modes. Self Refresh mode allows the SDRAM to be put into a low power state while still retaining memory
contents; since the SDRAM will continue to refresh itself even without clocks from the DSP. Powerdown
mode achieves even lower power, except the DSP must periodically wake the SDRAM up and issue
refreshes if data retention is required.
Finally, note that the EMIFA does not support Mobile SDRAM devices.
6.10.3 EMIFA Connection Examples
Figure 6-11 illustrates an example of how SDRAM, NOR, and NAND flash devices might be connected to
EMIFA of a OMAP-L137 device simultaneously. The SDRAM chip select must be EMA_CS[0]. Note that
the NOR flash is connected to EMA_CS[2] and the NAND flash is connected to EMA_CS[3] in this
example. Note that any type of asynchronous memory may be connected to EMA_CS[5:2].
The on-chip bootloader makes some assumptions on which chip select the contains the boot image, and
this depends on the boot mode. For NOR boot mode; the on-chip bootloader requires that the image be
stored in NOR flash on EMA_CS[2]. For NAND boot mode, the bootloader requires that the boot image is
stored in NAND flash on EMA_CS[3]. It is always possible to have the image span multiple chip selects,
but this must be supported by second stage boot code stored in the external flash.
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A likely use case with more than one EMIFA chip select used for NAND flash is illustrated in Figure 6-12.
This figure shows how two multiplane NAND flash devices with two chip selects each would connect to the
EMIFA. In this case if NAND is the boot memory, then the boot image needs to be stored in the NAND
area selected by EMA_CS[3]. Part of the application image could spill over into the NAND regions
selected by other EMIFA chip selects; but would rely on the code stored in the EMA_CS[3] area to
bootload it.
EMA_CS[0]
EMA_CAS
CE
CAS
EMIFA
EMA_RAS
RAS
EMA_WE
WE
SDRAM
2M x 16 x 4
Bank
EMA_CLK
CLK
EMA_SDCKE
EMA_BA[1:0]
EMA_A[12:0]
CKE
BA[1:0]
A[11:0]
LDQM
UDQM
DQ[15:0]
EMA_WE_DQM[0]
EMA_WE_DQM[1]
EMA_D[15:0]
EMA_CS[2]
EMA_CS[3]
EMA_WAIT
EMA_OE
A[0]
A[12:1]
DQ[15:0]
CE
GPIO
(6 Pins)
RESET
NOR
FLASH
512K x 16
WE
RESET
OE
RESET
A[18:13]
...
RY/BY
EMA_A[1]
EMA_A[2]
ALE
CLE
DQ[15:0]
CE
NAND
FLASH
1Gb x 16
DVDD
WE
RE
RB
Figure 6-11. OMAP-L137 Connection Diagram: SDRAM, NOR, NAND
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EMA_A[1]
EMA_A[2]
EMA_D[7:0]
EMA_CS[2]
EMA_CS[3]
EMA_WE
ALE
CLE
DQ[7:0]
CE1
CE2
WE
NAND
FLASH
x8,
MultiPlane
EMA_OE
EMIFA
RE
R/B1
R/B2
EMA_WAIT
DVDD
ALE
CLE
DQ[7:0]
CE1
CE2
WE
NAND
FLASH
x8,
EMA_CS[4]
EMA_CS[5]
MultiPlane
RE
R/B1
R/B2
Figure 6-12. OMAP-L137 EMIFA Connection Diagram: Multiple NAND Flash Planes
6.10.4 External Memory Interface (EMIF)
Table 6-17 is a list of the EMIF registers. For more information about these registers, see the C674x DSP
External Memory Interface (EMIF) User's Guide (literature number SPRU711).
Table 6-17. External Memory Interface (EMIFA) Registers
BYTE ADDRESS
0x6800 0000
0x6800 0004
0x6800 0008
0x6800 000C
0x6800 0010
0x6800 0014
0x6800 0018
0x6800 001C
0x6800 0020
0x6800 003C
0x6800 0040
0x6800 0044
0x6800 0048
0x6800 004C
0x6800 0060
0x6800 0064
0x6800 0070
0x6800 0074
0x6800 0078
0x6800 007C
0x6800 00BC
0x6800 00C0
0x6800 00C4
Register Name
MIDR
Register Description
Module ID Register
AWCC
Asynchronous Wait Cycle Configuration Register
SDRAM Configuration Register
SDCR
SDRCR
SDRAM Refresh Control Register
Asynchronous 1 Configuration Register
Asynchronous 2 Configuration Register
Asynchronous 3 Configuration Register
Asynchronous 4 Configuration Register
SDRAM Timing Register
CE2CFG
CE3CFG
CE4CFG
CE5CFG
SDTIMR
SDSRETR
INTRAW
SDRAM Self Refresh Exit Timing Register
EMIFA Interrupt Raw Register
INTMSK
EMIFA Interrupt Mask Register
INTMSKSET
INTMSKCLR
NANDFCR
NANDFSR
NANDF1ECC
NANDF2ECC
NANDF3ECC
NANDF4ECC
NAND4BITECCLOAD
NAND4BITECC1
NAND4BITECC2
EMIFA Interrupt Mask Set Register
EMIFA Interrupt Mask Clear Register
NAND Flash Control Register
NAND Flash Status Register
NAND Flash 1 ECC Register (CS2 Space)
NAND Flash 2 ECC Register (CS3 Space)
NAND Flash 3 ECC Register (CS4 Space)
NAND Flash 4 ECC Register (CS5 Space)
NAND Flash 4-Bit ECC Load Register
NAND Flash 4-Bit ECC Register 1
NAND Flash 4-Bit ECC Register 2
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Table 6-17. External Memory Interface (EMIFA) Registers (continued)
BYTE ADDRESS
Register Name
NAND4BITECC3
NAND4BITECC4
NANDERRADD1
NANDERRADD2
NANDERRVAL1
NANDERRVAL2
Register Description
0x6800 00C8
0x6800 00CC
0x6800 00D0
0x6800 00D4
0x6800 00D8
0x6800 00DC
NAND Flash 4-Bit ECC Register 3
NAND Flash 4-Bit ECC Register 4
NAND Flash 4-Bit ECC Error Address Register 1
NAND Flash 4-Bit ECC Error Address Register 2
NAND Flash 4-Bit ECC Error Value Register 1
NAND Flash 4-Bit ECC Error Value Register 2
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6.10.5 EMIFA Electrical Data/Timing
Table 6-18 through Table 6-21 assume testing over recommended operating conditions.
Table 6-18. EMIFA SDRAM Interface Timing Requirements
NO.
MIN
MAX UNIT
Input setup time, read data valid on EMA_D[31:0] before EMA_CLK
rising
19
tsu(EMA_DV-EM_CLKH)
th(CLKH-DIV)
1
ns
Input hold time, read data valid on EMA_D[31:0] after EMA_CLK
rising
20
1.5
ns
Table 6-19. EMIFA SDRAM Interface Switching Characteristics
NO.
1
PARAMETER
MIN
10
3
MAX UNIT
tc(CLK)
Cycle time, EMIF clock EMA_CLK
ns
ns
2
tw(CLK)
Pulse width, EMIF clock EMA_CLK high or low
Delay time, EMA_CLK rising to EMA_CS[0] valid
Output hold time, EMA_CLK rising to EMA_CS[0] invalid
Delay time, EMA_CLK rising to EMA_WE_DQM[1:0] valid
Output hold time, EMA_CLK rising to EMA_WE_DQM[1:0] invalid
3
td(CLKH-CSV)
toh(CLKH-CSIV)
td(CLKH-DQMV)
toh(CLKH-DQMIV)
7
7
ns
ns
ns
ns
4
1
1
5
6
Delay time, EMA_CLK rising to EMA_A[12:0] and EMA_BA[1:0]
valid
7
8
td(CLKH-AV)
7
ns
ns
Output hold time, EMA_CLK rising to EMA_A[12:0] and
EMA_BA[1:0] invalid
toh(CLKH-AIV)
1
9
td(CLKH-DV)
Delay time, EMA_CLK rising to EMA_D[15:0] valid
Output hold time, EMA_CLK rising to EMA_D[15:0] invalid
Delay time, EMA_CLK rising to EMA_RAS valid
7
7
7
7
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
11
12
13
14
15
16
17
18
toh(CLKH-DIV)
td(CLKH-RASV)
toh(CLKH-RASIV)
td(CLKH-CASV)
toh(CLKH-CASIV)
td(CLKH-WEV)
toh(CLKH-WEIV)
tdis(CLKH-DHZ)
tena(CLKH-DLZ)
1
1
1
1
1
Output hold time, EMA_CLK rising to EMA_RAS invalid
Delay time, EMA_CLK rising to EMA_CAS valid
Output hold time, EMA_CLK rising to EMA_CAS invalid
Delay time, EMA_CLK rising to EMA_WE valid
Output hold time, EMA_CLK rising to EMA_WE invalid
Delay time, EMA_CLK rising to EMA_D[15:0] tri-stated
Output hold time, EMA_CLK rising to EMA_D[15:0] driving
Table 6-20. EMIFA Asynchronous Memory Timing Requirements(1)
OMAP-L137
NO
.
UNIT
MIN
Nom
MAX
READS and WRITES
Pulse duration, EM_WAIT assertion and
deassertion
2
tw(EM_WAIT)
2E
ns
READS
12 tsu(EMDV-EMOEH) Setup time, EM_D[15:0] valid before EM_OE high
3
ns
ns
13 th(EMOEH-EMDIV)
Hold time, EM_D[15:0] valid after EM_OE high
0.5
tsu(EMOEL-
EMWAIT)
Setup Time, EM_WAIT asserted before end of
Strobe Phase(2)
14
4E+3
ns
WRITES
(1) E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL output clock divided by 4.5. As an example, when
SYSCLK3 is selected and set to 100MHz, E=10ns.
(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended
wait states. Figure 6-17 and Figure 6-18 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
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Table 6-20. EMIFA Asynchronous Memory Timing Requirements (continued)
OMAP-L137
Nom
NO
.
UNIT
MIN
MAX
tsu(EMWEL-
EMWAIT)
Setup Time, EM_WAIT asserted before end of
Strobe Phase(2)
28
4E+3
ns
Table 6-21. EMIFA Asynchronous Memory Switching Characteristics(1)(2)(3)
OMAP-L137
NO
.
PARAMETER
UNIT
MIN
Nom
MAX
READS and WRITES
(TA)*E - 3
1
3
td(TURNAROUND)
Turn around time
(TA)*E
(TA)*E + 3
ns
READS
(RS+RST+RH)*E
- 3
(RS+RST+RH)*E
+ 3
EMIF read cycle time (EW = 0)
EMIF read cycle time (EW = 1)
(RS+RST+RH)*E
ns
ns
ns
ns
ns
ns
ns
ns
ns
tc(EMRCYCLE)
(RS+RST+RH+(E (RS+RST+RH+(EW (RS+RST+RH+(E
WC*16))*E - 3
C*16))*E
WC*16))*E + 3
Output setup time, EMA_CE[5:2] low to
EMA_OE low (SS = 0)
(RS)*E-3
(RS)*E
(RS)*E+3
4
5
tsu(EMCEL-EMOEL)
Output setup time, EMA_CE[5:2] low to
EMA_OE low (SS = 1)
-3
(RH)*E - 3
-3
0
(RH)*E
0
+3
(RH)*E + 3
+3
Output hold time, EMA_OE high to
EMA_CE[5:2] high (SS = 0)
th(EMOEH-EMCEH)
Output hold time, EMA_OE high to
EMA_CE[5:2] high (SS = 1)
Output setup time, EMA_BA[1:0] valid to
EMA_OE low
6
7
8
9
tsu(EMBAV-EMOEL)
th(EMOEH-EMBAIV)
tsu(EMBAV-EMOEL)
th(EMOEH-EMAIV)
(RS)*E-3
(RH)*E-3
(RS)*E-3
(RS)*E
(RH)*E
(RS)*E
(RS)*E+3
(RH)*E+3
(RS)*E+3
Output hold time, EMA_OE high to
EMA_BA[1:0] invalid
Output setup time, EMA_A[13:0] valid to
EMA_OE low
Output hold time, EMA_OE high to
EMA_A[13:0] invalid
(RH)*E-3
(RH)*E
(RST)*E
(RH)*E+3
ns
ns
ns
EMA_OE active low width (EW = 0)
(RST)*E-3
(RST)*E+3
10 tw(EMOEL)
(RST+(EWC*16))
*E-3
(RST+(EWC*16))
*E+3
EMA_OE active low width (EW = 1)
(RST+(EWC*16))*E
td(EMWAITH-
EMOEH)
Delay time from EMA_WAIT deasserted to
EMA_OE high
11
3E-3
4E
4E+3
ns
WRITES
(WS+WST+WH)*
E-3
(WS+WST+WH)*
E+3
EMIF write cycle time (EW = 0)
EMIF write cycle time (EW = 1)
(WS+WST+WH)*E
ns
ns
ns
ns
15 tc(EMWCYCLE)
(WS+WST+WH+( (WS+WST+WH+(E (WS+WST+WH+(
EWC*16))*E - 3
WC*16))*E
EWC*16))*E + 3
Output setup time, EMA_CE[5:2] low to
EMA_WE low (SS = 0)
(WS)*E - 3
(WS)*E
(WS)*E + 3
16 tsu(EMCEL-EMWEL)
Output setup time, EMA_CE[5:2] low to
EMA_WE low (SS = 1)
-3
0
+3
(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,
MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle
Configuration Registers. These support the following range of values: TA[4-1], RS[16-1], RST[64-1], RH[8-1], WS[16-1], WST[64-1],
WH[8-1], and MEW[1-256]. See the OMAP-L137 Asynchronous External Memory Interface (EMIF) User's Guide (SPRUED1) for more
information.
(2) E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL output clock divided by 4.5. As an example, when
SYSCLK3 is selected and set to 100MHz, E=10ns.
(3) EWC = external wait cycles determined by EMA_WAIT input signal. EWC supports the following range of values EWC[256-1]. Note that
the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See the
OMAP-L137 Asynchronous External Memory Interface (EMIF) User's Guide (SPRUED1) for more information.
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Table 6-21. EMIFA Asynchronous Memory Switching Characteristics (continued)
OMAP-L137
Nom
NO
.
PARAMETER
UNIT
MIN
MAX
Output hold time, EMA_WE high to
EMA_CE[5:2] high (SS = 0)
(WH)*E-3
(WH)*E
0
(WH)*E+3
+3
ns
ns
ns
ns
ns
ns
ns
17 th(EMWEH-EMCEH)
Output hold time, EMA_WE high to
EMA_CE[5:2] high (SS = 1)
-3
(WS)*E-3
(WH)*E-3
(WS)*E-3
(WH)*E-3
(WS)*E-3
tsu(EMDQMV-
EMWEL)
Output setup time, EMA_BA[1:0] valid to
EMA_WE low
18
19
(WS)*E
(WH)*E
(WS)*E
(WH)*E
(WS)*E
(WS)*E+3
(WH)*E+3
(WS)*E+3
(WH)*E+3
(WS)*E+3
th(EMWEH-
EMDQMIV)
Output hold time, EMA_WE high to
EMA_BA[1:0] invalid
Output setup time, EMA_BA[1:0] valid to
EMA_WE low
20 tsu(EMBAV-EMWEL)
Output hold time, EMA_WE high to
EMA_BA[1:0] invalid
21 th(EMWEH-EMBAIV)
22 tsu(EMAV-EMWEL)
23 th(EMWEH-EMAIV)
Output setup time, EMA_A[13:0] valid to
EMA_WE low
Output hold time, EMA_WE high to
EMA_A[13:0] invalid
(WH)*E-3
(WH)*E
(WST)*E
(WH)*E+3
ns
ns
ns
EMA_WE active low width (EW = 0)
(WST)*E-3
(WST)*E+3
24 tw(EMWEL)
(WST+(EWC*16))
*E-3
(WST+(EWC*16))
*E+3
EMA_WE active low width (EW = 1)
(WST+(EWC*16))*E
td(EMWAITH-
EMWEH)
Delay time from EMA_WAIT deasserted to
EMA_WE high
25
3E-3
(WS)*E-3
(WH)*E-3
4E
(WS)*E
(WH)*E
4E+3
(WS)*E+3
(WH)*E+3
ns
ns
ns
Output setup time, EMA_D[15:0] valid to
EMA_WE low
26 tsu(EMDV-EMWEL)
Output hold time, EMA_WE high to
EMA_D[15:0] invalid
27 th(EMWEH-EMDIV)
1
BASIC SDRAM
WRITE OPERATION
2
2
EMA_CLK
3
5
7
7
9
4
EMA_CS[0]
EMA_WE_DQM[1:0]
EMA_BA[1:0]
6
8
8
EMA_A[12:0]
10
EMA_D[15:0]
EMA_RAS
EMA_CAS
EMA_WE
11
12
13
15
16
Figure 6-13. EMIFA Basic SDRAM Write Operation
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1
BASIC SDRAM
READ OPERATION
2
2
EMA_CLK
3
5
7
7
4
EMA_CS[0]
6
EMA_WE_DQM[1:0]
EMA_BA[1:0]
8
8
EMA_A[12:0]
19
2 EM_CLK Delay
17
20
18
EMA_D[15:0]
EMA_RAS
11
12
13
14
EMA_CAS
EMA_WE
Figure 6-14. EMIFA Basic SDRAM Read Operation
3
1
EMA_CE[5:2]
EMA_BA[1:0]
EMA_A[12:0]
EMA_WE_DQM[1:0]
4
8
5
9
6
7
29
30
10
EMA_OE
13
12
EMA_D[15:0]
EMA_WE
Figure 6-15. Asynchronous Memory Read Timing for EMIFA
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15
1
EMA_CE[5:2]
EMA_BA[1:0]
EMA_A[12:0]
EMA_WE_DQM[1:0]
16
18
20
22
17
19
21
23
24
EMA_WE
27
26
EMA_D[15:0]
EMA_OE
Figure 6-16. Asynchronous Memory Write Timing for EMIFA
SETUP
STROBE
Extended Due to EMA_WAIT
STROBE HOLD
EMA_CE[5:2]
EMA_BA[1:0]
EMA_A[12:0]
EMA_D[15:0]
14
11
EMA_OE
2
2
EMA_WAIT
Asserted
Deasserted
Figure 6-17. EMA_WAIT Read Timing Requirements
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SETUP
STROBE
Extended Due to EMA_WAIT
STROBE HOLD
EMA_CE[5:2]
EMA_BA[1:0]
EMA_A[12:0]
EMA_D[15:0]
28
25
EMA_WE
2
Asserted
2
EMA_WAIT
Deasserted
Figure 6-18. EMA_WAIT Write Timing Requirements
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6.11 EMIFB Peripheral Registers Description(s)
Figure 6-19, EMIFB Functional Block Diagram illustrates a high-level view of the EMIFB and its
connections within the device. Multiple requesters have access to EMIFB through a switched central
resource (indicated as crossbar in the figure). The EMIFB implements a split transaction internal bus,
allowing concurrence between reads and writes from the various requesters.
EMIFB
Registers
CPU
EMB_CS
EMB_CAS
EDMA
Cmd/Write
FIFO
EMB_RAS
EMB_WE
Crossbar
Master
Peripherals
(USB, UHPI...)
EMB_CLK
SDRAM
Interface
EMB_SDCKE
EMB_BA[1:0]
EMB_A[x:0]
Read
FIFO
EMB_D[x:0]
EMB_WE_DQM[x:0]
Figure 6-19. EMIFB Functional Block Diagram
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6.11.1 Interfacing to SDRAM
The EMIFB supports a glueless interface to SDRAM devices with the following characteristics:
•
•
•
Pre-charge bit is A[10]
The number of column address bits is 8, 9, 10 or 11
The number of row address bits is 13 (in case of mobile SDR, number of row address bits can be 9,
10, 11, 12, or 13)
•
The number of internal banks is 1, 2 or 4
Figure 6-20 shows an interface between the EMIFB and a 2M × 16 × 4 bank SDRAM device. In addition,
Figure 6-21 shows an interface between the EMIFB and a 2M × 32 × 4 bank SDRAM device and
Figure 6-22 shows an interface between the EMIFB and two 4M × 16 × 4 bank SDRAM devices. Refer to
Table 6-22, as an example that shows additional list of commonly-supported SDRAM devices and the
required connections for the address pins. Note that in Table 6-22, page size/column size (not indicated in
the table) is varied to get the required addressability range.
SDRAM
2M x 16 x 4
Bank
EMIFB
EMB_CS
CE
EMB_CAS
EMB_RAS
CAS
RAS
WE
EMB_WE
EMB_CLK
CLK
CKE
EMB_SDCKE
EMB_BA[1:0]
EMB_A[11:0]
EMB_WE_DQM[0]
EMB_WE_DQM[1]
EMB_D[15:0]
BA[1:0]
A[11:0]
LDQM
UDQM
DQ[15:0]
Figure 6-20. EMIFB to 2M × 16 × 4 bank SDRAM Interface
SDRAM
2M x 32 x 4
Bank
EMIFB
EMB_CS
CE
EMB_CAS
EMB_RAS
CAS
RAS
WE
EMB_WE
EMB_CLK
CLK
CKE
EMB_SDCKE
EMB_BA[1:0]
EMB_A[11:0]
EMB_WE_DQM[3:0]
EMB_D[31:0]
BA[1:0]
A[11:0]
DQM[3:0]
DQ[31:0]
Figure 6-21. EMIFB to 2M × 32 × 4 bank SDRAM Interface
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SDRAM
4M x 16 x 4
Bank
EMIFB
EMB_CS
EMB_CAS
CE
CAS
RAS
WE
EMB_RAS
EMB_WE
EMB_CLK
CLK
CKE
EMB_SDCKE
EMB_BA[1:0]
EMB_A[12:0]
EMB_WE_DQM[0]
EMB_WE_DQM[1]
EMB_D[15:0]
EMB_WE_DQM[2]
EMB_WE_DQM[3]
EMB_D[31:16]
BA[1:0]
A[12:0]
LDQM
UDQM
DQ[15:0]
SDRAM
4M x 16 x 4
Bank
CE
CAS
RAS
WE
CLK
CKE
BA[1:0]
A[12:0]
LDQM
UDQM
DQ[15:0]
Figure 6-22. EMIFB to Dual 4M × 16 × 4 bank SDRAM Interface
Table 6-22. Example of 16/32-bit EMIFB Address Pin Connections
SDRAM Size
Width
Banks
Address Pins
A[11:0]
64M bits
×16
4
SDRAM
EMIFB
SDRAM
EMIFB
SDRAM
EMIFB
SDRAM
EMIFB
SDRAM
EMIFB
SDRAM
EMIFB
SDRAM
EMIFB
SDRAM
EMIFB
EMB_A[11:0]
A[10:0]
×32
×16
×32
×16
×32
×16
×32
4
4
4
4
4
4
4
EMB_A[10:0]
A[11:0]
128M bits
256M bits
512M bits
EMB_A[11:0]
A[11:0]
EMB_A[11:0]
A[12:0]
EMB_A[12:0]
A[11:0]
EMB_A[11:0]
A[12:0]
EMB_A[12:0]
A[12:0]
EMB_A[12:0]
Table 6-23 is a list of the EMIFB registers.
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Table 6-23. EMIFB Base Controller Registers
BYTE ADDRESS
Acronym
MIDR
Register
0xB000 0000
0xB000 0008
0xB000 000C
0xB000 0010
0xB000 0014
0xB000 001C
0xB000 0020
0xB000 0040
0xB000 0044
0xB000 0048
0xB000 004C
0xB000 0050
0xB000 00C0
0xB000 00C4
0xB000 00C8
0xB000 00CC
Module ID Register
SDCFG
SDRFC
SDTIM1
SDTIM2
SDCFG2
BPRIO
PC1
SDRAM Configuration Register
SDRAM Refresh Control Register
SDRAM Timing Register 1
SDRAM Timing Register 2
SDRAM Configuration 2 Register
Peripheral Bus Burst Priority Register
Performance Counter 1 Register
Performance Counter 2 Register
Performance Counter Configuration Register
Performance Counter Master Region Select Register
Performance Counter Time Register
Interrupt Raw Register
PC2
PCC
PCMRS
PCT
IRR
IMR
Interrupt Mask Register
IMSR
Interrupt Mask Set Register
IMCR
Interrupt Mask Clear Register
6.11.2 EMIFB Electrical Data/Timing
Table 6-24. EMIFB SDRAM Interface Timing Requirements
NO.
MIN
MAX UNIT
Input setup time, read data valid on EMB_D[31:0] before EMB_CLK
rising
19
tsu(EMA_DV-EM_CLKH)
th(CLKH-DIV)
0.5
ns
Input hold time, read data valid on EMB_D[31:0] after EMB_CLK
rising
20
1.5
ns
Table 6-25. EMIFB SDRAM Interface Switching Characteristics
NO.
1
PARAMETER
MIN
7.5
3
MAX UNIT
tc(CLK)
Cycle time, EMIF clock EMB_CLK
ns
ns
2
tw(CLK)
Pulse width, EMIF clock EMB_CLK high or low
Delay time, EMB_CLK rising to EMB_CS[0] valid
Output hold time, EMB_CLK rising to EMB_CS[0] invalid
Delay time, EMB_CLK rising to EMB_WE_DQM[3:0] valid
Output hold time, EMB_CLK rising to EMB_WE_DQM[3:0] invalid
3
td(CLKH-CSV)
toh(CLKH-CSIV)
td(CLKH-DQMV)
toh(CLKH-DQMIV)
5.1 ns
ns
4
0.9
0.9
5
5.1 ns
ns
6
Delay time, EMB_CLK rising to EMB_A[12:0] and EMB_BA[1:0]
valid
7
8
td(CLKH-AV)
5.1 ns
ns
Output hold time, EMB_CLK rising to EMB_A[12:0] and
EMB_BA[1:0] invalid
toh(CLKH-AIV)
0.9
9
td(CLKH-DV)
Delay time, EMB_CLK rising to EMB_D[31:0] valid
Output hold time, EMB_CLK rising to EMB_D[31:0] invalid
Delay time, EMB_CLK rising to EMB_RAS valid
5.1 ns
ns
10
11
12
13
14
15
16
17
18
toh(CLKH-DIV)
td(CLKH-RASV)
toh(CLKH-RASIV)
td(CLKH-CASV)
toh(CLKH-CASIV)
td(CLKH-WEV)
toh(CLKH-WEIV)
tdis(CLKH-DHZ)
tena(CLKH-DLZ)
0.9
0.9
0.9
0.9
0.9
5.1 ns
ns
Output hold time, EMB_CLK rising to EMB_RAS invalid
Delay time, EMB_CLK rising to EMB_CAS valid
5.1 ns
ns
Output hold time, EMB_CLK rising to EMB_CAS invalid
Delay time, EMB_CLK rising to EMB_WE valid
5.1 ns
ns
Output hold time, EMB_CLK rising to EMB_WE invalid
Delay time, EMB_CLK rising to EMB_D[31:0] tri-stated
Output hold time, EMB_CLK rising to EMB_D[31:0] driving
5.1 ns
ns
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1
BASIC SDRAM
WRITE OPERATION
2
2
EMB_CLK
EMB_CS[0]
3
5
7
7
9
4
6
EMB_WE_DQM[3:0]
EMB_BA[1:0]
8
8
EMB_A[12:0]
10
EMB_D[31:0]
EMB_RAS
EMB_CAS
EMB_WE
11
12
13
15
16
Figure 6-23. EMIFB Basic SDRAM Write Operation
1
BASIC SDRAM
READ OPERATION
2
2
EMB_CLK
EMB_CS[0]
3
5
7
7
4
6
EMB_WE_DQM[3:0]
EMB_BA[1:0]
8
8
EMB_A[12:0]
19
20
2 EM_CLK Delay
17
18
EMB_D[31:0]
EMB_RAS
11
12
13
14
EMB_CAS
EMB_WE
Figure 6-24. EMIFB Basic SDRAM Read Operation
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6.12 MMC / SD / SDIO (MMCSD)
6.12.1 MMCSD Peripheral Description
The OMAP-L137 includes an MMCSD controller which is compliant with MMC V3.31, Secure Digital Part 1
Physical Layer Specification V1.1 and Secure Digital Input Output (SDIO) V2.0 specifications.
The MMC/SD Controller has following features:
•
•
•
•
•
•
•
MultiMediaCard (MMC).
Secure Digital (SD) Memory Card.
MMC/SD protocol support.
SDIO protocol support.
Programmable clock frequency.
512 bit Read/Write FIFO to lower system overhead.
Slave EDMA transfer capability.
The OMAP-L137 MMC/SD Controller does not support SPI mode.
6.12.2 MMCSD Peripheral Register Description(s)
Table 6-26. Multimedia Card/Secure Digital (MMC/SD) Card Controller Registers
Offset
Acronym
MMCCTL
Register Description
MMC Control Register
0x01C4 0000
0x01C4 0004
0x01C4 0008
0x01C4 000C
0x01C4 0010
0x01C4 0014
0x01C4 0018
0x01C4 001C
0x01C4 0020
0x01C4 0024
0x01C4 0028
0x01C4 002C
0x01C4 0030
0x01C4 0034
0x01C4 0038
0x01C4 003C
0x01C4 0040
0x01C4 0044
0x01C4 0048
0x01C4 0050
0x01C4 0064
0x01C4 0068
0x01C4 006C
0x01C4 0070
0x01C4 0074
MMCCLK
MMC Memory Clock Control Register
MMC Status Register 0
MMCST0
MMCST1
MMC Status Register 1
MMCIM
MMC Interrupt Mask Register
MMC Response Time-Out Register
MMC Data Read Time-Out Register
MMC Block Length Register
MMC Number of Blocks Register
MMC Number of Blocks Counter Register
MMC Data Receive Register
MMC Data Transmit Register
MMC Command Register
MMCTOR
MMCTOD
MMCBLEN
MMCNBLK
MMCNBLC
MMCDRR
MMCDXR
MMCCMD
MMCARGHL
MMCRSP01
MMCRSP23
MMCRSP45
MMCRSP67
MMCDRSP
MMCCIDX
SDIOCTL
MMC Argument Register
MMC Response Register 0 and 1
MMC Response Register 2 and 3
MMC Response Register 4 and 5
MMC Response Register 6 and 7
MMC Data Response Register
MMC Command Index Register
SDIO Control Register
SDIOST0
SDIO Status Register 0
SDIOIEN
SDIO Interrupt Enable Register
SDIO Interrupt Status Register
MMC FIFO Control Register
SDIOIST
MMCFIFOCTL
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6.12.3 MMC/SD Electrical Data/Timing
Table 6-27. Timing Requirements for MMC/SD Module
(see Figure 6-26 and Figure 6-28)
NO.
1
MIN
TBD
MAX
UNIT
ns
tsu(CMDV-CLKH)
th(CLKH-CMDV)
tsu(DATV-CLKH)
th(CLKH-DATV)
Setup time, SD_CMD valid before SD_CLK high
2
Hold time, SD_CMD valid after SD_CLK high
Setup time, SD_DATx valid before SD_CLK high
Hold time, SD_DATx valid after SD_CLK high
TBD
TBD
TBD
ns
3
ns
4
ns
Table 6-28. Switching Characteristics Over Recommended Operating Conditions for MMC/SD Module
(see Figure 6-25 through Figure 6-28)
NO.
7
PARAMETER
Operating frequency, SD_CLK
MIN
MAX
UNIT
f(CLK)
TBD
TBD
TBD
TBD
TBD MHz
8
f(CLK_ID)
tW(CLKL)
tW(CLKH)
tr(CLK)
Identification mode frequency, SD_CLK
Pulse width, SD_CLK low
TBD KHz
9
ns
ns
10
11
12
13
14
Pulse width, SD_CLK high
Rise time, SD_CLK
TBD
TBD
TBD
TBD
ns
ns
ns
ns
tf(CLK)
Fall time, SD_CLK
td(CLKL-CMD)
td(CLKL-DAT)
Delay time, SD_CLK low to SD_CMD transition
Delay time, SD_CLK low to SD_DATx transition
TBD
TBD
10
9
7
MMCSD_CLK
MMCSD_CMD
13
13
13
13
START
XMIT
Valid
Valid
Valid
END
Figure 6-25. MMC/SD Host Command Timing
9
10
7
MMCSD_CLK
MMCSD_CMD
1
2
Valid
START
XMIT
Valid
Valid
END
Figure 6-26. MMC/SD Card Response Timing
10
9
7
MMCSD_CLK
MMCSD_DATx
14
14
14
Dx
14
START
D0
D1
END
Figure 6-27. MMC/SD Host Write Timing
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9
10
7
MMCSD_CLK
MMCSD_DATx
4
4
3
3
End
Start
D0
D1
Dx
Figure 6-28. MMC/SD Host Read and Card CRC Status Timing
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6.13 Ethernet Media Access Controller (EMAC)
The Ethernet Media Access Controller (EMAC) provides an efficient interface between OMAP-L137 and
the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100
Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.
The EMAC controls the flow of packet data from the OMAP-L137 device to the PHY. The MDIO module
controls PHY configuration and status monitoring.
Both the EMAC and the MDIO modules interface to the OMAP-L137 device through a custom interface
that allows efficient data transmission and reception. This custom interface is referred to as the EMAC
control module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used
to multiplex and control interrupts.
6.13.1 EMAC Peripheral Register Description(s)
Table 6-29. Ethernet Media Access Controller (EMAC) Registers
Offset
0h
BYTE ADDRESS
0x01E2 3000
0x01E2 3004
0x01E2 3008
0x01E2 3010
0x01E2 3014
0x01E2 3018
0x01E2 3080
0x01E2 3084
0x01E2 3088
0x01E2 308C
0x01E2 3090
0x01E2 3094
0x01E2 30A0
0x01E2 30A4
0x01E2 30A8
0x01E2 30AC
0x01E2 30B0
0x01E2 30B4
0x01E2 30B8
0x01E2 30BC
0x01E2 3100
0x01E2 3104
0x01E2 3108
0x01E2 310C
0x01E2 3110
0x01E2 3114
0x01E2 3120
0x01E2 3124
0x01E2 3128
0x01E2 312C
0x01E2 3130
0x01E2 3134
0x01E2 3138
0x01E2 313C
REGISTER
TXREV
Register Description
Transmit Revision Register
4h
TXCONTROL
Transmit Control Register
8h
TXTEARDOWN
Transmit Teardown Register
10h
RXREV
Receive Revision Register
14h
RXCONTROL
Receive Control Register
18h
RXTEARDOWN
Receive Teardown Register
80h
TXINTSTATRAW
TXINTSTATMASKED
TXINTMASKSET
TXINTMASKCLEAR
MACINVECTOR
Transmit Interrupt Status (Unmasked) Register
Transmit Interrupt Status (Masked) Register
Transmit Interrupt Mask Set Register
Transmit Interrupt Clear Register
84h
88h
8Ch
90h
MAC Input Vector Register
94h
MACEOIVECTOR
RXINTSTATRAW
RXINTSTATMASKED
RXINTMASKSET
RXINTMASKCLEAR
MACINTSTATRAW
MACINTSTATMASKED
MACINTMASKSET
MACINTMASKCLEAR
RXMBPENABLE
RXUNICASTSET
RXUNICASTCLEAR
RXMAXLEN
MAC End Of Interrupt Vector Register
Receive Interrupt Status (Unmasked) Register
Receive Interrupt Status (Masked) Register
Receive Interrupt Mask Set Register
A0h
A4h
A8h
ACh
B0h
B4h
B8h
BCh
100h
104h
108h
10Ch
110h
114h
120h
124h
128h
12Ch
130h
134h
138h
13Ch
Receive Interrupt Mask Clear Register
MAC Interrupt Status (Unmasked) Register
MAC Interrupt Status (Masked) Register
MAC Interrupt Mask Set Register
MAC Interrupt Mask Clear Register
Receive Multicast/Broadcast/Promiscuous Channel Enable Register
Receive Unicast Enable Set Register
Receive Unicast Clear Register
Receive Maximum Length Register
RXBUFFEROFFSET
RXFILTERLOWTHRESH
RX0FLOWTHRESH
RX1FLOWTHRESH
RX2FLOWTHRESH
RX3FLOWTHRESH
RX4FLOWTHRESH
RX5FLOWTHRESH
RX6FLOWTHRESH
RX7FLOWTHRESH
Receive Buffer Offset Register
Receive Filter Low Priority Frame Threshold Register
Receive Channel 0 Flow Control Threshold Register
Receive Channel 1 Flow Control Threshold Register
Receive Channel 2 Flow Control Threshold Register
Receive Channel 3 Flow Control Threshold Register
Receive Channel 4 Flow Control Threshold Register
Receive Channel 5 Flow Control Threshold Register
Receive Channel 6 Flow Control Threshold Register
Receive Channel 7 Flow Control Threshold Register
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Table 6-29. Ethernet Media Access Controller (EMAC) Registers (continued)
Offset
140h
144h
148h
14Ch
150h
154h
158h
15Ch
160h
164h
168h
16Ch
170h
174h
1D0h
1D4h
1D8h
1DCh
1E0h
1E4h
1E8h
1ECh
BYTE ADDRESS
0x01E2 3140
0x01E2 3144
0x01E2 3148
0x01E2 314C
0x01E2 3150
0x01E2 3154
0x01E2 3158
0x01E2 315C
0x01E2 3160
0x01E2 3164
0x01E2 3168
0x01E2 316C
0x01E2 3170
0x01E2 3174
0x01E2 31D0
0x01E2 31D4
0x01E2 31D8
0x01E2 31DC
0x01E2 31E0
0x01E2 31E4
0x01E2 31E8
0x01E2 31EC
REGISTER
RX0FREEBUFFER
RX1FREEBUFFER
RX2FREEBUFFER
RX3FREEBUFFER
RX4FREEBUFFER
RX5FREEBUFFER
RX6FREEBUFFER
RX7FREEBUFFER
MACCONTROL
MACSTATUS
Register Description
Receive Channel 0 Free Buffer Count Register
Receive Channel 1 Free Buffer Count Register
Receive Channel 2 Free Buffer Count Register
Receive Channel 3 Free Buffer Count Register
Receive Channel 4 Free Buffer Count Register
Receive Channel 5 Free Buffer Count Register
Receive Channel 6 Free Buffer Count Register
Receive Channel 7 Free Buffer Count Register
MAC Control Register
MAC Status Register
EMCONTROL
Emulation Control Register
FIFOCONTROL
MACCONFIG
FIFO Control Register
MAC Configuration Register
SOFTRESET
Soft Reset Register
MACSRCADDRLO
MACSRCADDRHI
MACHASH1
MAC Source Address Low Bytes Register
MAC Source Address High Bytes Register
MAC Hash Address Register 1
MACHASH2
MAC Hash Address Register 2
BOFFTEST
Back Off Test Register
TPACETEST
Transmit Pacing Algorithm Test Register
Receive Pause Timer Register
RXPAUSE
TXPAUSE
Transmit Pause Timer Register
0x01E2 3200 - 0x01E2
32FC
(see Table 6-30)
EMAC Statistics Registers
500h
504h
0x01E2 3500
MACADDRLO
MACADDRHI
MAC Address Low Bytes Register, Used in Receive Address Matching
MAC Address High Bytes Register, Used in Receive Address
Matching
0x01E2 3504
508h
600h
604h
608h
60Ch
610h
614h
618h
61Ch
620h
624h
628h
62Ch
630h
634h
638h
63Ch
640h
644h
648h
64Ch
0x01E2 3508
0x01E2 3600
0x01E2 3604
0x01E2 3608
0x01E2 360C
0x01E2 3610
0x01E2 3614
0x01E2 3618
0x01E2 361C
0x01E2 3620
0x01E2 3624
0x01E2 3628
0x01E2 362C
0x01E2 3630
0x01E2 3634
0x01E2 3638
0x01E2 363C
0x01E2 3640
0x01E2 3644
0x01E2 3648
0x01E2 364C
MACINDEX
TX0HDP
TX1HDP
TX2HDP
TX3HDP
TX4HDP
TX5HDP
TX6HDP
TX7HDP
RX0HDP
RX1HDP
RX2HDP
RX3HDP
RX4HDP
RX5HDP
RX6HDP
RX7HDP
TX0CP
MAC Index Register
Transmit Channel 0 DMA Head Descriptor Pointer Register
Transmit Channel 1 DMA Head Descriptor Pointer Register
Transmit Channel 2 DMA Head Descriptor Pointer Register
Transmit Channel 3 DMA Head Descriptor Pointer Register
Transmit Channel 4 DMA Head Descriptor Pointer Register
Transmit Channel 5 DMA Head Descriptor Pointer Register
Transmit Channel 6 DMA Head Descriptor Pointer Register
Transmit Channel 7 DMA Head Descriptor Pointer Register
Receive Channel 0 DMA Head Descriptor Pointer Register
Receive Channel 1 DMA Head Descriptor Pointer Register
Receive Channel 2 DMA Head Descriptor Pointer Register
Receive Channel 3 DMA Head Descriptor Pointer Register
Receive Channel 4 DMA Head Descriptor Pointer Register
Receive Channel 5 DMA Head Descriptor Pointer Register
Receive Channel 6 DMA Head Descriptor Pointer Register
Receive Channel 7 DMA Head Descriptor Pointer Register
Transmit Channel 0 Completion Pointer Register
TX1CP
Transmit Channel 1 Completion Pointer Register
TX2CP
Transmit Channel 2 Completion Pointer Register
TX3CP
Transmit Channel 3 Completion Pointer Register
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Table 6-29. Ethernet Media Access Controller (EMAC) Registers (continued)
Offset
650h
654h
658h
65Ch
660h
664h
668h
66Ch
670h
674h
678h
67Ch
BYTE ADDRESS
0x01E2 3650
0x01E2 3654
0x01E2 3658
0x01E2 365C
0x01E2 3660
0x01E2 3664
0x01E2 3668
0x01E2 366C
0x01E2 3670
0x01E2 3674
0x01E2 3678
0x01E2 367C
REGISTER
TX4CP
TX5CP
TX6CP
TX7CP
RX0CP
RX1CP
RX2CP
RX3CP
RX4CP
RX5CP
RX6CP
RX7CP
Register Description
Transmit Channel 4 Completion Pointer Register
Transmit Channel 5 Completion Pointer Register
Transmit Channel 6 Completion Pointer Register
Transmit Channel 7 Completion Pointer Register
Receive Channel 0 Completion Pointer Register
Receive Channel 1 Completion Pointer Register
Receive Channel 2 Completion Pointer Register
Receive Channel 3 Completion Pointer Register
Receive Channel 4 Completion Pointer Register
Receive Channel 5 Completion Pointer Register
Receive Channel 6 Completion Pointer Register
Receive Channel 7 Completion Pointer Register
Table 6-30. EMAC Statistics Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
0x01E2 3200
RXGOODFRAMES
Good Receive Frames Register
Broadcast Receive Frames Register
(Total number of good broadcast frames received)
0x01E2 3204
RXBCASTFRAMES
Multicast Receive Frames Register
(Total number of good multicast frames received)
0x01E2 3208
0x01E2 320C
0x01E2 3210
RXMCASTFRAMES
RXPAUSEFRAMES
RXCRCERRORS
Pause Receive Frames Register
Receive CRC Errors Register (Total number of frames received with
CRC errors)
Receive Alignment/Code Errors Register
(Total number of frames received with alignment/code errors)
0x01E2 3214
0x01E2 3218
0x01E2 321C
0x01E2 3220
RXALIGNCODEERRORS
RXOVERSIZED
Receive Oversized Frames Register
(Total number of oversized frames received)
Receive Jabber Frames Register
(Total number of jabber frames received)
RXJABBER
Receive Undersized Frames Register
(Total number of undersized frames received)
RXUNDERSIZED
0x01E2 3224
0x01E2 3228
0x01E2 322C
RXFRAGMENTS
RXFILTERED
Receive Frame Fragments Register
Filtered Receive Frames Register
Received QOS Filtered Frames Register
RXQOSFILTERED
Receive Octet Frames Register
(Total number of received bytes in good frames)
0x01E2 3230
0x01E2 3234
RXOCTETS
Good Transmit Frames Register
(Total number of good frames transmitted)
TXGOODFRAMES
0x01E2 3238
0x01E2 323C
0x01E2 3240
0x01E2 3244
0x01E2 3248
0x01E2 324C
0x01E2 3250
0x01E2 3254
0x01E2 3258
0x01E2 325C
0x01E2 3260
0x01E2 3264
TXBCASTFRAMES
TXMCASTFRAMES
TXPAUSEFRAMES
TXDEFERRED
Broadcast Transmit Frames Register
Multicast Transmit Frames Register
Pause Transmit Frames Register
Deferred Transmit Frames Register
Transmit Collision Frames Register
Transmit Single Collision Frames Register
Transmit Multiple Collision Frames Register
Transmit Excessive Collision Frames Register
Transmit Late Collision Frames Register
Transmit Underrun Error Register
TXCOLLISION
TXSINGLECOLL
TXMULTICOLL
TXEXCESSIVECOLL
TXLATECOLL
TXUNDERRUN
TXCARRIERSENSE
TXOCTETS
Transmit Carrier Sense Errors Register
Transmit Octet Frames Register
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Table 6-30. EMAC Statistics Registers (continued)
HEX ADDRESS RANGE
ACRONYM
FRAME64
REGISTER NAME
0x01E2 3268
0x01E2 326C
0x01E2 3270
0x01E2 3274
0x01E2 3278
0x01E2 327C
0x01E2 3280
0x01E2 3284
0x01E2 3288
Transmit and Receive 64 Octet Frames Register
Transmit and Receive 65 to 127 Octet Frames Register
Transmit and Receive 128 to 255 Octet Frames Register
Transmit and Receive 256 to 511 Octet Frames Register
Transmit and Receive 512 to 1023 Octet Frames Register
Transmit and Receive 1024 to 1518 Octet Frames Register
Network Octet Frames Register
FRAME65T127
FRAME128T255
FRAME256T511
FRAME512T1023
FRAME1024TUP
NETOCTETS
RXSOFOVERRUNS
RXMOFOVERRUNS
Receive FIFO or DMA Start of Frame Overruns Register
Receive FIFO or DMA Middle of Frame Overruns Register
Receive DMA Start of Frame and Middle of Frame Overruns
Register
0x01E2 328C
RXDMAOVERRUNS
Table 6-31. EMAC Control Module Registers
BYTE ADDRESS
0x01E2 2000
0x01E2 2004
0x01E2 200C
0x01E2 2010
Acronym
Register Description
REV
EMAC Control Module Revision Register
EMAC Control Module Software Reset Register
EMAC Control Module Interrupt Control Register
SOFTRESET
INTCONTROL
C0RXTHRESHEN
EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Enable
Register
0x01E2 2014
0x01E2 2018
0x01E2 201C
C0RXEN
C0TXEN
EMAC Control Module Interrupt Core 0 Receive Interrupt Enable Register
EMAC Control Module Interrupt Core 0 Transmit Interrupt Enable Register
C0MISCEN
EMAC Control Module Interrupt Core 0 Miscellaneous Interrupt Enable
Register
0x01E2 2020
C1RXTHRESHEN
EMAC Control Module Interrupt Core 1 Receive Threshold Interrupt Enable
Register
0x01E2 2024
0x01E2 2028
0x01E2 202C
C1RXEN
C1TXEN
EMAC Control Module Interrupt Core 1 Receive Interrupt Enable Register
EMAC Control Module Interrupt Core 1 Transmit Interrupt Enable Register
C1MISCEN
EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Enable
Register
0x01E2 2030
C2RXTHRESHEN
EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Enable
Register
0x01E2 2034
0x01E2 2038
0x01E2 203C
C2RXEN
C2TXEN
EMAC Control Module Interrupt Core 2 Receive Interrupt Enable Register
EMAC Control Module Interrupt Core 2 Transmit Interrupt Enable Register
C2MISCEN
EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Enable
Register
0x01E2 2040
C0RXTHRESHSTAT
EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Status
Register
0x01E2 2044
0x01E2 2048
0x01E2 204C
C0RXSTAT
C0TXSTAT
C0MISCSTAT
EMAC Control Module Interrupt Core 0 Receive Interrupt Status Register
EMAC Control Module Interrupt Core 0 Transmit Interrupt Status Register
EMAC Control Module Interrupt Core 0 Miscellaneous Interrupt Status
Register
0x01E2 2050
C1RXTHRESHSTAT
EMAC Control Module Interrupt Core 1 Receive Threshold Interrupt Status
Register
0x01E2 2054
0x01E2 2058
0x01E2 205C
C1RXSTAT
C1TXSTAT
C1MISCSTAT
EMAC Control Module Interrupt Core 1 Receive Interrupt Status Register
EMAC Control Module Interrupt Core 1 Transmit Interrupt Status Register
EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Status
Register
0x01E2 2060
C2RXTHRESHSTAT
EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Status
Register
0x01E2 2064
0x01E2 2068
C2RXSTAT
C2TXSTAT
EMAC Control Module Interrupt Core 2 Receive Interrupt Status Register
EMAC Control Module Interrupt Core 2 Transmit Interrupt Status Register
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Table 6-31. EMAC Control Module Registers (continued)
BYTE ADDRESS
Acronym
Register Description
0x01E2 206C
C2MISCSTAT
EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Status
Register
0x01E2 2070
0x01E2 2074
0x01E2 2078
0x01E2 207C
0x01E2 2080
0x01E2 2084
C0RXIMAX
C0TXIMAX
C1RXIMAX
C1TXIMAX
C2RXIMAX
C2TXIMAX
EMAC Control Module Interrupt Core 0 Receive Interrupts Per Millisecond
Register
EMAC Control Module Interrupt Core 0 Transmit Interrupts Per Millisecond
Register
EMAC Control Module Interrupt Core 1 Receive Interrupts Per Millisecond
Register
EMAC Control Module Interrupt Core 1 Transmit Interrupts Per Millisecond
Register
EMAC Control Module Interrupt Core 2 Receive Interrupts Per Millisecond
Register
EMAC Control Module Interrupt Core 2 Transmit Interrupts Per Millisecond
Register
Table 6-32. EMAC Control Module RAM
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
EMAC Local Buffer Descriptor Memory
0x01E2 0000 - 0x01E2 1FFF
Table 6-33. RMII Timing Requirements
NO.
PARAMETER
MIN
TYP
MAX
UNIT
ns
1
tc(REFCLK)
Cycle Time, REF_CLK
Pulse Width, REF_CLK High
Pulse Width, REF_CLK Low
20
2
3
6
tw(REFCLKH)
tw(REFCLKL)
tsu(RXD-REFCLK)
7
7
4
13
13
ns
ns
Input Setup Time, RXD Valid before REF_CLK
High
ns
7
8
th(REFCLK-RXD)
Input Hold Time, RXD Valid after REF_CLK High
2
4
ns
ns
tsu(CRSDV-REFCLK)
Input Setup Time, CRSDV Valid before
REF_CLK High
9
th(REFCLK-CRSDV)
tsu(RXER-REFCLK)
th(REFCLKR-RXER)
Input Hold Time, CRSDV Valid after REF_CLK
High
2
4
2
ns
ns
ns
10
11
Input Setup Time, RXER Valid before REF_CLK
High
Input Hold Time, RXER Valid after REF_CLK
High
Table 6-34. RMII Timing Requirements
NO.
4
PARAMETER
MIN
TYP
MAX
13
UNIT
ns
td(REFCLK-TXD)
td(REFCLK-TXEN)
Output Delay Time, REF_CLK High to TXD Valid
2.5
2.5
5
Output Delay Time, REF_CLK High to TXEN
Valid
13
ns
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1
2
3
RMII_MHz_50_CLK
5
5
RMII_TXEN
4
RMII_TXD[1:0]
6
7
RMII_RXD[1:0]
RMII_CRS_DV
8
9
10
11
RMII_RXER
Figure 6-29. RMII Timing Diagram
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6.14 Management Data Input/Output (MDIO)
The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to
enumerate all PHY devices in the system.
The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to
interrogate and control Ethernet PHY(s) using a shared two-wire bus. Host software uses the MDIO
module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the
negotiation results, and configure required parameters in the EMAC module for correct operation. The
module is designed to allow almost transparent operation of the MDIO interface, with very little
maintenance from the core processor. Only one PHY may be connected at any given time.
For more detailed information on the MDIO peripheral, see the OMAP-L137 Applications Processor DSP
Peripherals Overview Reference Guide. – Literature Number SPRUGA6 .
6.14.1 MDIO Registers
For a list of supported MDIO registers see Table 6-35 [MDIO Registers].
Table 6-35. MDIO Register Memory Map
HEX ADDRESS RANGE
0x01E2 4000
ACRONYM
REV
REGISTER NAME
Revision Identification Register
0x01E2 4004
CONTROL
ALIVE
MDIO Control Register
0x01E2 4008
MDIO PHY Alive Status Register
0x01E2 400C
LINK
MDIO PHY Link Status Register
0x01E2 4010
LINKINTRAW
LINKINTMASKED
–
MDIO Link Status Change Interrupt (Unmasked) Register
MDIO Link Status Change Interrupt (Masked) Register
Reserved
0x01E2 4014
0x01E2 4018
0x01E2 4020
USERINTRAW
USERINTMASKED
USERINTMASKSET
MDIO User Command Complete Interrupt (Unmasked) Register
MDIO User Command Complete Interrupt (Masked) Register
MDIO User Command Complete Interrupt Mask Set Register
0x01E2 4024
0x01E2 4028
0x01E2 402C
USERINTMASKCLEAR MDIO User Command Complete Interrupt Mask Clear Register
0x01E2 4030 - 0x01E2 407C
0x01E2 4080
–
Reserved
USERACCESS0
USERPHYSEL0
USERACCESS1
USERPHYSEL1
–
MDIO User Access Register 0
MDIO User PHY Select Register 0
MDIO User Access Register 1
MDIO User PHY Select Register 1
Reserved
0x01E2 4084
0x01E2 4088
0x01E2 408C
0x01E2 4090 - 0x01E2 47FF
6.14.2 Management Data Input/Output (MDIO) Electrical Data/Timing
Table 6-36. Timing Requirements for MDIO Input (see Figure 6-30 and Figure 6-31)
NO.
UNIT
MIN
400
180
MAX
1
2
3
4
5
tc(MDCLK)
Cycle time, MDCLK
ns
ns
ns
ns
ns
tw(MDCLK)
Pulse duration, MDCLK high/low
tt(MDCLK)
Transition time, MDCLK
5
tsu(MDIO-MDCLKH)
th(MDCLKH-MDIO)
Setup time, MDIO data input valid before MDCLK high
Hold time, MDIO data input valid after MDCLK high
10
10
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1
3
3
MDCLK
4
5
MDIO
(input)
Figure 6-30. MDIO Input Timing
Table 6-37. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
(see Figure 6-31)
NO.
UNIT
MIN
MAX
7
td(MDCLKL-MDIO)
Delay time, MDCLK low to MDIO data output valid
0
100
ns
1
MDCLK
7
MDIO
(output)
Figure 6-31. MDIO Output Timing
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6.15 Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2)
The McASP serial port is specifically designed for multichannel audio applications. Its key features are:
•
•
•
Flexible clock and frame sync generation logic and on-chip dividers
Up to sixteen transmit or receive data pins and serializers
Large number of serial data format options, including:
–
–
–
–
–
TDM Frames with 2 to 32 time slots per frame (periodic) or 1 slot per frame (burst)
Time slots of 8,12,16, 20, 24, 28, and 32 bits
First bit delay 0, 1, or 2 clocks
MSB or LSB first bit order
Left- or right-aligned data words within time slots
•
•
•
DIT Mode (optional) with 384-bit Channel Status and 384-bit User Data registers
Extensive error checking and mute generation logic
All unused pins GPIO-capable
Additionally, while the OMAP-L13x McASP modules are backward compatible with the McASP on
previous devices; the OMAP-L13x McASP includes the following new features:
•
Transmit & Receive FIFO Buffers for each McASP. Allows the McASP to operate at a higher sample
rate by making it more tolerant to DMA latency.
•
Dynamic Adjustment of Clock Dividers
–
–
Clock Divider Value may be changed without resetting the McASP
A one-shot adjustment (+/-1 Input Clock) feature has been added to enable simple input/output
sample rate matching
The three McASPs on the OMAP-L137 are configured with the following options:
Table 6-38. OMAP-L137 McASP Configurations(1)
Module
Serializers
AFIFO
DIT
OMAP-L137 Pins
64 Word RX
64 Word TX
AXR0[15:0], AHCLKR0, ACLKR0, AFSR0, AHCLKX0, ACLKX0,
AFSX0, AMUTE0
McASP0
16
N
64 Word RX
64 Word TX
AXR1[11:10], AXR1[8:0], AHCLKR1, ACLKR1, AFSR1, AHCLKX1,
ACLKX1, AFSX1, AMUTE1
McASP1
McASP2
12
4
N
Y
16 Word RX
16 Word TX
AXR2[3:0], AHCLKR2, ACLKR2, AFSR2, AHCLKX2, ACLKX2,
AFSX2, AMUTE2
(1) Pins available are the maximum number of pins that may be configured for a particular McASP; not including pin multiplexing.
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Pins
Function
AHCLKRx Receive Master Clock
Receive Logic
Clock/Frame Generator
State Machine
Peripheral
Configuration
Bus
GIO
Control
ACLKRx
AFSRx
Receive Bit Clock
Receive Left/Right Clock or Frame Sync
The McASPs DO NOT have
dedicated AMUTEINx pins.
AMUTEINx
AMUTEx
Clock Check and
Error Detection
DIT RAM
384 C
384 U
AFSXx
ACLKXx
AHCLKXx
Transmit Left/Right Clock or Frame Sync
Transmit Bit Clock
Transmit Master Clock
Transmit Logic
Clock/Frame Generator
State Machine
Optional
Transmit
Formatter
Serializer 0
Serializer 1
AXRx[0]
AXRx[1]
Transmit/Receive Serial Data Pin
Transmit/Receive Serial Data Pin
McASP
DMA Bus
(Dedicated)
Receive
Formatter
Serializer y
AXRx[y]
Transmit/Receive Serial Data Pin
McASPx (x = 0, 1, 2)
Figure 6-32. McASP Block Diagram
6.15.1 McASP Peripheral Registers Description(s)
Registers for the McASP are summarized in Table 6-39. The registers are accessed through the
peripheral configuration port. The receive buffer registers (RBUF) and transmit buffer registers (XBUF) can
also be accessed through the DMA port, as listed in Table 6-40
Registers for the McASP Audio FIFO (AFIFO) are summarized in Table 6-41. Note that the AFIFO Write
FIFO (WFIFO) and Read FIFO (RFIFO) have independent control and status registers. The AFIFO control
registers are accessed through the peripheral configuration port.
Table 6-39. McASP Registers Accessed Through Peripheral Configuration Port
Offset
McASP0
BYTE
McASP1
BYTE
McASP2
BYTE
Acronym
Register Description
ADDRESS
ADDRESS
ADDRESS
0h
0x01D0 0000
0x01D0 0010
0x01D0 0014
0x01D0 0018
0x01D0 001C
0x01D0 001C
0x01D0 4000
0x01D0 4010
0x01D0 4014
0x01D0 4018
0x01D0 401C
0x01D0 401C
0x01D0 8000 REV
0x01D0 8010 PFUNC
0x01D0 8014 PDIR
0x01D0 8018 PDOUT
0x01D0 801C PDIN
0x01D0 801C PDSET
Revision identification register
Pin function register
10h
14h
18h
1Ch
1Ch
Pin direction register
Pin data output register
Read returns: Pin data input register
Writes affect: Pin data set register (alternate write
address: PDOUT)
20h
44h
48h
4Ch
50h
60h
0x01D0 0020
0x01D0 0044
0x01D0 0048
0x01D0 004C
0x01D0 0050
0x01D0 0060
0x01D0 4020
0x01D0 4044
0x01D0 4048
0x01D0 404C
0x01D0 4050
0x01D0 4060
0x01D0 8020 PDCLR
0x01D0 8044 GBLCTL
0x01D0 8048 AMUTE
0x01D0 804C DLBCTL
0x01D0 8050 DITCTL
0x01D0 8060 RGBLCTL
Pin data clear register (alternate write address: PDOUT)
Global control register
Audio mute control register
Digital loopback control register
DIT mode control register
Receiver global control register: Alias of GBLCTL, only
receive bits are affected - allows receiver to be reset
independently from transmitter
64h
68h
6Ch
70h
74h
0x01D0 0064
0x01D0 0068
0x01D0 006C
0x01D0 0070
0x01D0 0074
0x01D0 4064
0x01D0 4068
0x01D0 406C
0x01D0 4070
0x01D0 4074
0x01D0 8064 RMASK
0x01D0 8068 RFMT
Receive format unit bit mask register
Receive bit stream format register
Receive frame sync control register
Receive clock control register
0x01D0 806C AFSRCTL
0x01D0 8070 ACLKRCTL
0x01D0 8074 AHCLKRCTL
Receive high-frequency clock control register
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Table 6-39. McASP Registers Accessed Through Peripheral Configuration Port (continued)
Offset
McASP0
BYTE
McASP1
BYTE
McASP2
BYTE
Acronym
Register Description
ADDRESS
ADDRESS
ADDRESS
78h
7Ch
80h
84h
88h
8Ch
ACh
0x01D0 0078
0x01D0 007C
0x01D0 0080
0x01D0 0084
0x01D0 0088
0x01D0 008C
0x01D0 00A0
0x01D0 4078
0x01D0 407C
0x01D0 4080
0x01D0 4084
0x01D0 4088
0x01D0 408C
0x01D0 40A0
0x01D0 8078 RTDM
Receive TDM time slot 0-31 register
Receiver interrupt control register
Receiver status register
0x01D0 807C RINTCTL
0x01D0 8080 RSTAT
0x01D0 8084 RSLOT
0x01D0 8088 RCLKCHK
0x01D0 808C REVTCTL
0x01D0 80A0 XGBLCTL
Current receive TDM time slot register
Receive clock check control register
Receiver DMA event control register
Transmitter global control register. Alias of GBLCTL,
only transmit bits are affected - allows transmitter to be
reset independently from receiver
A4h
A8h
ACh
B0h
B4h
B8h
BCh
C0h
C4h
C8h
CCh
100h
0x01D0 00A4
0x01D0 00A8
0x01D0 40A4
0x01D0 40A8
0x01D0 80A4 XMASK
0x01D0 80A8 XFMT
Transmit format unit bit mask register
Transmit bit stream format register
Transmit frame sync control register
Transmit clock control register
0x01D0 00AC 0x01D0 40AC 0x01D0 80AC AFSXCTL
0x01D0 00B0
0x01D0 00B4
0x01D0 00B8
0x01D0 40B0
0x01D0 40B4
0x01D0 40B8
0x01D0 80B0 ACLKXCTL
0x01D0 80B4 AHCLKXCTL
0x01D0 80B8 XTDM
Transmit high-frequency clock control register
Transmit TDM time slot 0-31 register
Transmitter interrupt control register
Transmitter status register
0x01D0 00BC 0x01D0 40BC 0x01D0 80BC XINTCTL
0x01D0 00C0
0x01D0 00C4
0x01D0 00C8
0x01D0 40C0
0x01D0 40C4
0x01D0 40C8
0x01D0 80C0 XSTAT
0x01D0 80C4 XSLOT
0x01D0 80C8 XCLKCHK
Current transmit TDM time slot register
Transmit clock check control register
Transmitter DMA event control register
0x01D0 00CC 0x01D0 40CC 0x01D0 80CC XEVTCTL
0x01D0 0100
0x01D0 0104
0x01D0 0108
0x01D0 010C
0x01D0 0110
0x01D0 0114
0x01D0 0118
0x01D0 011C
0x01D0 0120
0x01D0 0124
0x01D0 0128
0x01D0 012C
0x01D0 0130
0x01D0 0134
0x01D0 0138
0x01D0 4100
0x01D0 4104
0x01D0 4108
0x01D0 410C
0x01D0 4110
0x01D0 4114
0x01D0 4118
0x01D0 411C
0x01D0 4120
0x01D0 4124
0x01D0 4128
0x01D0 412C
0x01D0 4130
0x01D0 4134
0x01D0 4138
0x01D0 8100 DITCSRA0
0x01D0 8104 DITCSRA1
0x01D0 8108 DITCSRA2
0x01D0 810C DITCSRA3
0x01D0 8110 DITCSRA4
0x01D0 8114 DITCSRA5
0x01D0 8118 DITCSRB0
0x01D0 811C DITCSRB1
0x01D0 8120 DITCSRB2
0x01D0 8124 DITCSRB3
0x01D0 8128 DITCSRB4
0x01D0 812C DITCSRB5
0x01D0 8130 DITUDRA0
0x01D0 8134 DITUDRA1
0x01D0 8138 DITUDRA2
Left (even TDM time slot) channel status register (DIT
mode) 0
104h
108h
10Ch
110h
114h
118h
11Ch
120h
124h
128h
12Ch
130h
134h
138h
Left (even TDM time slot) channel status register (DIT
mode) 1
Left (even TDM time slot) channel status register (DIT
mode) 2
Left (even TDM time slot) channel status register (DIT
mode) 3
Left (even TDM time slot) channel status register (DIT
mode) 4
Left (even TDM time slot) channel status register (DIT
mode) 5
Right (odd TDM time slot) channel status register (DIT
mode) 0
Right (odd TDM time slot) channel status register (DIT
mode) 1
Right (odd TDM time slot) channel status register (DIT
mode) 2
Right (odd TDM time slot) channel status register (DIT
mode) 3
Right (odd TDM time slot) channel status register (DIT
mode) 4
Right (odd TDM time slot) channel status register (DIT
mode) 5
Left (even TDM time slot) channel user data register
(DIT mode) 0
Left (even TDM time slot) channel user data register
(DIT mode) 1
Left (even TDM time slot) channel user data register
(DIT mode) 2
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Table 6-39. McASP Registers Accessed Through Peripheral Configuration Port (continued)
Offset
McASP0
BYTE
McASP1
BYTE
McASP2
BYTE
Acronym
Register Description
ADDRESS
ADDRESS
ADDRESS
13Ch
140h
144h
148h
14Ch
150h
154h
158h
15Ch
0x01D0 013C
0x01D0 0140
0x01D0 0144
0x01D0 0148
0x01D0 014C
0x01D0 0150
0x01D0 0154
0x01D0 0158
0x01D0 015C
0x01D0 413C
0x01D0 4140
0x01D0 4144
0x01D0 4148
0x01D0 414C
0x01D0 4150
0x01D0 4154
0x01D0 4158
0x01D0 415C
0x01D0 813C DITUDRA3
0x01D0 8140 DITUDRA4
0x01D0 8144 DITUDRA5
0x01D0 8148 DITUDRB0
0x01D0 814C DITUDRB1
0x01D0 8150 DITUDRB2
0x01D0 8154 DITUDRB3
0x01D0 8158 DITUDRB4
0x01D0 815C DITUDRB5
Left (even TDM time slot) channel user data register
(DIT mode) 3
Left (even TDM time slot) channel user data register
(DIT mode) 4
Left (even TDM time slot) channel user data register
(DIT mode) 5
Right (odd TDM time slot) channel user data register
(DIT mode) 0
Right (odd TDM time slot) channel user data register
(DIT mode) 1
Right (odd TDM time slot) channel user data register
(DIT mode) 2
Right (odd TDM time slot) channel user data register
(DIT mode) 3
Right (odd TDM time slot) channel user data register
(DIT mode) 4
Right (odd TDM time slot) channel user data register
(DIT mode) 5
180h
184h
188h
18Ch
190h
194h
198h
19Ch
1A0h
1A4h
1A8h
1ACh
1B0h
1B4h
1B8h
1BCh
200h
204h
208h
20Ch
210h
214h
218h
21Ch
220h
224h
228h
22Ch
230h
234h
0x01D0 0180
0x01D0 0184
0x01D0 0188
0x01D0 018C
0x01D0 0190
0x01D0 0194
0x01D0 0198
0x01D0 019C
0x01D0 01A0
0x01D0 01A4
0x01D0 01A8
0x01D0 4180
0x01D0 4184
0x01D0 4188
0x01D0 418C
0x01D0 4190
0x01D0 4194
0x01D0 4198
0x01D0 419C
0x01D0 41A0
0x01D0 41A4
0x01D0 41A8
0x01D0 8180 SRCTL0
0x01D0 8184 SRCTL1
0x01D0 8188 SRCTL2
0x01D0 818C SRCTL3
0x01D0 8190 SRCTL4
0x01D0 8194 SRCTL5
0x01D0 8198 SRCTL6
0x01D0 819C SRCTL7
0x01D0 81A0 SRCTL8
0x01D0 81A4 SRCTL9
0x01D0 81A8 SRCTL10
Serializer control register 0
Serializer control register 1
Serializer control register 2
Serializer control register 3
Serializer control register 4
Serializer control register 5
Serializer control register 6
Serializer control register 7
Serializer control register 8
Serializer control register 9
Serializer control register 10
0x01D0 01AC 0x01D0 41AC 0x01D0 81AC SRCTL11
Serializer control register 11
0x01D0 01B0
0x01D0 01B4
0x01D0 01B8
0x01D0 41B0
0x01D0 41B4
0x01D0 41B8
0x01D0 81B0 SRCTL12
0x01D0 81B4 SRCTL13
0x01D0 81B8 SRCTL14
Serializer control register 12
Serializer control register 13
Serializer control register 14
0x01D0 01BC 0x01D0 41BC 0x01D0 81BC SRCTL15
Serializer control register 15
0x01D0 0200
0x01D0 0204
0x01D0 0208
0x01D0 020C
0x01D0 0210
0x01D0 0214
0x01D0 0218
0x01D0 021C
0x01D0 0220
0x01D0 0224
0x01D0 0228
0x01D0 022C
0x01D0 0230
0x01D0 0234
0x01D0 4200
0x01D0 4204
0x01D0 4208
0x01D0 420C
0x01D0 4210
0x01D0 4214
0x01D0 4218
0x01D0 421C
0x01D0 4220
0x01D0 4224
0x01D0 4228
0x01D0 422C
0x01D0 4230
0x01D0 4234
0x01D0 8200 XBUF0(1)
0x01D0 8204 XBUF1(1)
0x01D0 8208 XBUF2(1)
0x01D0 820C XBUF3(1)
0x01D0 8210 XBUF4(1)
0x01D0 8214 XBUF5(1)
0x01D0 8218 XBUF6(1)
0x01D0 821C XBUF7(1)
0x01D0 8220 XBUF8(1)
0x01D0 8224 XBUF9(1)
0x01D0 8228 XBUF10(1)
0x01D0 822C XBUF11(1)
0x01D0 8230 XBUF12(1)
0x01D0 8234 XBUF13(1)
Transmit buffer register for serializer 0
Transmit buffer register for serializer 1
Transmit buffer register for serializer 2
Transmit buffer register for serializer 3
Transmit buffer register for serializer 4
Transmit buffer register for serializer 5
Transmit buffer register for serializer 6
Transmit buffer register for serializer 7
Transmit buffer register for serializer 8
Transmit buffer register for serializer 9
Transmit buffer register for serializer 10
Transmit buffer register for serializer 11
Transmit buffer register for serializer 12
Transmit buffer register for serializer 13
(1) Writes to XRBUF originate from peripheral configuration port only when XBUSEL = 1 in XFMT.
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Table 6-39. McASP Registers Accessed Through Peripheral Configuration Port (continued)
Offset
McASP0
BYTE
McASP1
BYTE
McASP2
BYTE
Acronym
Register Description
ADDRESS
ADDRESS
ADDRESS
238h
23Ch
280h
284h
288h
28Ch
290h
294h
298h
29Ch
2A0h
2A4h
2A8h
2ACh
2B0h
2B4h
2B8h
2BCh
0x01D0 0238
0x01D0 023C
0x01D0 0280
0x01D0 0284
0x01D0 0288
0x01D0 028C
0x01D0 0290
0x01D0 0294
0x01D0 0298
0x01D0 029C
0x01D0 02A0
0x01D0 02A4
0x01D0 02A8
0x01D0 4238
0x01D0 423C
0x01D0 4280
0x01D0 4284
0x01D0 4288
0x01D0 428C
0x01D0 4290
0x01D0 4294
0x01D0 4298
0x01D0 429C
0x01D0 42A0
0x01D0 42A4
0x01D0 42A8
0x01D0 8238 XBUF14(1)
0x01D0 823C XBUF15(1)
0x01D0 8280 RBUF0(2)
0x01D0 8284 RBUF1(2)
0x01D0 8288 RBUF2(2)
0x01D0 828C RBUF3(2)
0x01D0 8290 RBUF4(2)
0x01D0 8294 RBUF5(2)
0x01D0 8298 RBUF6(2)
0x01D0 829C RBUF7(2)
0x01D0 82A0 RBUF8(2)
0x01D0 82A4 RBUF9(2)
0x01D0 82A8 RBUF10(2)
Transmit buffer register for serializer 14
Transmit buffer register for serializer 15
Receive buffer register for serializer 0
Receive buffer register for serializer 1
Receive buffer register for serializer 2
Receive buffer register for serializer 3
Receive buffer register for serializer 4
Receive buffer register for serializer 5
Receive buffer register for serializer 6
Receive buffer register for serializer 7
Receive buffer register for serializer 8
Receive buffer register for serializer 9
Receive buffer register for serializer 10
Receive buffer register for serializer 11
Receive buffer register for serializer 12
Receive buffer register for serializer 13
Receive buffer register for serializer 14
Receive buffer register for serializer 15
0x01D0 02AC 0x01D0 42AC 0x01D0 82AC RBUF11(2)
0x01D0 02B0
0x01D0 02B4
0x01D0 02B8
0x01D0 42B0
0x01D0 42B4
0x01D0 42B8 0x01D0 82BB RBUF14(2)
0x01D0 82B0 RBUF12(2)
0x01D0 82B4 RBUF13(2)
0x01D0 02BC 0x01D0 42BC 0x01D0 82BC RBUF15(2)
(2) Reads from XRBUF originate on peripheral configuration port only when RBUSEL = 1 in RFMT.
Table 6-40. McASP Registers Accessed Through DMA Port
Hex Address
Register Name
Register Description
Read Accesses
RBUF
Receive buffer DMA port address. Cycles through receive serializers, skipping over transmit
serializers and inactive serializers. Starts at the lowest serializer at the beginning of each time slot.
Reads from DMA port only if XBUSEL = 0 in XFMT.
Write Accesses
XBUF
Transmit buffer DMA port address. Cycles through transmit serializers, skipping over receive and
inactive serializers. Starts at the lowest serializer at the beginning of each time slot. Writes to DMA
port only if RBUSEL = 0 in RFMT.
Table 6-41. McASP AFIFO Registers Accessed Through Peripheral Configuration Port
McASP0
McASP0
McASP0
Acronym
Register Description
BYTE ADDRESS
BYTE ADDRESS
BYTE ADDRESS
0x01D0 1000
0x01D0 1010
0x01D0 1014
0x01D0 1018
0x01D0 101C
0x01D0 5000
0x01D0 5010
0x01D0 5014
0x01D0 5018
0x01D0 501C
0x01D0 9000
0x01D0 9010
0x01D0 9014
0x01D0 9018
0x01D0 901C
AFIFOREV
WFIFOCTL
WFIFOSTS
RFIFOCTL
RFIFOSTS
AFIFO revision identification register
Write FIFO control register
Write FIFO status register
Read FIFO control register
Read FIFO status register
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6.15.2 McASP Electrical Data/Timing
6.15.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
Table 6-42 and Table 6-43 assume testing over recommended operating conditions (see Figure 6-33 and
Figure 6-34).
Table 6-42. McASP0 Timing Requirements(1)(2)
NO.
MIN
MAX UNIT
Cycle time, AHCLKR0 external, AHCLKR0 input
Cycle time, AHCLKX0 external, AHCLKX0 input
Pulse duration, AHCLKR0 external, AHCLKR0 input
Pulse duration, AHCLKX0 external, AHCLKX0 input
Cycle time, ACLKR0 external, ACLKR0 input
20
1
tc(AHCLKRX)
tw(AHCLKRX)
tc(ACLKRX)
tw(ACLKRX)
ns
20
10
2
3
4
ns
ns
ns
10
greater of 2P or 20
Cycle time, ACLKX0 external, ACLKX0 input
greater of 2P or 20
Pulse duration, ACLKR0 external, ACLKR0 input
Pulse duration, ACLKX0 external, ACLKX0 input
Setup time, AFSR0 input to ACLKR0 internal(3)
Setup time, AFSR0 input to ACLKX0 internal(4)
Setup time, AFSX0 input to ACLKX0 internal
10
10
9.4
9.4
9.4
2.9
2.9
2.9
2.9
2.9
2.9
-2.1
-2.1
-2.1
0.4
0.4
0.4
Setup time, AFSR0 input to ACLKR0 external input(3)
Setup time, AFSR0 input to ACLKX0 external input(4)
Setup time, AFSX0 input to ACLKX0 external input
Setup time, AFSR0 input to ACLKR0 external output(3)
Setup time, AFSR0 input to ACLKX0 external output(4)
Setup time, AFSX0 input to ACLKX0 external output
Hold time, AFSR0 input after ACLKR0 internal(3)
Hold time, AFSR0 input after ACLKX0 internal(4)
Hold time, AFSX0 input after ACLKX0 internal
Hold time, AFSR0 input after ACLKR0 external input(3)
Hold time, AFSR0 input after ACLKX0 external input(4)
Hold time, AFSX0 input after ACLKX0 external input
5
tsu(AFSRX-ACLKRX)
ns
6
th(ACLKRX-AFSRX)
ns
Hold time, AFSR0 input after ACLKR0 external
output(3)
0.4
0.4
Hold time, AFSR0 input after ACLKX0 external
output(4)
Hold time, AFSX0 input after ACLKX0 external output
Setup time, AXR0[n] input to ACLKR0 internal(3)
Setup time, AXR0[n] input to ACLKX0 internal(4)
Setup time, AXR0[n] input to ACLKR0 external input(3)
Setup time, AXR0[n] input to ACLKX0 external input(4)
0.4
9.4
9.4
2.9
2.9
7
tsu(AXR-ACLKRX)
ns
Setup time, AXR0[n] input to ACLKR0 external
output(3)
2.9
2.9
Setup time, AXR0[n] input to ACLKX0 external
output(4)
(1) ACLKX0 internal – McASP0 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) P = SYSCLK2 period
(3) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
(4) McASP0 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX0
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Table 6-42. McASP0 Timing Requirements (continued)
NO.
MIN
-2.1
-2.1
MAX UNIT
Hold time, AXR0[n] input after ACLKR0 internal(3)
Hold time, AXR0[n] input after ACLKX0 internal(4)
Hold time, AXR0[n] input after ACLKR0 external
input(3)
0.4
0.4
0.4
0.4
Hold time, AXR0[n] input after ACLKX0 external
input(4)
8
th(ACLKRX-AXR)
ns
Hold time, AXR0[n] input after ACLKR0 external
output(3)
Hold time, AXR0[n] input after ACLKX0 external
output(4)
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Table 6-43. McASP0 Switching Characteristics(1)
NO.
PARAMETER
MIN
20
MAX
UNIT
Cycle time, AHCLKX0 internal, AHCLKR0 output
Cycle time, AHCLKR0 external, AHCLKR0 output
Cycle time, AHCLKX0 internal, AHCLKX0 output
Cycle time, AHCLKX0 external, AHCLKX0 output
20
9
tc(AHCLKRX)
ns
20
20
Pulse duration, AHCLKR0 internal, AHCLKR0
output
(AHR/2) – 2.5(2)
(AHR/2) – 2.5(2)
(AHX/2) – 2.5(3)
(AHX/2) – 2.5(3)
Pulse duration, AHCLKR0 external, AHCLKR0
output
10
tw(AHCLKRX)
ns
Pulse duration, AHCLKX0 internal, AHCLKX0
output
Pulse duration, AHCLKX0 external, AHCLKX0
output
Cycle time, ACLKR0 internal, ACLKR0 output
Cycle time, ACLKR0 external, ACLKR0 output
Cycle time, ACLKX0 internal, ACLKX0 output
Cycle time, ACLKX0 external, ACLKX0 output
Pulse duration, ACLKR0 internal, ACLKR0 output
Pulse duration, ACLKR0 external, ACLKR0 output
Pulse duration, ACLKX0 internal, ACLKX0 output
Pulse duration, ACLKX0 external, ACLKX0 output
Delay time, ACLKR0 internal, AFSR output(7)
Delay time, ACLKX0 internal, AFSR output(8)
Delay time, ACLKX0 internal, AFSX output
greater of 2P or 20 ns(4)
greater of 2P or 20 ns(4)
greater of 2P or 20 ns(4)
greater of 2P or 20 ns(4)
11
12
tc(ACLKRX)
ns
ns
(AR/2) – 2.5(5)
(AR/2) – 2.5(5)
(AX/2) – 2.5(6)
(AX/2) – 2.5(6)
tw(ACLKRX)
0
0
0
3
3
3
5.8
5.8
5.8
Delay time, ACLKR0 external input, AFSR output(7)
Delay time, ACLKX0 external input, AFSR output(8)
Delay time, ACLKX0 external input, AFSX output
11.6
11.6
11.6
13
td(ACLKRX-AFSRX)
ns
Delay time, ACLKR0 external output, AFSR
output(7)
3
3
11.6
11.6
Delay time, ACLKX0 external output, AFSR
output(8)
Delay time, ACLKX0 external output, AFSX output
Delay time, ACLKX0 internal, AXR0[n] output
Delay time, ACLKX0 external input, AXR0[n] output
3
0
3
11.6
5.8
11.6
14
15
td(ACLKX-AXRV)
ns
ns
Delay time, ACLKX0 external output, AXR0[n]
output
3
0
3
11.6
5.8
Disable time, ACLKX0 internal, AXR0[n] output
Disable time, ACLKX0 external input, AXR0[n]
output
11.6
tdis(ACLKX-AXRHZ)
Disable time, ACLKX0 external output, AXR0[n]
output
3
11.6
(1) McASP0 ACLKX0 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKR0CTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) AHR - Cycle time, AHCLKR0.
(3) AHX - Cycle time, AHCLKX0.
(4) P = SYSCLK2 period
(5) AR - ACLKR0 period.
(6) AX - ACLKX0 period.
(7) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
(8) McASP0 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX0
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6.15.2.2 Multichannel Audio Serial Port 1 (McASP1) Timing
Table 6-44 and Table 6-45 assume testing over recommended operating conditions (see Figure 6-33 and
Figure 6-34).
Table 6-44. McASP1 Timing Requirements(1)(2)
NO.
MIN
MAX UNIT
Cycle time, AHCLKR1 external, AHCLKR1 input
Cycle time, AHCLKX1 external, AHCLKX1 input
Pulse duration, AHCLKR1 external, AHCLKR1 input
Pulse duration, AHCLKX1 external, AHCLKX1 input
Cycle time, ACLKR1 external, ACLKR1 input
20
1
tc(AHCLKRX)
tw(AHCLKRX)
tc(ACLKRX)
tw(ACLKRX)
ns
20
10
2
3
4
ns
ns
ns
10
greater of 2P or 20
Cycle time, ACLKX1 external, ACLKX1 input
greater of 2P or 20
Pulse duration, ACLKR1 external, ACLKR1 input
Pulse duration, ACLKX1 external, ACLKX1 input
Setup time, AFSR1 input to ACLKR1 internal(3)
Setup time, AFSR1 input to ACLKX1 internal(4)
Setup time, AFSX1 input to ACLKX1 internal
10
10
10.4
10.4
10.4
2.6
Setup time, AFSR1 input to ACLKR1 external input(3)
Setup time, AFSR1 input to ACLKX1 external input(4)
Setup time, AFSX1 input to ACLKX1 external input
Setup time, AFSR1 input to ACLKR1 external output(3)
Setup time, AFSR1 input to ACLKX1 external output(4)
Setup time, AFSX1 input to ACLKX1 external output
Hold time, AFSR1 input after ACLKR1 internal(3)
Hold time, AFSR1 input after ACLKX1 internal(4)
Hold time, AFSX1 input after ACLKX1 internal
Hold time, AFSR1 input after ACLKR1 external input(3)
Hold time, AFSR1 input after ACLKX1 external input(4)
Hold time, AFSX1 input after ACLKX1 external input
5
tsu(AFSRX-ACLKRX)
2.6
ns
2.6
2.6
2.6
2.6
-2.6
-2.6
-2.6
0.3
0.3
6
th(ACLKRX-AFSRX)
ns
0.3
Hold time, AFSR1 input after ACLKR1 external
output(3)
0.3
0.3
Hold time, AFSR1 input after ACLKX1 external
output(4)
Hold time, AFSX1 input after ACLKX1 external output
Setup time, AXR1[n] input to ACLKR1 internal(3)
Setup time, AXR1[n] input to ACLKX1 internal(4)
Setup time, AXR1[n] input to ACLKR1 external input(3)
Setup time, AXR1[n] input to ACLKX1 external input(4)
0.3
10.4
10.4
2.6
2.6
7
tsu(AXR-ACLKRX)
ns
Setup time, AXR1[n] input to ACLKR1 external
output(3)
2.6
2.6
Setup time, AXR1[n] input to ACLKX1 external
output(4)
(1) ACLKX1 internal – McASP1 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX1 external input – McASP1 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX1 external output – McASP1 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR1 internal – McASP1 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR1 external input – McASP1 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR1 external output – McASP1 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) P = SYSCLK2 period
(3) McASP1 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR1
(4) McASP1 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX1
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Table 6-44. McASP1 Timing Requirements (continued)
NO.
MIN
-2.6
-2.6
MAX UNIT
Hold time, AXR1[n] input after ACLKR1 internal(3)
Hold time, AXR1[n] input after ACLKX1 internal(4)
Hold time, AXR1[n] input after ACLKR1 external
input(3)
0.3
0.3
0.3
0.3
Hold time, AXR1[n] input after ACLKX1 external
input(4)
8
th(ACLKRX-AXR)
ns
Hold time, AXR1[n] input after ACLKR1 external
output(3)
Hold time, AXR1[n] input after ACLKX1 external
output(4)
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Table 6-45. McASP1 Switching Characteristics(1)
NO.
PARAMETER
MIN
20
MAX
UNIT
Cycle time, AHCLKX1 internal, AHCLKR1 output
Cycle time, AHCLKR1 external, AHCLKR1 output
Cycle time, AHCLKX1 internal, AHCLKX1 output
Cycle time, AHCLKX1 external, AHCLKX1 output
20
9
tc(AHCLKRX)
ns
20
20
Pulse duration, AHCLKR1 internal, AHCLKR1
output
(AHR/2) – 2.5(2)
(AHR/2) – 2.5(2)
(AHX/2) – 2.5(3)
(AHX/2) – 2.5(3)
Pulse duration, AHCLKR1 external, AHCLKR1
output
10
tw(AHCLKRX)
ns
Pulse duration, AHCLKX1 internal, AHCLKX1
output
Pulse duration, AHCLKX1 external, AHCLKX1
output
Cycle time, ACLKR1 internal, ACLKR1 output
Cycle time, ACLKR1 external, ACLKR1 output
Cycle time, ACLKX1 internal, ACLKX1 output
Cycle time, ACLKX1 external, ACLKX1 output
Pulse duration, ACLKR1 internal, ACLKR1 output
Pulse duration, ACLKR1 external, ACLKR1 output
Pulse duration, ACLKX1 internal, ACLKX1 output
Pulse duration, ACLKX1 external, ACLKX1 output
Delay time, ACLKR1 internal, AFSR output(7)
Delay time, ACLKX1 internal, AFSR output(8)
Delay time, ACLKX1 internal, AFSX output
greater of 2P or 20 ns(4)
greater of 2P or 20 ns(4)
greater of 2P or 20 ns(4)
greater of 2P or 20 ns(4)
11
12
tc(ACLKRX)
ns
ns
(AR/2) – 2.5(5)
(AR/2) – 2.5(5)
(AX/2) – 2.5(6)
(AX/2) – 2.5(6)
tw(ACLKRX)
0.5
0.5
0.5
3.9
3.9
3.9
6.7
6.7
6.7
Delay time, ACLKR1 external input, AFSR output(7)
Delay time, ACLKX1 external input, AFSR output(8)
Delay time, ACLKX1 external input, AFSX output
13.8
13.8
13.8
13
td(ACLKRX-AFSRX)
ns
Delay time, ACLKR1 external output, AFSR
output(7)
3.9
3.9
13.8
13.8
Delay time, ACLKX1 external output, AFSR
output(8)
Delay time, ACLKX1 external output, AFSX output
Delay time, ACLKX1 internal, AXR1[n] output
Delay time, ACLKX1 external input, AXR1[n] output
3.9
0.5
3.9
13.8
6.7
13.8
14
15
td(ACLKX-AXRV)
ns
ns
Delay time, ACLKX1 external output, AXR1[n]
output
3.9
0.5
3.9
13.8
6.7
Disable time, ACLKX1 internal, AXR1[n] output
Disable time, ACLKX1 external input, AXR1[n]
output
13.8
tdis(ACLKX-AXRHZ)
Disable time, ACLKX1 external output, AXR1[n]
output
3.9
13.8
(1) McASP1 ACLKX1 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
McASP1 ACLKX1 external input – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
McASP1 ACLKX1 external output – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
McASP1 ACLKR1 internal – ACLKR1CTL.CLKRM = 1, PDIR.ACLKR =1
McASP1 ACLKR1 external input – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
McASP1 ACLKR1 external output – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) AHR - Cycle time, AHCLKR1.
(3) AHX - Cycle time, AHCLKX1.
(4) P = SYSCLK2 period
(5) AR - ACLKR1 period.
(6) AX - ACLKX1 period.
(7) McASP1 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR1
(8) McASP1 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX1
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6.15.2.3 Multichannel Audio Serial Port 2 (McASP2) Timing
Table 6-46 and Table 6-47 assume testing over recommended operating conditions (see Figure 6-33 and
Figure 6-34).
Table 6-46. McASP2 Timing Requirements(1)(2)
NO.
MIN
MAX UNIT
Cycle time, AHCLKR2 external, AHCLKR2 input
Cycle time, AHCLKX2 external, AHCLKX2 input
Pulse duration, AHCLKR2 external, AHCLKR2 input
Pulse duration, AHCLKX2 external, AHCLKX2 input
Cycle time, ACLKR2 external, ACLKR2 input
13
1
tc(AHCLKRX)
tw(AHCLKRX)
tc(ACLKRX)
tw(ACLKRX)
ns
13
6.5
2
3
4
ns
ns
ns
6.5
greater of 2P or 13
Cycle time, ACLKX2 external, ACLKX2 input
greater of 2P or 13
Pulse duration, ACLKR2 external, ACLKR2 input
Pulse duration, ACLKX2 external, ACLKX2 input
Setup time, AFSR2 input to ACLKR2 internal(3)
Setup time, AFSR2 input to ACLKX2 internal(4)
Setup time, AFSX2 input to ACLKX2 internal
6.5
6.5
10
10
10
Setup time, AFSR2 input to ACLKR2 external input(3)
Setup time, AFSR2 input to ACLKX2 external input(4)
Setup time, AFSX2 input to ACLKX2 external input
Setup time, AFSR2 input to ACLKR2 external output(3)
Setup time, AFSR2 input to ACLKX2 external output(4)
Setup time, AFSX2 input to ACLKX2 external output
Hold time, AFSR2 input after ACLKR2 internal(3)
Hold time, AFSR2 input after ACLKX2 internal(4)
Hold time, AFSX2 input after ACLKX2 internal
Hold time, AFSR2 input after ACLKR2 external input(3)
Hold time, AFSR2 input after ACLKX2 external input(4)
Hold time, AFSX2 input after ACLKX2 external input
1.6
1.6
1.6
1.6
1.6
1.6
-2.2
-2.2
-2.2
1.3
1.3
1.3
5
tsu(AFSRX-ACLKRX)
ns
6
th(ACLKRX-AFSRX)
ns
Hold time, AFSR2 input after ACLKR2 external
output(3)
1.3
1.3
Hold time, AFSR2 input after ACLKX2 external
output(4)
Hold time, AFSX2 input after ACLKX2 external output
Setup time, AXR2[n] input to ACLKR2 internal(3)
Setup time, AXR2[n] input to ACLKX2 internal(4)
Setup time, AXR2[n] input to ACLKR2 external input(3)
Setup time, AXR2[n] input to ACLKX2 external input(4)
1.3
10
10
1.6
1.6
7
tsu(AXR-ACLKRX)
ns
Setup time, AXR2[n] input to ACLKR2 external
output(3)
1.6
1.6
Setup time, AXR2[n] input to ACLKX2 external
output(4)
(1) ACLKX2 internal – McASP2 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX2 external input – McASP2 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX2 external output – McASP2 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR2 internal – McASP2 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR2 external input – McASP2 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR2 external output – McASP2 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) P = SYSCLK2 period
(3) McASP2 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR2
(4) McASP2 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX2
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Table 6-46. McASP2 Timing Requirements (continued)
NO.
MIN
-2.2
-2.2
MAX UNIT
Hold time, AXR2[n] input after ACLKR2 internal(3)
Hold time, AXR2[n] input after ACLKX2 internal(4)
Hold time, AXR2[n] input after ACLKR2 external
input(3)
1.3
1.3
1.3
1.3
Hold time, AXR2[n] input after ACLKX2 external
input(4)
8
th(ACLKRX-AXR)
ns
Hold time, AXR2[n] input after ACLKR2 external
output(3)
Hold time, AXR2[n] input after ACLKX2 external
output(4)
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Table 6-47. McASP2 Switching Characteristics(1)
NO.
PARAMETER
MIN
13
MAX
UNIT
Cycle time, AHCLKX2 internal, AHCLKR2 output
Cycle time, AHCLKR2 external, AHCLKR2 output
Cycle time, AHCLKX2 internal, AHCLKX2 output
Cycle time, AHCLKX2 external, AHCLKX2 output
13
9
tc(AHCLKRX)
ns
13
13
Pulse duration, AHCLKR2 internal, AHCLKR2
output
(AHR/2) – 2.5(2)
(AHR/2) – 2.5(2)
(AHX/2) – 2.5(3)
(AHX/2) – 2.5(3)
Pulse duration, AHCLKR2 external, AHCLKR2
output
10
tw(AHCLKRX)
ns
Pulse duration, AHCLKX2 internal, AHCLKX2
output
Pulse duration, AHCLKX2 external, AHCLKX2
output
Cycle time, ACLKR2 internal, ACLKR2 output
Cycle time, ACLKR2 external, ACLKR2 output
Cycle time, ACLKX2 internal, ACLKX2 output
Cycle time, ACLKX2 external, ACLKX2 output
Pulse duration, ACLKR2 internal, ACLKR2 output
Pulse duration, ACLKR2 external, ACLKR2 output
Pulse duration, ACLKX2 internal, ACLKX2 output
Pulse duration, ACLKX2 external, ACLKX2 output
Delay time, ACLKR2 internal, AFSR output(7)
Delay time, ACLKX2 internal, AFSR output(8)
Delay time, ACLKX2 internal, AFSX output
greater of 2P or 13 ns(4)
greater of 2P or 13 ns(4)
greater of 2P or 13 ns(4)
greater of 2P or 13 ns(4)
11
12
tc(ACLKRX)
ns
ns
(AR/2) – 2.5(5)
(AR/2) – 2.5(5)
(AX/2) – 2.5(6)
(AX/2) – 2.5(6)
tw(ACLKRX)
-1.4
-1.4
-1.4
2.9
2.8
2.8
2.8
10
Delay time, ACLKR2 external input, AFSR output(7)
Delay time, ACLKX2 external input, AFSR output(8)
Delay time, ACLKX2 external input, AFSX output
2.9
10
13
td(ACLKRX-AFSRX)
ns
2.9
10
Delay time, ACLKR2 external output, AFSR
output(7)
2.9
2.9
10
10
Delay time, ACLKX2 external output, AFSR
output(8)
Delay time, ACLKX2 external output, AFSX output
Delay time, ACLKX2 internal, AXR2[n] output
Delay time, ACLKX2 external input, AXR2[n] output
2.9
-1.4
2.9
10
2.8
10
14
15
td(ACLKX-AXRV)
ns
ns
Delay time, ACLKX2 external output, AXR2[n]
output
2.9
-1.4
2.9
10
2.8
10
Disable time, ACLKX2 internal, AXR2[n] output
Disable time, ACLKX2 external input, AXR2[n]
output
tdis(ACLKX-AXRHZ)
Disable time, ACLKX2 external output, AXR2[n]
output
2.9
10
(1) McASP2 ACLKX2 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
McASP2 ACLKX2 external input – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
McASP2 ACLKX2 external output – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
McASP2 ACLKR2 internal – ACLKR2CTL.CLKRM = 1, PDIR.ACLKR =1
McASP2 ACLKR2 external input – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
McASP2 ACLKR2 external output – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) AHR - Cycle time, AHCLKR2.
(3) AHX - Cycle time, AHCLKX2.
(4) P = SYSCLK2 period
(5) AR - ACLKR2 period.
(6) AX - ACLKX2 period.
(7) McASP2 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR2
(8) McASP2 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX2
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2
1
2
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
4
3
4
(A)
ACLKR/X (CLKRP = CLKXP = 0)
(B)
ACLKR/X (CLKRP = CLKXP = 1)
6
5
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
8
7
AXR[n] (Data In/Receive)
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
Figure 6-33. McASP Input Timings
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10
10
9
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
12
11
12
(A)
ACLKR/X (CLKRP = CLKXP = 1)
(B)
ACLKR/X (CLKRP = CLKXP = 0)
13
13
13
13
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
AXR[n] (Data Out/Transmit)
13
13
13
14
15
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
Figure 6-34. McASP Output Timings
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6.16 Serial Peripheral Interface Ports (SPI0, SPI1)
Figure 6-35 is a block diagram of the SPI module, which is a simple shift register and buffer plus control
logic. Data is written to the shift register before transmission occurs and is read from the buffer at the end
of transmission. The SPI can operate either as a master, in which case, it initiates a transfer and drives
the SPIx_CLK pin, or as a slave. Four clock phase and polarity options are supported as well as many
data formatting options.
SPIx_SIMO
SPIx_SOMI
Peripheral
Configuration Bus
16-Bit Shift Register
16-Bit Buffer
SPIx_ENA
SPIx_SCS
SPIx_CLK
State
Machine
GPIO
Control
(all pins)
Interrupt and
DMA Requests
Clock
Control
Figure 6-35. Block Diagram of SPI Module
The SPI supports 3-, 4-, and 5-pin operation with three basic pins (SPIx_CLK, SPIx_SIMO, and
SPIx_SOMI) and two optional pins (SPIx_SCS, SPIx_ENA).
The optional SPIx_SCS (Slave Chip Select) pin is most useful to enable in slave mode when there are
other slave devices on the same SPI port. The OMAP-L137 will only shift data and drive the SPIx_SOMI
pin when SPIx_SCS is held low.
In slave mode, SPIx_ENA is an optional output and can be driven in either a push-pull or open-drain
manner. The SPIx_ENA output provides the status of the internal transmit buffer (SPIDAT0/1 registers). In
four-pin mode with the enable option, SPIx_ENA is asserted only when the transmit buffer is full, indicating
that the slave is ready to begin another transfer. In five-pin mode, the SPIx_ENA is additionally qualified
by SPIx_SCS being asserted. This allows a single handshake line to be shared by multiple slaves on the
same SPI bus.
In master mode, the SPIx_ENA pin is an optional input and the master can be configured to delay the start
of the next transfer until the slave asserts SPIx_ENA. The addition of this handshake signal simplifies SPI
communications and, on average, increases SPI bus throughput since the master does not need to delay
each transfer long enough to allow for the worst-case latency of the slave device. Instead, each transfer
can begin as soon as both the master and slave have actually serviced the previous SPI transfer.
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Optional − Slave Chip Select
SPIx_SCS
SPIx_ENA
SPIx_CLK
SPIx_SOMI
SPIx_SIMO
SPIx_SCS
SPIx_ENA
SPIx_CLK
SPIx_SOMI
SPIx_SIMO
Optional Enable (Ready)
MASTER SPI
SLAVE SPI
Figure 6-36. Illustration of SPI Master-to-SPI Slave Connection
6.16.1 SPI Peripheral Registers Description(s)
Table 6-48 is a list of the SPI registers.
Table 6-48. SPIx Configuration Registers
SPI0
BYTE ADDRESS
SPI1
REGISTER NAME
DESCRIPTION
BYTE ADDRESS
0x01E1 2000
0x01E1 2004
0x01E1 2008
0x01E1 200C
0x01E1 2010
0x01E1 2014
0x01E1 2018
0x01E1 201C
0x01E1 2020
0x01E1 2024
0x01E1 2028
0x01E1 202C
0x01E1 2030
0x01E1 2034
0x01E1 2038
0x01E1 203C
0x01E1 2040
0x01E1 2044
0x01C4 1000
0x01C4 1004
0x01C4 1008
0x01C4 100C
0x01C4 1010
0x01C4 1014
0x01C4 1018
0x01C4 101C
0x01C4 1020
0x01C4 1024
0x01C4 1028
0x01C4 102C
0x01C4 1030
0x01C4 1034
0x01C4 1038
0x01C4 103C
0x01C4 1040
0x01C4 1044
SPIGCR0
SPIGCR1
SPIINT0
SPILVL
Global Control Register 0
Global Control Register 1
Interrupt Register
Interrupt Level Register
SPIFLG
SPIPC0
SPIPC1
SPIPC2
SPIPC3
SPIPC4
SPIPC5
Reserved
Reserved
Reserved
SPIDAT0
SPIDAT1
SPIBUF
SPIEMU
Flag Register
Pin Control Register 0 (Pin Function)
Pin Control Register 1 (Pin Direction)
Pin Control Register 2 (Pin Data In)
Pin Control Register 3 (Pin Data Out)
Pin Control Register 4 (Pin Data Set)
Pin Control Register 5 (Pin Data Clear)
Reserved - Do not write to this register
Reserved - Do not write to this register
Reserved - Do not write to this register
Shift Register 0 (without format select)
Shift Register 1 (with format select)
Buffer Register
Emulation Register
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Table 6-48. SPIx Configuration Registers (continued)
SPI0
BYTE ADDRESS
SPI1
REGISTER NAME
DESCRIPTION
BYTE ADDRESS
0x01E1 2048
0x01E1 204C
0x01E1 2050
0x01E1 2054
0x01E1 2058
0x01E1 205C
0x01E1 2060
0x01E1 2064
0x01C4 1048
0x01C4 104C
0x01C4 1050
0x01C4 1054
0x01C4 1058
0x01C4 105C
0x01C4 1060
0x01C4 1064
SPIDELAY
SPIDEF
Delay Register
Default Chip Select Register
Format Register 0
SPIFMT0
SPIFMT1
SPIFMT2
SPIFMT3
INTVEC0
INTVEC1
Format Register 1
Format Register 2
Format Register 3
Interrupt Vector for SPI INT0
Interrupt Vector for SPI INT1
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6.16.2 SPI Electrical Data/Timing
6.16.2.1 Serial Peripheral Interface (SPI) Timing
Table 6-49 through Table 6-64 assume testing over recommended operating conditions (see Figure 6-37
through Figure 6-40).
Table 6-49. General Timing Requirements for SPI0 Master Modes(1)
NO.
1
MIN
greater of 2P or 20 ns
0.5tc(SPC)M - 1
MAX UNIT
tc(SPC)M
Cycle Time, SPI0_CLK, All Master Modes
Pulse Width High, SPI0_CLK, All Master Modes
Pulse Width Low, SPI0_CLK, All Master Modes
256P ns
2
tw(SPCH)M
tw(SPCL)M
ns
ns
3
0.5tc(SPC)M - 1
Polarity = 0, Phase = 0,
to SPI0_CLK rising
5
0.5tc(SPC)M - 5
5
Polarity = 0, Phase = 1,
Delay, initial data bit valid
to SPI0_CLK rising
4,5 td(SIMO_SPC)M
on SPI0_SIMO to initial
ns
edge on SPI0_CLK(2)
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5tc(SPC)M - 5
Polarity = 0, Phase = 0,
from SPI0_CLK rising
5
Polarity = 0, Phase = 1,
5
Delay, subsequent bits
from SPI0_CLK falling
5
6
7
8
td(SPC_SIMO)M
toh(SPC_SIMO)M
tsu(SOMI_SPC)M
tih(SPC_SOMI)M
valid on SPI0_SIMO after
ns
5
Polarity = 1, Phase = 0,
from SPI0_CLK falling
transmit edge of SPI0_CLK
Polarity = 1, Phase = 1,
from SPI0_CLK rising
5
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M -3
Polarity = 0, Phase = 1,
from SPI0_CLK rising
0.5tc(SPC)M -3
Output hold time,
SPI0_SIMO valid after
receive edge of SPI0_CLK
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5tc(SPC)M -3
Polarity = 1, Phase = 1,
from SPI0_CLK falling
0.5tc(SPC)M -3
Polarity = 0, Phase = 0,
to SPI0_CLK falling
0
0
0
0
5
5
5
5
Polarity = 0, Phase = 1,
Input Setup Time,
to SPI0_CLK rising
SPI0_SOMI valid before
receive edge of SPI0_CLK
ns
Polarity = 1, Phase = 0,
to SPI0_CLK rising
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
from SPI0_CLK rising
Input Hold Time,
SPI0_SOMI valid after
receive edge of SPI0_CLK
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
(1) P = SYSCLK2 period
(2) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on
SPI0_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI0_SOMI.
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Table 6-50. General Timing Requirements for SPI0 Slave Modes(1)
NO.
MIN
MAX UNIT
greater of 2P or
20 ns
9
tc(SPC)S
Cycle Time, SPI0_CLK, All Slave Modes
256P ns
10 tw(SPCH)S
11 tw(SPCL)S
Pulse Width High, SPI0_CLK, All Slave Modes
Pulse Width Low, SPI0_CLK, All Slave Modes
10
10
ns
ns
Polarity = 0, Phase = 0,
to SPI0_CLK rising
2P
2P
2P
2P
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Setup time, transmit data
written to SPI before initial
clock edge from
12 tsu(SOMI_SPC)S
13 td(SPC_SOMI)S
14 toh(SPC_SOMI)S
15 tsu(SIMO_SPC)S
ns
Polarity = 1, Phase = 0,
to SPI0_CLK falling
master.(2)(3)
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
from SPI0_CLK rising
9
Polarity = 0, Phase = 1,
from SPI0_CLK falling
9
Delay, subsequent bits
valid on SPI0_SOMI after
transmit edge of SPI0_CLK
ns
9
Polarity = 1, Phase = 0,
from SPI0_CLK falling
Polarity = 1, Phase = 1,
from SPI0_CLK rising
9
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)S -3
Polarity = 0, Phase = 1,
from SPI0_CLK rising
0.5tc(SPC)S -3
Output hold time,
SPI0_SOMI valid after
receive edge of SPI0_CLK
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5tc(SPC)S -3
Polarity = 1, Phase = 1,
from SPI0_CLK falling
0.5tc(SPC)S -3
Polarity = 0, Phase = 0,
to SPI0_CLK falling
0
0
0
0
5
5
5
5
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Input Setup Time,
SPI0_SIMO valid before
receive edge of SPI0_CLK
ns
Polarity = 1, Phase = 0,
to SPI0_CLK rising
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
from SPI0_CLK rising
Input Hold Time,
SPI0_SIMO valid after
receive edge of SPI0_CLK
16 tih(SPC_SIMO)S
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
(1) P = SYSCLK2 period
(2) First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on
SPI0_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI0_SIMO.
(3) Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus
cycles must be accounted for to allow data to be written to the SPI module by the DSP CPU.
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Table 6-51. Additional(1) SPI0 Master Timings, 4-Pin Enable Option(2)(3)
NO.
MIN
MAX UNIT
3P + 5
Polarity = 0, Phase = 0,
to SPI0_CLK rising
Polarity = 0, Phase = 1,
to SPI0_CLK rising
0.5tc(SPC)M + 3P + 5
Delay from slave assertion of
SPI0_ENA active to first
SPI0_CLK from master.(4)
17 td(ENA_SPC)M
ns
Polarity = 1, Phase = 0,
to SPI0_CLK falling
3P + 5
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5tc(SPC)M + 3P + 5
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Max delay for slave to deassert
SPI0_ENA after final SPI0_CLK
edge to ensure master does not
begin the next transfer.(5)
0
0.5tc(SPC)M
0
18 td(SPC_ENA)M
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
(1) These parameters are in addition to the general timings for SPI master modes (Table 6-49).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI0_ENA assertion.
(5) In the case where the master SPI is ready with new data before SPI0_EN A deassertion.
Table 6-52. Additional(1) SPI0 Master Timings, 4-Pin Chip Select Option(2)(3)
NO.
MIN
MAX UNIT
Polarity = 0, Phase = 0,
to SPI0_CLK rising
2P -3
Polarity = 0, Phase = 1,
to SPI0_CLK rising
0.5tc(SPC)M + 2P -3
Delay from SPI0_SCS active to
first SPI0_CLK(4)(5)
19 td(SCS_SPC)M
ns
Polarity = 1, Phase = 0,
to SPI0_CLK falling
2P -3
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5tc(SPC)M + 2P -3
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M
Polarity = 0, Phase = 1,
from SPI0_CLK falling
0
0.5tc(SPC)M
0
Delay from final SPI0_CLK edge
20 td(SPC_SCS)M
to master deasserting SPI0_SCS
ns
(6)(7)
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
(1) These parameters are in addition to the general timings for SPI master modes (Table 6-49).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI0_SCS assertion.
(5) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(6) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain
asserted.
(7) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
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Table 6-53. Additional(1) SPI0 Master Timings, 5-Pin Option(2)(3)
NO.
MIN
MAX UNIT
Polarity = 0, Phase = 0,
from SPI0_CLK falling
P + 5
Max delay for slave to
deassert SPI0_ENA after
final SPI0_CLK edge to
ensure master does not
begin the next
Polarity = 0, Phase = 1,
from SPI0_CLK falling
0.5tc(SPC)M + P + 5
18 td(SPC_ENA)M
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
P + 5
transfer.(4)
Polarity = 1, Phase = 1,
from SPI0_CLK rising
0.5tc(SPC)M + P + 5
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Delay from final
0
0.5tc(SPC)M
0
SPI0_CLK edge to
master deasserting
20 td(SPC_SCS)M
21 td(SCSL_ENAL)M
22 td(SCS_SPC)M
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
(5)(6)
SPI0_SCS
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Max delay for slave SPI to drive SPI0_ENA valid
after master asserts SPI0_SCS to delay the
master from beginning the next transfer,
C2TDELAY + P ns
Polarity = 0, Phase = 0,
to SPI0_CLK rising
2P -3
0.5tc(SPC)M + 2P -3
2P -3
Polarity = 0, Phase = 1,
Delay from SPI0_SCS
to SPI0_CLK rising
active to first
ns
SPI0_CLK(7)(8)(9)
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5tc(SPC)M + 2P -3
Polarity = 0, Phase = 0,
to SPI0_CLK rising
3P + 5
Polarity = 0, Phase = 1,
0.5tc(SPC)M + 3P + 5
Delay from assertion of
to SPI0_CLK rising
23 td(ENA_SPC)M
SPI0_ENA low to first
ns
SPI0_CLK edge.(10)
Polarity = 1, Phase = 0,
to SPI0_CLK falling
3P + 5
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5tc(SPC)M + 3P + 5
(1) These parameters are in addition to the general timings for SPI master modes (Table 6-50).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI0_ENA deassertion.
(5) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain
asserted.
(6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
(7) If SPI0_ENA is asserted immediately such that the transmission is not delayed by SPI0_ENA.
(8) In the case where the master SPI is ready with new data before SPI0_SCS assertion.
(9) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(10) If SPI0_ENA was initially deasserted high and SPI0_CLK is delayed.
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Table 6-54. Additional(1) SPI0 Slave Timings, 4-Pin Enable Option(2)(3)
NO.
MIN
MAX UNIT
2.5 P + 9
Polarity = 0, Phase = 0,
from SPI0_CLK falling
1.5 P -3
– 0.5tc(SPC)M + 1.5 P -3
1.5 P -3
Polarity = 0, Phase = 1,
from SPI0_CLK falling
– 0.5tc(SPC)M + 2.5 P + 9
2.5 P + 9
Delay from final
24 td(SPC_ENAH)S SPI0_CLK edge to slave
deasserting SPI0_ENA.
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
– 0.5tc(SPC)M + 1.5 P -3
– 0.5tc(SPC)M + 2.5 P + 9
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-50).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
Table 6-55. Additional(1) SPI0 Slave Timings, 4-Pin Chip Select Option(2)(3)
NO.
MIN
MAX UNIT
Required delay from SPI0_SCS asserted at slave to first
SPI0_CLK edge at slave.
25
td(SCSL_SPC)S
P
ns
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M + 0
Polarity = 0, Phase = 1,
0
0.5tc(SPC)M + 0
0
Required delay from final
from SPI0_CLK falling
26
td(SPC_SCSH)S
SPI0_CLK edge before
ns
Polarity = 1, Phase = 0,
SPI0_SCS is deasserted.
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Delay from master asserting SPI0_SCS to slave driving
SPI0_SOMI valid
27
28
tena(SCSL_SOMI)S
tdis(SCSH_SOMI)S
P + 9
P + 9
ns
ns
Delay from master deasserting SPI0_SCS to slave 3-stating
SPI0_SOMI
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-50).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
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Table 6-56. Additional(1) SPI0 Slave Timings, 5-Pin Option(2)(3)
NO.
MIN
MAX UNIT
Required delay from SPI0_SCS asserted at slave to first
SPI0_CLK edge at slave.
25
td(SCSL_SPC)S
P
ns
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M + 0
Polarity = 0, Phase = 1,
0
0.5tc(SPC)M + 0
0
Required delay from final
from SPI0_CLK falling
26
td(SPC_SCSH)S
SPI0_CLK edge before
ns
Polarity = 1, Phase = 0,
SPI0_SCS is deasserted.
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Delay from master asserting SPI0_SCS to slave driving
SPI0_SOMI valid
27
28
29
tena(SCSL_SOMI)S
tdis(SCSH_SOMI)S
tena(SCSL_ENA)S
P + 9
P + 9
ns
ns
ns
Delay from master deasserting SPI0_SCS to slave 3-stating
SPI0_SOMI
Delay from master deasserting SPI0_SCS to slave driving
SPI0_ENA valid
9
Polarity = 0, Phase = 0,
from SPI0_CLK falling
2.5 P + 9
2.5 P + 9
2.5 P + 9
2.5 P + 9
Polarity = 0, Phase = 1,
from SPI0_CLK rising
Delay from final clock receive
edge on SPI0_CLK to slave
3-stating or driving high
SPI0_ENA.(4)
30
tdis(SPC_ENA)S
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-50).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
(4) SPI0_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is
tri-stated. If tri-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying
several SPI slave devices to a single master.
Table 6-57. General Timing Requirements for SPI1 Master Modes(1)
NO.
1
MIN
greater of 2P or 20 ns
0.5tc(SPC)M - 1
MAX UNIT
tc(SPC)M
Cycle Time, SPI1_CLK, All Master Modes
Pulse Width High, SPI1_CLK, All Master Modes
Pulse Width Low, SPI1_CLK, All Master Modes
256P ns
2
tw(SPCH)M
tw(SPCL)M
ns
ns
3
0.5tc(SPC)M - 1
Polarity = 0, Phase = 0,
to SPI1_CLK rising
5
0.5tc(SPC)M - 5
5
Polarity = 0, Phase = 1,
Delay, initial data bit valid
to SPI1_CLK rising
4,5 td(SIMO_SPC)M
on SPI1_SIMO to initial
ns
edge on SPI1_CLK(2)
Polarity = 1, Phase = 0,
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5tc(SPC)M - 5
Polarity = 0, Phase = 0,
from SPI1_CLK rising
5
Polarity = 0, Phase = 1,
5
Delay, subsequent bits
from SPI1_CLK falling
5
td(SPC_SIMO)M
valid on SPI1_SIMO after
ns
5
Polarity = 1, Phase = 0,
from SPI1_CLK falling
transmit edge of SPI1_CLK
Polarity = 1, Phase = 1,
from SPI1_CLK rising
5
(1) P = SYSCLK2 period
(2) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on
SPI1_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI1_SOMI.
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Table 6-57. General Timing Requirements for SPI1 Master Modes (continued)
NO.
MIN
MAX UNIT
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)M -3
Polarity = 0, Phase = 1,
from SPI1_CLK rising
0.5tc(SPC)M -3
Output hold time,
SPI1_SIMO valid after
receive edge of SPI1_CLK
6
7
8
toh(SPC_SIMO)M
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5tc(SPC)M -3
Polarity = 1, Phase = 1,
from SPI1_CLK falling
0.5tc(SPC)M -3
Polarity = 0, Phase = 0,
to SPI1_CLK falling
0
0
0
0
5
5
5
5
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Input Setup Time,
SPI1_SOMI valid before
receive edge of SPI1_CLK
tsu(SOMI_SPC)M
ns
Polarity = 1, Phase = 0,
to SPI1_CLK rising
Polarity = 1, Phase = 1,
to SPI1_CLK falling
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Polarity = 0, Phase = 1,
from SPI1_CLK rising
Input Hold Time,
SPI1_SOMI valid after
receive edge of SPI1_CLK
tih(SPC_SOMI)M
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK falling
Table 6-58. General Timing Requirements for SPI1 Slave Modes(1)
NO.
MIN
MAX UNIT
greater of 2P or
9
tc(SPC)S
Cycle Time, SPI1_CLK, All Slave Modes
20 ns
256P ns
10 tw(SPCH)S
11 tw(SPCL)S
Pulse Width High, SPI1_CLK, All Slave Modes
Pulse Width Low, SPI1_CLK, All Slave Modes
10
10
ns
ns
Polarity = 0, Phase = 0,
to SPI1_CLK rising
2P
2P
2P
2P
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Setup time, transmit data
written to SPI before initial
clock edge from
12 tsu(SOMI_SPC)S
ns
Polarity = 1, Phase = 0,
to SPI1_CLK falling
master.(2)(3)
Polarity = 1, Phase = 1,
to SPI1_CLK falling
Polarity = 0, Phase = 0,
from SPI1_CLK rising
9.7
Polarity = 0, Phase = 1,
from SPI1_CLK falling
9.7
ns
Delay, subsequent bits
valid on SPI1_SOMI after
transmit edge of SPI1_CLK
13 td(SPC_SOMI)S
Polarity = 1, Phase = 0,
from SPI1_CLK falling
9.7
Polarity = 1, Phase = 1,
from SPI1_CLK rising
9.7
(1) P = SYSCLK2 period
(2) First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on
SPI1_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI1_SIMO.
(3) Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus
cycles must be accounted for to allow data to be written to the SPI module by the DSP CPU.
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Table 6-58. General Timing Requirements for SPI1 Slave Modes (continued)
NO.
MIN
MAX UNIT
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)S -3
Polarity = 0, Phase = 1,
from SPI1_CLK rising
0.5tc(SPC)S -3
Output hold time,
SPI1_SOMI valid after
receive edge of SPI1_CLK
14 toh(SPC_SOMI)S
ns
ns
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5tc(SPC)S -3
Polarity = 1, Phase = 1,
from SPI1_CLK falling
0.5tc(SPC)S -3
Polarity = 0, Phase = 0,
to SPI1_CLK falling
0
0
0
0
5
5
5
5
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Input Setup Time,
SPI1_SIMO valid before
receive edge of SPI1_CLK
15 tsu(SIMO_SPC)S
Polarity = 1, Phase = 0,
to SPI1_CLK rising
Polarity = 1, Phase = 1,
to SPI1_CLK falling
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Polarity = 0, Phase = 1,
from SPI1_CLK rising
Input Hold Time,
SPI1_SIMO valid after
receive edge of SPI1_CLK
16 tih(SPC_SIMO)S
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK falling
Table 6-59. Additional(1) SPI1 Master Timings, 4-Pin Enable Option(2)(3)
NO.
MIN
MAX UNIT
Polarity = 0, Phase = 0,
to SPI1_CLK rising
3P + 5
Polarity = 0, Phase = 1,
to SPI1_CLK rising
0.5tc(SPC)M + 3P + 5
Delay from slave assertion of
SPI1_ENA active to first
SPI1_CLK from master.(4)
17 td(EN A_SPC)M
ns
Polarity = 1, Phase = 0,
to SPI1_CLK falling
3P + 5
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5tc(SPC)M + 3P + 5
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)M
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Max delay for slave to deassert
SPI1_ENA after final SPI1_CLK
edge to ensure master does not
begin the next transfer.(5)
0
0.5tc(SPC)M
0
18 td(SPC_ENA)M
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
(1) These parameters are in addition to the general timings for SPI master modes (Table 6-57).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI1_ENA assertion.
(5) In the case where the master SPI is ready with new data before SPI1_ENA deassertion.
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Table 6-60. Additional(1) SPI1 Master Timings, 4-Pin Chip Select Option(2)(3)
NO.
MIN
MAX UNIT
Polarity = 0, Phase = 0,
to SPI1_CLK rising
2P -3
Polarity = 0, Phase = 1,
to SPI1_CLK rising
0.5tc(SPC)M + 2P -3
Delay from SPI1_SCS active to
first SPI1_CLK(4)(5)
19 td(SCS_SPC)M
ns
Polarity = 1, Phase = 0,
to SPI1_CLK falling
2P -3
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5tc(SPC)M + 2P -3
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)M
Polarity = 0, Phase = 1,
from SPI1_CLK falling
0
0.5tc(SPC)M
0
Delay from final SPI1_CLK edge
20 td(SPC_SCS)M
to master deasserting SPI1_SCS
ns
(6)(7)
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
(1) These parameters are in addition to the general timings for SPI master modes (Table 6-57).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI1_SCS assertion.
(5) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(6) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain
asserted.
(7) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
Table 6-61. Additional(1) SPI1 Master Timings, 5-Pin Option(2)(3)
NO.
MIN
MAX UNIT
Polarity = 0, Phase = 0,
from SPI1_CLK falling
P + 5
Max delay for slave to
deassert SPI1_ENA after
final SPI1_CLK edge to
ensure master does not
begin the next
Polarity = 0, Phase = 1,
from SPI1_CLK falling
0.5tc(SPC)M + P + 5
18 td(SPC_ENA)M
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
P + 5
transfer.(4)
Polarity = 1, Phase = 1,
from SPI1_CLK rising
0.5tc(SPC)M + P + 5
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)M
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Delay from final
0
0.5tc(SPC)M
0
SPI1_CLK edge to
master deasserting
20 td(SPC_SCS)M
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
(5)(6)
SPI1_SCS
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Max delay for slave SPI to drive SPI1_ENA valid
after master asserts SPI1_SCS to delay the
master from beginning the next transfer,
21 td(SCSL_ENAL)M
C2TDELAY + P ns
(1) These parameters are in addition to the general timings for SPI master modes (Table 6-58).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI1_ENA deassertion.
(5) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain
asserted.
(6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
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Table 6-61. Additional SPI1 Master Timings, 5-Pin Option (continued)
NO.
MIN
MAX UNIT
Polarity = 0, Phase = 0,
to SPI1_CLK rising
2P -3
Polarity = 0, Phase = 1,
to SPI1_CLK rising
0.5tc(SPC)M + 2P -3
2P -3
Delay from SPI1_SCS
active to first
22 td(SCS_SPC)M
ns
SPI1_CLK(7)(8)(9)
Polarity = 1, Phase = 0,
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5tc(SPC)M + 2P -3
Polarity = 0, Phase = 0,
to SPI1_CLK rising
3P + 5
Polarity = 0, Phase = 1,
to SPI1_CLK rising
0.5tc(SPC)M + 3P + 5
3P + 5
Delay from assertion of
SPI1_ENA low to first
SPI1_CLK edge.(10)
23 td(ENA_SPC)M
ns
Polarity = 1, Phase = 0,
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5tc(SPC)M + 3P + 5
(7) If SPI1_ENA is asserted immediately such that the transmission is not delayed by SPI1_ENA.
(8) In the case where the master SPI is ready with new data before SPI1_SCS assertion.
(9) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(10) If SPI1_ENA was initially deasserted high and SPI1_CLK is delayed.
Table 6-62. Additional(1) SPI1 Slave Timings, 4-Pin Enable Option(2)(3)
NO.
MIN
MAX UNIT
Polarity = 0, Phase = 0,
1.5 P -3
2.5 P + 9.7
from SPI1_CLK falling
Polarity = 0, Phase = 1,
from SPI1_CLK falling
– 0.5tc(SPC)M + 1.5 P -3
1.5 P -3
– 0.5tc(SPC)M + 2.5 P + 9.7
2.5 P + 9.7
Delay from final
24 td(SPC_ENAH)S SPI1_CLK edge to slave
deasserting SPI1_ENA.
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
– 0.5tc(SPC)M + 1.5 P -3
– 0.5tc(SPC)M + 2.5 P + 9.7
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-58).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
Table 6-63. Additional(1) SPI1 Slave Timings, 4-Pin Chip Select Option(2)(3)
NO.
MIN
MAX UNIT
Required delay from SPI1_SCS asserted at slave to first
SPI1_CLK edge at slave.
25
td(SCSL_SPC)S
P
ns
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)M + 0
Polarity = 0, Phase = 1,
0
0.5tc(SPC)M + 0
0
Required delay from final
from SPI1_CLK falling
26
td(SPC_SCSH)S
SPI1_CLK edge before
ns
Polarity = 1, Phase = 0,
SPI1_SCS is deasserted.
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Delay from master asserting SPI1_SCS to slave driving
SPI1_SOMI valid
27
28
tena(SCSL_SOMI)S
tdis(SCSH_SOMI)S
P + 9.7
P + 9.7
ns
ns
Delay from master deasserting SPI1_SCS to slave 3-stating
SPI1_SOMI
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-58).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
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Table 6-64. Additional(1) SPI1 Slave Timings, 5-Pin Option(2)(3)
NO.
MIN
MAX UNIT
Required delay from SPI1_SCS asserted at slave to first
SPI1_CLK edge at slave.
25
td(SCSL_SPC)S
P
ns
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)M + 0
Polarity = 0, Phase = 1,
from SPI1_CLK falling
0
0.5tc(SPC)M + 0
0
Required delay from final
SPI1_CLK edge before
SPI1_SCS is deasserted.
26
td(SPC_SCSH)S
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Delay from master asserting SPI1_SCS to slave driving
SPI1_SOMI valid
27
28
29
tena(SCSL_SOMI)S
tdis(SCSH_SOMI)S
tena(SCSL_ENA)S
P + 9.7
ns
ns
ns
Delay from master deasserting SPI1_SCS to slave 3-stating
SPI1_SOMI
P + 9.7
9.7
Delay from master deasserting SPI1_SCS to slave driving
SPI1_ENA valid
Polarity = 0, Phase = 0,
from SPI1_CLK falling
2.5 P + 9.7
2.5 P + 9.7
2.5 P + 9.7
2.5 P + 9.7
Polarity = 0, Phase = 1,
from SPI1_CLK rising
Delay from final clock receive
edge on SPI1_CLK to slave
3-stating or driving high
SPI1_ENA.(4)
30
tdis(SPC_ENA)S
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK falling
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-58).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
(4) SPI1_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is
tri-stated. If tri-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying
several SPI slave devices to a single master.
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1
MASTER MODE
POLARITY = 0 PHASE = 0
2
3
SPIx_CLK
5
4
6
SPIx_SIMO
SPIx_SOMI
MO(0)
7
MO(1)
MO(n−1)
MO(n)
MI(n)
8
MI(0)
MI(1)
MI(n−1)
MASTER MODE
POLARITY = 0 PHASE = 1
4
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
6
5
MO(0)
7
MO(1)
MI(1)
MO(n−1)
MI(n−1)
MO(n)
MI(n)
8
MI(0)
4
MASTER MODE
POLARITY = 1 PHASE = 0
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
5
6
MO(0)
7
MO(1)
MI(1)
MO(n−1)
MO(n)
MI(n)
8
MI(0)
MI(n−1)
MASTER MODE
POLARITY = 1 PHASE = 1
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
5
4
6
MO(0)
7
MO(1)
MI(1)
MO(n−1)
MI(n−1)
MO(n)
MI(n)
8
MI(0)
Figure 6-37. SPI Timings—Master Mode
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9
SLAVE MODE
POLARITY = 0 PHASE = 0
12
10
15
11
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
16
SI(0)
SI(1)
13
SI(n−1)
SI(n)
14
SO(0)
SO(1)
SO(n−1)
SO(n)
12
SLAVE MODE
POLARITY = 0 PHASE = 1
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
15
SI(0)
16
SI(1)
SI(n−1)
SI(n)
13
SO(1)
14
SO(0)
SO(n−1)
SO(n)
SLAVE MODE
POLARITY = 1 PHASE = 0
12
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
15
16
SI(0)
SI(1)
SI(n−1)
SI(n)
13
SO(1)
14
SO(n−1)
SO(0)
SO(n)
SLAVE MODE
POLARITY = 1 PHASE = 1
12
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
15
16
SI(0)
SI(1)
SI(n−1)
SI(n)
13
SO(1)
14
SO(0)
SO(n−1)
SO(n)
Figure 6-38. SPI Timings—Slave Mode
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MASTER MODE 4 PIN WITH ENABLE
17
18
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
SPIx_ENA
MO(0)
MI(0)
MO(n)
MI(n)
MO(n−1)
MI(n−1)
MO(1)
MI(1)
MASTER MODE 4 PIN WITH CHIP SELECT
19
20
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
SPIx_SCS
MO(0)
MO(n)
MI(n)
MO(n−1)
MI(n−1)
MO(1)
MI(1)
MI(0)
MASTER MODE 5 PIN
23
22
20
MO(1)
18
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
MO(0)
MO(n−1)
MO(n)
MI(0)
MI(1)
MI(n−1)
MI(n)
21
(A)
(A)
SPIx_ENA
SPIx_SCS
DESEL
DESEL
A. DESELECTED IS PROGRAMMABLE EITHER HIGH OR
3−STATE (REQUIRES EXTERNAL PULLUP)
Figure 6-39. SPI Timings—Master Mode (4-Pin and 5-Pin)
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SLAVE MODE 4 PIN WITH ENABLE
24
SPIx_CLK
SPIx_SOMI
SPIx_SIMO
SPIx_ENA
SO(0)
SI(0)
SO(1)
SO(n−1) SO(n)
SI(n−1) SI(n)
SI(1)
SLAVE MODE 4 PIN WITH CHIP SELECT
25
26
SPIx_CLK
27
28
SO(n−1)
SPIx_SOMI
SPIx_SIMO
SPIx_SCS
SO(0)
SO(1)
SO(n)
SI(0)
SI(1)
SI(n−1)
SI(n)
SLAVE MODE 5 PIN
25
26
30
SPIx_CLK
27
29
28
SO(1)
SPIx_SOMI
SPIx_SIMO
SO(0)
SI(0)
SO(n−1)
SO(n)
SI(1)
SI(n−1) SI(n)
SPIx_ENA
SPIx_SCS
(A)
(A)
DESEL
DESEL
A. DESELECTED IS PROGRAMMABLE EITHER HIGH OR
3−STATE (REQUIRES EXTERNAL PULLUP)
Figure 6-40. SPI Timings—Slave Mode (4-Pin and 5-Pin)
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6.17 ECAP Peripheral Registers Description(s)
The OMAP-L137 device contains up to three enhanced capture (eCAP) modules. Figure 6-41 shows a
functional block diagram of a module. See the OMAP-L137 Applications Processor DSP Peripherals
Overview Reference Guide. – Literature Number SPRUGA6 for more details.
Uses for ECAP include:
•
•
•
•
Speed measurements of rotating machinery (e.g. toothed sprockets sensed via Hall sensors)
Elapsed time measurements between position sensor triggers
Period and duty cycle measurements of Pulse train signals
Decoding current or voltage amplitude derived from cuty cycle encoded current/voltage sensors
The ECAP module described in this specification includes the following features:
•
•
•
•
•
•
•
•
•
32 bit time base
4 event time-stamp registers (each 32 bits)
Edge polarity selection for up to 4 sequenced time-stamp capture events
Interrupt on either of the 4 events
Single shot capture of up to 4 event time-stamps
Continuous mode capture of time-stamps in a 4 deep circular buffer
Absolute time-stamp capture
Difference mode time-stamp capture
All the above resources are dedicated to a single input pin
The eCAP modules are clocked at the SYSCLK2 rate.
The clock enable bits (ECAP1/2/3/4ENCLK) in the PCLKCR1 register are used to turn off the eCAP
modules individually (for low power operation). Upon reset, ECAP1ENCLK, ECAP2ENCLK,
ECAP3ENCLK, and ECAP4EN CLK are set to low, indicating that the peripheral clock is off.
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CTRPHS
(phase register−32 bit)
APWM mode
SYNCIn
CTR_OVF
OVF
CTR [0−31]
PWM
TSCTR
(counter−32 bit)
SYNCOut
Delta−mode
PRD [0−31]
compare
logic
RST
CMP [0−31]
32
CTR=PRD
CTR [0−31]
PRD [0−31]
CTR=CMP
32
eCAPx
32
32
LD1
CAP1
(APRD active)
Polarity
select
LD
APRD
shadow
32
CMP [0−31]
32
LD2
CAP2
(ACMP active)
Polarity
select
LD
Event
qualifier
Event
Pre-scale
32
ACMP
shadow
Polarity
select
32
32
LD3
LD4
CAP3
(APRD shadow)
LD
CAP4
(ACMP shadow)
Polarity
select
LD
4
Capture events
4
CEVT[1:4]
Interrupt
Trigger
and
Flag
Continuous /
Oneshot
Capture Control
to PIE
CTR_OVF
CTR=PRD
CTR=CMP
control
Figure 6-41. eCAP Functional Block Diagram
Table 6-65 is the list of the ECAP registers.
Table 6-65. ECAPx Configuration Registers
ECAP0
BYTE ADDRESS
ECAP1
BYTE ADDRESS
ECAP2
REGISTER NAME
DESCRIPTION
BYTE ADDRESS
0x01F0 8000
0x01F0 8004
0x01F0 8008
0x01F0 6000
0x01F0 6004
0x01F0 6008
0x01F0 7000
0x01F0 7004
0x01F0 7008
TSCTR
CTRPHS
CAP1
Time-Stamp Counter
Counter Phase Offset Value Register
Capture 1 Register
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Table 6-65. ECAPx Configuration Registers (continued)
ECAP0
BYTE ADDRESS
ECAP1
ECAP2
REGISTER NAME
DESCRIPTION
BYTE ADDRESS
0x01F0 700C
0x01F0 7010
0x01F0 7014
0x01F0 7028
0x01F0 702A
0x01F0 702C
0x01F0 702E
0x01F0 7030
0x01F0 7032
0x01F0 705C
BYTE ADDRESS
0x01F0 800C
0x01F0 8010
0x01F0 8014
0x01F0 8028
0x01F0 802A
0x01F0 802C
0x01F0 802E
0x01F0 8030
0x01F0 8032
0x01F0 805C
0x01F0 600C
0x01F0 6010
0x01F0 6014
0x01F0 6028
0x01F0 602A
0x01F0 602C
0x01F0 602E
0x01F0 6030
0x01F0 6032
0x01F0 605C
CAP2
CAP3
Capture 2 Register
Capture 3 Register
CAP4
Capture 4 Register
ECCTL1
ECCTL2
ECEINT
ECFLG
ECCLR
ECFRC
REVID
Capture Control Register 1
Capture Control Register 2
Capture Interrupt Enable Register
Capture Interrupt Flag Register
Capture Interrupt Clear Register
Capture Interrupt Force Register
Revision ID
Table 6-66 shows the eCAP timing requirement and Table 6-67 shows the eCAP switching characteristics.
Table 6-66. Enhanced Capture (eCAP) Timing Requirement
TEST CONDITIONS
Asynchronous
MIN
2tc(SCO)
MAX UNIT
cycles
tw(CAP)
Capture input pulse width
Synchronous
2tc(SCO)
cycles
With input qualifier
1tc(SCO) + tw(IQSW)
cycles
Table 6-67. eCAP Switching Characteristics
PARAMETER
Pulse duration, APWMx output high/low
TEST CONDITIONS
MIN
MAX
UNIT
tw(APWM)
20
ns
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6.18 EQEP Peripheral Registers Description(s)
The OMAP-L137 device contains up to two enhanced quadrature encoder (eQEP) modules. See the
OMAP-L137 Applications Processor DSP Peripherals Overview Reference Guide. – Literature Number
SPRUGA6 . for more details.
System
control registers
To CPU
EQEPxENCLK
SYSCLK2
QCPRD
QCAPCTL
16
QCTMR
16
16
Quadrature
capture unit
(QCAP)
QCTMRLAT
QCPRDLAT
QUTMR
QUPRD
QWDTMR
QWDPRD
Registers
used by
multiple units
32
16
QEPCTL
QEPSTS
QFLG
UTOUT
UTIME
QWDOG
QDECCTL
16
WDTOUT
EQEPxAIN
EQEPxBIN
EQEPxIIN
EQEPxINT
16
QCLK
QDIR
QI
EQEPxA/XCLK
EQEPxB/XDIR
EQEPxI
Position counter/
control unit
(PCCU)
Quadrature
decoder
(QDU)
EQEPxIOUT
EQEPxIOE
EQEPxSIN
EQEPxSOUT
EQEPxSOE
QS
GPIO
MUX
QPOSLAT
QPOSSLAT
QPOSILAT
PHE
PCSOUT
EQEPxS
32
32
16
QPOSCNT
QPOSINIT
QPOSMAX
QEINT
QFRC
QPOSCMP
QCLR
QPOSCTL
Enhanced QEP (eQEP) peripheral
Figure 6-42. eQEP Functional Block Diagram
Table 6-68 is the list of the EQEP registers.
Table 6-69 shows the eQEP timing requirement and Table 6-70 shows the eQEP switching
characteristics.
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Table 6-68. EQEP Registers
EQEP0
EQEP1
BYTE ADDRESS
BYTE ADDRESS
0x01F0 A000
0x01F0 A004
0x01F0 A008
0x01F0 A00C
0x01F0 A010
0x01F0 A014
0x01F0 A018
0x01F0 A01C
0x01F0 A020
0x01F0 A024
0x01F0 A026
0x01F0 A028
0x01F0 A02A
0x01F0 A02C
0x01F0 A02E
0x01F0 A030
0x01F0 A032
0x01F0 A034
0x01F0 A036
0x01F0 A038
0x01F0 A03A
0x01F0 A03C
0x01F0 A03E
0x01F0 A040
0x01F0 A05C
REGISTER NAME
QPOSCNT
QPOSINIT
QPOSMAX
QPOSCMP
QPOSILAT
QPOSSLAT
QPOSLAT
QUTMR
DESCRIPTION
0x01F0 9000
0x01F0 9004
0x01F0 9008
0x01F0 900C
0x01F0 9010
0x01F0 9014
0x01F0 9018
0x01F0 901C
0x01F0 9020
0x01F0 9024
0x01F0 9026
0x01F0 9028
0x01F0 902A
0x01F0 902C
0x01F0 902E
0x01F0 9030
0x01F0 9032
0x01F0 9034
0x01F0 9036
0x01F0 9038
0x01F0 903A
0x01F0 903C
0x01F0 903E
0x01F0 9040
0x01F0 905C
eQEP Position Counter
eQEP Initialization Position Count
eQEP Maximum Position Count
eQEP Position-compare
eQEP Index Position Latch
eQEP Strobe Position Latch
eQEP Position Latch
eQEP Unit Timer
QUPRD
eQEP Unit Period Register
eQEP Watchdog Timer
QWDTMR
QWDPRD
QDECCTL
QEPCTL
eQEP Watchdog Period Register
eQEP Decoder Control Register
eQEP Control Register
QCAPCTL
QPOSCTL
QEINT
eQEP Capture Control Register
eQEP Position-compare Control Register
eQEP Interrupt Enable Register
eQEP Interrupt Flag Register
eQEP Interrupt Clear Register
eQEP Interrupt Force Register
eQEP Status Register
QFLG
QCLR
QFRC
QEPSTS
QCTMR
eQEP Capture Timer
QCPRD
eQEP Capture Period Register
eQEP Capture Timer Latch
eQEP Capture Period Latch
eQEP Revision ID
QCTMRLAT
QCPRDLAT
REVID
Table 6-69. Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
TEST CONDITIONS
Asynchronous/synchronous
With input qualifier
MIN
MAX
UNIT
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
tw(QEPP)
QEP input period
2tc(SCO)
2(1tc(SCO) + tw(IQSW)
)
tw(INDEXH)
tw(INDEXL)
tw(STROBH)
tw(STROBL)
QEP Index Input High time
QEP Index Input Low time
QEP Strobe High time
QEP Strobe Input Low time
Asynchronous/synchronous
With input qualifier
2tc(SCO)
2tc(SCO) +tw(IQSW)
2tc(SCO)
Asynchronous/synchronous
With input qualifier
2tc(SCO) + tw(IQSW)
2tc(SCO)
2tc(SCO) + tw(IQSW)
2tc(SCO)
Asynchronous/synchronous
With input qualifier
Asynchronous/synchronous
With input qualifier
2tc(SCO) +tw(IQSW)
Table 6-70. eQEP Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
MAX
4tc(SCO)
6tc(SCO)
UNIT
cycles
cycles
td(CNTR)xin
Delay time, external clock to counter increment
td(PCS-OUT)QEP Delay time, QEP input edge to position compare sync output
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6.19 eHRPWM
The OMAP-L137 device contains up to three enhanced PWM Modules (eHRPWM). Figure 6-43 shows a
block diagram of multiple eHRPWM modules. Figure 4-4 shows the signal interconnections with the
eHRPWM. See the OMAP-L137 Applications Processor DSP Peripherals Overview Reference Guide. –
Literature Number SPRUGA6 for more details.
EPWM1SYNCI
EPWM1SYNCI
EPWM1INT
EPWM1A
ePWM1 module
EPWM1B
TZ
EPWM1SYNCO
to eCAP1
module
(sync in)
EPWM1SYNCO
.
EPWM2SYNCI
ePWM2 module
EPWM2SYNCO
EPWM2INT
EPWM2A
EPWM2B
TZ
GPIO
MUX
EPWMxSYNCI
ePWMx module
EPWMxINT
EPWMxA
EPWMxB
TZ
Interrupt
Controllers
EPWMxSYNCO
Peripheral Bus
Figure 6-43. Multiple PWM Modules in a OMAP-L137 System
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Time−base (TB)
Sync
in/out
select
Mux
CTR=ZERO
CTR=CMPB
Disabled
TBPRD shadow (16)
TBPRD active (16)
EPWMxSYNCO
EPWMxSYNCI
CTR=PRD
TBCTL[SYNCOSEL]
TBCTL[CNTLDE]
Counter
up/down
(16 bit)
TBCTL[SWFSYNC]
(software forced sync)
CTR=ZERO
TBCNT
active (16)
CTR_Dir
TBPHSHR (8)
16
8
CTR = PRD
CTR = ZERO
CTR = CMPA
CTR = CMPB
CTR_Dir
Phase
Event
trigger
and
interrupt
(ET)
TBPHS active (24)
control
EPWMxINT
Counter compare (CC)
CTR=CMPA
CMPAHR (8)
Action
qualifier
(AQ)
16
8
HiRes PWM (HRPWM)
CMPA active (24)
EPWMA
EPWMB
EPWMxA
CMPA shadow (24)
CTR=CMPB
Dead
band
(DB)
PWM
chopper
(PC)
Trip
zone
(TZ)
16
EPWMxB
EPWMxTZINT
TZ
CMPB active (16)
CMPB shadow (16)
CTR = ZERO
Figure 6-44. eHRPWM Sub-Modules Showing Critical Internal Signal Interconnections
Table 6-71. eHRPWM Module Control and Status Registers Grouped by Submodule
eHRPWM1
BYTE ADDRESS BYTE ADDRESS
eHRPWM2
eHRPWM3
BYTE ADDRESS Acronym
Size Shad
(×16) ow
Register Description
Time-Base Submodule Registers
0x01F0 0000
0x01F0 0002
0x01F0 0004
0x01F0 2000
0x01F0 2002
0x01F0 2004
0x01F0 4000
0x01F0 4002
0x01F0 4004
TBCTL
1
1
1
No
No
No
Time-Base Control Register
Time-Base Status Register
TBSTS
TBPHSHR
Extension for HRPWM Phase Register
(1)
0x01F0 0006
0x01F0 0008
0x01F0 000A
0x01F0 2006
0x01F0 2008
0x01F0 200A
0x01F0 4006
0x01F0 4008
0x01F0 400A
TBPHS
TBCNT
TBPRD
1
1
1
No
No
Time-Base Phase Register
Time-Base Counter Register
Yes Time-Base Period Register
Counter-Compare Submodule Registers
0x01F0 000E
0x01F0 0010
0x01F0 200E
0x01F0 2010
0x01F0 400E
0x01F0 4010
CMPCTL
CMPAHR
1
1
No
No
Counter-Compare Control Register
Extension for HRPWM
Counter-Compare A Register
(1)
0x01F0 0012
0x01F0 0014
0x01F0 2012
0x01F0 2014
0x01F0 4012
0x01F0 4014
CMPA
CMPB
1
1
Yes Counter-Compare A Register
Yes Counter-Compare B Register
(1) These registers are only available on eHRPWM instances that include the high-resolution PWM (HRPWM) extension; otherwise, these
locations are reserved.
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Table 6-71. eHRPWM Module Control and Status Registers Grouped by Submodule (continued)
eHRPWM1
BYTE ADDRESS BYTE ADDRESS
eHRPWM2
eHRPWM3
BYTE ADDRESS Acronym
Size Shad
(×16) ow
Register Description
Action-Qualifier Submodule Registers
0x01F0 0016
0x01F0 0018
0x01F0 2016
0x01F0 2018
0x01F0 4016
0x01F0 4018
AQCTLA
1
No
No
No
Action-Qualifier Control Register for
Output A (eHRPWMxA)
AQCTLB
1
Action-Qualifier Control Register for
Output B (eHRPWMxB)
0x01F0 001A
0x01F0 001C
0x01F0 201A
0x01F0 201C
0x01F0 401A
0x01F0 401C
AQSFRC
1
1
Action-Qualifier Software Force Register
AQCSFRC
Yes Action-Qualifier Continuous S/W Force
Register Set
Dead-Band Generator Submodule Registers
0x01F0 001E
0x01F0 0020
0x01F0 201E
0x01F0 2020
0x01F0 401E
0x01F0 4020
DBCTL
DBRED
1
1
No
No
Dead-Band Generator Control Register
Dead-Band Generator Rising Edge
Delay Count Register
0x01F0 0022
0x01F0 003C
0x01F0 2022
0x01F0 203C
0x01F0 4022
0x01F0 403C
DBFED
1
No
Dead-Band Generator Falling Edge
Delay Count Register
PWM-Chopper Submodule Registers
PCCTL
1
No
PWM-Chopper Control Register
Trip-Zone Submodule Registers
0x01F0 0024
0x01F0 0028
0x01F0 002A
0x01F0 002C
0x01F0 002E
0x01F0 0030
0x01F0 2024
0x01F0 2028
0x01F0 202A
0x01F0 202C
0x01F0 202E
0x01F0 2030
0x01F0 4024
0x01F0 4028
0x01F0 402A
0x01F0 402C
0x01F0 402E
0x01F0 4030
TZSEL
TZCTL
TZEINT
TZFLG
TZCLR
TZFRC
1
1
1
1
1
1
No
No
No
No
No
No
Trip-Zone Select Register
Trip-Zone Control Register
Trip-Zone Enable Interrupt Register
Trip-Zone Flag Register
Trip-Zone Clear Register
Trip-Zone Force Register
Event-Trigger Submodule Registers
0x01F0 0032
0x01F0 0034
0x01F0 0036
0x01F0 0038
0x01F0 003A
0x01F0 2032
0x01F0 2034
0x01F0 2036
0x01F0 2038
0x01F0 203A
0x01F0 4032
0x01F0 4034
0x01F0 4036
0x01F0 4038
0x01F0 403A
ETSEL
ETPS
1
1
1
1
1
No
No
No
No
No
Event-Trigger Selection Register
Event-Trigger Pre-Scale Register
Event-Trigger Flag Register
Event-Trigger Clear Register
Event-Trigger Force Register
ETFLG
ETCLR
ETFRC
High-Resolution PWM (HRPWM) Submodule Registers
HRCNFG No HRPWM Configuration Register
(1)
0x01F0 1020
0x01F0 3020
0x01F0 5020
1
6.20 Enhanced Pulse Width Modulator (eHRPWM) Timing
PWM refers to PWM outputs on eHRPWM1-6. Table 6-72 shows the PWM timing requirements and
Table 6-73, switching characteristics.
Table 6-72. eHRPWM Timing Requirements
TEST CONDITIONS
Asynchronous
MIN
2tc(SCO)
MAX
UNIT
cycles
cycles
cycles
tw(SYCIN)
Sync input pulse width
Synchronous
2tc(SCO)
With input qualifier
1tc(SCO) + tw(IQSW)
Table 6-73. eHRPWM Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
20
MAX
UNIT
ns
tw(PWM)
Pulse duration, PWMx output high/low
Sync output pulse width
tw(SYNCOUT)
td(PWM)tza
8tc(SCO)
cycles
ns
Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low
no pin load
25
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Table 6-73. eHRPWM Switching Characteristics (continued)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
td(TZ-PWM)HZ
Delay time, trip input active to PWM Hi-Z
20
ns
6.21 Trip-Zone Input Timing
t
w(TZ)
TZ
t
d(TZ-PWM)HZ
(A)
PWM
A. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM
recovery software.
Figure 6-45. PWM Hi-Z Characteristics
Table 6-74. Trip-Zone input Timing Requirements
MIN
1tc(SCO)
MAX UNIT
cycles
tw(TZ)
Pulse duration, TZx input low
Asynchronous
Synchronous
2tc(SCO)
cycles
With input qualifier
1tc(SCO) + tw(IQSW)
cycles
Table 6-75 shows the high-resolution PWM switching characteristics.
Table 6-75. High Resolution PWM Characteristics at SYSCLKOUT = (60 - 100 MHz)
MIN
TYP
MAX UNIT
Micro Edge Positioning (MEP) step size(1)
150
310
ps
(1) Maximum MEP step size is based on worst-case process, maximum temperature and maximum voltage. MEP step size will increase
with low voltage and high temperature and decrease with voltage and cold temperature.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLKOUT period dynamically while the HRPWM is in operation.
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6.22 LCD Controller
Table 6-76 lists the LCD Controller registers
Table 6-76. LCD Controller (LCDC) Registers
Address Offset Acronym
Register Description
0x01E1 3000
0x01E1 3004
0x01E1 3008
0x01E1 300C
0x01E1 3010
0x01E1 3014
0x01E1 3018
0x01E1 301C
0x01E1 3020
0x01E1 3024
0x01E1 3028
0x01E1 302C
0x01E1 3030
0x01E1 3034
0x01E1 3038
0x01E1 3040
0x01E1 3044
0x01E1 3048
0x01E1 304C
0x01E1 3050
REVID
LCD Revision Identification Register
LCD Control Register
LCD_CTRL
LCD_STAT
LCD Status Register
LIDD_CTRL
LCD LIDD Control Register
LIDD_CS0_CONF
LIDD_CS0_ADDR
LIDD_CS0_DATA
LIDD_CS1_CONF
LIDD_CS1_ADDR
LIDD_CS1_DATA
RASTER_CTRL
LCD LIDD CS0 Configuration Register
LCD LIDD CS0 Address Read/Write Register
LCD LIDD CS0 Data Read/Write Register
LCD LIDD CS1 Configuration Register
LCD LIDD CS1 Address Read/Write Register
LCD LIDD CS1 Data Read/Write Register
LCD Raster Control Register
RASTER_TIMING_0
RASTER_TIMING_1
RASTER_TIMING_2
RASTER_SUBPANEL
LCDDMA_CTRL
LCDDMA_FB0_BASE
LCDDMA_FB0_CEILING
LCDDMA_FB1_BASE
LCDDMA_FB1_CEILING
LCD Raster Timing 0 Register
LCD Raster Timing 1 Register
LCD Raster Timing 2 Register
LCD Raster Subpanel Display Register
LCD DMA Control Register
LCD DMA Frame Buffer 0 Base Address Register
LCD DMA Frame Buffer 0 Ceiling Address Register
LCD DMA Frame Buffer 1 Base Address Register
LCD DMA Frame Buffer 1 Ceiling Address Register
6.22.1 LCD Interface Display Driver (LIDD Mode)
Table 6-77. LCD LIDD Mode Timing Requirements(1)
NO
PARAMETER
MIN
MAX
UNIT
Setup time, LCD_D[15:0] valid
before LCD_MCLK ↑
16
tsu(LCD_D)
th(LCD_D)
7
ns
Hold time, LCD_D[15:0] valid after
LCD_MCLK ↑
17
0
ns
(1) Over operating free-air temperature range (unless otherwise noted)
Table 6-78. LCD LIDD Mode Timing Characteristics
NO
PARAMETER
MIN
MAX
UNIT
Delay time, LCD_MCLK ↑ to
LCD_D[15:0] valid (write)
4
td(LCD_D_V)
0
7
ns
Delay time, LCD_MCLK ↑ to
LCD_D[15:0] invalid (write)
5
6
7
8
9
td(LCD_D_I)
0
7
7
7
7
7
ns
ns
ns
ns
ns
Delay time, LCD_MCLK ↑ to
LCD_AC_ENB_CS↓
td(LCD_E_A
td(LCD_E_I)
td(LCD_A_A)
td(LCD_A_I)
)
0
Delay time, LCD_MCLK ↑ to
LCD_AC_ENB_CS↑
0
Delay time, LCD_MCLK ↑ to
LCD_VSYNC↓
0
Delay time, LCD_MCLK ↑ to
LCD_VSYNC↑
0
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Table 6-78. LCD LIDD Mode Timing Characteristics (continued)
NO
PARAMETER
MIN
MAX
UNIT
Delay time, LCD_MCLK ↑ to
LCD_HSYNC↓
10
td(LCD_W_A)
0
7
ns
Delay time, LCD_MCLK ↑ to
LCD_HSYNC↑
11
12
13
14
td(LCD_W_I)
0
0
0
0
7
7
7
7
ns
ns
ns
ns
Delay time, LCD_MCLK ↑ to
LCD_PCLK↑
td(LCD_STRB_A)
td(LCD_STRB_I)
td(LCD_D_Z)
Delay time, LCD_MCLK ↑ to
LCD_PCLK↓
Delay time, LCD_MCLK ↑ to
LCD_D[15:0] in 3-state
Delay time, LCD_MCLK ↑ to 15
td(Z_LCD_D) 3-state) LCD_D[15:0]
(valid from 3-state)
15
td(Z_LCD_D)
0
7
ns
CS_DELAY
(0 to 3)
1
2
R_SU
(0 to 31)
R_HOLD
(1 to 15)
W_SU
(0 to 31)
W_STROBE
CS_DELAY
(0 to 3)
R_STROBE
(1 to 63)
W_HOLD
3
(1 to 63)
(1 to 15)
LCD_MCLK
4
5
14
17
16
15
LCD_D[15:0]
LCD_PCLK
Write Data
Data[7:0]
Read Status
Not Used
RS
8
9
LCD_VSYNC
LCD_HSYNC
10
11
R/W
12
12
13
13
E0
E1
LCD_AC_ENB_CS
Figure 6-46. Character Display HD44780 Write
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W_HOLD
(1–15)
R_SU
(0–31)
R_STROBE R_HOLD CS_DELAY
(1–63) (1–5) (0−3)
W_SU
(0–31)
W_STROBE
(1–63)
CS_DELAY
(0 − 3)
1
2
Not
Used
3
LCD_MCLK
LCD_D[7:0]
4
17
15
5
14
16
Data[7:0]
Write Instruction
Read
Data
LCD_PCLK
Not
Used
8
9
RS
LCD_VSYNC
LCD_HSYNC
10
11
R/W
12
13
13
12
E0
E1
LCD_AC_ENB_CS
Figure 6-47. Character Display HD44780 Read
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W_HOLD
(1−15)
W_HOLD
(1−15)
W_SU
(0−31)
W_STROBE
(1−63)
CS_DELAY
(0−3)
W_SU
(0−31)
W_STROBE
(1−63)
CS_DELAY
(0−3)
1
2
3
Clock
LCD_MCLK
LCD_D[15:0]
4
5
7
5
4
Write Address
Write Data
Data[15:0]
6
6
8
7
LCD_AC_ENB_CS
(async mode)
CS0
CS1
9
A0
R/W
E
LCD_VSYNC
10
11
10
11
LCD_HSYNC
LCD_PCLK
12
13
12
13
Figure 6-48. Micro-Interface Graphic Display 6800 Write
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W_HOLD
(1−15)
R_SU
(0−31)
W_SU
(0−31)
W_STROBE
(1−63)
CS_DELAY
(0−3)
R_STROBE R_HOLD CS_DELAY
(1−63 (0−3)
1
(1−15)
3
2
Clock
LCD_MCLK
4
6
14
5
7
16
15
Data[15:0]
17
LCD_D[15:0]
Write Address
Read
Data
6
7
LCD_AC_ENB_CS
(async mode)
CS0
CS1
9
8
LCD_VSYNC
LCD_HSYNC
LCD_PCLK
A0
R/W
E
11
10
13
12
13
12
Figure 6-49. Micro-Interface Graphic Display 6800 Read
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R_SU
(0−31)
R_SU
(0−31)
R_STROBE R_HOLD CS_DELAY
R_HOLD CS_DELAY
R_STROBE
(1−63)
1
(1−63)
(1−15)
(0−3)
(1−15)
(0−3)
2
3
Clock
LCD_MCLK
LCD_D[15:0]
17
17
14 16
14
15
7
16
15
Data[15:0]
Read
Status
Read
Data
6
7
6
LCD_AC_ENB_CS
(async mode)
CS0
CS1
8
9
LCD_VSYNC
LCD_HSYNC
A0
R/W
E
13
12
12
13
LCD_PCLK
Figure 6-50. Micro-Interface Graphic Display 6800 Status
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W_HOLD
(1−15)
W_HOLD
(1−15)
W_SU
W_STROBE
CS_DELAY
(0−3)
W_SU
(0−31)
W_STROBE
(1−63)
CS_DELAY
(0 − 3)
1
2
(0−31)
3
(1−63)
Clock
LCD_MCLK
4
5
4
5
LCD_D[15:0]
Write Address
Write Data
7
6
6
8
7
LCD_AC_ENB_CS
(async mode)
CS0
CS1
9
LCD_VSYNC
LCD_HSYNC
LCD_PCLK
A0
WR
RD
11
10
10
11
Figure 6-51. Micro-Interface Graphic Display 8080 Write
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W_HOLD
(1−15)
R_SU
(0−31)
W_SU
(0−31)
W_STROBE
(1−63)
CS_DELAY
(0−3)
R_STROBE
(1−63)
R_HOLD CS_DELAY
(1−15) (0−3)
1
Clock
2
3
LCD_MCLK
4
6
5
16
17
15
Data[15:0]
14
LCD_D[15:0]
Write Address
Read
Data
7
7
6
LCD_AC_ENB_CS
(async mode)
CS0
CS1
9
8
LCD_VSYNC
LCD_HSYNC
LCD_PCLK
A0
11
10
WR
12
13
RD
Figure 6-52. Micro-Interface Graphic Display 8080 Read
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R_SU
(0−31)
R_SU
(0−31)
R_STROBE R_HOLD CS_DELAY
R_STROBE R_HOLD
CS_DELAY
(0−3)
1
2
(1−15)
(1−63)
(1−63)
(1−15)
(0−3)
3
Clock
LCD_MCLK
LCD_D[15:0]
17
16
17
15
14
6
16
15
7
14
6
Data[15:0]
Read Data
Read Status
7
9
LCD_AC_ENB_CS
CS0
CS1
8
A0
WR
RD
LCD_VSYNC
LCD_HSYNC
12
13
13
12
LCD_PCLK
Figure 6-53. Micro-Interface Graphic Display 8080 Status
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6.22.2 LCD Raster Mode
Table 6-79. LCD Raster Mode Timing
See Figure 6-54 through Figure 6-58
NO.
PARAMETER
MIN
MAX
F/2(1)
UNIT
MHz
ns
fclock(PIXEL_CLK)
tc(PIXEL_CLK)
Clock frequency, pixel clock
1
2
Cycle time, pixel clock
23.81
tw(PIXEL_CLK_H)
tw(PIXEL_CLK_L)
td(LCD_D_V)
Pulse duration, pixel clock high
10
10
0
ns
3
Pulse duration, pixel clock low
ns
4
Delay time, LCD_PCLK↑ to LCD_D[15:0] valid (write)
Delay time, LCD_PCLK↑ to LCD_D[15:0] invalid (write)
Delay time, LCD_PCLK↓ to LCD_AC_ENB_CS↑
Delay time, LCD_PCLK↓ to LCD_AC_ENB_CS↓
Delay time, LCD_PCLK↓ to LCD_VSYNC↑
Delay time, LCD_PCLK↓ to LCD_VSYNC↓
Delay time, LCD_PCLK↑ to LCD_HSYNC↑
Delay time, LCD_PCLK↑ to LCD_HSYNC↓
12
12
12
12
12
12
12
12
ns
5
td(LCD_D_IV)
0
ns
6
td(LCD_AC_ENB_CS_A)
td(LCD_AC_ENB_CS_I)
td(LCD_VSYNC_A)
td(LCD_VSYNC_I)
td(LCD_HSYNC_A)
td(LCD_HSYNC_I)
0
ns
7
0
ns
8
0
ns
9
0
ns
10
11
0
ns
0
ns
(1) F = frequency of LCD_PCLK in ns
Frame-to-frame timing is derived through the following parameters in the LCD (RASTER_TIMING_1)
register:
•
•
•
•
Vertical front porch (VFP)
Vertical sync pulse width (VSW)
Vertical back porch (VBP)
Lines per panel (LPP)
Line-to-line timing is derived through the following parameters in the LCD (RASTER_TIMING_0) register:
•
•
•
•
Horizontal front porch (HFP)
Horizontal sync pulse width (HSW)
Horizontal back porch (HBP)
Pixels per panel (PPL)
LCD_AC_ENB_CS timing is derived through the following parameter in the LCD (RASTER_TIMING_2)
register:
•
AC bias frequency (ACB)
The display format produced in raster mode is shown in Figure 6-54. An entire frame is delivered one line
at a time. The first line delivered starts at data pixel (1, 1) and ends at data pixel (P, 1). The last line
delivered starts at data pixel (1, L) and ends at data pixel (P, L). The beginning of each new frame is
denoted by the activation of I/O signal LCD_VSYNC. The beginning of each new line is denoted by the
activation of I/O signal LCD_HSYNC.
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Data Pixels (From 1 to P)
P−2,
1
P−1,
1
1, 1
1, 2
1, 3
2, 1
2, 2
3, 1
P, 1
P, 2
P, 3
P−1,
2
LCD
P,
1,
L−2
L−2
1,
L−1
2,
L−1
P,
L−1
P−1,
L−1
P−2,
L
P−1,
L
1, L
2, L
3, L
P, L
Figure 6-54. LCD Raster-Mode Display Format
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Frame Time ~ 70Hz
Active TFT
VSW
(1 to 64)
VBP
(0 to 255)
LPP
VFP
VSW
(1 to 64)
(1 to 1024)
(0 to 255)
Line
Time
Hsync
LCD_HSYNC
LCD_VSYNC
Vsync
Data
LCD_D[15:0]
1, L−1
P, L−1
1, L
P, L
1, 2
P, 2
1, 1
P, 1
Enable
LCD_AC_ENB_CS
ACB
(0 to 255)
ACB
(0 to 255)
10
11
Hsync
LCD_HSYNC
CLK
LCD_PCLK
Data
LCD_D[15:0]
2, 1
1, 2
P, 2
P, 1
1, 1
2, 2
PLL
HFP
HSW
HBP
(1 to 256)
PLL
16 y (1 to 1024)
16 y (1 to 1024)
(1 to 256)
(1 to 64)
Line 1
Line 2
Figure 6-55. LCD Raster-Mode Active
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Frame Time ~ 70Hz
VBP = 0
VFP = 0
VBP = 0
VFP = 0
VSW = 1
(1 to 64)
VSW = 1
(1 to 64)
LPP
Passive STN
(1 to 1024)
Line
Time
LP
LCD_HSYNC
LCD_VSYNC
LCD_D[7:0]
FP
1, L
Data
1, 2
P, 2
1, 1:
P, 1
1, 5:
P, 5
1, L
P, L
1, 1
P, 1
1, L:
P, L
1, 3: 1, 4:
P, 3 P, 4
1, 6:
P, 6
1, 2:
P, 2
1, L−1
P, L−1
1, L−4 1, L−3
P, L−4 P, L−3
1, L−2
P, L−2
1, L−1
P, L−1
M
LCD_AC_ENB_CS
ACB
ACB
(0 to 255)
(0 to 255)
11
10
LP
LCD_HSYNC
LCD_PCLK
LCD_D[7:0]
CP
Data
1, 5
P, 6
1, 6
2, 6
2, 5
P, 5
PPL
HFP
HSW
(1 to 64)
HBP
PPL
16 y (1 to 1024)
(1 to 256)
(1 to 256)
16 y (1 to 2024)
Line 6
Line 5
Figure 6-56. LCD Raster-Mode Passive
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6
LCD_AC_ENB_CS
LCD_VSYNC
8
11
10
LCD_HSYNC
1
3
2
LCD_PCLK
(passive mode)
5
4
LCD_D[7:0]
(passive mode)
2, L
2, 1
1, L
P, L
1, 1
P, 1
1
3
2
LCD_PCLK
(active mode)
4
5
LCD_D[15:0]
(active mode)
1, L
P, L
2, L
VBP = 0
VFP = 0
VSW = 1
PPL
HSW
HBP
PPL
16 y (1 to 256)
HFP
(1 to 256
16 y (1 to 1024)
(1 to 256)
(1 to 64)
Line L
Line 1 (Passive Only)
Figure 6-57. LCD Raster-Mode Control Signal Activation
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6
LCD_AC_ENB_CS
LCD_VSYNC
8
11
10
LCD_HSYNC
1
3
2
LCD_PCLK
(passive mode)
5
4
LCD_D[7:0]
(passive mode)
2, L
2, 1
1, L
P, L
1, 1
P, 1
1
3
2
LCD_PCLK
(active mode)
4
5
LCD_D[15:0]
(active mode)
1, L
P, L
2, L
VBP = 0
VFP = 0
VSW = 1
PPL
HSW
HBP
PPL
16 y (1 to 256)
HFP
(1 to 256
16 y (1 to 1024)
(1 to 256)
(1 to 64)
Line L
Line 1 (Passive Only)
Figure 6-58. LCD Raster-Mode Control Signal Deactivation
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6.23 Timers
The timers support the following features:
•
•
•
•
•
•
Configurable as single 64-bit timer or two 32-bit timers
Period timeouts generate interrupts, DMA events or external pin events
8 32-bit compare registers
Compare matches generate interrupt events
Capture capability
64-bit Watchdog capability (Timer64P1 only)
Table 6-80 lists the timer registers.
Table 6-80. Timer Registers
Timer64P 0
0x01C2 0000
0x01C2 0004
0x01C2 0008
0x01C2 000C
0x01C2 0010
0x01C2 0014
0x01C2 0018
0x01C2 001C
0x01C2 0020
0x01C2 0024
0x01C2 0028
0x01C2 0034
0x01C2 0038
0x01C2 003C
0x01C2 0040
0x01C2 0044
0x01C2 0060
0x01C2 0064
0x01C2 0068
0x01C2 006C
0x01C2 0070
0x01C2 0074
0x01C2 0078
0x01C2 007C
Timer64P 1
0x01C2 1000
0x01C2 1004
0x01C2 1008
0x01C2 100C
0x01C2 1010
0x01C2 1014
0x01C2 1018
0x01C2 101C
0x01C2 1020
0x01C2 1024
0x01C2 1028
0x01C2 1034
0x01C2 1038
0x01C2 103C
0x01C2 1040
0x01C2 1044
0x01C2 1060
0x01C2 1064
0x01C2 1068
0x01C2 106C
0x01C2 1070
0x01C2 1074
0x01C2 1078
0x01C2 107C
Acronym
REV
Register Description
Revision Register
EMUMGT
GPINTGPEN
GPDATGPDIR
TIM12
Emulation Management Register
GPIO Interrupt and GPIO Enable Register
GPIO Data and GPIO Direction Register
Timer Counter Register 12
Timer Counter Register 34
Timer Period Register 12
Timer Period Register 34
Timer Control Register
TIM34
PRD12
PRD34
TCR
TGCR
Timer Global Control Register
Watchdog Timer Control Register
Timer Reload Register 12
Timer Reload Register 34
Timer Capture Register 12
Timer Capture Register 34
Timer Interrupt Control and Status Register
Compare Register 0
WDTCR
REL12
REL34
CAP12
CAP34
INTCTLSTAT
CMP0
CMP1
Compare Register 1
CMP2
Compare Register 2
CMP3
Compare Register 3
CMP4
Compare Register 4
CMP5
Compare Register 5
CMP6
Compare Register 6
CMP7
Compare Register 7
6.23.1 Timer Electrical Data/Timing
Table 6-81. Timing Requirements for Timer Input(1)(2) (see Figure 6-59)
NO.
UNIT
MIN
4P
MAX
1
2
3
4
tc(TM64Px_IN12) Cycle time, TM64Px_IN12
ns
ns
ns
ns
tw(TINPH)
tw(TINPL)
Pulse duration, TM64Px_IN12 high
Pulse duration, TM64Px_IN12 low
0.45C
0.45C
0.55C
0.55C
0.05C
tt(TM64Px_IN12) Transition time, TM64Px_IN12
(1) P = OSCIN cycle time in ns. For example, when OSCIN frequency is 27 MHz, use P = 37.037 ns.
(2) C = TM64P0_IN12 cycle time in ns. For example, when TM64Px_IN12 frequency is 27 MHz, use C = 37.037 ns
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1
2
3
4
4
TM64P0_IN12
Figure 6-59. Timer Timing
Table 6-82. Switching Characteristics Over Recommended Operating Conditions for Timer Output
(1)
NO.
UNIT
MIN
4P
MAX
5
6
tw(TOUTH)
tw(TOUTL)
Pulse duration, TM64P0_OUT12 high
Pulse duration, TM64P0_OUT12 low
ns
ns
4P
(1) P = OSCIN cycle time in ns. For example, when OSCIN frequency is 27 MHz, use P = 37.037 ns.
5
6
TM64P0_OUT12
Figure 6-60. Timer Timing
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6.24 Inter-Integrated Circuit Serial Ports (I2C0, I2C1)
6.24.1 I2C Device-Specific Information
Having two I2C modules on the OMAP-L137 simplifies system architecture, since one module may be
used by the DSP to control local peripherals ICs (DACs, ADCs, etc.) while the other may be used to
communicate with other controllers in a system or to implement a user interface. Figure 6-61 is block
diagram of the OMAP-L137 I2C Module.
Each I2C port supports:
•
•
•
•
•
•
•
Compatible with Philips® I2C Specification Revision 2.1 (January 2000)
Fast Mode up to 400 Kbps (no fail-safe I/O buffers)
Noise Filter to Remove Noise 50 ns or less
Seven- and Ten-Bit Device Addressing Modes
Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality
Events: DMA, Interrupt, or Polling
General-Purpose I/O Capability if not used as I2C
Clock Prescaler
I2CPSCx
Control
I2CCOARx
Prescaler
Register
Own Address
Register
Slave Address
Register
I2CSARx
Bit Clock Generator
I2CCLKHx
Noise
Filter
I2Cx_SCL
Clock Divide
High Register
I2CCMDRx
I2CEMDRx
I2CCNTx
I2CPID1
Mode Register
Extended Mode
Register
Clock Divide
Low Register
I2CCLKLx
Data Count
Register
Peripheral
Configuration
Bus
Transmit
I2CXSRx
Peripheral ID
Register 1
Transmit Shift
Register
Peripheral ID
Register 2
I2CPID2
I2CDXRx
Transmit Buffer
Noise
Filter
I2Cx_SDA
Interrupt/DMA
Interrupt Enable
Register
Receive
I2CIERx
Interrupt DMA
Requests
Receive Buffer
I2CDRRx
Interrupt Status
Register
I2CSTRx
I2CSRCx
Receive Shift
Register
Interrupt Source
Register
I2CRSRx
Control
Pin Function
Register
Pin Data Out
Register
I2CPDOUT
I2CPFUNC
Pin Direction
Register
Pin Data In
Register
Pin Data Set
Register
Pin Data Clear
Register
I2CPDIR
I2CPDIN
I2CPDSET
I2CPDCLR
Figure 6-61. I2C Module Block Diagram
6.24.2 I2C Peripheral Registers Description(s)
Table 6-83 is the list of the I2C registers.
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Table 6-83. Inter-Integrated Circuit (I2C) Registers
I2C0
I2C1
Acronym
Register Description
BYTE ADDRESS
0x01C2 2000
0x01C2 2004
0x01C2 2008
0x01C2 200C
0x01C2 2010
0x01C2 2014
0x01C2 2018
0x01C2 201C
0x01C2 2020
0x01C2 2024
0x01C2 2028
0x01C2 202C
0x01C2 2030
0x01C2 2034
0x01C2 2038
0x01C2 2048
0x01C2 204C
0x01C2 2050
0x01C2 2054
0x01C2 2058
0x01C2 205C
BYTE ADDRESS
0x01E2 8000
0x01E2 8004
0x01E2 8008
0x01E2 800C
0x01E2 8010
0x01E2 8014
0x01E2 8018
0x01E2 801C
0x01E2 8020
0x01E2 8024
0x01E2 8028
0x01E2 802C
0x01E2 8030
0x01E2 8034
0x01E2 8038
0x01E2 8048
0x01E2 804C
0x01E2 8050
0x01E2 8054
0x01E2 8058
0x01E2 805C
ICOAR
I2C Own Address Register
I2C Interrupt Mask Register
I2C Interrupt Status Register
I2C Clock Low-Time Divider Register
I2C Clock High-Time Divider Register
I2C Data Count Register
ICIMR
ICSTR
ICCLKL
ICCLKH
ICCNT
ICDRR
I2C Data Receive Register
I2C Slave Address Register
I2C Data Transmit Register
I2C Mode Register
ICSAR
ICDXR
ICMDR
ICIVR
I2C Interrupt Vector Register
I2C Extended Mode Register
I2C Prescaler Register
ICEMDR
ICPSC
REVID1
REVID2
ICPFUNC
ICPDIR
ICPDIN
ICPDOUT
ICPDSET
ICPDCLR
I2C Revision Identification Register 1
I2C Revision Identification Register 2
I2C Pin Function Register
I2C Pin Direction Register
I2C Pin Data In Register
I2C Pin Data Out Register
I2C Pin Data Set Register
I2C Pin Data Clear Register
6.24.3 I2C Electrical Data/Timing
6.24.3.1 Inter-Integrated Circuit (I2C) Timing
Table 6-84 and Table 6-85 assume testing over recommended operating conditions (see Figure 6-62 and
Figure 6-63).
Table 6-84. I2C Input Timing Requirements
NO.
MIN
10
MAX UNIT
Standard Mode
Fast Mode
1
tc(SCL)
Cycle time, I2Cx_SCL
µs
2.5
4.7
0.6
4
Standard Mode
Fast Mode
Setup time, I2Cx_SCL high before I2Cx_SDA
low
2
3
4
5
6
7
8
tsu(SCLH-SDAL)
th(SCLL-SDAL)
tw(SCLL)
µs
µs
µs
µs
ns
Standard Mode
Fast Mode
Hold time, I2Cx_SCL low after I2Cx_SDA low
Pulse duration, I2Cx_SCL low
0.6
4.7
1.3
4
Standard Mode
Fast Mode
Standard Mode
Fast Mode
tw(SCLH)
Pulse duration, I2Cx_SCL high
0.6
250
100
0
Standard Mode
Fast Mode
tsu(SDA-SCLH)
th(SDA-SCLL)
tw(SDAH)
Setup time, I2Cx_SDA before I2Cx_SCL high
Hold time, I2Cx_SDA after I2Cx_SCL low
Pulse duration, I2Cx_SDA high
Standard Mode
Fast Mode
µs
0
0.9
Standard Mode
Fast Mode
4.7
1.3
µs
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Table 6-84. I2C Input Timing Requirements (continued)
NO.
MIN
20 + 0.1Cb
20 + 0.1Cb
20 + 0.1Cb
MAX UNIT
Standard Mode
Fast Mode
1000
ns
9
tr(SDA)
Rise time, I2Cx_SDA
Rise time, I2Cx_SCL
Fall time, I2Cx_SDA
Fall time, I2Cx_SCL
300
Standard Mode
Fast Mode
1000
ns
10
11
12
13
14
15
tr(SCL)
300
Standard Mode
Fast Mode
300
ns
tf(SDA)
300
Standard Mode
Fast Mode
300
ns
tf(SCL)
20 + 0.1Cb
300
Standard Mode
Fast Mode
4
0.6
N/A
0
Setup time, I2Cx_SCL high before I2Cx_SDA
high
tsu(SCLH-SDAH)
µs
Standard Mode
Fast Mode
tw(SP)
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
ns
50
Standard Mode
Fast Mode
400
pF
Cb
400
Table 6-85. I2C Switching Characteristics(1)
NO.
PARAMETER
MIN
10
2.5
4.7
0.6
4
MAX UNIT
Standard Mode
16
tc(SCL)
Cycle time, I2Cx_SCL
µs
Fast Mode
Standard Mode
Fast Mode
Setup time, I2Cx_SCL high before I2Cx_SDA
low
17
18
19
20
21
22
23
28
tsu(SCLH-SDAL)
th(SDAL-SCLL)
tw(SCLL)
µs
µs
µs
µs
ns
Standard Mode
Fast Mode
Hold time, I2Cx_SCL low after I2Cx_SDA low
Pulse duration, I2Cx_SCL low
0.6
4.7
1.3
4
Standard Mode
Fast Mode
Standard Mode
Fast Mode
tw(SCLH)
Pulse duration, I2Cx_SCL high
0.6
250
100
0
Standard Mode
Fast Mode
Setup time, I2Cx_SDA valid before I2Cx_SCL
high
tsu(SDAV-SCLH)
th(SCLL-SDAV)
tw(SDAH)
Standard Mode
Fast Mode
Hold time, I2Cx_SDA valid after I2Cx_SCL low
Pulse duration, I2Cx_SDA high
µs
0
0.9
Standard Mode
Fast Mode
4.7
1.3
4
µs
µs
Standard Mode
Fast Mode
Setup time, I2Cx_SCL high before I2Cx_SDA
high
tsu(SCLH-SDAH)
0.6
(1) I2C must be configured correctly to meet the timings in Table 6-85.
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11
9
I2Cx_SDA
6
8
14
4
13
5
10
I2Cx_SCL
1
12
3
2
7
3
Stop
Start
Repeated
Start
Stop
Figure 6-62. I2C Receive Timings
26
24
I2Cx_SDA
I2Cx_SCL
21
23
19
28
20
25
16
27
18
17
22
18
Stop
Start
Repeated
Start
Stop
Figure 6-63. I2C Transmit Timings
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6.25 Universal Asynchronous Receiver/Transmitter (UART)
OMAP-L137 has 3 UART peripherals. Each UART has the following features:
•
•
•
•
•
•
•
•
•
16-byte storage space for both the transmitter and receiver FIFOs
1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA
DMA signaling capability for both received and transmitted data
Programmable auto-rts and auto-cts for autoflow control
Programmable Baud Rate up to 3MBaud
Programmable Oversampling Options of x13 and x16
Frequency pre-scale values from 1 to 65,535 to generate appropriate baud rates
Prioritized interrupts
Programmable serial data formats
–
–
–
5, 6, 7, or 8-bit characters
Even, odd, or no parity bit generation and detection
1, 1.5, or 2 stop bit generation
•
•
•
False start bit detection
Line break generation and detection
Internal diagnostic capabilities
–
–
Loopback controls for communications link fault isolation
Break, parity, overrun, and framing error simulation
•
Modem control functions (CTS, RTS) on UART0 only.
The UART registers are listed in Section 6.25.1
6.25.1 UART Peripheral Registers Description(s)
Table 6-86 is the list of UART registers.
Table 6-86. UART Registers
UART0
UART1
UART2
REGISTER NAME Register Description
BYTE ADDRESS
BYTE ADDRESS
BYTE ADDRESS
0x01D0 D000
0x01D0 D000
0x01D0 D004
0x01D0 D008
0x01D0 D008
0x01D0 D00C
0x01D0 D010
0x01D0 D014
0x01D0 D020
0x01D0 D024
0x01D0 D028
0x01D0 D030
0x01D0 D034
0x01C4 2000
0x01C4 2000
0x01C4 2004
0x01C4 2008
0x01C4 2008
0x01C4 200C
0x01C4 2010
0x01C4 2014
0x01C4 2020
0x01C4 2024
0x01C4 2028
0x01C4 2030
0x01C4 2034
0x01D0 C000
0x01D0 C000
0x01D0 C004
0x01D0 C008
0x01D0 C008
0x01D0 C00C
0x01D0 C010
0x01D0 C014
0x01D0 C020
0x01D0 C024
0x01D0 C028
0x01D0 C030
0x01D0 C034
RBR
THR
IER
Receiver Buffer Register (read only)
Transmitter Holding Register (write only)
Interrupt Enable Register
IIR
Interrupt Identification Register (read only)
FIFO Control Register (write only)
Line Control Register
FCR
LCR
MCR
LSR
DLL
Modem Control Register
Line Status Register
Divisor LSB Latch
DLH
REVID1
Divisor MSB Latch
Revision Identification Register 1
PWREMU_MGMT Power and Emulation Management Register
MDR Mode Definition Register
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6.25.2 UART Electrical Data/Timing
Table 6-87. Timing Requirements for UARTx Receive(1) (see Figure 6-64)
NO.
UNIT
MIN
0.96U
0.96U
MAX
1.05U
1.05U
4
5
tw(URXDB)
tw(URXSB)
Pulse duration, receive data bit (RXDn)
Pulse duration, receive start bit
ns
ns
(1) U = UART baud time = 1/programmed baud rate.
Table 6-88. Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit(1)
(see Figure 6-64)
NO.
PARAMETER
UNIT
MIN
MAX
1
2
3
f(baud)
Maximum programmable baud rate
Pulse duration, transmit data bit (TXDn)
Pulse duration, transmit start bit
3
MBaud
ns
tw(UTXDB)
tw(UTXSB)
U - 2
U - 2
U + 2
U + 2
ns
(1) U = UART baud time = 1/programmed baud rate.
3
2
Start
Bit
UART_TXDn
Data Bits
5
4
Start
Bit
UART_RXDn
Data Bits
Figure 6-64. UART Transmit/Receive Timing
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6.26 USB1 Host Controller Registers (USB1.1 OHCI)
All OMAP-L137 USB interfaces are compliant with Universal Serial Bus Specifications, Revision 1.1.
Table 6-89 is the list of USB Host Controller registers.
Table 6-89. USB Host Controller Registers
USB
REGISTER NAME
Register Description
BYTE ADDRESS
0x01E2 5000
0x01E2 5004
0x01E2 5008
0x01E2 500C
0x01E2 5010
0x01E2 5014
0x01E2 5018
0x01E2 501C
0x01E2 5020
0x01E2 5024
0x01E2 5028
0x01E2 502C
0x01E2 5030
0x01E2 5034
0x01E2 5038
0x01E2 503C
0x01E2 5040
0x01E2 5044
0x01E2 5048
0x01E2 504C
0x01E2 5050
0x01E2 5054
0x01E2 5058
HCREVISION
OHCI Revision Number Register
HC Operating Mode Register
HC Command and Status Register
HC Interrupt and Status Register
HC Interrupt Enable Register
HC Interrupt Disable Register
HC HCAA Address Register(1)
HC Current Periodic Register(1)
HC Head Control Register(1)
HC Current Control Register(1)
HC Head Bulk Register(1)
HCCONTROL
HCCOMMANDSTATUS
HCINTERRUPTSTATUS
HCINTERRUPTENABLE
HCINTERRUPTDISABLE
HCHCCA
HCPERIODCURRENTED
HCCONTROLHEADED
HCCONTROLCURRENTED
HCBULKHEADED
HCBULKCURRENTED
HCDONEHEAD
HC Current Bulk Register(1)
HC Head Done Register(1)
HCFMINTERVAL
HC Frame Interval Register
HCFMREMAINING
HCFMNUMBER
HC Frame Remaining Register
HC Frame Number Register
HC Periodic Start Register
HCPERIODICSTART
HCLSTHRESHOLD
HCRHDESCRIPTORA
HCRHDESCRIPTORB
HCRHSTATUS
HC Low-Speed Threshold Register
HC Root Hub A Register
HC Root Hub B Register
HC Root Hub Status Register
HC Port 1 Status and Control Register(2)
HC Port 2 Status and Control Register(3)
HCRHPORTSTATUS1
HCRHPORTSTATUS2
(1) Restrictions apply to the physical addresses used in these registers.
(2) Connected to the integrated USB1.1 phy pins (USB1_DM, USB1_DP).
(3) Although the controller implements two ports, the second port cannot be used.
Table 6-90. Switching Characteristics Over Recommended Operating Conditions for USB
LOW SPEED
FULL SPEED
NO.
PARAMETER
UNIT
MIN
MAX
300(1)
300(1)
120(2)
2(1)
MAX
MAX
20(1)
20(1)
110(2)
2(1)
U1
U2
U3
U4
U5
U6
tr
Rise time, USB.DP and USB.DM signals(1)
Fall time, USB.DP and USB.DM signals(1)
Rise/Fall time matching(2)
Output signal cross-over voltage(1)
Differential propagation jitter(3)
Operating frequency(4)
75(1)
75(1)
80(2)
1.3(1)
-25(3)
4(1)
4(1)
90(2)
1.3(1)
-2(3)
ns
ns
tf
tRFM
VCRS
tj
%
V
25(3)
2(3)
ns
fop
1.5
12
MHz
(1) Low Speed: CL = 200 pF. High Speed: CL = 50pF
(2) tRFM =( tr/tf ) x 100
(3) t jr = t px(1) - tpx(0)
(4) fop = 1/tper
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6.27 USB0 OTG (USB2.0 OTG)
The OMAP-L137 USB2.0 peripheral supports the following features:
•
•
•
•
•
USB 2.0 peripheral at speeds high speed (HS: 480 Mb/s) and full speed (FS: 12 Mb/s)
USB 2.0 host at speeds HS, FS, and low speed (LS: 1.5 Mb/s)
All transfer modes (control, bulk, interrupt, and isochronous)
4 Transmit (TX) and 4 Receive (RX) endpoints in addition to endpoint 0
FIFO RAM
–
–
4K endpoint
Programmable size
•
•
•
Integrated USB 2.0 High Speed PHY
Connects to a standard Charge Pump for VBUS 5 V generation
RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB
Table 6-91 is the list of USB OTG registers.
Table 6-91. Universal Serial Bus OTG (USB0) Registers
BYTE ADDRESS
0x01E0 0000
0x01E0 0004
0x01E0 0008
0x01E0 000C
0x01E0 0010
0x01E0 0014
0x01E0 0018
0x01E0 001C
0x01E0 0020
0x01E0 0024
0x01E0 0028
0x01E0 002C
0x01E0 0030
0x01E0 0034
0x01E0 0038
0x01E0 003C
0x01E0 0040
0x01E0 0050
0x01E0 0054
0x01E0 0058
0x01E0 005C
0x01E0 0400
0x01E0 0401
0x01E0 0402
0x01E0 0404
0x01E0 0406
0x01E0 0408
0x01E0 040A
0x01E0 040B
0x01E0 040C
0x01E0 040E
0x01E0 040F
Acronym
Register Description
REVID
CTRLR
Revision Register
Control Register
STATR
Status Register
EMUR
Emulation Register
MODE
Mode Register
AUTOREQ
SRPFIXTIME
TEARDOWN
INTSRCR
INTSETR
Autorequest Register
SRP Fix Time Register
Teardown Register
USB Interrupt Source Register
USB Interrupt Source Set Register
USB Interrupt Source Clear Register
USB Interrupt Mask Register
INTCLRR
INTMSKR
INTMSKSETR
INTMSKCLRR
INTMASKEDR
EOIR
USB Interrupt Mask Set Register
USB Interrupt Mask Clear Register
USB Interrupt Source Masked Register
USB End of Interrupt Register
USB Interrupt Vector Register
Generic RNDIS Size EP1
INTVECTR
GENRNDISSZ1
GENRNDISSZ2
GENRNDISSZ3
GENRNDISSZ4
FADDR
Generic RNDIS Size EP2
Generic RNDIS Size EP3
Generic RNDIS Size EP4
Function Address Register
POWER
Power Management Register
INTRTX
Interrupt Register for Endpoint 0 plus Transmit Endpoints 1 to 4
Interrupt Register for Receive Endpoints 1 to 4
Interrupt enable register for INTRTX
Interrupt Enable Register for INTRRX
Interrupt Register for Common USB Interrupts
Interrupt Enable Register for INTRUSB
Frame Number Register
INTRRX
INTRTXE
INTRRXE
INTRUSB
INTRUSBE
FRAME
INDEX
Index Register for Selecting the Endpoint Status and Control Registers
Register to Enable the USB 2.0 Test Modes
TESTMODE
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Table 6-91. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
Acronym
Register Description
Indexed Registers
These registers operate on the endpoint selected by the INDEX register
0x01E0 0410
0x01E0 0412
TXMAXP
PERI_CSR0
HOST_CSR0
PERI_TXCSR
HOST_TXCSR
RXMAXP
Maximum Packet Size for Peripheral/Host Transmit Endpoint (Index
register set to select Endpoints 1-4 only)
Control Status Register for Endpoint 0 in Peripheral Mode. (Index
register set to select Endpoint 0)
Control Status Register for Endpoint 0 in Host Mode.
(Index register set to select Endpoint 0)
Control Status Register for Peripheral Transmit Endpoint. (Index
register set to select Endpoints 1-4)
Control Status Register for Host Transmit Endpoint.
(Index register set to select Endpoints 1-4)
0x01E0 0414
0x01E0 0416
Maximum Packet Size for Peripheral/Host Receive Endpoint (Index
register set to select Endpoints 1-4 only)
PERI_RXCSR
HOST_RXCSR
COUNT0
Control Status Register for Peripheral Receive Endpoint. (Index register
set to select Endpoints 1-4)
Control Status Register for Host Receive Endpoint.
(Index register set to select Endpoints 1-4)
0x01E0 0418
0x01E0 041A
0x01E0 041B
Number of Received Bytes in Endpoint 0 FIFO.
(Index register set to select Endpoint 0)
RXCOUNT
Number of Bytes in Host Receive Endpoint FIFO.
(Index register set to select Endpoints 1- 4)
HOST_TYPE0
Defines the speed of Endpoint 0
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Transmit endpoint. (Index register set to select
Endpoints 1-4 only)
HOST_NAKLIMIT0
Sets the NAK response timeout on Endpoint 0.
(Index register set to select Endpoint 0)
HOST_TXINTERVAL
Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Transmit endpoint.
(Index register set to select Endpoints 1-4 only)
0x01E0 041C
0x01E0 041D
0x01E0 041F
HOST_RXTYPE
HOST_RXINTERVAL
CONFIGDATA
Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Receive endpoint. (Index register set to select
Endpoints 1-4 only)
Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Receive endpoint.
(Index register set to select Endpoints 1-4 only)
Returns details of core configuration. (Index register set to select
Endpoint 0)
FIFO
0x01E0 0420
0x01E0 0424
0x01E0 0428
0x01E0 042C
0x01E0 0430
FIFO0
FIFO1
FIFO2
FIFO3
FIFO4
Transmit and Receive FIFO Register for Endpoint 0
Transmit and Receive FIFO Register for Endpoint 1
Transmit and Receive FIFO Register for Endpoint 2
Transmit and Receive FIFO Register for Endpoint 3
Transmit and Receive FIFO Register for Endpoint 4
OTG Device Control
0x01E0 0460
DEVCTL
Device Control Register
Dynamic FIFO Control
0x01E0 0462
0x01E0 0463
0x01E0 0464
0x01E0 0464
TXFIFOSZ
RXFIFOSZ
TXFIFOADDR
HWVERS
Transmit Endpoint FIFO Size
(Index register set to select Endpoints 1-4 only)
Receive Endpoint FIFO Size
(Index register set to select Endpoints 1-4 only)
Transmit Endpoint FIFO Address
(Index register set to select Endpoints 1-4 only)
Hardware Version Register
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Table 6-91. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
Acronym
Register Description
0x01E0 0466
RXFIFOADDR
Receive Endpoint FIFO Address
(Index register set to select Endpoints 1-4 only)
Target Endpoint 0 Control Registers, Valid Only in Host Mode
0x01E0 0480
0x01E0 0482
TXFUNCADDR
Address of the target function that has to be accessed through the
associated Transmit Endpoint.
TXHUBADDR
Address of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 0483
TXHUBPORT
Port of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 0484
0x01E0 0486
RXFUNCADDR
RXHUBADDR
Address of the target function that has to be accessed through the
associated Receive Endpoint.
Address of the hub that has to be accessed through the associated
Receive Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 0487
RXHUBPORT
Port of the hub that has to be accessed through the associated Receive
Endpoint. This is used only when full speed or low speed device is
connected via a USB2.0 high-speed hub.
Target Endpoint 1 Control Registers, Valid Only in Host Mode
0x01E0 0488
0x01E0 048A
TXFUNCADDR
Address of the target function that has to be accessed through the
associated Transmit Endpoint.
TXHUBADDR
Address of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 048B
TXHUBPORT
Port of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 048C
0x01E0 048E
RXFUNCADDR
RXHUBADDR
Address of the target function that has to be accessed through the
associated Receive Endpoint.
Address of the hub that has to be accessed through the associated
Receive Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 048F
RXHUBPORT
Port of the hub that has to be accessed through the associated Receive
Endpoint. This is used only when full speed or low speed device is
connected via a USB2.0 high-speed hub.
Target Endpoint 2 Control Registers, Valid Only in Host Mode
0x01E0 0490
0x01E0 0492
TXFUNCADDR
Address of the target function that has to be accessed through the
associated Transmit Endpoint.
TXHUBADDR
Address of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 0493
TXHUBPORT
Port of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 0494
0x01E0 0496
RXFUNCADDR
RXHUBADDR
Address of the target function that has to be accessed through the
associated Receive Endpoint.
Address of the hub that has to be accessed through the associated
Receive Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 0497
0x01E0 0498
RXHUBPORT
Port of the hub that has to be accessed through the associated Receive
Endpoint. This is used only when full speed or low speed device is
connected via a USB2.0 high-speed hub.
Target Endpoint 3 Control Registers, Valid Only in Host Mode
TXFUNCADDR Address of the target function that has to be accessed through the
associated Transmit Endpoint.
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Table 6-91. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
Acronym
Register Description
0x01E0 049A
TXHUBADDR
Address of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 049B
TXHUBPORT
Port of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 049C
0x01E0 049E
RXFUNCADDR
RXHUBADDR
Address of the target function that has to be accessed through the
associated Receive Endpoint.
Address of the hub that has to be accessed through the associated
Receive Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 049F
RXHUBPORT
Port of the hub that has to be accessed through the associated Receive
Endpoint. This is used only when full speed or low speed device is
connected via a USB2.0 high-speed hub.
Target Endpoint 4 Control Registers, Valid Only in Host Mode
0x01E0 04A0
0x01E0 04A2
TXFUNCADDR
Address of the target function that has to be accessed through the
associated Transmit Endpoint.
TXHUBADDR
Address of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 04A3
TXHUBPORT
Port of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 04A4
0x01E0 04A6
RXFUNCADDR
RXHUBADDR
Address of the target function that has to be accessed through the
associated Receive Endpoint.
Address of the hub that has to be accessed through the associated
Receive Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 04A7
RXHUBPORT
Port of the hub that has to be accessed through the associated Receive
Endpoint. This is used only when full speed or low speed device is
connected via a USB2.0 high-speed hub.
Control and Status Register for Endpoint 0
0x01E0 0502
PERI_CSR0
HOST_CSR0
COUNT0
Control Status Register for Endpoint 0 in Peripheral Mode
Control Status Register for Endpoint 0 in Host Mode
Number of Received Bytes in Endpoint 0 FIFO
Defines the Speed of Endpoint 0
0x01E0 0508
0x01E0 050A
0x01E0 050B
0x01E0 050F
HOST_TYPE0
HOST_NAKLIMIT0
CONFIGDATA
Sets the NAK Response Timeout on Endpoint 0
Returns details of core configuration.
Control and Status Register for Endpoint 1
0x01E0 0510
0x01E0 0512
TXMAXP
Maximum Packet Size for Peripheral/Host Transmit Endpoint
PERI_TXCSR
Control Status Register for Peripheral Transmit Endpoint (peripheral
mode)
HOST_TXCSR
Control Status Register for Host Transmit Endpoint
(host mode)
0x01E0 0514
0x01E0 0516
RXMAXP
Maximum Packet Size for Peripheral/Host Receive Endpoint
PERI_RXCSR
Control Status Register for Peripheral Receive Endpoint (peripheral
mode)
HOST_RXCSR
Control Status Register for Host Receive Endpoint
(host mode)
0x01E0 0518
0x01E0 051A
RXCOUNT
Number of Bytes in Host Receive endpoint FIFO
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Transmit endpoint.
0x01E0 051B
HOST_TXINTERVAL
Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Transmit endpoint.
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Table 6-91. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
Acronym
Register Description
0x01E0 051C
HOST_RXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Receive endpoint.
0x01E0 051D
HOST_RXINTERVAL
Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Receive endpoint.
Control and Status Register for Endpoint 2
0x01E0 0520
0x01E0 0522
TXMAXP
Maximum Packet Size for Peripheral/Host Transmit Endpoint
PERI_TXCSR
Control Status Register for Peripheral Transmit Endpoint (peripheral
mode)
HOST_TXCSR
Control Status Register for Host Transmit Endpoint
(host mode)
0x01E0 0524
0x01E0 0526
RXMAXP
Maximum Packet Size for Peripheral/Host Receive Endpoint
PERI_RXCSR
Control Status Register for Peripheral Receive Endpoint (peripheral
mode)
HOST_RXCSR
Control Status Register for Host Receive Endpoint
(host mode)
0x01E0 0528
0x01E0 052A
RXCOUNT
Number of Bytes in Host Receive endpoint FIFO
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Transmit endpoint.
0x01E0 052B
0x01E0 052C
0x01E0 052D
HOST_TXINTERVAL
HOST_RXTYPE
Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Transmit endpoint.
Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Receive endpoint.
HOST_RXINTERVAL
Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Receive endpoint.
Control and Status Register for Endpoint 3
0x01E0 0530
0x01E0 0532
TXMAXP
Maximum Packet Size for Peripheral/Host Transmit Endpoint
PERI_TXCSR
Control Status Register for Peripheral Transmit Endpoint (peripheral
mode)
HOST_TXCSR
Control Status Register for Host Transmit Endpoint
(host mode)
0x01E0 0534
0x01E0 0536
RXMAXP
Maximum Packet Size for Peripheral/Host Receive Endpoint
PERI_RXCSR
Control Status Register for Peripheral Receive Endpoint (peripheral
mode)
HOST_RXCSR
Control Status Register for Host Receive Endpoint
(host mode)
0x01E0 0538
0x01E0 053A
RXCOUNT
Number of Bytes in Host Receive endpoint FIFO
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Transmit endpoint.
0x01E0 053B
0x01E0 053C
0x01E0 053D
HOST_TXINTERVAL
HOST_RXTYPE
Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Transmit endpoint.
Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Receive endpoint.
HOST_RXINTERVAL
Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Receive endpoint.
Control and Status Register for Endpoint 4
0x01E0 0540
0x01E0 0542
TXMAXP
Maximum Packet Size for Peripheral/Host Transmit Endpoint
PERI_TXCSR
Control Status Register for Peripheral Transmit Endpoint (peripheral
mode)
HOST_TXCSR
RXMAXP
Control Status Register for Host Transmit Endpoint
(host mode)
0x01E0 0544
Maximum Packet Size for Peripheral/Host Receive Endpoint
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Table 6-91. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
Acronym
Register Description
0x01E0 0546
PERI_RXCSR
Control Status Register for Peripheral Receive Endpoint (peripheral
mode)
HOST_RXCSR
Control Status Register for Host Receive Endpoint
(host mode)
0x01E0 0548
0x01E0 054A
RXCOUNT
Number of Bytes in Host Receive endpoint FIFO
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Transmit endpoint.
0x01E0 054B
0x01E0 054C
0x01E0 054D
HOST_TXINTERVAL
HOST_RXTYPE
Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Transmit endpoint.
Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Receive endpoint.
HOST_RXINTERVAL
Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Receive endpoint.
DMA Registers
0x01E0 1000
0x01E0 1004
0x01E0 1008
0x01E0 1800
0x01E0 1808
0x01E0 180C
0x01E0 1810
0x01E0 1820
0x01E0 1828
0x01E0 182C
0x01E0 1830
0x01E0 1840
0x01E0 1848
0x01E0 184C
0x01E0 1850
0x01E0 1860
0x01E0 1868
0x01E0 186C
0x01E0 1870
0x01E0 2C00
0x01E0 2D00
0x01E0 2D04
. . .
DMAREVID
TDFDQ
DMA Revision Register
DMA Teardown Free Descriptor Queue Control Register
DMA Emulation Control Register
DMAEMU
TXGCR[0]
Transmit Channel 0 Global Configuration Register
Receive Channel 0 Global Configuration Register
Receive Channel 0 Host Packet Configuration Register A
Receive Channel 0 Host Packet Configuration Register B
Transmit Channel 1 Global Configuration Register
Receive Channel 1 Global Configuration Register
Receive Channel 1 Host Packet Configuration Register A
Receive Channel 1 Host Packet Configuration Register B
Transmit Channel 2 Global Configuration Register
Receive Channel 2 Global Configuration Register
Receive Channel 2 Host Packet Configuration Register A
Receive Channel 2 Host Packet Configuration Register B
Transmit Channel 3 Global Configuration Register
Receive Channel 3 Global Configuration Register
Receive Channel 3 Host Packet Configuration Register A
Receive Channel 3 Host Packet Configuration Register B
DMA Scheduler Control Register
RXGCR[0]
RXHPCRA[0]
RXHPCRB[0]
TXGCR[1]
RXGCR[1]
RXHPCRA[1]
RXHPCRB[1]
TXGCR[2]
RXGCR[2]
RXHPCRA[2]
RXHPCRB[2]
TXGCR[3]
RXGCR[3]
RXHPCRA[3]
RXHPCRB[3]
DMA_SCHED_CTRL
ENTRY[0]
DMA Scheduler Table Word 0
ENTRY[1]
DMA Scheduler Table Word 1
. . .
. . .
0x01E0 2DFC
ENTRY[63]
DMA Scheduler Table Word 63
Queue Manager Registers
0x01E0 4000
0x01E0 4008
0x01E0 4020
0x01E0 4024
0x01E0 4028
0x01E0 402C
0x01E0 4080
0x01E0 4084
0x01E0 4088
0x01E0 4090
QMGRREVID
DIVERSION
FDBSC0
Queue Manager Revision Register
Queue Diversion Register
Free Descriptor/Buffer Starvation Count Register 0
Free Descriptor/Buffer Starvation Count Register 1
Free Descriptor/Buffer Starvation Count Register 2
Free Descriptor/Buffer Starvation Count Register 3
Linking RAM Region 0 Base Address Register
Linking RAM Region 0 Size Register
FDBSC1
FDBSC2
FDBSC3
LRAM0BASE
LRAM0SIZE
LRAM1BASE
PEND0
Linking RAM Region 1 Base Address Register
Queue Pending Register 0
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Table 6-91. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
Acronym
PEND1
Register Description
Queue Pending Register 1
0x01E0 4094
0x01E0 5000
0x01E0 5004
0x01E0 5010
0x01E0 5014
. . .
QMEMRBASE[0]
QMEMRCTRL[0]
QMEMRBASE[1]
QMEMRCTRL[1]
. . .
Memory Region 0 Base Address Register
Memory Region 0 Control Register
Memory Region 1 Base Address Register
Memory Region 1 Control Register
. . .
0x01E0 5070
0x01E0 5074
0x01E0 600C
0x01E0 601C
. . .
QMEMRBASE[7]
QMEMRCTRL[7]
CTRLD[0]
Memory Region 7 Base Address Register
Memory Region 7 Control Register
Queue Manager Queue 0 Control Register D
Queue Manager Queue 1 Control Register D
. . .
CTRLD[1]
. . .
0x01E0 63FC
0x01E0 6800
0x01E0 6804
0x01E0 6808
0x01E0 6810
0x01E0 6814
0x01E0 6818
. . .
CTRLD[63]
QSTATA[0]
QSTATB[0]
QSTATC[0]
QSTATA[1]
QSTATB[1]
QSTATC[1]
. . .
Queue Manager Queue 63 Status Register D
Queue Manager Queue 0 Status Register A
Queue Manager Queue 0 Status Register B
Queue Manager Queue 0 Status Register C
Queue Manager Queue 1 Status Register A
Queue Manager Queue 1 Status Register B
Queue Manager Queue 1 Status Register C
. . .
0x01E0 6BF0
0x01E0 6BF4
0x01E0 6BF8
QSTATA[63]
QSTATB[63]
QSTATC[63]
Queue Manager Queue 63 Status Register A
Queue Manager Queue 63 Status Register B
Queue Manager Queue 63 Status Register C
6.27.1 USB2.0 Electrical Data/Timing
Table 6-92. Switching Characteristics Over Recommended Operating Conditions for USB2.0 (see
Figure 6-65)
LOW SPEED
1.5 Mbps
FULL SPEED
12 Mbps
HIGH SPEED
480 Mbps
NO.
PARAMETER
UNIT
MIN
75
MAX
MIN
4
MAX
MIN
0.5
0.5
–
MAX
1
2
3
4
5
tr(D)
Rise time, USB_DP and USB_DM signals(1)
Fall time, USB_DP and USB_DM signals(1)
Rise/Fall time, matching(2)
Output signal cross-over voltage(1)
Source (Host) Driver jitter, next transition
Function Driver jitter, next transition
Source (Host) Driver jitter, paired transition(4)
Function Driver jitter, paired transition
Pulse duration, EOP transmitter
Pulse duration, EOP receiver
300
300
120
2
20
20
111
2
ns
ns
%
tf(D)
75
4
trfM
80
90
1.3
–
–
VCRS
1.3
–
V
tjr(source)NT
tjr(FUNC)NT
tjr(source)PT
tjr(FUNC)PT
tw(EOPT)
tw(EOPR)
t(DRATE)
2
2
(3)ns
ns
ns
ns
ns
ns
(3)
(3)
(3)
25
2
6
1
1
10
1
7
8
9
1250
670
1500
160
82
175
–
–
–
Data Rate
1.5
–
12
480 Mb/s
10 ZDRV
11 ZINP
Driver Output Resistance
–
40.5
49.5
40.5
-
49.5
-
Ω
Ω
Receiver Input Impedance
100k
100k
(1) Low Speed: CL = 200 pF, Full Speed: CL = 50 pF, High Speed: CL = 50 pF
(2) tRFM = (tr/tf) x 100. [Excluding the first transaction from the Idle state.]
(3) For more detailed information, see the Universal Serial Bus Specification Revision 2.0, Chapter 7. Electrical.
(4) tjr = tpx(1) - tpx(0)
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t
t
per − jr
USB_DM
90% V
OH
V
CRS
10% V
OL
USB_DP
t
f
t
r
Figure 6-65. USB2.0 Integrated Transceiver Interface Timing
6.32 Power and Sleep Controller (PSC)
The Power and Sleep Controllers (PSC) are responsible for managing transitions of system power on/off,
clock on/off, resets (device level and module level). It is used primarily to provide granular power control
for on chip modules (peripherals and CPU). A PSC module consists of a Global PSC (GPSC) and a set of
Local PSCs (LPSCs). The GPSC contains memory mapped registers, PSC interrupts, a state machine for
each peripheral/module it controls. An LPSC is associated with every module that is controlled by the PSC
and provides clock and reset control.
The PSC includes the following features:
•
Provides a software interface to:
–
–
–
Control module clock enable/disable
Control module reset
Control CPU local reset
•
Supports IcePick emulation features: power, clock and reset
Table 6-100. Power and Sleep Controller (PSC) Registers
PSC0
PSC1
0x01E2 7000
Register
REVID
Description
0x01C1 0000
0x01C1 0018
0x01C1 0040
Peripheral Revision and Class Information Register
Interrupt Evaluation Register
0x01E2 7018
0x01E2 7040
INTEVAL
MERRPR0
Module Error Pending Register 0 (module 0-15) (PSC0)
Module Error Pending Register 0 (module 0-31) (PSC1)
Module Error Clear Register 0 (module 0-15) (PSC0)
Module Error Clear Register 0 (module 0-31) (PSC1)
Power Error Pending Register
0x01C1 0050
0x01E2 7050
MERRCR0
0x01C1 0060
0x01C1 0068
0x01C1 0120
0x01C1 0128
0x01C1 0200
0x01C1 0204
0x01C1 0300
0x01C1 0304
0x01C1 0400
0x01C1 0404
0x01E2 7060
0x01E2 7068
0x01E2 7120
0x01E2 7128
0x01E2 7200
0x01E2 7204
0x01E2 7300
0x01E2 7304
0x01E2 7400
0x01E2 7404
PERRPR
PERRCR
PTCMD
Power Error Clear Register
Power Domain Transition Command Register
Power Domain Transition Status Register
Power Domain 0 Status Register
PTSTAT
PDSTAT0
PDSTAT1
PDCTL0
PDCTL1
PDCFG0
PDCFG1
Power Domain 1 Status Register
Power Domain 0 Control Register
Power Domain 1 Control Register
Power Domain 0 Configuration Register
Power Domain 1 Configuration Register
Module Status n Register (modules 0-15) (PSC0)
0x01C1 0800 - 0x01C1
083C
0x01E2 7800 -
0x01E2 787C
MDSTAT0-
MDSTAT15
MDSTAT0-
MDSTAT31
Module Status n Register (modules 0-31) (PSC1)
Module Control n Register (modules 0-15) (PSC0)
Module Status n Register (modules 0-31) (PSC1)
0x01C1 0A00 - 0x01C1
0A3C
0x01E2 7A00 -
0x01E2 7A7C
MDCTL0-
MDCTL15
MDSTAT0-
MDSTAT31
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6.32.1 Power Domain and Module Topology
The SoC includes two PSC modules.
Each PSC module controls clock states for several on the on chip modules, controllers and interconnect
components. Table 6-101 and Table 6-102 lists the set of peripherals/modules that are controlled by the
PSC, the power domain they are associated with, the LPSC assignment and the default (power-on reset)
module states. See the device-specific data manual for the peripherals available on a given device. The
module states and terminology are defined in Section 6.32.1.2.
Table 6-101. PSC0 Default Module Configuration
LPSC Number
Module Name
Power Domain
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
-
Default Module State
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
Enable
Auto Sleep/Wake Only
0
1
2
3
4
5
6
7
8
9
10
EDMA3 Channel Controller
EDMA3 Transfer Controller 0
EDMA3 Transfer Controller 1
EMIFA (BR7)
—
—
—
—
—
—
—
Yes
-
SPI 0
MMC/SD 0
ARM Interrupt Controller
ARM RAM/ROM
-
-
UART 0
AlwaysON (PD0)
AlwaysON (PD0)
SwRstDisable
Enable
—
Yes
SCR0
(Br 0, Br 1, Br 2, Br 8)
11
12
SCR1
(Br 4)
AlwaysON (PD0)
AlwaysON (PD0)
Enable
Enable
Yes
Yes
SCR2
(Br 3, Br 5, Br 6)
13
14
15
-
-
-
-
ARM
DSP
AlwaysON (PD0)
PD_DSP (PD1)
SwRstDisable
Enable
—
—
Table 6-102. PSC1 Default Module Configuration
LPSC Number
Module Name
Not Used
Power Domain
—
Default Module State
—
Auto Sleep/Wake Only
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
USB0 (USB2.0)
USB1 (USB1.1)
GPIO
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
—
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
—
2
3
4
UHPI
5
EMAC
6
EMIFB (Br 20)
McASP0 ( + McASP0 FIFO)
McASP1 ( + McASP1 FIFO)
McASP2( + McASP2 FIFO)
SPI 1
7
8
9
10
11
12
13
14-15
16
I2C 1
UART 1
UART 2
Not Used
LCDC
AlwaysON (PD0)
SwRstDisable
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Table 6-102. PSC1 Default Module Configuration (continued)
LPSC Number
Module Name
eHRPWM0/1/2
Not Used
Power Domain
AlwaysON (PD0)
—
Default Module State
SwRstDisable
—
Auto Sleep/Wake Only
17
—
18-19
20
—
ECAP0/1/2
EQEP0/1
AlwaysON (PD0)
AlwaysON (PD0)
—
SwRstDisable
SwRstDisable
—
—
21
—
22-23
24
Not Used
—
SCR8
AlwaysON (PD0)
Enable
Yes
(Br 15)
25
26
SCR7
(Br 12)
AlwaysON (PD0)
AlwaysON (PD0)
Enable
Enable
Yes
Yes
SCR12
(Br 18)
27-30
31
Not Used
—
—
—
Shared RAM
(Br 13)
PD_SHRAM
Enable
Yes
6.32.1.1 Power Domain States
A power domain can only be in one of the two states: ON or OFF, defined as follows:
•
•
ON: power to the domain is on
OFF: power to the domain is off
In the SoC , for both PSC0 and PSC1, the Always ON domain, or PD0 power domain, is always in the ON
state when the chip is powered-on. This domain is not programmable to OFF state.
•
•
On PSC0 PD1/PD_DSP Domain: Controls the sleep state for DSP L1 and L2 Memories
On PSC1 PD1/PD_SHRAM Domain: Controls the sleep state for the 128K Shared RAM
6.32.1.2 Module States
The PSC defines several possible states for a module. This states are essentially a combination of the
module reset asserted or de-asserted and module clock on/enabled or off/disabled. The module states are
defined in Table 6-103.
Table 6-103. Module States
Module State
Module Reset
Module Clock
Module State Definition
Enable
De-asserted
On
A module in the enable state has its module reset de-asserted and it has its
clock on. This is the normal operational state for a given module
Disable
De-asserted
Off
A module in the disabled state has its module reset de-asserted and it has its
module clock off. This state is typically used for disabling a module clock to
save power. The SoC is designed in full static CMOS, so when you stop a
module clock, it retains the module’s state. When the clock is restarted, the
module resumes operating from the stopping point.
SyncReset
Asserted
Asserted
On
Off
A module state in the SyncReset state has its module reset asserted and it has
its clock on. Generally, software is not expected to initiate this state
SwRstDisable
A module in the SwResetDisable state has its module reset asserted and it has
its clock disabled. After initial power-on, several modules come up in the
SwRstDisable state. Generally, software is not expected to initiate this state
Auto Sleep
De-asserted
Off
A module in the Auto Sleep state also has its module reset de-asserted and its
module clock disabled, similar to the Disable state. However this is a special
state, once a module is configured in this state by software, it can
“automatically” transition to “Enable” state whenever there is an internal
read/write request made to it, and after servicing the request it will
“automatically” transition into the sleep state (with module reset re de-asserted
and module clock disabled), without any software intervention. The transition
from sleep to enabled and back to sleep state has some cycle latency
associated with it. It is not envisioned to use this mode when peripherals are
fully operational and moving data.
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Table 6-103. Module States (continued)
Module State
Module Reset
Module Clock
Module State Definition
Auto Wake
De-asserted
Off
A module in the Auto Wake state also has its module reset de-asserted and its
module clock disabled, similar to the Disable state. However this is a special
state, once a module is configured in this state by software, it will
“automatically” transition to “Enable” state whenever there is an internal
read/write request made to it, and will remain in the “Enabled” state from then
on (with module reset re de-asserted and module clock on), without any
software intervention. The transition from sleep to enabled state has some
cycle latency associated with it. It is not envisioned to use this mode when
peripherals are fully operational and moving data.
6.34 Emulation Logic
This section describes the steps to use a third party debugger on the ARM926EJ-S within the
OMAP-L137. The debug capabilities and features for DSP and ARM are as shown below.
DSP:
•
•
•
Basic Debug
–
–
Execution Control
System Visibility
Real-Time Debug
–
–
Interrupts serviced while halted
Low/non-intrusive system visibility while running
Advanced Debug
–
–
–
–
Global Start
Global Stop
Specify targeted memory level(s) during memory accesses
HSRTDX (High Speed Real Time Data eXchange)
•
•
Advanced System Control
–
–
–
Subsystem reset via debug
Peripheral notification of debug events
Cache-coherent debug accesses
Security
–
–
–
–
Configurable levels of security and debug visibility
Halting on a security violation
Debug halts prevented during secure code execution
Memory accesses prevented to secure memory
•
•
Analysis Actions
–
–
–
–
–
–
Stop program execution
Generate debug interrupt
Benchmarking with counters
External trigger generation
Debug state machine state transition
Combinational and Sequential event generation
Analysis Events
–
–
–
–
–
Program event detection
Data event detection
External trigger Detection
System event detection (i.e. cache miss)
Debug state machine state detection
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•
Analysis Configuration
–
–
Application access
Debugger access
Table 6-105. DSP Debug Features
Category
Hardware Feature
Availability
Unlimited
Software breakpoint
Up to 10 HWBPs, including:
4 precise HWBPs inside DSP core and one of them is
associated with a counter.
Basic Debug
Hardware breakpoint
2 imprecise HWBPs from AET.
4 imprecise HWBPs from AET which are shared for
watch point.
Up to 4 watch points, which are shared with HWBPs,
and can also be used as 2 watch points with data (32
bits)
Watch point
Watch point with Data
Counters/timers
Up to 2, Which can also be used as 4 watch points.
Analysis
1x64-bits (cycle only) + 2x32-bits (water marke counters)
External Event Trigger In
External Event Trigger Out
2
2
ARM:
•
•
•
Basic Debug
–
–
Execution Control
System Visibility
Advanced Debug
–
–
Global Start
Global Stop
Advanced System Control
–
–
–
Subsystem reset via debug
Peripheral notification of debug events
Cache-coherent debug accesses
•
•
Security
–
–
Halting on a security violation (by cross-triggering via INTC)
Memory accesses prevented to secure memory (this is ensured by system level security
mechanism)
Program Trace
–
–
–
–
Program flow corruption
Code coverage
Path coverage
Thread/interrupt synchronization problems
•
•
•
Data Trace
–
Memory corruption
Timing Trace
–
Profiling
Analysis Actions
–
–
–
Stop program execution
Control trace streams
Generate debug interrupt
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–
–
–
–
Benchmarking with counters
External trigger generation
Debug state machine state transition
Combinational and Sequential event generation
•
•
Analysis Events
–
–
–
–
–
Program event detection
Data event detection
External trigger Detection
System event detection (i.e. cache miss)
Debug state machine state detection
Analysis Configuration
–
–
Application access
Debugger access
Table 6-106. ARM Debug Features
Category
Hardware Feature
Availability
Unlimited
Software breakpoint
Up to 14 HWBPs, including:
2 precise HWBP inside ARM core which are shared with
watch points.
Basic Debug
Hardware breakpoint
8 imprecise HWBPs from ETM’s address comparators,
which are shared with trace function, and can be used
as watch point too.
4 imprecise HWBPs from ICECrusher.
Up to 6 watch points, including:
2 from ARM core which is shared with HWBPs and can
be associated with a data.
Watch point
8 from ETM’s address comparators, which are shared
with trace function, and HWBPs.
2 from ARM core which is shared with HWBPs.
Analysis
8 watch points from ETM can be associated with a data
comparator, and ETM of Primus has total 4 data
comparators.
Watch point with Data
Counters/timers
3x32-bit (1 cycle ; 2 event)
External Event Trigger In
External Event Trigger Out
Address range for trace
2
2
4
Data qualification for trace
System events for trace control
Counters/Timers for trace control
State Machines/Sequencers
Context/Thread ID Comparator
Independent trigger control units
Capture depth PC
2
20
Trace Control
2x16-bit
1x3-State State Machine
1
12
Primus has 4k bytes ETB
Primus has 4k bytes ETB
Y
On-chip Trace
Capture
Capture depth PC + Timing
Application accessible
6.34.1 JTAG Port Description
The OMAP-L137 target debug interface uses the five standard IEEE 1149.1(JTAG) signals (TRST, TCK,
TMS, TDI, and TDO), a return clock (RTCK) due to the clocking requirements of the ARM926EJ-S and
EMU0.
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Table 6-107. JTAG Port Description
PIN
TYPE
NAME
DESCRIPTION
When asserted (active low) causes all test and debug logic in
OMAP-L137 to be reset along with the IEEE 1149.1 interface
TRST
I
Test Logic Reset
This is the test clock used to drive an IEEE 1149.1 TAP state machine
and logic. Depending on the emulator attached to OMAP-L137 , this is a
free running clock or a gated clock depending on RTCK monitoring.
TCK
I
Test Clock
Synchronized TCK. Depending on the emulator attached to OMAP-L137
, the JTAG signals are clocked from RTCK or RTCK is monitored by the
emulator to gate TCK.
RTCK
O
Returned Test Clock
TMS
TDI
I
I
Test Mode Select
Test Data Input
Test Data Output
Emulation 0
Directs the next state of the IEEE 1149.1 test access port state machine
Scan data input to the device
TDO
EMU0
O
I/O
Scan data output of the device
Channel 0 trigger + HSRTDX
6.34.2 Initial Scan Chain Configuration
The first level of debug interface that sees the scan controller is the TAP router module. The debugger
can configure the TAP router for serially linking up to 16 TAP controllers or individually scanning one of
the TAP controllers without disrupting the IR state of the other TAPs.
6.34.2.1 Adding TAPS to the Scan Chain
The TAP router must be programmed to add additional TAPs to the scan chain. The following JTAG scans
must be completed to add the ARM926EJ-S to the scan chain.
TDO
TDI
Router
CLK
TMS
Steps
Router
ARM926EJ-S/ETM
Figure 6-67. Adding ARM926EJ-S to the scan chain
Pre-amble: The device whose data reaches the emulator first is listed first in the board configuration file.
This device is a pre-amble for all the other devices. This device has the lowest device ID.
Post-amble: The device whose data reaches the emulator last is listed last in the board configuration file.
This device is a post-amble for all the other devices. This device has the highest device ID.
•
Function : Update the JTAG preamble and post-amble counts.
–
–
–
–
–
–
Parameter : The IR pre-amble count is '0'.
Parameter : The IR post-amble count is '0'.
Parameter : The DR pre-amble count is '0'.
Parameter : The DR post-amble count is '0'.
Parameter : The IR main count is '6'.
Parameter : The DR main count is '1'.
•
Function : Do a send-only JTAG IR/DR scan.
–
–
Parameter : The route to JTAG shift state is 'shortest transition'.
Parameter : The JTAG shift state is 'shift-ir'.
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–
–
–
–
Parameter : The JTAG destination state is 'pause-ir'.
Parameter : The bit length of the command is '6'.
Parameter : The send data value is '0x00000007'.
Parameter : The actual receive data is 'discarded'.
•
Function : Do a send-only JTAG IR/DR scan.
–
–
–
–
–
–
Parameter : The route to JTAG shift state is 'shortest transition'.
Parameter : The JTAG shift state is 'shift-dr'.
Parameter : The JTAG destination state is 'pause-dr'.
Parameter : The bit length of the command is '8'.
Parameter : The send data value is '0x00000089'.
Parameter : The actual receive data is 'discarded'.
•
Function : Do a send-only JTAG IR/DR scan.
–
–
–
–
–
–
Parameter : The route to JTAG shift state is 'shortest transition'.
Parameter : The JTAG shift state is 'shift-ir'.
Parameter : The JTAG destination state is 'pause-ir'.
Parameter : The bit length of the command is '6'.
Parameter : The send data value is '0x00000002'.
Parameter : The actual receive data is 'discarded'.
•
•
Function : Embed the port address in next command.
–
–
Parameter : The port address field is '0x0f000000'.
Parameter : The port address value is '3'.
Function : Do a send-only JTAG IR/DR scan.
–
–
–
–
–
–
Parameter : The route to JTAG shift state is 'shortest transition'.
Parameter : The JTAG shift state is 'shift-dr'.
Parameter : The JTAG destination state is 'pause-dr'.
Parameter : The bit length of the command is '32'.
Parameter : The send data value is '0xa3002108'.
Parameter : The actual receive data is 'discarded'.
•
Function : Do a send-only all-ones JTAG IR/DR scan.
–
–
–
–
–
Parameter : The JTAG shift state is 'shift-ir'.
Parameter : The JTAG destination state is 'run-test/idle'.
Parameter : The bit length of the command is '6'.
Parameter : The send data value is 'all-ones'.
Parameter : The actual receive data is 'discarded'.
•
•
Function : Wait for a minimum number of TCLK pulses.
Parameter : The count of TCLK pulses is '10'.
Function : Update the JTAG preamble and post-amble counts.
–
–
–
–
–
–
–
Parameter : The IR pre-amble count is '0'.
Parameter : The IR post-amble count is '6'.
Parameter : The DR pre-amble count is '0'.
Parameter : The DR post-amble count is '1'.
Parameter : The IR main count is '4'.
Parameter : The DR main count is '1'.
The initial scan chain contains only the TAP router module. The following steps must be completed in
order to add ETB TAP to the scan chain.
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ARM926EJ-S/ETM
TDI
Router
TDO
CLK
TMS
Steps
ETB
ARM926EJ-S/ETM
Router
Figure 6-68. Adding ETB to the scan chain
Function : Do a send-only JTAG IR/DR scan.
•
•
•
–
–
–
–
–
–
Parameter : The route to JTAG shift state is 'shortest transition'.
Parameter : The JTAG shift state is 'shift-ir'.
Parameter : The JTAG destination state is 'pause-ir'.
Parameter : The bit length of the command is '6'.
Parameter : The send data value is '0x00000007'.
Parameter : The actual receive data is 'discarded'.
Function : Do a send-only JTAG IR/DR scan.
–
–
–
–
–
–
Parameter : The route to JTAG shift state is 'shortest transition'.
Parameter : The JTAG shift state is 'shift-dr'.
Parameter : The JTAG destination state is 'pause-dr'.
Parameter : The bit length of the command is '8'.
Parameter : The send data value is '0x00000089'.
Parameter : The actual receive data is 'discarded'.
Function : Do a send-only JTAG IR/DR scan.
–
–
–
–
–
–
Parameter : The route to JTAG shift state is 'shortest transition'.
Parameter : The JTAG shift state is 'shift-ir'.
Parameter : The JTAG destination state is 'pause-ir'.
Parameter : The bit length of the command is '6'.
Parameter : The send data value is '0x00000002'.
Parameter : The actual receive data is 'discarded'.
•
•
Function : Embed the port address in next command.
–
–
Parameter : The port address field is '0x0f000000'.
Parameter : The port address value is '3'.
Function : Do a send-only JTAG IR/DR scan.
–
–
–
–
–
–
Parameter : The route to JTAG shift state is 'shortest transition'.
Parameter : The JTAG shift state is 'shift-dr'.
Parameter : The JTAG destination state is 'pause-dr'.
Parameter : The bit length of the command is '32'.
Parameter : The send data value is '0xa4302108'.
Parameter : The actual receive data is 'discarded'.
•
Function : Do a send-only all-ones JTAG IR/DR scan.
–
–
–
–
Parameter : The JTAG shift state is 'shift-ir'.
Parameter : The JTAG destination state is 'run-test/idle'.
Parameter : The bit length of the command is '6'.
Parameter : The send data value is 'all-ones'.
212
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–
Parameter : The actual receive data is 'discarded'.
Function : Wait for a minimum number of TCLK pulses.
Parameter : The count of TCLK pulses is '10'.
Function : Update the JTAG preamble and post-amble counts.
•
•
–
–
–
–
–
–
–
Parameter : The IR pre-amble count is '0'.
Parameter : The IR post-amble count is '6 + 4'.
Parameter : The DR pre-amble count is '0'.
Parameter : The DR post-amble count is '1 + 1'.
Parameter : The IR main count is '4'.
Parameter : The DR main count is '1'.
6.35 Real Time Clock (RTC)
The RTC provides a time reference to an application running on the device. The current date and time is
tracked in a set of counter registers that update once per second. The time can be represented in 12-hour
or 24-hour mode. The calendar and time registers are buffered during reads and writes so that updates do
not interfere with the accuracy of the time and date.
Alarms are available to interrupt the CPU at a particular time, or at periodic time intervals, such as once
per minute or once per day. In addition, the RTC can interrupt the CPU every time the calendar and time
registers are updated, or at programmable periodic intervals.
The real-time clock (RTC) provides the following features:
•
•
•
•
•
•
•
•
•
100-year calendar (xx00 to xx99)
Counts seconds, minutes, hours, day of the week, date, month, and year with leap year compensation
Binary-coded-decimal (BCD) representation of time, calendar, and alarm
12-hour clock mode (with AM and PM) or 24-hour clock mode
Alarm interrupt
Periodic interrupt
Single interrupt to the CPU
Supports external 32.768-kHz crystal or external clock source of the same frequency
Separate isolated power supply
Figure 6-69 shows a block diagram of the RTC.
Oscillator
Compensation
Week
Days
Counter
32 kHz
RTC_XI
XTAL
Hours
Days
Years
Seconds
Minutes
Months
RTC_XO
Oscillator
Alarm
Interrupts
Alarm
Periodic
Interrupts
Timer
Figure 6-69. Real-Time Clock Block Diagram
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6.35.1 Clock Source
The clock reference for the RTC is an external 32.768-kHz crystal or an external clock source of the same
frequency. The RTC also has a separate power supply that is isolated from the rest of the system. When
the CPU and other peripherals are without power, the RTC can remain powered to preserve the current
time and calendar information.
The source for the RTC reference clock may be provided by a crystal or by an external clock source. The
RTC has an internal oscillator buffer to support direct operation with a crystal. The crystal is connected
between pins RTC_XI and RTC_XO. RTC_XI is the input to the on-chip oscillator and RTC_XO is the
output from the oscillator back to the crystal.
An external 32.768-kHz clock source may be used instead of a crystal. In such a case, the clock source is
connected to RTC_XI, and RTC_XO is left unconnected.
If the RTC is not used, the RTC_XI pin should be held low and RTC_XO should be left unconnected.
Switch for Device
Core Power
+1.2V
CVDD
Real Time Clock
C2
RTC_CVDD
RTC_X1
XTAL
32.768
kHz
Real
Time
Clock
(RTC)
Module
RTC_X0
32K
OSC
C1
RTC_VSS
Isolated RTC
Power Domain
Figure 6-70. Clock Source
6.35.2 Registers
Table 6-108 lists the memory-mapped registers for the RTC. See the device-specific data manual for the
memory address of these registers.
Table 6-108. Real-Time Clock (RTC) Registers
BYTE ADDRESS
0x01C2 3000
0x01C2 3004
0x01C2 3008
0x01C2 300C
0x01C2 3010
0x01C2 3014
0x01C2 3018
0x01C2 3020
Acronym
SECOND
MINUTE
HOUR
Register Description
Seconds Register
Minutes Register
Hours Register
DAY
Day of the Month Register
Month Register
MONTH
YEAR
Year Register
DOTW
Day of the Week Register
Alarm Seconds Register
ALARMSECOND
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Table 6-108. Real-Time Clock (RTC) Registers (continued)
BYTE ADDRESS
0x01C2 3024
0x01C2 3028
0x01C2 302C
0x01C2 3030
0x01C2 3034
0x01C2 3040
0x01C2 3044
0x01C2 3048
0x01C2 304C
0x01C2 3050
0x01C2 3054
0x01C2 3060
0x01C2 3064
0x01C2 3068
0x01C2 306C
0x01C2 3070
Acronym
Register Description
ALARMMINUTE
ALARMHOUR
ALARMDAY
ALARMMONTH
ALARMYEAR
CTRL
Alarm Minutes Register
Alarm Hours Register
Alarm Days Register
Alarm Months Register
Alarm Years Register
Control Register
STATUS
Status Register
INTERRUPT
COMPLSB
COMPMSB
OSC
Interrupt Enable Register
Compensation (LSB) Register
Compensation (MSB) Register
Oscillator Register
SCRATCH0
SCRATCH1
SCRATCH2
KICK0
Scratch 0 (General-Purpose) Register
Scratch 1 (General-Purpose) Register
Scratch 2 (General-Purpose) Register
Kick 0 (Write Protect) Register
Kick 1 (Write Protect) Register
KICK1
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7 Mechanical Packaging and Orderable Information
This section describes the OMAP-L137 orderable part numbers, packaging options, materials, thermal and
mechanical parameters.
7.1 Thermal Data for ZKB
The following table(s) show the thermal resistance characteristics for the PBGA–ZKB mechanical
package.
Table 7-1. Thermal Resistance Characteristics (PBGA Package) [ZKB]
NO.
°C/W(1)
°C/W(2)
AIR FLOW
(m/s)(3)
1
2
RΘJC
RΘJB
RΘJA
Junction-to-case
Junction-to-board
Junction-to-free air
12.8
15.1
24.5
21.9
21.1
20.4
19.6
0.6
13.5
19.7
33.8
30
N/A
N/A
3
0.00
0.50
1.00
2.00
4.00
0.00
0.50
1.00
2.00
4.00
0.00
0.50
1.00
2.00
4.00
4
5
28.7
27.4
26
RΘJMA
Junction-to-moving air
6
7
8
0.8
9
0.8
1
10
11
12
13
14
15
16
17
PsiJT
Junction-to-package top
0.9
1.2
1.1
1.4
1.3
1.8
14.9
14.4
14.4
14.3
14.1
19.1
18.2
18
PsiJB
Junction-to-board
17.7
17.4
(1) These measurements were conducted in a JEDEC defined 2S2P system and will change based on environment as well as application.
For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment
Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount
Packages. Power dissipation of 1W and ambient temp of 70C assumed. PCB with 2oz (70um) top and bottom copper thickness and
1.5oz (50um) inner copper thickness
(2) Simulation data, using the same model but with 1oz (35um) top and bottom copper thickness and 0.5oz (18um) inner copper thickness.
Power dissipation of 1W and ambient temp of 70C assumed.
(3) m/s = meters per second
7.2 Mechanical Drawings
This section contains mechanical drawings for the ZKB Ball Grid Array package .
216
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PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
BGA
BGA
Drawing
OMAPL137ZKB3
XOMAPL137ZKB3
PREVIEW
ACTIVE
ZKB
256
256
TBD
TBD
Call TI
Call TI
Call TI
Call TI
ZKB
90
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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