NS41256L35E/883 [TI]
32KX8 STANDARD SRAM, 35ns, CQCC32, 0.450 X 0.550 INCH, CERAMIC, LCC-32;
| 型号： | NS41256L35E/883 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 32KX8 STANDARD SRAM, 35ns, CQCC32, 0.450 X 0.550 INCH, CERAMIC, LCC-32 静态存储器 内存集成电路 |
| 文件： | 总18页 (文件大小：41K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MICROCIRCUIT DATA SHEET
Original Creation Date: 11/28/95
Last Update Date: 02/05/97
MNNS41256L35-X REV 0A0
Last Major Revision Date: 11/28/95
256K Static RAM (32K x 8 bit)
General Description
NS41256L35 is a high performance, low power version CMOS static RAM organized as 32,768 X
8 bits with 35nS address to access time. The NS41256 operates from a single +5V power
supply and all the inputs and outputs are fully TTL compatible.
Industry Part Number
NS Part Numbers
NS41256L35
NS41256L35E/883
NS41256L35J/883
Prime Die
PDM41256V
Processing
Subgrp Description
Temp (oC)
MIL-STD-883, Method 5004
1
Static tests at
+25
2
Static tests at
+125
-55
3
Static tests at
4
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
+25
Quality Conformance Inspection
5
+125
-55
6
MIL-STD-883, Method 5005
7
+25
8A
8B
9
+125
-55
+25
10
11
+125
-55
1
MICROCIRCUIT DATA SHEET
MNNS41256L35-X REV 0A0
Features
Truth Table:
OE
X
WE
X
CE
H
I/O
MODE
STANDBY
READ
HI-Z
DOUT
DIN
L
H
L
X
L
L
WRITE
H
H
L
HI-Z
OUTPUT DISABLE
Note: H=Vih, L=Vil, X=Dont care
Applications
Graphic Notes: * = This note does not apply for this device.
*1. The parameter is tested with CL = 5pF as shown in Fig. 2. Transition is
measured +200mV from steady state voltage.
*2. At any given temperature and voltage condition, tHZCE is less than tLZCE.
*3. This parameter is sampled.
*4. WE is high for a READ cycle.
5. The device is continously selected. All the Chip Enables are held in their
active state. Applies to READ cycle 1.
6. The address is valid prior to or coincident with the latest occuring Chip
Enable. Applies to READ cycle 2.
*7. Vcc = 5V +10%.
2
MICROCIRCUIT DATA SHEET
MNNS41256L35-X REV 0A0
(Absolute Maximum Ratings)
(Note 1)
Terminal Voltage with Respect to GND (VTERM)
Temperature Under Bias (TBIAS)
Storage Temperature (TSTG)
-0.5V to +7.0V
-65 C to +135 C
-65 C to +150 C
1.0W
Power Dissipation (PT)
DC Output Current (IOUT)
50mA
Note 1: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Recommended Operating Conditions
DC Supply Voltage (VCC)
4.5V to 5.5V
DC Supply Voltage (GND)
0V
Operating Temperature Range Ambient
-55 C to +125 C
3
MICROCIRCUIT DATA SHEET
MNNS41256L35-X REV 0A0
Electrical Characteristics
DC PARAMETERS: ELECTRICAL CHARACTERISTICS
(The following conditions apply to all the following parameters, unless otherwise specified.)
DC: Vcc=5.0V +10%, TA=-55 C to +125 C
PIN-
NAME
SUB-
SYMBOL
ILI
PARAMETER
CONDITIONS
NOTES
MIN
-5
MAX UNIT
GROUPS
Input Leakage
Current
Vcc=Max., Vin=Gnd to Vcc
5
5
uA
1, 2,
3
ILO
Vih
Vil
Vol
Output Leakage
Current
Vcc=Max., CE=Vih, Vout=Gnd to Vcc
-5
uA
1, 2,
3
Input High
Voltage
2.2
-0.5
6.0
0.8
0.4
0.5
V
V
V
V
V
1, 2,
3
Input Low Voltage
6
1, 2,
3
Output Low
Voltage
Iol=8mA, Vcc=Min.
Iol=10mA, Vcc=Min.
Ioh=-4mA, Vcc=Min.
1, 2,
3
1, 2,
3
Voh
Output High
Voltage
2.4
1, 2,
3
DC PARAMETERS: Power Supply Characteristics
(The following conditions apply to all the following parameters, unless otherwise specified.)
DC: Vcc=5V +10%
Icc
Operating Current CE=Vil, f=fmax=1/trc, Vcc=Max.,
Iout=0mA
130
mA
mA
mA
1, 2,
3
ISB
Standby Current
CE=Vih, f=fmax=1/trc, Vcc=Max.
30
10
1, 2,
3
ISB1
Full Standby
Current
CE>Vcc-0.2V, f=0, Vcc=Max.,
Vin>Vcc-0.2V or <0.2V
1, 2,
3
4
MICROCIRCUIT DATA SHEET
MNNS41256L35-X REV 0A0
Electrical Characteristics
AC PARAMETERS: ELECTRICAL CHARACTERISTICS
(The following conditions apply to all the following parameters, unless otherwise specified.)
AC: Vcc=5V +10%, TA=-55 C to +125 C, Input pulse levels=Gnd to 3.0V, Input rise and fall times=5nS, Input
timing reference levels=1.5V, Output reference levels=1.5V, Output load for 12-35nS speed grades=See
fig. 1 & 2.
PIN-
NAME
SUB-
SYMBOL
tRC
PARAMETER
CONDITIONS
NOTES
MIN
35
MAX UNIT
GROUPS
Read Cycle Time
nS
9, 10,
11
tAA
Address Access
Time
35
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
9, 10,
11
tACE
tOH
Chip Enable
Access Time
35
10
9, 10,
11
Output Hold from
Address Change
3
5
9, 10,
11
tLZCE
tHZCE
tPU
Chip Enable to
Output in Low Z
3,
9, 10,
11
4, 5
Chip Disable to
Output in High Z
3,
4, 5
9, 10,
11
Chip Enable to
Power Up Time
4
0
0
9, 10,
11
tPD
Chip Disable to
Power Down Time
4
35
15
9, 10,
11
tAOE
tLZOE
tHZOE
tWC
Output Enable
Access Time
9, 10,
11
Output Enable to
Output in Low Z
4, 5
4, 5
9, 10,
11
Output Disable to
Output in High Z
10
9, 10,
11
Write Cycle Time
35
20
20
0
9, 10,
11
tCW
Chip Enable to
end of Write
9, 10,
11
tAW
Address Valid to
end of Write
9, 10,
11
tAS
Address Setup
Time
9, 10,
11
tAH
Address Hold from
end of Write
0
9, 10,
11
tWP
Write Pulse Width
Data Setup Time
Data Hold Time
20
12
0
9, 10,
11
tDS
9, 10,
11
tDH
9, 10,
11
5
MICROCIRCUIT DATA SHEET
MNNS41256L35-X REV 0A0
Electrical Characteristics
AC PARAMETERS: ELECTRICAL CHARACTERISTICS(Continued)
(The following conditions apply to all the following parameters, unless otherwise specified.)
AC: Vcc=5V +10%, TA=-55 C to +125 C, Input pulse levels=Gnd to 3.0V, Input rise and fall times=5nS, Input
timing reference levels=1.5V, Output reference levels=1.5V, Output load for 12-35nS speed grades=See
fig. 1 & 2.
PIN-
NAME
SUB-
SYMBOL
tLZWE
tHZWE
PARAMETER
CONDITIONS
NOTES
MIN
MAX UNIT
GROUPS
Write Disable to
Output in Low Z
4, 5
0
nS
9, 10,
11
Write Enable to
Output in High Z
4, 5
8
nS
9, 10,
11
AC PARAMETERS: Capacitance
(The following conditions apply to all the following parameters, unless otherwise specified.)
AC: TA=+25 C, f=1.0Mhz
Cin
Input Capacitance
7
8
pF
pF
9, 10,
11
Cout
Output
Capacitance
7
8
9, 10,
11
Data Retention Electrical Characteristics: DC
Vdr
Vcc for Retention
Data
2
V
1, 2,
3
Iccdr
Iccdr
Data Retention
CE>Vcc-0.2V, Vin>Vcc-0.2V or <0.2V,
500
750
uA
uA
1, 2,
3
Current (15-35nS) Vcc=2V
Data Retention
Current
CE>Vcc-0.2V, Vin>Vcc-0.2V or <0.2V,
Vcc=3V
1, 2,
3
Data Retention Electrical Characteristics: AC
tCDR
Chip Deselect to
Data Retention
Time
0
nS
nS
9, 10,
11
tR
Operation
Recovery Time
4
tRC
9, 10,
11
Note 1: The device is continously selected. All the Chip Enables are held in their active
state.
Note 2: The address is valid prior to or coincident with the latest occuring Chip Enable.
Note 3: At any given temperature and voltage condition, tHZCE is less than tLZCE.
Note 4: This parameter is sampled.
Note 5: The parameter is tested with CL=5pF as shown in Figure 2. Transition is measured
+200mV from steady state voltage.
Note 6: Vil(Min)=-3.0V for pulse width less than 20nS.
Note 7: This parameter is determined by device characterization but is not production tested.
6
MICROCIRCUIT DATA SHEET
MNNS41256L35-X REV 0A0
Graphics and Diagrams
GRAPHICS#
DESCRIPTION
AN00012A
AN00016A
AN00017A
AN00019A
AN00020A
AN00022A
AN00025A
AN00027A
AN00029A
P000141A
P000142A
BLOCK DIAGRAM - NS41256
FIGURE 1 - OUTPUT LOAD EQUIVALENT
FIGURE 2 - OUTPUT LOAD EQUIVALENT
FIGURE 4 - CAPACITIVE LOADING GRAPH
READ CYCLE 1 (APPLICATION NOTES)
READ CYCLE 2 (APPLICATION NOTES)
WRITE CYCLE 1 - WRITE ENABLE CONTROLLED
WRITE CYCLE 2 - CHIP ENABLE CONTROLLED
LOW VCC DATA RETENTION WAVEFORM
CERDIP (J), 28 LEAD, 300 MIL (PIN OUT)
CERAMIC LCC (E), 32 LEAD, 450 X 550 MIL (PIN OUT)
See attached graphics following this page.
7
AN00012A
Functional Block Diagram
A
•
0
Decoder
Memory
Matrix
•
•
•
•
•
•
•
•
Addresses
•
•
A 14
• • • • •
I/O0
Input
Column I/O
Data
Control
•
•
I/O7
•
•
•
CE
WE
OE
NS41256
AN00016A
Output Load Equivalent
+5V
480Ω
D
OUT
255Ω
30 pF
FIG. 1
AN00017A
FIG. 2
Output Load Equivalent
(for tLZCE, tHZWE, tLZWE, tHZWE, tLZOE, tHZOE)
+5V
480Ω
D
OUT
255Ω
5 pF
NS41024
NS41096
NS41256
NS4A024
NS4A028
NS4M096
NS4R024
AN00019A
FIG. 4
Typical Delta t
AA
vs Capacitive Loading
5
4
3
2
1
0
0
30
60
90
120
Additional Lumped Capacitive Loading (pF)
NS41256
NS41257
NS41258
NS4A024
NS4A028
AN00020A
Read Cycle #1
Notes : 4,5,6 apply
t
RC
ADDR
t
AA
t
OH
D
DATA VALID
PREVIOUS DATA VALID
OUT
NS41024
NS41096
NS41256
NS41257
NS41258
NS4A024
NS4A028
NS4M096
NS4R024
AN00022A
Read Cycle #2 Notes 2,4,6 & 7
t
RC
CE
OE
t
t
HZCE
ACE
t
HZOE
t
AOE
t
LZOE
D
HIGH Z
DATA VALID
OUT
t
LZCE
NS41096
NS41256
NS4M096
AN00025A
Write Cycle #1 (write enable controlled)
t
WC
ADDR
t
AW
t
t
t
t
AH
CW
CE
t
AS
WP
WE
t
DH
DS
D
IN
DATA VALID
t
t
HZWE
LZWE
HIGH Z
D
OUT
NS41096
NS41256
NS41257
NS41258
NS4A028
NS4M096
AN00027A
Write Cycle #2 (chip enable controlled)
t
WC
ADDR
CE
t
AW
t
t
t
AS
CW
AH
t
WP
UNDEFINED
DON'T CARE
WE
t
t
DS
DATA VALID
DH
D
IN
NS41096
NS41256
NS41257
NS41258
NS4A028
NS4M096
AN00029A
Low Vcc Data Retention Waveform
Data Retention Mode
V
4.5V
4.5V
CC
V
DR
t
t
CDR
R
V
V
DR
IH
CE
V
IL
DON'T CARE
NS41096
NS41256
NS41257
NS41258
NS4A028
NS4M096
P000141A
Pin Configuration
CERDIP (J Suffix)
28LD (pinout)
Vcc
WE
A13
A8
1
2
3
4
5
6
7
8
A14
A12
A7
28
27
26
25
24
23
A6
A9
A5
A11
OE
A4
A3
22
21
20
19
18
17
16
15
A10
CE
A2
9
A1
10
11
12
13
14
I/O7
I/O6
I/O5
I/O4
I/O3
A0
I/O0
I/O1
I/O2
GND
NS41256
P000142A
Pin Configuration
32LD (pinout)
LCC (E Suffix)
4 3 2
32 31 30
1
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
5
29
A8
6
28
27
26
25
24
23
22
21
A9
7
A11
NC
OE
A10
CE
I/07
I/06
8
9
10
11
12
13
14 15 16 17 18 19 20
NS41256
相关型号：
NS41256S15E/883
IC 32K X 8 STANDARD SRAM, 15 ns, CQCC32, 0.450 X 0.550 INCH, CERAMIC, LCC-32, Static RAM
NSC
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