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NS41256S15J-SMD [NSC]

IC,SRAM,32KX8,CMOS,DIP,28PIN,CERAMIC;
NS41256S15J-SMD
型号： NS41256S15J-SMD
厂家： National Semiconductor    National Semiconductor
描述：

IC,SRAM,32KX8,CMOS,DIP,28PIN,CERAMIC

静态存储器 内存集成电路
文件： 总18页 (文件大小：39K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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MICROCIRCUIT DATA SHEET  
Original Creation Date: 11/28/95  
Last Update Date: 02/05/97  
MDNS41256S15-X REV 0A0  
Last Major Revision Date: 11/28/95  
256K Static RAM (32K x 8 bit)  
General Description  
NS41256S15 is a high performance, standard power version CMOS static RAM organized as  
32,768 X 8 bits with 15nS address to access time. NS41256 operates from a single +5V power  
supply and all the inputs and outputs are fully TTL compatible.  
Industry Part Number  
NS Part Numbers  
NS41256S15  
NS41256S15E-SMD *  
NS41256S15J-SMD **  
Prime Die  
PDM41256V  
Controlling Document  
5962-8866208YA*, UA** REV C  
Processing  
Subgrp Description  
Temp (oC)  
MIL-STD-883, Method 5004  
1
Static tests at  
+25  
2
Static tests at  
+125  
-55  
3
Static tests at  
4
Dynamic tests at  
Dynamic tests at  
Dynamic tests at  
Functional tests at  
Functional tests at  
Functional tests at  
Switching tests at  
Switching tests at  
Switching tests at  
+25  
Quality Conformance Inspection  
5
+125  
-55  
6
MIL-STD-883, Method 5005  
7
+25  
8A  
8B  
9
+125  
-55  
+25  
10  
11  
+125  
-55  
1
MICROCIRCUIT DATA SHEET  
MDNS41256S15-X REV 0A0  
Features  
Truth Table:  
CE  
WE  
X
OE  
X
I/O  
FUNCTION  
H
HI-Z  
HI-Z  
HI-Z  
DOUT  
DIN  
STANDBY (ICC2)  
STANDBY (ICC3)  
OUTPUT DISABLE  
READ  
> VCC -0.2V  
X
X
L
L
L
H
H
H
L
L
X
WRITE  
Applications  
Graphic Notes: * = This note does not apply for this device.  
*1. The parameter is tested with CL = 5pF as shown in Fig. 2. Transition is  
measured +200mV from steady state voltage.  
*2. At any given temperature and voltage condition, tHZCE is less than tLZCE.  
*3. This parameter is sampled.  
*4. WE is high for a READ cycle.  
5. The device is continously selected. All the Chip Enables are held in their  
active state. Applies to READ cycle 1.  
6. The address is valid prior to or coincident with the latest occuring Chip  
Enable. Applies to READ cycle 2.  
*7. Vcc = 5V +10%.  
2
MICROCIRCUIT DATA SHEET  
MDNS41256S15-X REV 0A0  
(Absolute Maximum Ratings)  
(Note 1)  
Supply Voltage Range (VCC)  
(Note 2)  
-0.5Vdc to +7.0Vdc  
Input Voltage Range  
-0.5Vdc to +6.0Vdc  
-65 C to +150 C  
See MIL-STD-1835  
Ambient Storage Temperature  
Thermal Resistance  
Junction-to-Case (ThetaJC)  
Junction Temperature (TJ)  
(Note 3)  
+150 C  
1.0W  
Power Dissipation (PD)  
Lead Temperature  
(Soldering, 10 seconds)  
+260 C  
Note 1: Generic numbers are listed on the Standardized Military Drawing Source Approval  
Bulletin at the end of document 5962-88662, and will also be listed in MIL-BUL-103.  
Note 2: All voltages referenced to VSS.  
Note 3: Maximum junction temperature shall not be exceeded except for allowable short  
duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883.  
Recommended Operating Conditions  
Supply Voltage Range (VCC)  
(Note 1)  
4.5Vdc to 5.5Vdc  
Ground Voltage (VSS)  
0 Vdc  
Input High Voltage Range (VIH)  
2.2Vdc to Vcc +0.5Vdc  
Input Low Voltage Range (VIL)  
-0.5Vdc to 0.8Vdc  
Operating Case Temperature (TC)  
-55 C to +125 C  
Note 1: All voltages referenced to VSS.  
3
MICROCIRCUIT DATA SHEET  
MDNS41256S15-X REV 0A0  
Electrical Characteristics  
DC PARAMETERS: ELECTRICAL CHARACTERISTICS  
(The following conditions apply to all the following parameters, unless otherwise specified.)  
DC: -55 C < Tc < +125 C, Vss = 0V, 4.5V < Vcc < 5.5V  
PIN-  
NAME  
SUB-  
SYMBOL  
ILI  
PARAMETER  
CONDITIONS  
NOTES  
MIN  
MAX UNIT  
GROUPS  
Input Leakage  
Current  
Vcc = max, Vin = Gnd to Vcc  
10  
uA  
uA  
V
1, 2,  
3
ILO  
Vol  
Voh  
Output Leakage  
Current  
Vcc = max, Vout = Gnd to Vcc,  
CE > Vih; WE < Vil  
10  
1, 2,  
3
Output Low  
Voltage  
Vcc = 4.5V, Iol = 8mA, Vil=0.8V,  
Vih=2.2V  
0.4  
1, 2,  
3
Output High  
Voltage  
Vcc = 4.5V, Ioh = -4mA, Vil = 0.8V,  
Vih = 2.2V  
2.4  
V
1, 2,  
3
DC PARAMETERS: Maximum Operating Conditions  
(The following conditions apply to all the following parameters, unless otherwise specified.)  
DC: -55 C < Tc < +125 C, Vss = 0V, 4.5V < Vcc < 5.5V  
Icc1  
Operating Supply Vcc=5.5V, f=fmax, CE = Vil,  
1
180  
mA  
mA  
1, 2,  
3
Current  
outputs open, all other inputs at Vil  
Icc2  
Standby Power  
Supply Current  
(TTL)  
CE > Vih, outputs open,  
Vcc=5.5V  
50  
1, 2,  
3
Icc3  
Standby Power  
Supply Current  
(CMOS)  
CE > (Vcc-0.2V), f=0MHz,  
outputs open, Vcc=5.5Vall other  
inputs < 0.2V or > (Vcc-0.2V)  
20  
mA  
1, 2,  
3
AC PARAMETERS: Capacitance  
(The following conditions apply to all the following parameters, unless otherwise specified.)  
DC: -55 C < Tc < +125 C, Vss = 0V, 4.5V < Vcc < 5.5V  
Cin  
Input Capacitance Vi=5.0V or Gnd, f=1MHz, TC=+25 C  
2, 6  
2, 6  
11  
11  
pF  
pF  
4
4
Cout  
Output  
Vo=5.0V or Gnd, f=1MHz, TC=+25 C  
Capacitance  
4
MICROCIRCUIT DATA SHEET  
MDNS41256S15-X REV 0A0  
Electrical Characteristics  
AC PARAMETERS: ELECTRICAL CHARACTERISTICS  
(The following conditions apply to all the following parameters, unless otherwise specified.)  
AC: -55 C < Tc < +125 C, Vss = 0V, 4.5V < Vcc < 5.5V  
PIN-  
NAME  
SUB-  
SYMBOL  
tAVAV  
PARAMETER  
CONDITIONS  
NOTES  
MIN  
15  
MAX UNIT  
GROUPS  
Read Cycle Time  
3
nS  
9, 10,  
11  
tAVQV  
tELQV  
tAVQX  
tOLQV  
tELQX  
tEHQZ  
Address Access  
Time  
3
15  
nS  
nS  
ns  
nS  
nS  
nS  
9, 10,  
11  
Chip Enable  
Access Time  
3
15  
9, 10,  
11  
Output Hold after  
Address Change  
3
3
3
9, 10,  
11  
Output Enable to  
Output Valid  
3, 5  
8
9, 10,  
11  
Chip Select to  
Output in Low Z  
2,  
3, 4  
9, 10,  
11  
Chip Deselect to  
Output in High Z  
2,  
10  
10  
10  
9, 10,  
11  
3,  
4, 5  
tOHQZ  
tWLQZ  
tOLQX  
Output Disable to  
Output in High Z  
2,  
nS  
nS  
9, 10,  
11  
3,  
4, 5  
Write Enable to  
Output in High Z  
2,  
9, 10,  
11  
3,  
4, 5  
Output Enable to  
Output in Low Z  
2,  
3, 4  
0
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
9, 10,  
11  
tDVWH/  
tDVEH  
Data Valid to end  
of Write  
3, 5  
10  
0
9, 10,  
11  
tWHDX/  
tEHDX  
Data Hold Time  
3
9, 10,  
11  
tWHQX  
tAVAV  
tELWH  
tAVWH  
tAVWL  
tWLWH  
Output Active  
from end of Write  
2,  
3, 4  
0
9, 10,  
11  
Write Cycle Time  
3
3
3
3
3
3
15  
12  
12  
0
9, 10,  
11  
Chip Select to  
end of Write  
9, 10,  
11  
Address Valid to  
end of Write  
9, 10,  
11  
Address-setup  
Time  
9, 10,  
11  
Write Pulse Width  
12  
0
9, 10,  
11  
tWHAX/  
tEHAX  
Write Recovery  
Time  
9, 10,  
11  
Note 1: fmax = 1/tAVAV (minimum).  
5
MICROCIRCUIT DATA SHEET  
MDNS41256S15-X REV 0A0  
(Continued)  
Note 2: This parameter tested initially and after any design or process change which could  
affect this parameter, and therefore shall be guaranteed to the limits specified in  
table I.  
Note 3: For load circuits see figure 3 and for timing waveforms see figure 4.  
Note 4: Transition is measured +500mV from steady state voltage.  
Note 5: This parameter has been tightened for device type 04. Any date code prior to the date  
of Rev C of this drawing may not meet this limit. See Rev B for the electrical  
parameter value that applies to prior date codes.  
Note 6: Subgroup 4 (Cin and Cout measurements) shall be measured only for the initial test  
and after any process or design changes which may affect capacitance. Sample size is  
fifteen devices with no failures, and all input and output terminals tested.  
6
MICROCIRCUIT DATA SHEET  
MDNS41256S15-X REV 0A0  
Graphics and Diagrams  
GRAPHICS#  
DESCRIPTION  
AN00012A  
AN00016A  
AN00017A  
AN00019A  
AN00020A  
AN00022A  
AN00025A  
AN00027A  
AN00029A  
P000141A  
P000142A  
BLOCK DIAGRAM - NS41256  
FIGURE 1 - OUTPUT LOAD EQUIVALENT  
FIGURE 2 - OUTPUT LOAD EQUIVALENT  
FIGURE 4 - CAPACITIVE LOADING GRAPH  
READ CYCLE 1 (APPLICATION NOTES)  
READ CYCLE 2 (APPLICATION NOTES)  
WRITE CYCLE 1 - WRITE ENABLE CONTROLLED  
WRITE CYCLE 2 - CHIP ENABLE CONTROLLED  
LOW VCC DATA RETENTION WAVEFORM  
CERDIP (J), 28 LEAD, 300 MIL (PIN OUT)  
CERAMIC LCC (E), 32 LEAD, 450 X 550 MIL (PIN OUT)  
See attached graphics following this page.  
7
AN00012A  
Functional Block Diagram  
A
•
0
Decoder  
Memory  
Matrix  
•
•
•
•
•
•
•
•
Addresses  
•
•
A 14  
• • • • •  
I/O0  
Input  
Column I/O  
Data  
Control  
•
•
I/O7  
•
•
•
CE  
WE  
OE  
NS41256  
AN00016A  
Output Load Equivalent  
+5V  
480Ω  
D
OUT  
255Ω  
30 pF  
FIG. 1  
AN00017A  
FIG. 2  
Output Load Equivalent  
(for tLZCE, tHZWE, tLZWE, tHZWE, tLZOE, tHZOE)  
+5V  
480Ω  
D
OUT  
255Ω  
5 pF  
NS41024  
NS41096  
NS41256  
NS4A024  
NS4A028  
NS4M096  
NS4R024  
AN00019A  
FIG. 4  
Typical Delta t  
AA  
vs Capacitive Loading  
5
4
3
2
1
0
0
30  
60  
90  
120  
Additional Lumped Capacitive Loading (pF)  
NS41256  
NS41257  
NS41258  
NS4A024  
NS4A028  
AN00020A  
Read Cycle #1  
Notes : 4,5,6 apply  
t
RC  
ADDR  
t
AA  
t
OH  
D
DATA VALID  
PREVIOUS DATA VALID  
OUT  
NS41024  
NS41096  
NS41256  
NS41257  
NS41258  
NS4A024  
NS4A028  
NS4M096  
NS4R024  
AN00022A  
Read Cycle #2 Notes 2,4,6 & 7  
t
RC  
CE  
OE  
t
t
HZCE  
ACE  
t
HZOE  
t
AOE  
t
LZOE  
D
HIGH Z  
DATA VALID  
OUT  
t
LZCE  
NS41096  
NS41256  
NS4M096  
AN00025A  
Write Cycle #1 (write enable controlled)  
t
WC  
ADDR  
t
AW  
t
t
t
t
AH  
CW  
CE  
t
AS  
WP  
WE  
t
DH  
DS  
D
IN  
DATA VALID  
t
t
HZWE  
LZWE  
HIGH Z  
D
OUT  
NS41096  
NS41256  
NS41257  
NS41258  
NS4A028  
NS4M096  
AN00027A  
Write Cycle #2 (chip enable controlled)  
t
WC  
ADDR  
CE  
t
AW  
t
t
t
AS  
CW  
AH  
t
WP  
UNDEFINED  
DON'T CARE  
WE  
t
t
DS  
DATA VALID  
DH  
D
IN  
NS41096  
NS41256  
NS41257  
NS41258  
NS4A028  
NS4M096  
AN00029A  
Low Vcc Data Retention Waveform  
Data Retention Mode  
V
4.5V  
4.5V  
CC  
V
DR  
t
t
CDR  
R
V
V
DR  
IH  
CE  
V
IL  
DON'T CARE  
NS41096  
NS41256  
NS41257  
NS41258  
NS4A028  
NS4M096  
P000141A  
Pin Configuration  
CERDIP (J Suffix)  
28LD (pinout)  
Vcc  
WE  
A13  
A8  
1
2
3
4
5
6
7
8
A14  
A12  
A7  
28  
27  
26  
25  
24  
23  
A6  
A9  
A5  
A11  
OE  
A4  
A3  
22  
21  
20  
19  
18  
17  
16  
15  
A10  
CE  
A2  
9
A1  
10  
11  
12  
13  
14  
I/O7  
I/O6  
I/O5  
I/O4  
I/O3  
A0  
I/O0  
I/O1  
I/O2  
GND  
NS41256  
P000142A  
Pin Configuration  
32LD (pinout)  
LCC (E Suffix)  
4 3 2  
32 31 30  
1
A6  
A5  
A4  
A3  
A2  
A1  
A0  
NC  
I/O0  
5
29  
A8  
6
28  
27  
26  
25  
24  
23  
22  
21  
A9  
7
A11  
NC  
OE  
A10  
CE  
I/07  
I/06  
8
9
10  
11  
12  
13  
14 15 16 17 18 19 20  
NS41256  

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