MM54HCT05J [TI]
IC HCT SERIES, HEX 1-INPUT INVERT GATE, CDIP14, CERAMIC, DIP-14, Gate;
| 型号： | MM54HCT05J |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC HCT SERIES, HEX 1-INPUT INVERT GATE, CDIP14, CERAMIC, DIP-14, Gate 栅 CD 输入元件 |
| 文件： | 总4页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 1988
MM54HCT05/MM74HCT05
Hex Inverter (Open Drain)
General Description
The MM54HCT05/MM74HCT05 are logic functions fabri-
cated by using advanced silicon-gate CMOS technology,
which provides the inherent benefits of CMOSÐlow quies-
cent power and wide power supply range. These devices
are also input and output characteristic and pinout compati-
ble with standard DM54LS/DM74LS logic families. The
MM54HCT05/MM74HCT05 open drain Hex Inverter re-
quires the addition of an external resistor to perform a wire-
NOR function.
MM54HCT/MM74HCT devices are intended to interface be-
tween TTL and NMOS components and standard CMOS
devices. These parts are also plug-in replacements for LS-
TTL devices and can be used to reduce power consumption
in existing designs.
Features
Y
Open drain for wire-NOR function
Y
LS-TTL pinout and threshold compatible
All inputs are protected from static discharge damage by
and ground.
Y
Fanout of 10 LS-TTL loads
internal diodes to V
CC
Y
Typical propagation delays:
t
t
(with 1 kX resistor) 10 ns
(with 1 kX resistor) 8 ns
PLH
PHL
Connection Diagram
Dual-In-Line Package
TL/F/5358–1
Top View
Order Number MM54HCT05 or MM74HCT05
Logic Diagram
Typical Application
TL/F/5358–3
TL/F/5358–2
Note: Can be extended to more than 2 inputs.
C
1995 National Semiconductor Corporation
TL/F/5358
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Conditions
Min
Max
5.5
Units
V
V
Supply Voltage (V
)
4.5
0
CC
DC Input or Output Voltage
(V , V
V
CC
)
IN OUT
b
a
0.5 to 7.0V
Supply Voltage (V
)
CC
Operating Temp. Range (T )
A
MM74HCT
MM54HCT
b
b
a
a
DC Input Voltage (V
)
1.5 to V
1.5V
0.5V
IN
CC
CC
b
b
a
85
40
55
C
C
§
§
DC Output Voltage (V
)
0.5 to V
a
125
OUT
Input Rise or Fall Times
(t , t )
g
g
g
Clamp Diode Current (I , I
)
20 mA
25 mA
50 mA
IK OK
500
ns
r
f
DC Output Current, per pin (I
)
OUT
DC V or GND Current, per pin (I
CC
)
CC
b
a
65 C to 150 C
Storage Temperature Range (T
)
§
§
STG
Power Dissipation (P )
D
(Note 3)
600 mW
500 mW
S.O. Package only
Lead Temperature (T )
L
(Soldering 10 seconds)
260 C
§
e
g
5V 10%, unless otherwise specified)
DC Electrical Characteristics (V
CC
74HCT
54HCT
e
T
25 C
§
A
eb
eb
T
A
40 to 85 C
T
A
55 to 125 C
§
§
Guaranteed Limits
Symbol
Parameter
Conditions
Units
Typ
V
V
V
Minimum High Level
Input Voltage
2.0
0.8
2.0
2.0
0.8
V
V
IH
Maximum Low Level
Input Voltage
0.8
IL
e
V
IH
Maximum Low Level
Voltage
V
I
OL
IN
e
e
e
20 mA
0
0.1
0.1
0.1
0.4
0.4
V
V
V
l
l
l
OUT
OUT
OUT
l
l
l
e
e
I
I
4.0 mA, V
4.8 mA, V
4.5V
5.5V
0.2
0.2
0.26
0.26
0.33
0.33
CC
CC
e
g
g
g
1.0
I
I
Maximum Input
Current
V
V
or GND,
0.1
1.0
mA
IN
IN
IH
CC
or V
V
IL
e
e
V
CC
Minimum High Level
Output Leakage
Current
V
IN
V
IH
or VIL, V
OUT
0.5
5.0
10
mA
LKG
CC
e
I
Maximum Quiescent
Supply Current
V
IN
V or GND
CC
2.0
0.3
20
40
mA
e
I
0mA
OUT
e
(Note 4)
V
IN
2.4V or 0.5V
0.4
0.5
mA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
b
b
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: 12 mW/ C from 65 C to 85 C; ceramic ‘‘J’’ package: 12 mW/ C from 100 C to 125 C.
§
§
§
§
§
§
Note 4: This is measured per input with all other inputs held at V
CC
or ground.
2
e
e
e
e e
15 pF, t t 6 ns unless otherwise noted.
r f
AC Electrical Characteristics V
5V, T
25 C, C
§
CC
A
L
Guaranteed
Limit
Symbol
Parameter
Conditions
Typ
Units
e
e
t
t
Maximum Propagation Delay
Maximum Propagation Delay
R
R
1 kX
1 kX
8
9
15
16
ns
ns
PZL
L
PLZ
L
e
e
e e
50 pF, t t 6 ns unless otherwise specified
r f
g
5V 10%, C
AC Electrical Characteristics V
CC
L
74HCT
eb
54HCT
e
T
25 C
§
A
eb
T
A
40 to 85 C
T
55 to 125 C
§
§
Guaranteed Limits
Symbol
Parameter
Conditions
Units
A
Typ
e
e
t
t
t
Maximum Propagation
Delay
R
R
1 kX
1 kX
10
22
28
33
30
22
ns
ns
ns
pF
pF
PZL
PLZ
THL
L
Maximum Propagation
Delay
12
10
20
15
20
5
25
19
L
Maximum Output
Fall Time
C
C
Power Dissipation
(per gate)
e%
R
L
PD
IN
Capacitance (Note 5)
Maximum Input
Capacitance
10
10
2
e
a
e
a
V f I
PD CC CC
Note 5:
C
determines the no load dynamic power consumption, P
C V
PD CC
f
I
V
CC CC
, and the no load dynamic current consumption, I
C
.
PD
D
S
3
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number MM54HCT05J
See NS Package J14A
Molded Dual-In-Line Package (N)
Order Number MM74HCT05J, N
See NS Package N14A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Corporation
National Semiconductor
Europe
National Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
a
1111 West Bardin Road
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(
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