MM54HCT109 [NSC]
Dual J-K Flip-Flops with Preset and Clear; 双J-K·触发器与预置和清除
| 型号： | MM54HCT109 |
| 厂家： | 
National Semiconductor |
| 描述： | Dual J-K Flip-Flops with Preset and Clear |
| 文件： | 总4页 (文件大小：117K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 1988
MM54HCT109/MM74HCT109
Dual J-K Flip-Flops with Preset and Clear
General Description
These high speed J-K FLIP-FLOPS utilize advanced silicon-
gate CMOS technology. They possess the low power con-
sumption and high noise immunity of standard CMOS inte-
grated circuits, along with the ability to drive 10 LS-TTL
loads.
MM54HCT/MM74HCT devices are intended to interface be-
tween TTL and NMOS components and standard CMOS
devices. These parts are also plug-in replacements for LS-
TTL devices and can be used to reduce power consumption
in existing designs.
Each flip flop has independent J, K, PRESET, CLEAR, and
CLOCK inputs and Q and Q outputs. These devices are
edge sensitive to the clock input and change state on the
positive going transition of the clock pulse. Clear and preset
are independent of the clock and accomplished by a low
logic level on the corresponding input.
Features
Y
Typical propagation delay: 20 ns
Y
Low input current: 1 mA maximum
Y
Low quiescent current: 40 mA maximum (74HCT Series)
Y
Output drive capability: 10 LS-TTL loads
The 54HCT/74HCT logic family is functionally as well as
pin-out compatible with the standard 54LS/74LS logic fami-
ly. All inputs are protected from damage due to static dis-
charge by internal diode clamps to V
and ground.
CC
Connection and Logic Diagrams
Function Table
Dual-In-Line Package
Inputs
CLK
Outputs
PR
CLR
J
K
Q
Q
L
H
L
H
L
X
X
X
X
X
L
X
X
X
L
H
L
L
H
L
X
H*
L
H*
H
H
H
H
H
H
H
H
H
H
H
u
u
u
u
L
H
L
L
TOGGLE
H
H
X
Q0
H
Q0
L
H
X
Q0
Q0
Order Number MM54HCT109 or MM74HCT109
TL/F/5361–1
TL/F/5361–2
C
1995 National Semiconductor Corporation
TL/F/5361
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Conditions
Min
Max
5.5
Units
V
Supply Voltage (V
)
CC
4.5
DC Input or Output Voltage
(V , V
0
V
CC
V
b
a
0.5 to 7.0V
Supply Voltage (V
)
CC
)
IN OUT
b
b
a
a
DC Input Voltage (V
)
1.5 to V
1.5V
0.5V
Operating Temp. Range (T )
A
MM74HCT
MM54HCT
IN
CC
CC
b
b
a
85
40
55
C
C
§
DC Output Voltage (V
)
0.5 to V
OUT
a
125
§
g
g
g
Clamp Diode Current (I , I
)
20 mA
25 mA
50 mA
IK OK
Input Rise or Fall Times
(t , t )
DC Output Current, per pin (I
)
OUT
500
ns
r
f
DC V or GND Current, per pin (I
CC
)
CC
b
a
65 C to 150 C
Storage Temperature Range (T
)
§
§
STG
Power Dissipation (P )
D
(Note 3)
600 mW
500 mW
S.O. Package only
Lead Temperature (T )
L
(Soldering 10 seconds)
260 C
§
e
g
5V 10% (unless otherwise specified)
DC Electrical Characteristics V
CC
74HCT
54HCT
e
T
A
25 C
§
eb
eb
A
T
40 to 85 C
§
T
55 to 125 C
§
Symbol
Parameter
Conditions
Units
A
Typ
Guaranteed Limits
V
V
V
Minimum High Level
Input Voltage
2.0
0.8
2.0
2.0
0.8
V
V
IH
Maximum Low Level
Input Voltage
0.8
IL
e
V or V
IH IL
Minimum High Level
Output Voltage
V
I
OH
IN
e
e
e
b
b
b
0.1
CC
20 mA
V
V
0.1
V
0.1
V
V
V
V
l
l
l
OUT
OUT
OUT
l
l
l
CC
CC
CC
e
e
I
I
4.0 mA, V
4.8 mA, V
4.5V 4.2
5.5V 5.2
3.98
4.98
3.84
4.84
3.7
4.7
CC
CC
e
V or V
IH IL
V
OL
Maximum Low Level
Voltage
V
IN
e
e
e
I
20 mA
0
4.5V 0.2
5.5V 0.2
0.1
0.1
0.1
0.4
0.4
V
V
V
l
l
l
OUT
OUT
OUT
l
l
l
e
e
I
I
4.0 mA, V
4.8 mA, V
0.26
0.26
0.33
0.33
CC
CC
e
V
CC
g
g
g
1.0
I
I
Maximum Input
Current
V
or GND,
0.1
1.0
mA
mA
mA
IN
IN
IH
V
or V
IL
e
Maximum Quiescent
Supply Current
V
IN
V
CC
or GND
4.0
40
80
CC
e
I
0 mA
OUT
e
V
IN
2.4V or 0.5V (Note 4)
0.3
0.4
0.5
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
b
b
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: 12 mW/ C from 65 C to 85 C; ceramic ‘‘J’’ package: 12 mW/ C from 100 C to 125 C.
§
§
§
§
§
§
Note 4: Measured per pin, all other inputs held at V
CC
or GND.
2
e
e
e
e e
15 pF, t t 6 ns
r f
AC Electrical Characteristics V
5V, T
25 C, C
§
CC
A
L
Guaranteed
Limit
Symbol
Parameter
Conditions Typ
Units
f
t
t
t
t
t
t
Maximum Operating
50
30
30
30
20
20
0
MHz
MAX
Frequency
, t
PHL PLH
Maximum Propagation
18
18
ns
ns
ns
ns
ns
ns
Delay from Clock to Q or Q
, t
PHL PLH
Maximum Propagation
Delay from Preset or Clear to Q or Q
Minimum Removal Time,
Preset or Clear to Clock
REM
S
Minimum Setup Time
J or K Clock
10
b
Minimum Hold Time
Clock to J or K
3
H
Minimum Pulse Width
Clock, Preset or Clear
8
16
W
e
e
e
t
f
e
g
5.0V 10%, C
AC Electrical Characteristics V
50 pF, t
6 ns (unless otherwise specified)
CC
L
r
74HCT
54HCT
e
T
25 C
§
A
eb
eb
T
A
40 to 85 C
T
A
55 to 125 C
§
§
Guaranteed Limits
§
§
Symbol
Parameter
Conditions
Units
Typ
f
t
Maximum Operating
Frequency
27
35
22
18
52
MHz
ns
MAX
, t
PHL PLH
Maximum Propagation
Delay from Clock to
Q or Q
22
22
44
44
t , t
PHL PLH
Maximum Propagation
Delay from Preset
or Clear to Q or Q
35
52
ns
t
t
t
t
Minimum Removal Time
Preset or Clear to Clock
20
20
0
25
25
0
30
30
0
ns
ns
ns
ns
ns
ns
pF
pF
REM
Minimum Setup Time
J or K to Clock
10
S
b
Minimum Hold Time
Clock to J or K
3
H
Minimum Pulse Width
Clock, Preset or Clear
16
20
500
19
24
500
22
W
t , t
r
Maximum Input Rise and
Fall Time
500
15
f
t , t
THL TLH
Maximum Output
Rise and Fall Time
C
C
Power Dissipation
(per flip-flop)
35
5
PD
Capacitance (Note 5)
Maximum Input
Capacitance
10
10
10
IN
2
e
a
e
a
V f I
PD CC CC
Note 5:
C
determines the no load dynamic power consumption, P
C V
PD CC
f
I
V
CC CC
, and the no load dynamic current consumption, I
C
.
PD
D
S
3
Physical Dimensions inches (millimeters)
Order Number MM54HCT109J or MM74HCT109J
NS Package J16A
Order Number MM74HCT109N
NS Package N16E
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Corporation
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