LSF0204-Q1 [TI]
适用于开漏或推挽接口的汽车类 4 位双向多电压电平转换器;
| 型号： | LSF0204-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于开漏或推挽接口的汽车类 4 位双向多电压电平转换器 转换器 电平转换器 |
| 文件： | 总26页 (文件大小：1334K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LSF0204-Q1
ZHCSID1B –JUNE 2018 –REVISED APRIL 2021
通过汽车认证的LSF0204-Q1 4 位自动双向多电压电平转换器
当 An 或 Bn 端口为低电平时，此开关处于接通状态，
并且在 An 和 Bn 端口之间存在一个低电阻连接。此开
关具有低导通电阻，可以在最短传播延迟和最小信号失
真情况下建立连接。A 侧或 B 侧上的电压将低于
Vref_A，且可上拉至Vref_A 到5.5V 之间的任何电平
1 特性
• 符合面向汽车应用的AEC-Q100 标准
– 温度等级1：–40°C ≤TA ≤125°C
– 器件HBM ESD 分类等级2
– CDM ESD 分类等级C6
您可以使用上拉电阻器单独设置每个通道的电源电压
(VPUn)。例如，CH1 可用于上行转换模式 (1.2V ↔
3.3V)，CH2 可用于下行转换模式(2.5V ↔ 1.8V)。
• 可在无方向引脚的情况下提供自动双向电压转换
• 支持开漏或推挽应用，如I2C、I2S、SPI、UART、
JTAG、MDIO、SDIO 和GPIO
当 EN 为高电平时，转换器开关打开，并且 An I/O 分
别连接至 Bn I/O，从而实现端口间的双向数据流。当
EN 为低电平时，转换器开关关闭，端口之间呈高阻抗
状态。EN 输入电路被设计成由Vref_A 供电。EN 必须
为低电平，从而确保上电或断电期间的高阻抗状态。
• 在电容负载不超过30pF 的情况下，支持最高
100MHz 的上行转换和大于100MHz 的下行转换，
在50pF 电容负载下支持最高40MHz 的上行/下行
转换
• 支持Ioff 局部断电模式（请参阅节7.3）
• 可实现以下电压之间的双向电压电平转换
– 0.95V ↔ 1.8、2.5、3.3、5.5V
– 1.2V ↔ 1.8、2.5、3.3、5.5V
器件信息(1)
封装尺寸（标称值）
器件型号
封装
LSF0204QPWRQ1
TSSOP (14)
5.00mm x 4.40mm
– 1.8V ↔ 2.5、3.3、5.5V
– 2.5V ↔ 3.3、5.5V
– 3.3V ↔ 5.5V
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• I/O 端口可耐受5V 电压
LSF0204-Q1
200 KΩ
Vref_B
• 低Ron 可实现更佳的信号完整性
• 采用直通引脚排列来简化PCB 布线
• 闩锁性能超过100mA，符合JESD17 规范
Vref_A
Level Converter
EN
2 应用
• I2S、JTAG、SPI、SDIO、UART、I2C、MDIO、
PMBus、SMBus 和其他接口
• 信息娱乐系统音响主机
• 图形群集
• ADAS 融合
• ADAS 前置摄像头
A1
A2
A3
A4
B1
B2
B3
B4
• HEV 电池管理系统
简化版原理图
3 说明
LSF0204-Q1 是一款通过汽车认证的四通道自动双向电
压转换器，可在 0.8V 至 4.5V (Vref_A) 和 1.8V 至
5.5V (Vref_B) 电压范围内运行。该范围支持在 0.8 至
5V 之间进行双向电压转换，而无须使用方向引脚。
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSEM4
LSF0204-Q1
ZHCSID1B –JUNE 2018 –REVISED APRIL 2021
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Table of Contents
7.1 Overview................................................................... 11
7.2 Functional Block Diagram......................................... 11
7.3 Feature Description...................................................12
7.4 Device Functional Modes..........................................12
8 Application and Implementation..................................13
8.1 Application Information............................................. 13
8.2 Typical Applications.................................................. 13
9 Power Supply Recommendations................................17
10 Layout...........................................................................17
10.1 Layout Guidelines................................................... 17
10.2 Layout Example...................................................... 17
11 Device and Documentation Support..........................18
11.1 Documentation Support.......................................... 18
11.2 接收文档更新通知................................................... 18
11.3 支持资源..................................................................18
11.4 Trademarks............................................................. 18
11.5 静电放电警告...........................................................18
11.6 术语表..................................................................... 18
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics: AC Performance
(Translating Down, 3.3 V to 1.8 V)................................ 6
6.7 Switching Characteristics: AC Performance
(Translating Down, 3.3 V to 1.2 V)................................ 6
6.8 Switching Characteristics: AC Performance
(Translating Up, 1.8 V to 3.3 V).....................................7
6.9 Switching Characteristics: AC Performance
(Translating Up, 1.2 V to 1.8 V).....................................7
6.10 Typical Characteristics..............................................8
7 Detailed Description......................................................11
Information.................................................................... 18
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (September 2018) to Revision B (April 2021)
Page
• 更新了整个文档的表、图和交叉参考的编号格式................................................................................................ 1
• Updated the Bidrectional Translation section to include inclusive terminology.................................................14
Changes from Revision * (June 2018) to Revision A (September 2018)
Page
• 将产品状态从“预告信息”更改为“量产数据”................................................................................................ 1
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5 Pin Configuration and Functions
VREF_A
A1
1
2
3
4
5
6
7
14
13
12
11
10
9
VREF_B
B1
A2
B2
A3
B3
A4
B4
NC
NC
GND
8
EN
Not to scale
图5-1. PW Package
14-Pin TSSOP
Top View
表5-1. Pin Functions 2
PIN
I/O
DESCRIPTION
NAME
VREF_A
A1
NO.
1
Reference supply voltage; see 节8 section
Input/output 1.
—
2
I/O
I/O
I/O
I/O
A2
3
Input/output 2.
A3
4
Input/output 3.
A4
5
Input/output 4.
NC
6
No connection. Not internally connected.
Ground
—
—
I
GND
EN
7
8
Translation enable input, EN is active-high
No connection. Not internally connected.
Input/output 4.
NC
9
—
B4
10
11
12
13
14
I/O
I/O
I/O
I/O
B3
Input/output 3.
B2
Input/output 2.
B1
Input/output 1.
VREF_B
Reference supply voltage; see 节8 section
—
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
–0.5
MAX
UNIT
V
(2)
Input voltage, VI
7
7
(2)
Input and output voltage, VI/O
V
–0.5
Continuous channel current
Input clamp current, IIK
128
–50
150
150
mA
mA
°C
VI < 0
Junction temperature, TJ
Storage temperature, Tstg
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The input and input/output negative-voltage ratings may be exceeded if the input and input/output clamp-current ratings are observed.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-001
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
0
MAX
UNIT
V
VI/O
Input/output voltage
5.5
5.5
64
Vref_A/B/EN
IPASS
TA
Reference voltage
0
V
Pass transistor current
Operating free-air temperature
mA
°C
125
–40
6.4 Thermal Information
LSF0204-Q1
PW (TSSOP)
14 PINS
157.9
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C
°C
°C
°C
°C
°C
RθJC(top)
RθJB
82.3
100.0
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
22.9
ψJT
99.0
ψJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, refer to the Semiconductor and IC Package Thermal Metrics
application report.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
Input clamp
voltage
VIK
II = -18 mA, VEN = 0
VI = 5 V, VEN = 0
V
–1.2
I/O input high
leakage
IIH
5.0
3.5
µA
µA
Leakage from
Vref_B to Vref_A
Vref_B = 3.3 V, Vref_A = 1.8 V, VEN = Vref_A IO = 0, VI = 3.3 V or
GND
ICCBA
Total Current
through GND
Vref_B = 3.3 V, Vref_A = 1.8 V, VEN = Vref_A IO = 0, VI = 3.3 V or
GND
(3)
ICCA + ICCB
IIN
0.2
µA
µA
µA
pF
pF
Control pin current Vref_B = 5.5 V, Vref_A = 4.5 V, VEN = 0 to Vref_A IO = 0
±1
±1
Power Off
Ioff
Vref_B = Vref_A = 0 V, VEN = GND IO = 0, VI = 5 V or GND
Leakage Current
CI(ref_A/B/EN)
Cio(off)
Input capacitance VI = 3 V or 0
7
I/O pin off-state
VO = 3 V or 0, VEN = 0
capacitance
5.0
6.0
13
I/O pin on-state
Cio(on)
VO = 3 V or 0, VEN = Vref_A
capacitance
10.5
pF
V
High-level input
Vref_A = 1.5 V to 4.5 V
voltage
VIH (EN pin)
VIL (EN pin)
VIH (EN pin)
VIL (EN pin)
0.7×Vref_A
0.8×Vref_A
Low-level input
Vref_A = 1.5 V to 4.5 V
voltage
0.3×Vref_A
0.3×Vref_A
V
High-level input
Vref_A= 1.0 V to 1.5 V
voltage
V
Low-level input
Vref_A = 1.0 V to 1.5 V
voltage
V
Input transition rise
or fall rate for EN
pin
10
ns/V
∆t/∆v (EN pin)
Vref_A = VEN = 3.3 V; Vref_B = 5 V
VI = 0, IO = 64 mA
3
4
Ω
Ω
Vref_A = VEN = 1.8 V; Vref_B = 5 V
Vref_A = VEN = 1.0 V; Vref_B = 5 V
VI = 0, IO = 32 mA
9
Vref_A = VEN = 1.8 V; Vref_B = 5 V
4
On-state
resistance
(2)
ron
VI = 0, IO = 32 mA , Vref_A = VEN = 2.5 V; Vref_B = 5 V
10
5
Ω
Ω
Ω
Ω
Ω
VI = 1.8 V, IO = 15 mA, Vref_A = VEN = 3.3 V; Vref_B = 5 V
VI = 1.0 V, IO = 10 mA, Vref_A = VEN = 1.8 V; Vref_B = 3.3 V
VI = 0 V, IO = 10 mA, Vref_A = VEN = 1.0 V; Vref_B = 3.3 V
VI = 0 V, IO = 10 mA, Vref_A = VEN = 1.0 V; Vref_B = 1.8 V
8
6
6
(1) All typical values are at TA = 25°C.
(2) Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is
determined by the lowest voltage of the two (A or B) terminals.
(3) The actual supply current for LSF0204 is ICCA + ICCB; the leakage from Vref_B to Vref_A can be measured on Vref_A and Vref_B pin
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6.6 Switching Characteristics: AC Performance (Translating Down, 3.3 V to 1.8 V)
over recommended operating free-air temperature range, Vrev-A = 1.8 V, Vrev-B = 3.3 V, VEN = 1.8 V, Vpu_1 = 3.3 V,
Vpu_2 = 1.8 V, RL = NA, VIH = 3.3 V, VIL = 0 VM = 1.15 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
0.7
0.5
0.3
0.9
0.7
0.5
13
MAX
5.49
5.29
5.19
4.9
4.7
4.5
18
UNIT
CL = 50 pF
Propagation delay time
(low-to-high output)
tPLH
tPHL
tPLZ
tPZL
fMAX
(Input) A or B-to-B or A (Output)
(Input) A or B-to-B or A (Output)
(Input) A or B-to-B or A (Output)
(Input) A or B-to-B or A (Output)
(Input) A or B-to-B or A (Output)
CL = 30 pF
CL = 15 pF
CL = 50 pF
CL = 30 pF
CL = 15 pF
CL = 50 pF
CL = 30 pF
CL = 15 pF
CL = 50 pF
CL = 30 pF
CL = 15 pF
CL = 50 pF
CL = 30 pF
CL = 15 pF
ns
Propagation delay time
(high-to-low output)
ns
ns
Disable time
(from low level)
12
16.5
15
11
33
45
Disable time
30
40
ns
23
37
50
Maximum time
100
100
MHz
6.7 Switching Characteristics: AC Performance (Translating Down, 3.3 V to 1.2 V)
over recommended operating free-air temperature range Vrev-A = 1.2 V, Vrev-B = 3.3 V, VEN = 1.2 V, Vpu_1 = 3.3 V,
Vpu_2 = 1.2 V, RL = NA, VIH = 3.3V, VIL = 0 VM = 0.85 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
0.8
0.5
0.3
0.9
0.7
0.6
50
MAX
4.1
3.9
3.8
4.7
4.5
4.3
UNIT
CL = 50 pF
Propagation delay time
(low-to-high output)
tPLH
(Input) A or B-to-B or A (Output)
(Input) A or B-to-B or A (Output)
(Input) A or B-to-B or A (Output)
CL = 30 pF
CL = 15 pF
CL = 50 pF
CL = 30 pF
CL = 15 pF
CL = 50 pF
CL = 30 pF
CL = 15 pF
ns
Propagation delay time
(high-to-low output)
tPHL
ns
fMAX Maximum time
100
100
MHz
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6.8 Switching Characteristics: AC Performance (Translating Up, 1.8 V to 3.3 V)
over recommended operating free-air temperature range Vrev-A = 1.8 V, Vrev-B = 3.3 V, VEN = 1.8 V, Vpu_1 = 3.3 V,
Vpu_2 = 1.8V, RL = 500 Ω, VIH = 1.8V,VIL = 0 VM = 0.9V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
0.6
0.4
0.2
1.3
1
MAX
5.7
UNIT
CL = 50 pF
Propagation delay time
(low-to-high output)
tPLH
tPHL
tPLZ
tPZL
fMAX
(Input) A or B-to-B or A (Output)
(Input) A or B-to-B or A (Output)
(Input) A or B-to-B or A (Output)
(Input) A or B-to-B or A (Output)
(Input) A or B-to-B or A (Output)
CL = 30 pF
CL = 15 pF
CL = 50 pF
CL = 30 pF
CL = 15 pF
CL = 50 pF
CL = 30 pF
CL = 15 pF
CL = 50 pF
CL = 30 pF
CL = 15 pF
CL = 50 pF
CL = 30 pF
CL = 15 pF
5.3
5.13
6.7
6.4
5.3
18
ns
Propagation delay time
(high-to-low output)
ns
ns
0.7
13
Disable time
(from low level)
12
16.5
15
11
33
45
Disable time
30
40
ns
23
37
50
Maximum time
100
100
MHz
6.9 Switching Characteristics: AC Performance (Translating Up, 1.2 V to 1.8 V)
over recommended operating free-air temperature range, Vrev-A = 1.2 V, Vrev-B = 1.8 V, VEN = 1.2 V, Vpu_1 = 1.8 V,
Vpu_2 = 1.2 V, RL = 500 Ω, VIH = 1.2V, VIL = 0 VM = 0.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
0.65
0.4
0.2
1.6
1.3
1
MAX
7.25
UNIT
CL = 50 pF
Propagation delay time
(low-to-high output)
tPLH
tPHL
fMAX
(Input) A or B-to-B or A (Output)
(Input) A or B-to-B or A (Output)
(Input) A or B-to-B or A (Output)
CL = 30 pF
CL = 15 pF
CL = 50 pF
CL = 30 pF
CL = 15 pF
CL = 50 pF
CL = 30 pF
CL = 15 pF
7.05
6.85
7.03
6.5
ns
Propagation delay time
(high-to-low output)
ns
5.4
50
Maximum time
100
100
MHz
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6.10 Typical Characteristics
4
Input
Output
3.5
3
2.5
2
1.5
1
0.5
0
-0.5
0
5
10
15
20
Time (ns)
图6-1. Signal Integrity (1.8 V to 3.3 V Translation Up at 50 MHz)
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Parameter Measurement Information
The outputs are measured one at a time, with one transition per measurement. All input pulses are supplied by
generators that have the following characteristics:
• PRR ≤10 MHz
• ZO = 50 Ω
• Tr ≤2 ns
• Tf ≤2 ns
V
T
R
L
S1
Open
S2
From Output
Under Test
(1)
L
C
A. CL includes probe and jig capacitance.
图7-1. Load Circuit for Outputs
USAGE
SWITCH
S1
Translating up
Translating down
S2
3.3 V
Input
V
V
M
M
M
V
IL
5 V
Output
V
M
V
V
OL
TRANSLATING UP
5 V
Input
V
V
V
M
M
V
IL
2 V
Output
V
M
M
V
OL
图7-2. Translating Down
Vref_B
S1
Open
500 Ω
From Output
Under Test
15 pF
TEST
S1
Vref_B
tPZL/tPLZ
图7-3. Load Circuit for Enable/Disable Time Measurement
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7.1 Load Circuit AC Waveform for Outputs
tr 2.0 ns
tf 2.0 ns
VCCA
90%
50%
Input
(An, Bn)
10%
GND
VOH
VOL
Output
(Bn, An)
tpLH
tpHL
图7-4. tPLH, tPHL
tr 2.0 ns
tf 2.0 ns
VCCA
90%
50%
Output Enabled
Control OE, OE
10%
GND
VOH
tpLZ
tpZL
Output (An or Bn)
Low to off to Low
50%
10%
Outputs
enabled
Outputs
disabled
Outputs
enabled
图7-5. tPLZ, tPZL
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7 Detailed Description
7.1 Overview
The LSF0204-Q1 may be used in level translation applications for interfacing devices or systems operating at
different interface voltages. The LSF0204-Q1 is ideal for use in applications where an open-drain driver is
connected to the data I/Os. LSF0204-Q1 can achieve 100 MHz data rate with the appropriate pull-up resistors
and layout design. The LSF0204-Q1 can also be used in applications where a push-pull driver is connected to
the data I/Os.
7.2 Functional Block Diagram
LSF0204-Q1
200 KΩ
Vref_B
Vref_A
Level Converter
EN
A1
A2
A3
A4
B1
B2
B3
B4
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7.3 Feature Description
7.3.1 Auto-Bidirectional Voltage Translation Without DIR Pin Terminal
The LSF0204-Q1 device is an auto bidirectional voltage level translator that operates from 0.95 V to 4.5 V on
Vref_A and 1.8 V to 5.5 V on Vref_B. This allows bidirectional voltage translation between 0.95 V and 5.5 V
without the need for a direction pin in open-drain or push-pull applications.
7.3.2 Support Multiple High Speed Translation Interfaces
The LSF0204-Q1 device is able to perform voltage translation for open-drain interfaces such as I2C, MDIO,
SMBUS, and PMBUS or push-pull interfaces such as I2S, SPI, UART, SDIO, and GPIO. The LSF0204-Q1
device supports level translation applications with transmission speeds greater than 100 MHz using a 200-Ω
pullup resistor with a 15-pF capacitive load. See the Down Translation with the LSF family and Up Translation
with the LSF family videos.
7.3.3 5-V Tolerance on IO Port and 125°C Support
The LSF0204-Q1, provides up to 5-V over-voltage tolerance on each of its IO channels. The device operating
ambient temperature from –40°C to 125°C is critical in supporting automotive applications.
7.3.4 Channel Specific Translation
The LSF0204-Q1 can work as multi-voltage level translator using specific pullup voltage (Vpu) on each IO
channel. Watch the Multi-Voltage Translation with the LSF Family video.
7.3.5 Ioff, Partial Power Down Mode
When Vref_A or Vref_B = 0, all the data IO pins are in high impedance.
EN logic circuit is referenced to Vref_A supply. No power sequence is required to enable and operate LSF0204-
Q1.
7.4 Device Functional Modes
表7-1 lists the device functional modes of the LSF0204-Q1 device.
表7-1. Function Table
INPUT EN(1) TERMINAL
FUNCTION
An = Bn
Hi-Z
H
L
(1) EN is controlled by Vref_A logic levels.
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8 Application and Implementation
Note
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
LSF0204-Q1 performs voltage translation for open-drain or push-pull interface. 表 8-1 provides examples of
interfaces as reference in regards to the different channel numbers that are supported by the LSF0204-Q1.
表8-1. Voltage Translator by Interface
CHANNEL
NUMBER
PART NAME
INTERFACE
Open Drain : I2C, MDIO, SMBus, PMBus, GPIO
Push Pull: GPIO, SPI, I2S, UART, JTAG, SD
LSF0204-Q1
4
8.2 Typical Applications
8.2.1 I2C, PMBus, SMBus, GPIO Application
Vpu_1 = 3.3 V
Vpu_2 = 1.8 V
Vrev_A = 1.8 V
Vrev_B = 3.3 V
1.8V
enable signal
ON
LSF0204-Q1
Off
Rpu
Rpu
EN
B1
Rpu
Rpu
A1
Vcc
Vcc
SW
SW
SW
SW
SDA
SCL
SDA
A2
A3
A4
B2
B3
B4
SCL
GND
图8-1. Bidirectional Translation to Multiple Voltage Levels
8.2.1.1 Design Requirements
8.2.1.1.1 Enable, Disable, and Reference Voltage Guidelines
The LSF0204-Q1 has an EN input that is used to disable the device by setting EN LOW, which places all I/Os in
the high-impedance state. Since LSF0204-Q1 is switch-type voltage translator, the power consumption is very
low. It is recommended to always enable LSF0204-Q1 for bidirectional application (I2C, SMBus, PMBus, or
MDIO).
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表8-2. Application Operating Condition
SYMBOL
Vref_A
PARAMETER
MIN
TYP
MAX
UNIT
Reference voltage (A)
0.8
4.5
5.5
V
V
V
V
Vref_B
Reference voltage (B)
Vref_A + 0.8
(1)
VI(EN)
Input voltage on EN terminal
Pull-up supply voltage
0
0
Vref_A
Vref_B
Vpu
(1) Refer VIH and VIL for VI(EN)
Vref_B is recommended to be 1.0 V higher than Vref_A for best signal integrity.
The LSF0204-Q1 device enables multi-voltage translation by using the desired pull up voltage on each of the
channels.
Note
Vref_A must be set as lowest voltage level while using the device in multi-voltage translation
application.
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Bidirectional Translation
The controller output driver may be push-pull (pull-up resistors may be required) or open-drain (pull-up resistors
required) and the peripheral device output can be push-pull or open-drain (pull-up resistors are required to pull
the Bn outputs to Vpu).
Note
However, if either output is push-pull, data must be unidirectional or the outputs must be 3-state and
be controlled by some direction-control mechanism to prevent HIGH-to-LOW contentions in either
direction. If both outputs are open-drain, no direction control is needed.
In 图 8-1, the reference supply voltage (Vref_A) is connected to the processor core power supply voltage. When
Vref_B is connected through to a 3.3 V Vpu power supply, and Vref_A is set 1.0 V. The output of A3 and B4 has
a maximum output voltage equal to Vref_A, and the bidirectional interface (Ch1/2, MDIO) has a maximum output
voltage equal to Vpu.
8.2.1.2.1.1 Pull-Up Resistor Sizing
The pull-up resistor value needs to limit the current through the pass transistor when it is in the ON state to about
15 mA. This ensures a pass voltage of 260 mV to 350 mV. If the current through the pass transistor is higher
than 15 mA, the pass voltage also is higher in the ON state. To set the current through each pass transistor at 15
mA, to calculate the pull-up resistor value use 方程式1.
Rpu = (Vpu –0.35 V) / 0.015 A
(1)
表 8-3 summarizes resistor values, reference voltages, and currents at 15 mA, 10 mA, and 3 mA. The resistor
value shown in the +10% column (or a larger value) should be used to ensure that the pass voltage of the
transistor is 350 mV or less. The external driver must be able to sink the total current from the resistors on both
sides of the LSF0204-Q1 device at 0.175 V, although the 15 mA applies only to current flowing through the
LSF0204-Q1 device.
The LSF0204-Q1 does not provide any drive capability. Therefore higher frequency applications will require
higher drive strength from the host side. No pullup resistor is needed on the host side (3.3 V) if the LSF0204-Q1
is being driven by standard CMOS totem pole output driver. Best practice is to minimize the trace length from the
LSF0204-Q1 on the sink side (1.8 V) to minimize signal degradation.
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表8-3. Pull-Up Resistor Values
PULLUP RESISTOR VALUE (Ω)
15 mA
10mA
NOMINAL
3 mA
VDPU
NOMINAL
310
+10%(1)
341
217
158
106
85
+10%(1)
512
NOMINAL
1550
983
+10%(1)
1705
1082
788
5 V
465
295
215
145
115
85
3.3 V
2.5 V
1.8 V
1.5 V
1.2 V
197
325
143
237
717
97
160
483
532
77
127
383
422
57
63
94
283
312
(1) +10% to compensate for VDD range and resistor tolerance.
8.2.1.3 Application Curve
4
Input
Output
3
2
±
0
±±
0
50 ±00 ±50 200 250 300 350 400 450 500
Time (ns)
图8-2. Captured Waveform From Above I2C Set-Up (1.8 V to 3.3 V at 2.5 MHz)
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8.2.2 MDIO Application
Vpu_1 = 3.3 V
Vpu_2 = 1.0 V
Vrev_A = 1.0 V
Vrev_B = 3.3 V
1.0V
enable signal
ON
LSF0204-Q1
Off
Rpu
Rpu
EN
B1
Rpu
Rpu
Vcc
A1
A2
A3
A4
Vcc
SW
SW
SW
SW
MDC
MDC
B2
B3
B4
MDIO
MDIO
GND
图8-3. Typical Application Circuit (MDIO/Bidirectional Interface)
8.2.2.1 Design Requirements
See the Design Requirements.
8.2.2.2 Detailed Design Procedure
See the Detailed Design Procedure.
8.2.3 Multiple Voltage Translation in Single Device, Application
Vpu_1 = 3.3 V
Vrev_A = 1.8 V
Vrev_B = 3.3 V
Vpu_2 = 1.8 V
1.8V
enable signal
ON
LSF0204-Q1
Off
Rpu
Rpu
EN
B1
Rpu Rpu
Rpu
A1
Vcc
Vcc
SW
MDC
MDC
A2
A3
A4
B2
B3
B4
Vpu = 1.0 V
MDIO
SW
SW
SW
MDIO
Vcc
GPIO
GPIO
GND
图8-4. Bidirectional Translation to Multiple voltage levels
8.2.3.1 Design Requirements
See the Design Requirements.
8.2.3.2 Detailed Design Procedure
See the Detailed Design Procedure.
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9 Power Supply Recommendations
There are no power sequence requirements for the LSF0204-Q1. See 表 8-2 for recommended operating
voltages for all supply and input pins.
10 Layout
10.1 Layout Guidelines
The signal integrity of the switch-type based LSF0204-Q1 level translator is dependent on the pull-up resistor
and the PCB board parasitic capacitance. Consider the following recommendations when designing with the
LSF0204-Q1:
• Minimize the trace length to reduce the parasitic capacitance
• The trace length should be less than half the time of flight to reduce ringing and line reflections or non-
monotonic behavior in the switching region
• Minimize stubs on the signal path
• Place the LSF0204-Q1 device near the high voltage side
10.2 Layout Example
Short signal trace
VREF_A
1
14
13
VREF_B
B1
A1
2
A2
A3
3
4
5
6
7
12
11
B2
B3
A4
10
9
B4
NC
NC
EN
Minimize stub
GND
8
Not to scale
图10-1. Short Trace Layout
TP1
SDIO Connector
(3.3V IO)
SD Controller
(1.8V IO)
LSF0204-Q1
SDIO level translator
Device PCB
TP2
图10-2. Device Placement
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, TI Logic Minute: Introduction –Voltage Level Translation with the LSF Family video
• Texas Instruments, Voltage-Level Translation with the LSF Family application report
• Texas Instruments, Biasing requirements for TXS, TXB, LSF Translators application report
• Texas Instruments, Factors affecting Vol for TXS and LSF translation devices application report
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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重要声明和免责声明
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有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LSF0204QPWRQ1
ACTIVE
TSSOP
PW
14
2000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LSF204Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LSF0204-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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Catalog : LSF0204
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LSF0204QPWRQ1
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 14
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
LSF0204QPWRQ1
2000
Pack Materials-Page 2
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
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