LSF0204DYZPR_技术文档

LSF0204, LSF0204D

ZHCSD68H –JULY 2014 –REVISED APRIL 2021

LSF0204x 适用于漏极开路和推挽应用的4 位双向多电压电平转换器

1 特性

3 说明

• 无需方向端子即可提供双向电压转换

• 在电容负载不超过30pF 的情况下，支持最高

100MHz 的上行转换和大于100MHz 的下行转换，

在50pF 电容负载下支持最高40MHz 的上行/下行

转换

• 支持I_off、局部断电模式（参阅特性说明）

• 可实现以下电压之间的双向电压电平转换

– 0.8V ↔ 1.8/2.5/3.3/5V

LSF 系列包含双向电压电平转换器，该转换器可在

0.8V 至 4.5V (Vref_A) 和 1.8V 至 5.5V (Vref_B) 电压

范围内运行。该范围支持在 0.8V 和 5.0V 之间进行双

向电压转换，无需在漏极开路或推挽应用中使用方向端

子。对于采用 15pF 电容器和 165Ω 上拉电阻器的漏

极开路系统，LSF 系列支持传输速度大于 100MHz 的

电平转换应用。

当 An 或 Bn 端口为低电平时，此开关处于接通状态，

而且 An 和 Bn 端口之间存在低电阻连接。开关的低

R_on可实现具有超小传播延迟和信号失真的连接。A 端

或 B 端的电压将限制为 Vref_A，且可上拉至 Vref_A

到 5V 之间的任何电压水平。利用此功能，可在无需方

向控制的情况下，在用户选择的较高和较低电压之间实

现无缝转换。

– 1.2V ↔ 1.8/2.5/3.3/5V

– 1.8V ↔ 2.5/3.3/5V

– 2.5V ↔ 3.3/5V

– 3.3V ↔ 5V

• 低待机电流

• 支持TTL 的5V 耐受I/O 端口

• 低R_on可实现较少的信号失真

• 实现EN = 低电平的高阻抗I/O 端子

• 采用直通引脚排列来简化PCB 布线

• 闩锁性能超过100mA，符合JESD17 规范

• –40°C 至125°C 工作温度范围

• ESD 性能测试符合JESD 22 标准

器件信息⁽¹⁾

封装尺寸（标称值）

器件型号

封装

TSSOP (14)

UQFN (12)

VQFN (14)

DSBGA (12)

5.00mm × 4.40mm

2.00mm × 1.70mm

3.50mm × 3.50mm

1.90mm × 1.40mm

LSF0204x

– 2000V 人体放电模型（A114-B，II 类）

– 200V 机器放电模型(A115-A)

– 1000V 充电器件模型(C101)

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

2 应用

Vref_B

Vref_A

• GPIO、MDIO、PMBus、SMBus、SDIO、

UART、I²C 和电信基础设施中的其他接口

LSF0204

EN

• 工业类

• 汽车类

• 个人计算

A1

A2

A3

A4

B1

SW

B2

B3

B4

GND

简化原理图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSCP5

LSF0204, LSF0204D

ZHCSD68H –JULY 2014 –REVISED APRIL 2021

www.ti.com.cn

Table of Contents

8.1 Load Circuit AC Waveform for Outputs.....................10

9 Detailed Description......................................................11

9.1 Overview................................................................... 11

9.2 Functional Block Diagram......................................... 11

9.3 Feature Description...................................................12

9.4 Device Functional Modes..........................................12

10 Application and Implementation................................13

10.1 Application Information........................................... 13

10.2 Typical Applications................................................ 13

11 Power Supply Recommendations..............................19

12 Layout...........................................................................19

12.1 Layout Guidelines................................................... 19

12.2 Layout Example...................................................... 19

13 Device and Documentation Support..........................21

13.1 接收文档更新通知................................................... 21

13.2 支持资源..................................................................21

13.3 Trademarks.............................................................21

13.4 Electrostatic Discharge Caution..............................21

13.5 术语表..................................................................... 21

14 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 说明（续）.........................................................................4

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 6

7.1 Absolute Maximum Ratings........................................ 6

7.2 ESD Ratings............................................................... 6

7.3 Recommended Operating Conditions.........................6

7.4 Thermal Information....................................................6

7.5 Electrical Characteristics.............................................7

7.6 Switching Characteristics: AC Performance

(Translating Down, 3.3 V to 1.8 V)................................ 7

7.7 Switching Characteristics: AC Performance

(Translating Down, 3.3 V to 1.2 V)................................ 8

7.8 Switching Characteristics: AC Performance

(Translating Up, 1.8 V to 3.3 V).....................................8

7.9 Switching Characteristics: AC Performance

(Translating Up, 1.2 V to 1.8 V).....................................8

7.10 Typical Characteristics..............................................8

8 Parameter Measurement Information............................9

Information.................................................................... 21

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision G (November 2019) to Revision H (April 2021)

Page

• 更新了整个文档的表、图和交叉参考的编号格式................................................................................................ 1

• Updated the Bidirectional Translation section to include inclusive terminology................................................14

Changes from Revision F (January 2019) to Revision G (November 2019)

Page

• Changed V_{ref_A/B/EN}max voltage to 5.5 V in the Recommended Operating Conditions table............................6

Changes from Revision E (December 2018) to Revision F (January 2019)

Page

• Changed location of YZP-package indicator dot to A3 position. ........................................................................4

• Added YZP package to Thermal Information table.............................................................................................6

Changes from Revision D (December 2015) to Revision E (December 2018)

Page

• Changed location of YZP-package A1-pin indicator dot. View is looking through the device, as in an X-ray. ....

4

Changes from Revision C (August 2015) to Revision D (December 2015)

Page

• Added Type Column to Pin Functions table........................................................................................................4

• Added Junction Temperatures to Thermal Information table..............................................................................6

Changes from Revision B (April 2015) to Revision C (August 2015)

Page

• 删除了“特性”中的“低于最大传播延迟1.5ns”项目符号............................................................................... 1

• 更新了“特性”中的“支持100MHz 以上的高速转换”项目符号......................................................................1

2

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Changes from Revision A (December 2014) to Revision B (April 2015)

Page

• 向器件添加了YZP 封装......................................................................................................................................1

Changes from Revision * (November 2014) to Revision A (December 2014) Page

• 从首页“产品预发布”更改为完整数据表...........................................................................................................1

• 将节3 中的文本从“传输速度大于100Mbps”更改为“传输速度大于100MHz”............................................1

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5 说明（续）

每个通道的电源电压 (V_pu#) 可以用上拉电阻器单独进行设置。例如，CH1 可用于上行转换模式 (1.2V ↔ 3.3V)，

CH2 可用于下行转换模式(2.5V ↔ 1.8V)。

当 EN 为高电平时，转换器开关打开，并且 An I/O 分别连接至 Bn I/O，从而实现端口间的双向数据流。当 EN 为

低电平时，转换器开关关闭，端口之间呈高阻抗状态。EN 输入电路被设计成由 Vref_A 供电。EN 必须为低电

平，从而确保上电或断电期间的高阻抗状态。

器件比较表

EN

An

Bn

器件型号

说明

三态输出模式启用

（低电平有效；以Vref_A 为基

准）

将所有数据引脚置于三态模式（高阻

态）

LSF0204D

H

将所有数据引脚置于三态模式（高阻态）

LSF0204D

LSF0204

L

输入或输出

H

三态输出模式启用

（高电平有效，以Vref_A 为基

准）

将所有数据引脚置于三态模式（高阻

态）

LSF0204

L

将所有数据引脚置于三态模式（高阻态）

6 Pin Configuration and Functions

Vref_B

Vref_A

1

2

14 Vref_B

13 B1

1

14

A1

A2

A1

A2

A3

A4

NC

B1

B2

B3

13

12

11

10

9

2

3

4

5

6

3

4

5

12

11

10

B2

B3

B4

NC

EN

A3

A4

9

8

NC

6

7

B4

GND

NC

8

7

图6-1. PW Package,

14-Pin TSSOP

(Top View)

GND

EN

图6-2. RGY Package,

14-Pin VQFN

(Transparent Top View)

EN

Vref_A

A1

1

2

3

11

10

9

Vref_B

B1

12

A2

A3

A4

B2

4

5

8

7

B3

B4

6

GND

图6-4. YZP Package,

12-Pin DSBGA

(Transparent Top View)

图6-3. RUT Package,

12-Pin UQFN

(Transparent Top View)

4

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NAME

表6-1. Pin Functions

NO.

RUT

TYPE⁽¹⁾

DESCRIPTION

PW, RGY

YZP

B2

V_{ref_A}

A1

1

2

3

4

5

6

7

1

2

3

4

5

Reference supply voltage; see Application and Implementation section

—

A3

I/O

Input/output 1.

A2

B3

Input/output 2.

A3

C3

D3

Input/output 3.

A4

Input/output 4.

NC

GND

No connection. Not internally connected.

Ground

–

—

6

D2

Switch enable input; LSF0204: EN is high-active; LSF0204D: EN is

low-active

EN

8

12

C2

I

NC

B4

9

No connection. Not internally connected.

–

7

—

D1

C1

B1

A1

A2

—

10

11

12

13

14

I/O

Input/output 4.

B3

8

Input/output 3.

B2

9

Input/output 2.

B1

10

11

Input/output 1.

V_{ref_B}

Reference supply voltage; see Application and Implementation section

—

(1) I = input, O = output

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

MIN

–0.5

MAX

UNIT

V

V_I

Input voltage ⁽²⁾

7

V_I/OInput/output voltage ⁽²⁾

Continuous channel current

V

–0.5

128

–50

150

mA

°C

I_IK

T_J

Input clamp current

Junction temperature

VI < 0

T_stgStorage temperature

°C

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) The input and input/output negative-voltage ratings may be exceeded if the input and input/output clamp-current ratings are observed.

7.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 500-V HBM is possible with the necessary precautions.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 250-V CDM is possible with the necessary precautions.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

0

MAX

5.5

UNIT

V

V_I/O

Input/output voltage

V_{ref_A/B/EN}

I_PASS

T_A

Reference voltage

0

5.5

V

Pass transistor current

Operating free-air temperature

64

mA

°C

125

–40

7.4 Thermal Information

LSF0204

THERMAL METRIC⁽¹⁾

RGY (VQFN)

14 PINS

83.2

RUT (UQFN)

12 PINS

195.8

PW (TSSOP) YZP (DSBGA)

UNIT

14 PINS

12 BALLS

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

157.9

83.7

°C

R_θ

98.2

98.7

82.3

0.6

JC(top)

R_θJB

ψ_JT

Junction-to-board thermal resistance

59.2

17.4

59.4

122.6

6.2

100.0

22.9

99.0

23.7

0.4

°C

Junction-to-top characterization parameter

Junction-to-board characterization parameter

122.6

23.7

ψ_JB

R_θ

Junction-to-case (bottom) thermal resistance

38.7

N/A

°C

JC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6

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7.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX

–1.2

5.0

UNIT

V

V_IK

I_IH

I_I= -18 mA, V_EN= 0

V_I= 5 V, V_EN= 0

µA

Leakage from

Vref_B to Vref_A

I_CCBA

V_{ref_B}= 3.3 V, V_{ref_A}= 1.8 V, V_EN= V_{ref_A}I_O= 0, V_I= 3.3 V or GND

3.5

µA

Total Current

through GND

(4)

I_CCA+ I_CCB

0.2

µA

I_IN

I_off

Control pin current V_{ref_B}= 5.5 V, V_{ref_A}= 4.5 V, V_EN= 0 to V_{ref_A}I_O= 0

±1

Power Off

V_{ref_B}= V_{ref_A}= 0 V, V_EN= GND I_O= 0, V_I= 5 V or GND

Leakage Current

C_{I(ref_A/B/EN)}

C_io(off)

V_I= 3 V or 0

7

5.0

pF

V_O= 3 V or 0, VEN = 0

V_O= 3 V or 0, VEN = Vref_A

6.0

13

C_io(on)

10.5

High-level input

V_{ref_A}= 1.5 V to 4.5 V

voltage

(3)

V

0.7×Vref_A

0.8×Vref_A

V

IH (EN pin)

Low-level input

V_{ref_A}= 1.5 V to 4.5 V

voltage

V_{IL (EN pin)}

V_{IH (EN pin)}

V_{IL (EN pin)}

0.3×Vref_A

High-level input

V_{ref_A}= 1.0 V to 1.5 V

voltage

Low-level input

V_{ref_A}= 1.0 V to 1.5 V

voltage

Input transition rise

or fall rate for EN

10

ns/V

∆t/∆v (EN pin)

V_{ref_A}= V_EN= 3.3 V; V_{ref_B}= 5 V

V_I= 0, I_O= 64 mA

3

4

Ω

V_{ref_A}= V_EN= 1.8 V; V_{ref_B}= 5 V

V_{ref_A}= V_EN= 1.0 V; V_{ref_B}= 5 V

V_I= 0, I_O= 32 mA

9

V_{ref_A}= V_EN= 1.8 V; V_{ref_B}= 5 V

4

(2)

r_on

V_I= 0, I_O= 32 mA , V_{ref_A}= V_EN= 2.5 V; V_{ref_B}= 5 V

V_I= 1.8 V, I_O= 15 mA, V_{ref_A}= V_EN= 3.3 V; V_{ref_B}= 5 V

V_I= 1.0 V, I_O= 10 mA, V_{ref_A}= V_EN= 1.8 V; V_{ref_B}= 3.3 V

V_I= 0 V, I_O= 10 mA, V_{ref_A}= V_EN= 1.0 V; V_{ref_B}= 3.3 V

V_I= 0 V, I_O= 10 mA, V_{ref_A}= V_EN= 1.0 V; V_{ref_B}= 1.8 V

10

5

Ω

8

6

(1) All typical values are at T_A= 25°C.

(2) Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is

determined by the lowest voltage of the two (A or B) terminals.

(3) Enable pin test conditions are for the LSF0204. The enable pin test conditions for LSF0204D are oppositely set.

(4) The actual supply current for LSF0204 is I_CCA+ I_CCB; the leakage from Vref_B to Vref_A can be measured on Vref_A and Vref_B pin

7.6 Switching Characteristics: AC Performance (Translating Down, 3.3 V to 1.8 V)

over recommended operating free-air temperature range, V_rev-A= 1.8 V, V_rev-B= 3.3 V, V_EN= 1.8 V, Vpu_1 = 3.3 V,

Vpu_2 = 1.8 V, R_L= NA, V_IH= 3.3 V, V_IL= 0 V_M= 1.15 V (unless otherwise noted)

C_L= 50 pF

C_L= 30 pF

TYP

0.5

C_L= 15 pF

PARAMETER

FROM (INPUT) TO (OUTPUT)

UNIT

TYP

0.7

0.9

13

MAX

5.49

4.9

MAX

5.29

4.7

TYP

0.3

0.5

11

MAX

5.19

4.5

t_PLH

t_PHL

t_PLZ

t_PZL

f_MAX

ns

0.7

A or B

B or A

18

12

16.5

40

15

ns

33

45

30

23

37

ns

50

100

MHz

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7.7 Switching Characteristics: AC Performance (Translating Down, 3.3 V to 1.2 V)

over recommended operating free-air temperature range V_rev-A= 1.2 V, V_rev-B= 3.3 V, V_EN= 1.2 V, Vpu_1 = 3.3 V,

Vpu_2 = 1.2 V, R_L= NA, V_IH= 3.3 V, V_IL= 0 V_M= 0.85 V (unless otherwise noted)

C_L= 50 pF

C_L= 30 pF

C_L= 15 pF

PARAMETER

FROM (INPUT) TO (OUTPUT)

UNIT

TYP

0.8

0.9

50

MAX

4.1

TYP

MAX

3.9

TYP

MAX

3.8

t_PLH

t_PHL

f_MAX

0.5

0.3

ns

A or B

B or A

4.7

0.7

4.5

0.6

4.3

100

MHz

7.8 Switching Characteristics: AC Performance (Translating Up, 1.8 V to 3.3 V)

over recommended operating free-air temperature range V_rev-A= 1.8 V, V_rev-B= 3.3 V, V_EN= 1.8 V, Vpu_1 = 3.3 V, Vpu_2 =

1.8 V, R_L= 500 Ω, V_IH= 1.8 V,_VIL= 0 V_M= 0.9 V (unless otherwise noted)

C_L= 50 pF

C_L= 30 pF

C_L= 15 pF

PARAMETER

FROM (INPUT) TO (OUTPUT)

UNIT

TYP

0.6

1.3

13

MAX

5.7

6.7

18

TYP

0.4

1

MAX

5.3

TYP

0.2

0.7

11

MAX

5.13

5.3

t_PLH

t_PHL

t_PLZ

t_PZL

f_MAX

ns

6.4

A or B

B or A

12

16.5

40

15

ns

33

45

30

23

37

ns

50

100

MHz

7.9 Switching Characteristics: AC Performance (Translating Up, 1.2 V to 1.8 V)

over recommended operating free-air temperature range, V_rev-A= 1.2 V, V_rev-B= 1.8 V, V_EN= 1.2 V, Vpu_1 = 1.8 V,

Vpu_2 = 1.2 V, R_L= 500 Ω, V_IH= 1.2 V, V_IL= 0 V_M= 0.6 V (unless otherwise noted)

C_L= 50 pF

C_L= 30 pF

C_L= 15 pF

PARAMETER

FROM (INPUT) TO (OUTPUT)

UNIT

TYP

MAX

7.25

7.03

TYP

MAX

7.05

6.5

TYP

0.2

1

MAX

6.85

5.4

t_PLH

t_PHL

f_MAX

0.65

0.4

ns

A or B

B or A

1.6

1.3

50

100

MHz

7.10 Typical Characteristics

4

Input

Output

3.5

3

2.5

2

1.5

1

0.5

0

-0.5

0

5

10

Time (ns)

15

20

图7-1. Signal Integrity (1.8 V to 3.3 V Translation Up at 50 MHz)

8

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8 Parameter Measurement Information

V

T

USAGE

SWITCH

S1

Translating up

R

L

Translating down

S2

S1

Open

S2

From Output

Under Test

3.3 V

Input

V

M

C

L

V

IL

(see Note A)

5 V

Output

V

M

V

LOAD CIRCUIT

V

OL

TRANSLATING UP

5 V

Input

V

M

V

IL

2 V

Output

V

M

V

OL

TRANSLATING DOWN

NOTES: A. C includes probe and jig capacitance.

L

B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.

C. The outputs are measured one at a time, with one transition per measurement.

O

r

f

图8-1. Load Circuit for Outputs

Vref_B

S1

Open

500 Ω

From Output

Under Test

15 pF

TEST

S1

Vref_B

t_PZL/t_PLZ

图8-2. Load Circuit for Enable/Disable Time Measurement

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8.1 Load Circuit AC Waveform for Outputs

t_r2.0 ns

t_f2.0 ns

V_CCA

90%

50%

Input

(An, Bn)

10%

GND

V_OH

V_OL

Output

(Bn, An)

t_pLH

t_pHL

图8-3. t_PLH, t_PHL

t_r2.0 ns

t_f2.0 ns

V_CCA

90%

50%

Output Enabled

Control OE, OE

10%

GND

V_OH

t_pLZ

t_pZL

Output (An or Bn)

Low to off to Low

50%

10%

Outputs

enabled

Outputs

disabled

Outputs

enabled

图8-4. t_PLZ, t_PZL

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9 Detailed Description

9.1 Overview

The LSF Family may be used in level translation applications for interfacing devices or systems operating at

different interface voltages with one another. The LSF Family is ideal for use in applications where an open-drain

driver is connected to the data I/Os. LSF can achieve 100 MHz with the appropriate pull-up resistors and layout.

The LSF Family may also be used in applications where a push-pull driver is connected to the data I/Os.

9.2 Functional Block Diagram

LSF0204

200 KΩ

Vref_B

Vref_A

Level Converter

EN

A1

A2

A3

A4

B1

B2

B3

B4

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9.3 Feature Description

9.3.1 Support High Speed Translation, Greater than 100 MHz

Allows the LSF family to support more consumer or telecom interfaces (MDIO or SDIO).

9.3.2 Bidirectional Voltage Translation Without DIR Terminal

Minimizes system effort to develop voltage translation for bidirectional interface (PMBus, I2C, or SMbus).

9.3.3 5-V Tolerance on IO Port and 125°C Support

The LSF family, with 5-V tolerance and 125°C support, is flexible and compliant with TTL levels in industrial and

telecom applications.

9.3.4 Channel Specific Translation

The LSF family is able to set up different voltage translation levels on each channel.

9.3.5 Ioff, Partial Power Down Mode

When V_{ref_A}, V_{ref_B}= 0, all of data pins and EN pin are Hi-Z.

EN logic circuit is supplied by V_{ref_A}, once V_{ref_A}power up first and all of data pins are unknown state until V_{ref_B}

and EN ready. No power sequence is required to enable LSF0204 and operate function normally.

9.4 Device Functional Modes

表9-1 lists the device functional modes of the LSF0204x family of devices.

表9-1. Function Table

INPUT EN⁽¹⁾TERMINAL

FUNCTION

An = Bn

Hi-Z

H

L

(1) EN is controlled by V_{ref_A}logic levels.

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10 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

10.1 Application Information

LSF performs voltage translation for open-drain or push-pull interface. 表 10-1 provides some consumer/telecom

interfaces as reference in regards to the different channel numbers that are supported by the LSF family.

表10-1. Voltage Translator for Consumer/Telecom Interface

PART NAME

LSF0101

LSF0102

LSF0204

LSF0108

CH#

INTERFACE

1

2

4

8

GPIO

GPIO, MDIO, SMBus, PMBus, I2C

GPIO, SPI. MDIO, SMBus, PMBus, I2C, UART, SVID

GPIO, MDIO, SDIO, SVID, UART, SMBus, PMBus, I2C, SPI

10.2 Typical Applications

10.2.1 I²C PMBus, SMBus, GPIO, Application

Vpu_1 = 3.3 V

Vpu_2 = 1.8 V

Vrev_A = 1.8 V

Vrev_B = 3.3 V

1.8V

enable signal

ON

LSF0204

Off

Rpu

EN

B1

Rpu

A1

Vcc

SW

SDA

SCL

SDA

A2

A3

A4

B2

B3

B4

SCL

GND

图10-1. Bidirectional Translation to Multiple Voltage Levels

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10.2.1.1 Design Requirements

10.2.1.1.1 Enable, Disable, and Reference Voltage Guidelines

The LSF family has an EN input that is used to disable the device by setting EN LOW, which places all I/Os in

the high-impedance state. Since LSF family is switch-type voltage translator, the power consumption is very low.

It is recommended to always enable LSF family for bidirectional application (I2C, SMBus, PMBus, or MDIO).

表10-2. Application Operating Condition

SYMBOL PARAMETER

MIN

TYP

MAX

4.5

UNIT

Vref_A

Vref_B

Reference voltage (A)

0.8

V

Reference voltage (B)

Vref_A + 0.8

5.5

(1)

V_I(EN)

Vpu

Input voltage on EN terminal

Pull-up supply voltage

0

Vref_A

Vref_B

(1) Refer V_IHand V_ILfor V_I(EN)

Also Vref_B is recommended to be at 1.0 V higher than Vref_A for best signal integrity.

The LSF Family is able to set different voltage translation level on each channel.

备注

Vref_A must be set as lowest voltage level.

10.2.1.2 Detailed Design Procedure

10.2.1.2.1 Bidirectional Translation

The controller output driver may be push-pull or open-drain (pull-up resistors may be required) and the

peripheral device output can be push-pull or open-drain (pull-up resistors are required to pull the Bn outputs to

Vpu).

备注

However, if either output is push-pull, data must be unidirectional or the outputs must be 3-state and

be controlled by some direction-control mechanism to prevent HIGH-to-LOW contentions in either

direction. If both outputs are open-drain, no direction control is needed.

In 图 10-1, the reference supply voltage (Vref_A) is connected to the processor core power supply voltage.

When Vref_B is connected through to a 3.3 V Vpu power supply, and Vref_A is set 1.0V. The output of A3 and

B4 has a maximum output voltage equal to Vref_A, and the bidirectional interface (Ch1/2, MDIO) has a

maximum output voltage equal to Vpu.

10.2.1.2.1.1 Pull-Up Resistor Sizing

The pull-up resistor value needs to limit the current through the pass transistor when it is in the ON state to about

15 mA. This ensures a pass voltage of 260 mV to 350 mV. If the current through the pass transistor is higher

than 15 mA, the pass voltage also is higher in the ON state. To set the current through each pass transistor at 15

mA, to calculate the pull-up resistor value use 方程式1.

Rpu = (Vpu –0.35 V) / 0.015 A

(1)

表 10-3 summarizes resistor values, reference voltages, and currents at 15 mA, 10 mA, and 3 mA. The resistor

value shown in the +10% column (or a larger value) should be used to ensure that the pass voltage of the

transistor is 350 mV or less. The external driver must be able to sink the total current from the resistors on both

sides of the LSF family device at 0.175 V, although the 15 mA applies only to current flowing through the LSF

family device.

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表10-3. Pullup Resistor Values

PULLUP RESISTOR VALUE (Ω)

15 mA

NOMINAL

310

10 mA

+10%⁽¹⁾

341

3 mA

NOMINAL

465

V_DPU

+10%⁽¹⁾

512

NOMINAL

1550

983

+10%⁽¹⁾

1705

1082

788

5 V

3.3 V

2.5 V

1.8 V

1.5 V

1.2 V

197

217

295

325

143

158

215

237

717

97

106

145

160

483

532

77

85

115

127

383

422

57

63

85

94

283

312

(1) +10% to compensate for V_DDrange and resistor tolerance

10.2.1.2.2 LS Family Bandwidth

The maximum frequency of the LSF family is dependent on the application. The device may operate at speeds

of >100 MHz gave the correct conditions. The maximum frequency is dependent upon the loading of the

application. The LSF family behaves like a standard switch where the bandwidth of the device is dictated by the

on resistance and on capacitance of the device.

图10-2 shows a bandwidth measurement of the LSF family using a two-port network analyzer.

0

–1

–2

–3

–4

–5

–6

–7

–8

–9

0.1

1

10 100

Frequency (MHz)

1000

图10-2. 3-dB Bandwidth

The 3-dB point of the LSF family is ≈600 MHz; however, this measurement is an analog type of measurement.

For digital applications, the signal should not degrade up to the fifth harmonic of the digital signal. The frequency

bandwidth should be at least five times the maximum digital clock rate. This component of the signal is important

in determining the overall shape of the digital signal. In the case of the LSF family, a digital clock frequency of

greater than 100 MHz may be achieved.

The LSF family does not provide any drive capability. Therefore higher frequency applications will require higher

drive strength from the host side. No pullup resistor is needed on the host side (3.3 V) if the LSF family is being

driven by standard CMOS totem pole output driver. Best practice is to minimize the trace length from the LSF

family on the sink side (1.8 V) to minimize signal degradation.

All fast edges have an infinite spectrum of frequency components; however, there is an inflection (or knee) in the

frequency spectrum of fast edges where frequency components higher than f_kneeare insignificant in determining

the shape of the signal.

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To calculate the maximum practical frequency component, or the knee frequency (f_knee), use the following

equations:

f_knee= 0.5/RT (10–80%)

f_knee= 0.4/RT (20–80%)

(2)

(3)

For signals with rise time characteristics based on 10- to 90-percent thresholds, f_kneeis equal to 0.5 divided by

the rise time of the signal. For signals with rise time characteristics based on 20% to 80% thresholds, which is

very common in many of today's device specifications, f_kneeis equal to 0.4 divided by the rise time of the signal.

Some guidelines to follow that will help maximize the performance of the device:

• Keep trace length to a minimum by placing the LSF family close to the I²C output of the processor.

• The trace length should be less than half the time of flight to reduce ringing and line reflections or non-

monotonic behavior in the switching region.

• To reduce overshoots, a pullup resistor can be added on the 1.8 V side; be aware that a slower fall time is to

be expected.

10.2.1.3 Application Curve

4

Input

Output

3

2

±

0

±±

0

50 ±00 ±50 200 250 300 350 400 450 500

Time (ns)

图10-3. Captured Waveform From Above I²C Set-Up (1.8 V to 3.3 V at 2.5 MHz)

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10.2.2 MDIO Application

Vpu_1 = 3.3 V

Vpu_2 = 1.0 V

Vrev_A = 1.0 V

Vrev_B = 3.3 V

1.0V

enable signal

ON

LSF0204

Off

Rpu

EN

B1

Rpu

Vcc

A1

A2

A3

A4

Vcc

SW

MDC

B2

B3

B4

MDIO

GND

图10-4. Typical Application Circuit (MDIO/Bidirectional Interface)

10.2.2.1 Design Requirements

Refer to Design Requirements.

10.2.2.2 Detailed Design Procedure

Refer to Detailed Design Procedure

10.2.2.3 Application Curve

Input (3.3V)

Output (1.0V)

图10-5. Captured Waveform From Above MDIO Setup

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10.2.3 Multiple Voltage Translation in Single Device, Application

Vpu_1 = 3.3 V

Vrev_A = 1.8 V

Vrev_B = 3.3 V

Vpu_2 = 1.8 V

1.8V

enable signal

ON

LSF0204

Off

Rpu

EN

B1

Rpu Rpu

Rpu

A1

Vcc

SW

MDC

A2

A3

A4

B2

B3

B4

Vpu = 1.0 V

MDIO

SW

MDIO

Vcc

GPIO

GND

10.2.3.1 Design Requirements

Refer to Design Requirements.

10.2.3.2 Detailed Design Procedure

Refer to Detailed Design Procedure

10.2.3.3 Application Curve

3.5

3

Input

Output

2.5

2

1.5

1

0.5

0

-0.5

0

Time (ns)

图10-6. Translation Down (3.3 V to 1.8 V) at 150 MHz

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11 Power Supply Recommendations

There are no power sequence requirements for the LSF Family. Refer to 节 10.2.1.1.1 for enabling and

reference voltage guidelines.

12 Layout

12.1 Layout Guidelines

The signal integrity is highly related with pull-up resistor and PCB capacitance condition because LSF Family is

switch-type level translator

• Short signal trace as possible to reduce capacitance and minimize stub from pull-up resistor.

• Place LSF close to high voltage side.

• Select the appropriate pull-up resistor that applies to translation levels and driving capability of transmitter.

12.2 Layout Example

LSF0102

EN

GND

8

7

6

5

1

2

3

4

Short Signal Trace as possible

Vref_B

Vref_A

A1

A2

B1

B2

Minimize Stub as possible

图12-1. Short Trace Layout

TP1

SDIO Connector

(3.3V IO)

SD Controller

(1.8V IO)

LSF0108

SDIO level translator

Device PCB

TP2

图12-2. Device Placement

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3.5E+0

3E+0

2.5E+0

2E+0

1.5E+0

1E+0

5E-1

3.5

3

Intput

Output

Input

2.5

2

1.5

1

0.5

0

-5E-1

0

-0.5

0

Time (ns)

图12-3. Waveform From TP1 (Pullup Resistor: 160-

Ωand 50-pF Capacitance 3.3 to 1.8 V at 100 MHz)

图12-4. Waveform From TP2 (Pullup Resistor: 160-

Ωand 50-pF Capacitance 1.8 to 3.3 V at 100 MHz)

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13 Device and Documentation Support

13.1 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

13.2 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

13.3 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

13.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

13.5 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE

LSF0204/LSF0204D

YZP0012-C01

DSBGA - 0.5 mm max height

SCALE 8.000

DIE SIZE BALL GRID ARRAY

A

B

E

BALL A3

INDEX

AREA

D

C

0.5 MAX

SEATING PLANE

0.05 C

BALL TYP

0.19

0.15

1

TYP

SYMM

D

C

B

A

SYMM

1.5

TYP

D: Max = 1.972 mm, Min = 1.912 mm

E: Max = 1.472 mm, Min = 1.412 mm

0.5

TYP

1

2

3

0.25

0.21

12X

0.015

0.5 TYP

C A B

4224761/A 01/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

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EXAMPLE BOARD LAYOUT

LSF0204/LSF0204D

YZP0012-C01

DSBGA - 0.5 mm max height

DIE SIZE BALL GRID ARRAY

(0.5) TYP

12X ( 0.225)

A

B

(0.5) TYP

SYMM

C

D

1

2

3

SYMM

LAND PATTERN EXAMPLE

SCALE:30X

0.05 MAX

0.05 MIN

(

0.225)

METAL

UNDER

MASK

(

0.225)

SOLDER MASK

OPENING

SOLDER MASK

OPENING

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4224761/A 01/2019

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For more information, see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017).

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EXAMPLE STENCIL DESIGN

LSF0204/LSF0204D

YZP0012-C01

DSBGA - 0.5 mm max height

DIE SIZE BALL GRID ARRAY

(0.5) TYP

(R0.05) TYP

12X ( 0.25)

A

B

(0.5)

TYP

SYMM

METAL

TYP

C

D

2

SYMM

3

1

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE:30X

4224761/A 01/2019

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release.

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PACKAGE OUTLINE

RUT0012A

UQFN - 0.55 mm max height

SCALE 6.800

PLASTIC QUAD FLATPACK - NO LEAD

1.8

1.6

A

B

0.6

0.4

PIN 1 INDEX AREA

0.25

(0.15)

0.15

2.1

1.9

PIN 1 ID

OPTIONAL TERMINAL & PIN 1 ID

C

0.55 MAX

SEATING PLANE

0.08 C

0.05

0.00

SYMM

6

(0.15) TYP

10X 0.4

5

7

2X

SYMM

1.6

11

1

0.25

0.15

12

12X

PIN 1 ID

(OPTIONAL)

0.6

0.4

12X

0.1

C B A

C

0.05

4220310/A 11/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

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EXAMPLE BOARD LAYOUT

RUT0012A

UQFN - 0.55 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

SYMM

12

12X (0.7)

(R0.05) TYP

11

1

12X (0.2)

SYMM

(1.7)

8X (0.4)

7

5

6

(1.4)

LAND PATTERN EXAMPLE

SCALE:30X

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4220310/A 11/2016

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

RUT0012A

UQFN - 0.55 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

SYMM

12

12X (0.7)

(R0.05) TYP

11

1

12X (0.2)

SYMM

(1.7)

8X (0.4)

7

5

6

(1.4)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE: 30X

4220310/A 11/2016

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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型号：	LSF0204DYZPR
厂家：	TEXAS INSTRUMENTS
描述：	适用于漏极开路和推挽应用的 4 位双向多电压电平转换器 \| YZP \| 12 \| -40 to 125 转换器电平转换器
文件：	总35页 (文件大小：2056K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LSF0204DYZPR [TI]

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