LMH7324SQ/NOPB [TI]
具有 RSPECL 输出的微功耗 700ps 高速四路比较器 | RTV | 32 | -40 to 85;
| 型号： | LMH7324SQ/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 RSPECL 输出的微功耗 700ps 高速四路比较器 | RTV | 32 | -40 to 85 放大器 比较器 电视 |
| 文件： | 总32页 (文件大小：1059K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMH7324
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SNOSAZ2G –SEPTEMBER 2007–REVISED MARCH 2013
LMH7324 Quad 700 ps High Speed Comparator with RSPECL Outputs
Check for Samples: LMH7324
1
FEATURES
DESCRIPTION
The LMH7324 is a quad comparator with 700 ps
propagation delay and low dispersion of 20 ps for a
supply voltage of 5V. The input voltage range
extends 200 mV below the negative supply. This
enables the LMH7324 to ground sense even when
operating on a single power supply. The device
operates from a wide supply voltage range from 5V to
12V, which allows for a wide input voltage range.
However, if a wide input voltage range is not
required, operating from a single-ended 5V supply
results in a significant power savings, and less heat
dissipation.
2
•
•
•
•
•
•
(VCCI = VCCO = +5V, VEE = 0V.)
Propagation Delay 700 ps
Overdrive Dispersion 20 ps
Fast Rise and Fall Times 150 ps
Supply Range 5V to 12V
Input Common Mode Range Extends 200 mV
Below Negative Rail
•
RSPECL outputs
APPLICATIONS
The outputs of the LMH7324 are RSPECL compatible
and can also be configured to create LVDS levels.
The LMH7324 operates over the industrial
temperature range of −40°C to 125°C. The LMH7324
is available in a 32-Pin WQFN package.
•
•
•
•
•
•
Digital Receivers
High Speed Signal Restoration
Zero-crossing Detectors
High Speed Sampling
Window Comparators
High Speed Signal Triggering
Typical Application
V
CCI
V
CCO
10 nF
10 nF
V
CCO
V
CCI
IN-
Q
DEVICE WITH
RS(P)ECL INPUTS
¼ LMH7324
IN+
Q
51:
51:
V
EE
V
EE
51:
51:
VT
+
V
REF
10 nF
10 PF
GND
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
LMH7324
SNOSAZ2G –SEPTEMBER 2007–REVISED MARCH 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)
(2)
ESD Tolerance
Human Body Model
Machine Model
2.5 kV
250V
(3) (4)
Output Short Circuit Duration
See
Supply Voltages (VCCx –VEE
)
13.2V
±13V
Voltage at Input/Output Pins
Soldering Information
Infrared or Convection (20 sec.)
Wave Soldering (10 sec.)
Storage Temperature Range
235°C
260°C
−65°C to +150°C
+150°C
(3)
Junction Temperature
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Conditions indicate specifications
for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
(2) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC)
(3) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
(4) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
Operating Ratings(1)
Supply Voltage (VCCx – VEE
)
5V to 12V
Temperature Range
−40°C to +125°C
Package Thermal Resistance
32-Pin WQFN
36°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Conditions indicate specifications
for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
12V DC Electrical Characteristics
Unless otherwise specified, all limits are ensured for TJ = 25°C. VCCI = VCCO = 12V, VEE = 0V, RL = 50Ω to VCCO-2V, VCM = 300
(1)
mV.
Symbol Parameter
Input Characteristics
Conditions
Min(2)
Typ(3)
Max(2)
Units
(4)
IB
Input Bias Current
Input Offset Current
VIN Differential = 0V
VIN Differential = 0V
VIN Differential = 0V
VCM = 0V
−5
−2.5
40
µA
nA
IOS
−250
250
(5)
(5)
TC IOS
VOS
Input Offset Current TC
Input Offset Voltage
Input Offset Voltage TC
Input Voltage Range
0.15
nA/°C
mV
−9.5
+9.5
TC VOS
VRI
VCM = 0V
7
μV/°C
V
CMRR > 50 dB
VEE
VCCI−2
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self heating where TJ > TA.
(2) All limits are specified by testing or statistical analysis.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) Positive current corresponds to current flowing into the device.
(5) Average Temperature Coefficient is determined by dividing the change in a parameter at temperature extremes by the total temperature
change.
2
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12V DC Electrical Characteristics (continued)
Unless otherwise specified, all limits are ensured for TJ = 25°C. VCCI = VCCO = 12V, VEE = 0V, RL = 50Ω to VCCO-2V, VCM = 300
(1)
mV.
Symbol Parameter
VRID Input Differential Voltage Range
Conditions
Min(2)
Typ(3)
Max(2)
Units
V
VEE ≤ INP or INM ≤ VCCI
0V ≤ VCM ≤ VCC−2V
VCM = 0V, 5V ≤ VCC ≤ 12V
−12
+12
CMRR
PSRR
AV
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Active Gain
83
75
dB
dB
54
dB
Hyst
Hysteresis
Fixed Internal Value
20.8
mV
Output Characteristics
VOH
VOL
VOD
Output Voltage High
VIN Differential = 25 mV
VIN Differential = 25 mV
VIN Differential = 25 mV
10.78
10.43
300
10.85
10.50
345
10.93
10.58
400
V
V
Output Voltage Low
Output Voltage Differential
mV
Power Supplies
IVCCI
VCCI Supply Current/Channel
VCCO Supply Current/Channel
VIN Differential = 25 mV
VIN Differential = 25 mV
5.6
8
mA
IVCCO
11.6
17
12V AC Electrical Characteristics
Unless otherwise specified, all limits are ensured for TJ = 25°C. VCCI = VCCO = 12V, VEE = 0V, RL = 50Ω to VCCO-2V, VCM
300 mV.
=
(1)
Symbol
TR
Parameter
Conditions
Min(2)
Typ(3)
Max(2)
Units
Maximum Toggle Rate
Overdrive = ±50 mV, CL = 2 pF
@ 50% Output Swing
3.84
Gb/s
Minimum Pulse Width
RMS Random Jitter
Overdrive = ±50 mV, CL = 2 pF
@ 50% Output Swing
280
615
ps
fs
tjitter-RMS
Overdrive = ±100 mV, CL = 2 pF
Center Frequency = 140 MHz
Bandwidth = 10 Hz–20 MHz
tPDH
Propagation Delay
(see Figure 15 application note)
Overdrive 20 mV
737
720
706
731
31
Overdrive 50 mV
ps
Input SR = Constant
VIN Startvalue = VREF −100 mV
Overdrive 100 mV
Overdrive 1V
tOD-disp
Input Overdrive Dispersion
tPDH @ Overdrive 20 mV ↔ 100 mV
tPDH @ Overdrive 100 mV ↔ 1V
ps
ps
25
tSR-disp
tCM-disp
ΔtPDLH
ΔtPDHL
Input Slew Rate Dispersion
0.1 V/ns to 1 V/ns
Overdrive 100 mV
40
Input Common Mode Dispersion
SR = 1 V/ns, Overdrive 100 mV,
0V ≤ VCM ≤ VCCI – 2V
28
55
40
ps
ps
ps
Q to Q Time Skew
Overdrive = 50 mV, CL = 2 pF
(4)
| tPDH - tPDL
|
Q to Q Time Skew
Overdrive = 50 mV, CL = 2 pF
(4)
| tPDL - tPDH
|
tr
tf
Output Rise Time (20% - 80%)(5)
Output Fall Time (20% - 80%)(5)
Overdrive = 50 mV, CL = 2 pF
Overdrive = 50 mV, CL = 2 pF
140
140
ps
ps
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self heating where TJ > TA.
(2) All limits are specified by testing or statistical analysis.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) Propagation Delay Skew, ΔtPD, is defined as the average of ΔtPDLH and ΔtPDHL
.
(5) The rise or fall time is the average of the Q and Q rise or fall time.
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5V DC Electrical Characteristics
Unless otherwise specified, all limits are ensured for TJ = 25°C. VCCI = VCCO = 5V, VEE = 0V, RL = 50Ω to VCCO-2V, VCM = 300
(1)
mV.
Symbol
Parameter
Conditions
VIN Differential = 0V
Min
Typ
Max
Units
(2)
(3)
(2)
(4)
IB
Input Bias Current
−5
−2.2
30
µA
nA
IOS
Input Offset Current
Input Offset Current TC
Input Offset Voltage
Input Offset Voltage TC
Input Voltage Range
VIN Differential = 0V
VIN Differential = 0V
VCM = 0V
−250
+250
+9.5
(5)
(5)
TC IOS
VOS
0.1
nA/°C
mV
μV/°C
V
−9.5
TC VOS
VRI
VCM = 0V
7
CMRR > 50 dB
VEE
VCCI−2
VRID
Input Differential Voltage Range
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Active Gain
VEE ≤ INP or INM ≤ VCCI
0V ≤ VCM ≤ VCC−2V
VCM = 0V, 5V ≤ VCC ≤ 12V
−5
+5
V
CMRR
PSRR
AV
80
75
dB
dB
54
dB
Hyst
Hysteresis
Fixed Internal Value
22.5
mV
Output Characteristics
VOH
VOL
VOD
Output Voltage High
VIN Differential = 25 mV
VIN Differential = 25 mV
VIN Differential = 25 mV
3.8
3.45
300
3.87
3.52
345
3.95
3.60
400
V
V
Output Voltage Low
Output Voltage Differential
mV
Power Supplies
IVCCI
VCCI Supply Current/Channel
VCCO Supply Current/Channel
VIN Differential = 25 mV
VIN Differential = 25 mV
5.4
11
7.5
15
mA
mA
IVCCO
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self heating where TJ > TA.
(2) All limits are specified by testing or statistical analysis.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) Positive current corresponds to current flowing into the device.
(5) Average Temperature Coefficient is determined by dividing the change in a parameter at temperature extremes by the total temperature
change.
5V AC Electrical Characteristics
Unless otherwise specified, all limits are ensured for TJ = 25°C. VCCI = VCCO = 5V, VEE = 0V, RL = 50Ω to VCCO-2V, VCM = 300
(1)
mV.
Symbol
TR
Parameter
Maximum Toggle Rate
Minimum Pulse Width
RMS Random Jitter
Conditions
Min
Typ
Max
Units
Gb/s
ps
(2)
(3)
(2)
Overdrive = ±50 mV, CL = 2 pF
@ 50% Output Swing
3.72
290
602
Overdrive = ±50 mV, CL = 2 pF
@ 50% Output Swing
tjitter-RMS
Overdrive = ±100 mV, CL = 2 pF
Center Frequency = 140 MHz
Bandwidth = 10 Hz–20 MHz
fs
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self heating where TJ > TA.
(2) All limits are specified by testing or statistical analysis.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
4
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SNOSAZ2G –SEPTEMBER 2007–REVISED MARCH 2013
5V AC Electrical Characteristics (continued)
Unless otherwise specified, all limits are ensured for TJ = 25°C. VCCI = VCCO = 5V, VEE = 0V, RL = 50Ω to VCCO-2V, VCM = 300
(1)
mV.
Symbol
tPDH
Parameter
Propagation Delay
Conditions
Overdrive 20 mV
Min
Typ
Max
Units
(2)
(3)
(2)
740
731
722
740
18
(see Figure 15 application note)
Overdrive 50 mV
ps
Input SR = Constant
VIN Startvalue = VREF −100 mV
Overdrive 100 mV
Overdrive 1V
tOD-disp
Input Overdrive Dispersion
TPDH @ Overdrive 20 mV ↔ 100 mV
TPDH @ Overdrive 100 mV ↔ 1V
ps
ps
19
tSR-disp
tCM-disp
Input Slew Rate Dispersion
0.1 V/ns to 1 V/ns,
Overdrive = 100 mV
40
Input Common Mode Dispersion
SR = 1 V/ns, Overdrive 100 mV,
0V ≤ VCM ≤ VCCI – 2V
24
60
ps
ps
ps
ps
ps
ΔtPDLH-disp Q to Q Time Skew
Overdrive = 50 mV, CL = 2 pF
Overdrive = 50 mV, CL = 2 pF
Overdrive = 50 mV, CL = 2 pF
Overdrive = 50 mV, CL = 2 pF
(4)
| tPDH - tPDL
|
ΔtPDHL
Q to Q Time Skew
40
(4)
| tPDL - tPDH
|
tr
tf
Output Rise Time (20% - 80%)
145
145
(5)
Output Fall Time (20% - 80%)
(5)
(4) Propagation Delay Skew, ΔtPD, is defined as the average of ΔtPDLH and ΔtPDHL
(5) The rise or fall time is the average of the Q and Q rise or fall time.
.
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Connection Diagram
V
V
CCO
CCI
IN-
Q
¼
LMH7324
IN+
Q
V
V
EE
EE
32
31
30
29
28
27
26
25
V
CCOA
1
2
3
4
5
6
24
23
22
21
20
19
18
17
V
CCOD
QA
QD
QD
QA
V
V
V
EEA
EED
EEC
LMH7324
V
EEB
QB
QC
QC
QB
7
8
V
V
CCOC
CCOB
15
9
10
11
12
13
14
16
Figure 1. 32-Pin WQFN
Top View
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SNOSAZ2G –SEPTEMBER 2007–REVISED MARCH 2013
Typical Performance Characteristics
At TJ = 25°C, V+ = +5V, V− = 0V, unless otherwise specified.
Propagation Delay vs.Supply Voltage
Propagation Delay vs.Temperature
900
850
800
750
700
650
600
900
850
800
750
700
650
600
V
V
= 300 mV
CM
= ±100 mV
INDIFF
125°C
85°C
V
= 5V
S
-40°C
0°and 25°C
V
= 12V
50
S
V
V
= 300 mV
CM
= ±100 mV
IN
10
12
125
75 100
5
6
7
8
9
11
-50 -25
0
25
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
Figure 2.
Figure 3.
Propagation Delay vs.Supply Voltage for Different
Propagation Delay vs.Overdrive Voltage
Overdrive
900
850
800
750
700
650
600
850
V
= 300 mV
CM
V
= 300 mV
CM
825
800
775
750
725
700
675
650
V
= (V
- 100 mV) to
IN
CM
V
= (V
- 100 mV) to
IN
CM
(V
+ V
)
OVERDRIVE
CM
(V
+ V
)
CM
OVERDRIVE
1000 mV
12V
50 mV
100 mV
8
5
6
9
11
12
0
300
600
900
1200
1500
SUPPLY VOLTAGE (V)
OVERDRIVE VOLTAGE (mV)
Figure 4.
Figure 5.
Propagation Delay vs.Common Mode Voltage
800
Propagation Delay vs.Slew Rate
900
850
800
750
700
650
600
V
V
= 300 mV
= 100 mV
CM
OD
750
5V
12V
5V
12V
700
650
SR = 2 V/ns
V
= ±100 mV
IN
600
-1
0
200
400
600
800
1000
1
2 4
6
3 5 7 8
9 10 11 12
0
SLEW RATE (V/µs)
COMMON MODE VOLTAGE (V)
Figure 6.
Figure 7.
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Typical Performance Characteristics (continued)
At TJ = 25°C, V+ = +5V, V− = 0V, unless otherwise specified.
Pulse Response and Maximum Toggle Rate
Bias Current vs.Temperature
400
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
140 MHz
300
200
100
0
-100
-200
-300
-400
-500
V
V
V
= 5V
S
= 2.5V
CM
INDIFF
= 0V
V
= 5V
S
0
2
4
6
8
10
-50 -25
0
25
50
75 100 125
TIME (ns)
Figure 8.
TEMPERATURE (°C)
Figure 9.
Input Current vs.Differential Input Voltage
Output Voltage vs.Input Voltage
0.4
0.3
0.2
0.1
0
1
25°C & -40°C
0
V
V
V
V
= 2.5V
CM
-1
-2
-3
-4
-5
= 5V
S
= 0 to 5V
= 5 to 0V
IN+
IN-
125°C
125°C
-0.1
-0.2
-0.3
-0.4
I
I
V
V
= 5V
B+
B-
S
= 300 mV
CM
-5 -4 -3 -2 -1
0
1
2
3
4
5
-40 -30 -20 -10
0
10 20 30 40
DIFFERENTIAL INPUT VOLTAGE (V)
DIFFERENTIAL INPUT VOLTAGE (mV)
Figure 10.
Figure 11.
Hysteresis Voltage vs. Temperature
30
29
28
27
26
25
24
23
22
21
20
V
V
= 5V
S
= 300 mV
CM
-50 -25
0
25
50
75 100 125
TEMPERATURE (°C)
Figure 12.
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APPLICATION INFORMATION
INTRODUCTION
The LMH7324 is a high speed comparator with RS(P)ECL (Reduced Swing Positive Emitter Coupled Logic)
outputs, and is compatible with LVDS (Low Voltage Differential Signaling) if VCCO is set to 2.5V. The use of
complementary outputs gives a high level of suppression for common mode noise. The very fast rise and fall
times of the LMH7324 enable data transmission rates up to several Gigabits per second (Gbps). The LMH7324
inputs have a common mode voltage range that extends 200 mV below the negative supply voltage thus allowing
ground sensing when used with a single supply. The rise and fall times of the LMH7324 are about 150 ps, while
the propagation delay time is about 700 ps. The LMH7324 can operate over the supply voltage range of 5V to
12V, while using single or dual supply voltages. This is a flexible way to interface between several high speed
logic families. Several configurations are described in the section INTERFACE BETWEEN LOGIC FAMILIES.
The outputs are referenced to the positive VCCO supply rail. The supply current is 17 mA at 5V (per comparator,
load current excluded.) The LMH7324 is offered in a 32-Pin WQFN package. This small package is ideal where
space is an important issue.
INPUT & OUTPUT TOPOLOGY
All input and output pins are protected against excessive voltages by ESD diodes. These diodes are conducting
from the negative supply to the positive supply. As can be seen in Figure 13, both inputs are connected to these
diodes. Protection against excessive supply voltages is provided by two power clamps per comparator: one
between the VCCI and the VEE and one between the VCCO and the VEE
.
V
CCI
V
CCI
V
V
CCI
CCI
V
CCO
IN-
IN+
V
V
EE
V
EE
EE
Power
Clamp
2X per Comparator
Figure 13. Equivalent Input Circuitry
The output stage of the LMH7324 is built using two emitter followers, which are referenced to the VCCO. (See
Figure 14.) Each of the output transistors is active when a current is flowing through any external output resistor
connected to a lower supply rail. Activating the outputs is done by connecting the emitters to a termination
voltage which lies 2V below the VCCO. In this case a termination resistor of 50Ω can be used and a transmission
line of 50Ω can be driven. Another method is to connect the emitters through a resistor to the most negative
supply by calculating the right value for the emitter current in accordance with the datasheet tables. Both
methods are useful, but they each have good and bad aspects.
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V
CCO
Output Q
Output Q
V
EE
Figure 14. Equivalent Output Circuitry
The output voltages for ‘1’ and ‘0’ have a difference of approximately 400 mV and are respectively 1.1V (for the
‘1’) and 1.5V (for the ‘0’) below the VCCO. This swing of 400 mV is enough to drive any LVDS input but can also
be used to drive any ECL or PECL input, when the right supply voltage is chosen, especially the right level for
the VCCO
.
DEFINITIONS
This table provides a short description of the parameters used in the datasheet and in the timing diagram of
Figure 15.
Symbol
Text
Input Bias Current
Description
IB
Current flowing in or out of the input pins, when both are biased at the VCM
voltage as specified in the tables.
IOS
Input Offset Current
Difference between the input bias current of the inverting and non-inverting
inputs.
TC IOS
VOS
Average Input Offset Current Drift
Input Offset Voltage
Temperature coefficient of IOS.
Voltage difference needed between IN+ and IN− to make the outputs change
state, averaged for H to L and L to H transitions.
TC VOS
VRI
Average Input Offset Voltage Drift
Input Voltage Range
Temperature coefficient of VOS.
Voltage which can be applied to the input pin maintaining normal operation.
VRID
Input Differential Voltage Range
Differential voltage between positive and negative input at which the input clamp
is not working. The difference can be as high as the supply voltage but excessive
input currents are flowing through the clamp diodes and protection resistors.
CMRR
PSRR
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Ratio of input offset voltage change and input common mode voltage change.
Ratio of input offset voltage change and supply voltage change from VS-MIN to VS-
.
MAX
AV
Active Gain
Overall gain of the circuit.
Hyst
VOH
VOL
Hysteresis
Difference between the switching point ‘0’ to ‘1’ and vice versa.
High state single ended output voltage (Q or Q). (See Figure 29)
Low state single ended output voltage (Q or Q). (See Figure 29)
(VODH + VODL)/2
Output Voltage High
Output Voltage Low
Average of VODH and VODL
Supply Current Input Stage
Supply Current Output Stage
VOD
IVCCI
IVCCO
Supply current into the input stage.
Supply current into the output stage while current through the load resistors is
excluded.
IVEE
TR
Supply Current VEE Pin
Maximum Toggle Rate
Current flowing out of the negative supply pin.
Maximum frequency at which the outputs can toggle at 50% of the nominal VOH
and VOL
.
PW
Pulse Width
Time from 50% of the rising edge of a signal to 50% of the falling edge.
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Symbol
Text
Propagation Delay
Description
tPDH resp tPDL
Delay time between the moment the input signal crosses the switching level L to
H and the moment the output signal crosses 50% of the rising edge of Q output
(tPDH), or delay time between the moment the input signal crosses the switching
level H to L and the moment the output signal crosses 50% of the falling edge of
Q output (tPDL).
tPDLresp tPDH
Delay time between the moment the input signal crosses the switching level L to
H and the moment the output signal crosses 50% of the falling edge of Q output
(tPDL), or delay time between the moment the input signal crosses the switching
level H to L and the moment the output signal crosses 50% of the rising edge of
Q output (tPDH).
tPDLH
Average of tPDH and tPDL
Average of tPDL and tPDH
Average of tPDLH and tPDHL
tPDHL
tPD
tPDHd resp tPDLd
Delay time between the moment the input signal crosses the switching level L to
H and the zero crossing of the rising edge of the differential output signal (tPDHd),
or delay time between the moment the input signal crosses the switching level H
to L and the zero crossing of the falling edge of the differential output signal
(tPDLd).
tOD-disp
tSR-disp
tCM-disp
Input Overdrive Dispersion
Input Slew Rate Dispersion
Input Common Mode Dispersion
Q to Q Time Skew
Change in tPD for different overdrive voltages at the input pins.
Change in tPD for different slew rates at the input pins.
Change in tPD for different common mode voltages at the input pins.
ΔtPDLH resp
ΔtPDHL
Time skew between 50% levels of the rising edge of Q output and the falling
edge of Q output (ΔtPDLH), or time skew between 50% levels of falling edge of Q
output and rising edge of Q output (ΔtPDHL).
ΔtPD
ΔtPDd
tr/trd
Average Q to Q Time Skew
Average Diff. Time Skew
Average of tPDLH and tPDHL for L to H and H to L transients.
Average of tPDHd and tPDLd for L to H and H to L transients.
Output Rise Time (20% - 80%)
Time needed for the (single ended or differential) output voltage to change from
20% of its nominal value to 80%.
tf/tfd
Output Fall Time (20% - 80%)
Time needed for the (single ended or differential) output voltage to change from
80% of its nominal value to 20%.
PW
V
overdrive
Differential
Input Signal
t
t
t
= (t
= (t
+ t
+ t
)/ 2
)/ 2
)/ 2
PDLH
PDHL
PD
PDH
PDL
PDL
0
't
PDH
PDLH
't
PDHL
t
f
= (t
+ t
PDHL
PDLH
t
r
t
PDH
80%or90%
10%or20%
't
't
= | t
- t
PDH PDL
|
|
PDLH
V
V
t
O
PDL
Output Q
Output Q
= | t
- t
PDL PDH
PDHL
t
PDH
't = ꢀ't
PD PDLH
+ 't
)/ 2
PDHL
O
t
PDL
't
't
= | t
- t
PDH PDL
|
|
PDQ
PDQ
t
rd
= | t - t
PDL PDH
t
PDHd
80% or 90%
Differential
Output Signal
0
t
= (t
+ t
PDLd
)/ 2
PDd
PDHd
t
PDLd 10% or 20%
't
= | t
- t |
PDHd PDLd
PDd
t
fd
Figure 15. Timing Definitions
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PIN DESCRIPTIONS
Pin Name
Description
Part
Comment
1.
VCCO
Positive Supply Output Stage
A
This supply pin is independent of the supply for the input stage. This
allows output levels of different logic families.
2.
3.
4.
Q
Inverted Output
Output
A
A
A
Output levels are determined by the choice of VCCOA
.
.
Q
Output levels are determined by the choice of VCCOA
VEE
Negative Supply
All four VEE pins are circular connected together via two antiparallel
diodes. (See Figure 16)
5.
VEE
Negative Supply
B
All four VEE pins are circular connected together via two antiparallel
diodes. (See Figure 16)
6.
7.
8.
Q
Output
B
B
B
Output levels are determined by the choice of VCCOB
.
.
Q
Inverted Output
Output levels are determined by the choice of VCCOB
VCCO
Positive Supply Output Stage
This supply pin is independent of the supply for the input stage. This
allows output levels of different logic families.
9.
VCCI
Positive Supply for Input Stage
Negative Input
B
B
B
B
C
C
C
C
C
This supply pin is independent of the supply for the output stage.
VCCIand VCCO share the same ground pin VEE
Input for analog voltages between 200 mV below VEE and 2V below
VCCI
Input for analog voltages between 200 mV below VEE and 2V below
VCCI
.
10. IN−
11. IN+
12. VEE
13. VEE
14. IN+
15. IN−
16. VCCI
17. VCCO
.
Positive Input
.
Negative Supply
All four VEE pins are circular connected together via two antiparallel
diodes. (See Figure 16)
Negative Supply
All four VEE pins are circular connected together via two antiparallel
diodes. (See Figure 16)
Positive Input
Input for analog voltages between 200 mV below VEE and 2V below
VCCI
Input for analog voltages between 200 mV below VEE and 2V below
VCCI
This supply pin is independent of the supply for the output stage. VCCI
and VCCO share the same ground pin VEE
.
Negative Input
.
Positive Supply for Input Stage
Positive Supply Output Stage
.
This supply pin is independent of the supply for the input stage. This
allows output levels of different logic families.
18.
19.
Q
Q
Inverted Output
Output
C
C
C
Output levels are determined by the choice of VCCOC
Output levels are determined by the choice of VCCOC
.
.
20. VEE
Negative Supply
All four VEE pins are circular connected together via two antiparallel
diodes. (See Figure 16)
21. VEE
Negative Supply
D
All four VEE pins are circular connected together via two antiparallel
diodes. (See Figure 16)
22.
23.
Q
Q
Output
D
D
D
Output levels are determined by the choice of VCCOD
Output levels are determined by the choice of VCCOD
.
.
Inverted Output
24. VCCO
25. VCCI
26. IN−
27. IN+
28. VEE
29. VEE
30. IN+
31. IN−
Positive Supply Output Stage
This supply pin is independent of the supply for the input stage. This
allows output levels of different logic families.
Positive Supply for Input Stage
Negative Input
D
D
D
D
A
A
A
This supply pin is independent of the supply for the output stage. VCCI
and VCCO share the same ground pin VEE
Input for analog voltages between 200 mV below VEE and 2V below
VCCI
Input for analog voltages between 200 mV below VEE and 2V below
VCCI
.
.
Positive Input
.
Negative Supply
Negative Supply
Positive Input
All four VEE pins are circular connected together via two antiparallel
diodes. (See Figure 16)
All four VEE pins are circular connected together via two antiparallel
diodes. (See Figure 16)
Input for analog voltages between 200 mV below VEE and 2V below
VCCI
Input for analog voltages between 200 mV below VEE and 2V below
VCCI
.
Negative Input
.
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PIN DESCRIPTIONS (continued)
Pin Name
Description
Part
Comment
32. VCCI
Positive Supply for Input Stage
A
This supply pin is independent of the supply for the output stage. VCCI
and VCCO share the same ground pin VEE
.
33. DAP
Central Pad at the Bottom of the
Package
All
The purpose of this pad is to transfer heat outside the part.
TIPS & TRICKS USING THE LMH7324
This section discusses several aspects concerning special applications using the LMH7324.Topics include the
connection of the DAP in conjunction to the VEE pins and the use of this part as an interface between several
logic families. Other sections discuss several widely used definitions and terms for comparators. The final
sections explain some aspects of transmission lines and the choice for the most suitable components handling
very fast pulses.
THE DAP AND THE VEE PINS
To protect the device against damage during handling and production, two antiparallel connected diodes are
placed between the VEE pins. Under normal operating conditions (all VEE pins have the same voltage level) these
diodes are not functioning, as can be seen in Figure 16.
The DAP (Die Attach Paddle) functions as a heat sink which means that heat can be transferred, using vias
below this pad, to any appropriate copper plane. The DAP is isolated from all other electrical connections and
therefore it is possible to connect this pad to any voltage within the allowed voltage range of the part. Using a
DAP connection it is common practice to connect such a pad to the lowest supply voltage. However in high
frequency designs it can be useful to connect this pad to another supply such as e.g. the ground plane, while the
VEE is for example -5 Volt.
V
EE
D
C
A
B
DAP
V
EE
Figure 16. DAP and VEE Configuration
INTERFACE BETWEEN LOGIC FAMILIES
The LMH7324 can be used to interface between different logic families. The feature that facilitates this is the fact
that the input stage and the output stage use different positive power supply pins which can be used at different
voltages. The only restriction is that both input (VCCI) and output (VCCO) supplies require a minimum of 5V
difference relative to VEE. The negative supply pins are connected together for all four parts. Using the power
pins at different supply voltages enables level-translation between two logic families. For example, it is possible
to translate from logic at negative voltage levels , such as ECL, to logic at positive levels, such as RSPECL and
LVDS and vice versa.
Interface from ECL to RSPECL
The supply pin VCCI can be connected to ground because the input levels are negative and VEE is at −5.2V. With
this setup the minimum requirements for the supply voltage of 5V are obtained. The VCCO pin must operate at
+5V to create the RSPECL levels. (See Figure 17.)
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5V
+
V
CCI
V
CCO
Line Termination
Coupled
Transmission Line
ECL Driver
IN+
IN-
Q
RS-PECL Output
¼
LMH7324
V
OH
= 3.9V
V
OL
= 3.5V
Q
V
EE
V
EE
-5.2V
+
Figure 17. ECL TO RSPECL
Interface from PECL to (RS) ECL
This setup needs the VCCI pin at +5V because the input logic levels are positive. To obtain the ECL levels at the
output it is necessary to connect the VCCO to the ground while the VEE has to be connected to the −5.2V. The
reason for this is that the minimum requirement for the supply is 5V. The high level of the output of the LMH7324
is normally 1.1V below the VCCO supply voltage, and the low level is 1.5V below this supply. The output levels
are now −1100 mV for the logic ‘1’ and −1500 mV for the logic ‘0’. (See Figure 18.)
5V
+
V
CCI
V
CCO
Line Termination
PECL Driver
Coupled
IN+
IN-
Transmission Line
Q
RSECL Levels:
¼
LMH7324
V
OH
OL
= -1100 mV
V
= -1500 mV
Q
PECL levels:
V
= 3.9V
OH
OL
V
= 3.5V
V
EE
V
EE
-5.2V
+
Figure 18. PECL TO RSECL
Interface from Analog to LVDS
As seen in Figure 19, the LMH7324 can be configured to create LVDS levels. This is done by connecting the
VCCO to 2.5V. As discussed before, the output levels are now at VCCO −1.1V for the logic ‘1’ and at VCCO -1.5V for
the logic ‘0’. These levels of 1000 mV and 1400 mV comply with the LVDS levels. As can be seen in this setup,
an AC coupled signal via a transmission line is used. This signal is terminated with 50Ω to the ground. The input
stage has its supply from +5V to −5V, which means that the input common mode level is midway between the
input stage supply voltages.
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2.5V
+
5V
+
V
CCI
V
CCO
50:
+
-
IN+
IN-
Q
Levels:
¼
LMH7324
V
OH
V
OL
= 1.4V
= 1.0V
Q
Signal Source
50:
50:
V
V
EE
EE
-5V
+
Figure 19. ANALOG TO LVDS
STANDARD COMPARATOR SETUP
Figure 20 shows a standard comparator setup which creates RSPECL levels because the VCCO supply voltage is
+5V. In this setup the VEE pin is connected to the ground level. The VCCI pin is connected to the VCCO pin
because there is no need to use different positive supply voltages. The input signal is AC coupled to the positive
input. To maintain reliable results, even for signals with larger amplitudes, the input pins IN+ and IN− are biased
at 1.4V through a resistive divider using a resistor of 1 kΩ to ground and a resistor of 2.5 kΩ to the VCC and by
adding two decoupling capacitors. Both inputs are connected to the bias level by the use of a 10 kΩ resistor.
With this input configuration the input stage can work in a linear area with signals of approximately 3 VPP. (See
input level restrictions in the data tables.)
5V
+
V
CCI
V
CCO
2.5 k:
V
IN
IN+
IN- LMH7324
Q
Levels:
¼
V
OH
= 3.9V
V
OL
= 3.5V
Q
10 k:
10 k:
V
EE
V
EE
V
REF
+
1 k:
Figure 20. Standard Setup
DELAY AND DISPERSION
Comparators are widely used to connect the analog world to the digital one. The accuracy of a comparator is
dictated by its DC properties, such as offset voltage and hysteresis, and by its timing aspects, such as rise and
fall times and delay. For low frequency applications most comparators are much faster than the analog input
signals they handle. The timing aspects are less important here than the accuracy of the input switching levels.
The higher the frequencies, the more important the timing properties of the comparator become, because the
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response of the comparator can make a noticeable change in critical parameters such as time frame or duty
cycle. A designer has to know these effects and has to deal with them. In order to predict what the output signal
will do, several parameters are defined which describe the behavior of the comparator. For a good understanding
of the timing parameters discussed in the following section, a brief explanation is given and several timing
diagrams are shown for clarification.
PROPAGATION DELAY
The propagation delay parameter is described in the definition section. Two delay parameters can be
distinguished, tPDH and tPDL as shown in Figure 21. Both parameters do not necessarily have the same value. It is
possible that differences will occur due to a different response of the internal circuitry. As a derivative of this
effect another parameter is defined: ΔtPD. This parameter is defined as the absolute value of the difference
between tPDH and tPDL
.
PW
80%
50%
20%
80%
50%
20%
V
IN
t
PDH
t
PDL
80%
50%
20%
80%
50%
20%
Output Q
t
t
f
r
Figure 21. Propagation Delay
If ΔtPD is not zero, duty cycle distortion will occur. For example when applying a symmetrical waveform (e.g. a
sinewave) at the input, it is expected that the comparator will produce a symmetrical square wave at the output
with a duty cycle of 50%. When tPDH and tPDL are different, the duty cycle of the output signal will not remain at
50%, but will be increased or decreased. In addition to the propagation delay parameters for single ended
outputs discussed before, there are other parameters in the case of complementary outputs. These parameters
describe the delay from input to each of the outputs and the difference between both delay times. (See
Figure 22.) When the differential input signal crosses the reference level from L to H, both outputs will switch to
their new state with some delay. This is defined as tPDH for the Q output and tPDL for the Q output, while the
difference between both signals is defined as ΔtPDLH. Similar definitions for the falling slope of the input signal
can be seen in Figure 15.
V
REF
time
time
t
PDH
V
O
't
PDLH
V
O
time
t
PDL
Figure 22. tPD with Complementary Outputs
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Both output circuits should be symmetrical. At the moment one output is switching ‘on’ the other is switching ‘off’
with ideally no skew between both outputs. The design of the LMH7324 is optimized so that this timing difference
is minimized. The propagation delay, tPD, is defined as the average delay of both outputs at both slopes: (tPDLH
tPDHL)/2. Both overdrive and starting point should be equally divided around the VREF (absolute values).
+
DISPERSION
There are several circumstances that will produce a variation of the propagation delay time. This effect is called
dispersion.
Amplitude Overdrive Dispersion
One of the parameters that causes dispersion is the amplitude variation of the input signal. Figure 23 shows the
dispersion due to a variation of the input overdrive voltage. The overdrive is defined as the ‘go to’ differential
voltage applied to the inputs. Figure 23 shows the impact it has on the propagation delay time if the overdrive is
varied from 10 mV to 100 mV. This parameter is measured with a constant slew rate of the input signal.
Overdrive 100 mV
+
Overdrive 10 mV
0
time
-100 mV
-
Overdrive Dispersion
+
Dispersion
0
time
-
Figure 23. Overdrive Dispersion
The overdrive dispersion is caused by the switching currents in the input stage which are dependent on the level
of the differential input signal.
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Slew Rate Dispersion
The slew rate is another parameter that affects propagation delay. The higher the input slew rate, the faster the
input stage switches. (See Figure 24.)
+
0
time
-
Slew Rate Dispersion
+
Dispersion
0
time
-
Figure 24. Slew Rate Dispersion
A combination of overdrive and slew rate dispersion occurs when applying signals with different amplitudes at
constant frequency. A small amplitude will produce a small voltage change per time unit (dV/dt) but also a small
maximum switching current (overdrive) in the input transistors. High amplitudes produce a high dV/dt and a
bigger overdrive.
Common Mode Dispersion
Dispersion will also occur when changing the common mode level of the input signal. (See Figure 25.) When
VREF is swept through the CMVR (Common Mode Voltage Range), it results in a variation of the propagation
delay time. This variation is called Common Mode Dispersion.
Vin cm
+
Vin cm
0
time
-
Common Mode Dispersion
+
Dispersion
0
time
-
Figure 25. Common Mode Dispersion
All of the dispersion effects described previously influence the propagation delay. In practice the dispersion is
often caused by a combination of more than one varied parameter.
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HYSTERESIS & OSCILLATIONS
In contrast to an op amp, the output of a comparator has only two defined states ‘0’ or ‘1.’ Due to finite
comparator gain however, there will be a small band of input differential voltage where the output is in an
undefined state. An input signal with fast slopes will pass this band very quickly without problems. During slow
slopes however, passing the band of uncertainty can take a relatively long time. This enables the comparators
output to switch back and forth several times between ‘0’ and ‘1’ on a single slope. The comparator will switch on
its input noise, ground bounce (possible oscillations), ringing etc. Noise in the input signal will also contribute to
these undesired switching actions.
The next sections explain these phenomena in situations where no hysteresis is applied, and discuss the
possible improvement hysteresis can give.
Using No Hysteresis
Figure 26 shows what happens when the input signal rises from just under the threshold VREF to a level just
above it. From the moment the input reaches the lowest dotted line around VREF at t = 0, the output toggles on
noise etc. Toggling ends when the input signal leaves the undefined area at t = 1. In this example the output was
fast enough to toggle three times. Due to this behavior digital circuitry connected to the output will count a wrong
number of pulses. One way to prevent this is to choose a very slow comparator with an output that is not able to
switch more than once between ‘0’ and ‘1’ during the time the input state is undefined.
mV
V
REF
time
time
1
0
1
0
time
t = 0
t = 1
Figure 26. Oscillations on Output Signal
In most circumstances this is not an option because the slew rate of the input signal will vary.
Using Hysteresis
A good way to avoid oscillations and noise during slow slopes is the use of hysteresis. With hysteresis the
switching level is forced to a new level at the moment the input signal crosses this level. This can be seen in
Figure 27.
mV
A
V
REF
B
1
0
t = 0
t = 1
Figure 27. Hysteresis
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In this picture there are two dotted lines A and B, both indicating the resulting level at which the comparator
output will switch over. Assume that for this situation the input signal is connected to the negative input and the
switching level (VREF) to the positive input. The LMH7324 has a built-in hysteresis voltage that is fixed at
approximately 20 mVPP. The input level of Figure 27 starts much lower than the reference level and this means
that the state of the input stage is well defined with the inverting input much lower than the non-inverting input.
As a result the output will be in the high state. Internally the switching level is at A, with the input signal sloping
up, this situation remains until VIN crosses level A at t = 1. Now the output toggles, and the internal switching
level is lowered to level B. So before the output has the possibility to toggle again, the difference between the
inputs is made sufficient to have a stable situation again. When the input signal comes down from high to low,
the situation is stable until level B is reached at t = 0. At this moment the output will toggle back, and the circuit is
back in the starting situation with the inverting input at a much lower level than the non-inverting input. In the
situation without hysteresis, the output will toggle exactly at VREF. With hysteresis this happens at the internally
introduced levels A and B, as can be seen in Figure 27. If the levels A and B change, due to a change in the
built-in hysteresis voltage depending of e.g. temperature variations, then the timing of t = 0 and t = 1 will also
vary. The variation of the hysteresis voltage over temperature is very low and ranges from 22 mV to 23 mV at 5V
Supply over a temperature variation of -25 °C to 125 °C (see Figure 28). When designing a circuit be aware of
this effect. Introducing hysteresis will cause some time shift between output and input (e.g. duty cycle variations),
but will eliminate undesired switching of the output.
30
29
28
V
V
= 5V
S
27
26
25
24
23
22
21
20
= 300 mV
CM
-50 -25
0
25
50
75 100 125
TEMPERATURE (°C)
Figure 28. Hysteresis Voltage over Temperature
THE OUTPUT
Output Swing Properties
The LMH7324 has differential outputs, which means that both outputs have the same swing but in opposite
directions. (See Figure 29.) Both outputs swing around the common mode output voltage (VO). This voltage can
be measured at the midpoint between two equal resistors connected to each output. The absolute value of the
difference between both voltages is called VOD. The outputs cannot be held at the VO level because of their
digital nature. They only cross this level during a transition. Due to the symmetrical structure of the circuit, both
output voltages cross at VO regardless of whether the output changes from ‘0’ to ‘1’ or vise versa.
Output Q
V
OH
V
OD
V
O
V
OL
Output Q
Figure 29. Output Swing
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Loading the Output
Both outputs are activated when current is flowing through a resistor that is externally connected to VT. The
termination voltage should be set 2V below the VCCO. This makes it possible to terminate each of the outputs
directly with 50Ω, and if needed to connect through a transmission line with the same impedance. (See
Figure 30.) Due to the low ohmic nature of the output emitter followers and the 50Ω load resistor, a capacitive
load of several pF does not dramatically affect the speed and shape of the signal. When transmitting the signal
from one output to any input the termination resistor should match the transmission line. The capacitive load (CP)
will distort the received signal. When measuring this input with a probe, a certain amount of capacitance from the
probe is parallel to the termination resistor. The total capacitance can be as large as 10 pF. In this case there is
a pole at:
f = 1/(2*π*C*R)
f = 1e9/ π
f = 318 MHz
For this frequency the current IP has the same value as the current through the termination resistor. This means
that the voltage drops at the input and the rise and fall times are dramatically different from the specified
numbers for this part.
Another parasitic capacity that can affect the output signal is the capacity directly between both outputs, called
CPAR. (See Figure 30.) The LMH7324 has two complementary outputs so there is the possibility that the output
signal will be transported by a symmetrical transmission line. In this case both output tracks form a coupled line
with their own parasitics and both receiver inputs are connected to the transmission line. Actually the line
termination looks like 100Ω and the input capacities, which are in series, are parallel to the 100Ω termination.
The best way to measure the input signal is to use a differential probe directly across both inputs. Such a probe
is very suitable for measuring these fast signals because it has good high frequency characteristics and low
parasitic capacitance.
I
P
C
P
V
CCI
V
CCO
R
T
IN+
IN-
+
Q
Q
C
PAR
-
V
EE
R
C
T
P
I
P
V
T
Figure 30. Parasitic Capacities
TRANSMISSION LINES & TERMINATION TECHNOLOGIES
The LMH7324 uses complementary RSPECL outputs and emitter followers, which means high output current
capability and low sensitivity to parasitic capacitance. The use of Reduced Swing Positive Emitter Coupled Logic
gives advantages concerning speed and supply. Data rates are growing, which requires increasing speed. Data
is not only connected to other IC’s on a single PCB board but, in many cases, there are interconnections from
board to board or from equipment to equipment. Distances can be short or long but it is always necessary to
have a reliable connection, which consumes low power and is able to handle high data rates. The
complementary outputs of the LMH7324 make it possible to use symmetrical transmission lines. The advantage
over single ended signal transmission is that the LMH7324 has higher immunity to common mode noise.
Common mode signals are signals that are equally apparent on both lines and because the receiver only looks at
the difference between both lines, this noise is canceled.
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Maximum Bit Rates
The maximum toggle rate is defined at an amplitude of 50% of the nominal output signal. This toggle rate is a
number for the maximum transfer rate of the part and can be given in Hz or in Bps. When transmitting signals in
a NRZ (Non Return to Zero) format the bitrate is double this frequency number, because during one period two
bits can be transmitted. (See Figure 31.) The rise and fall times are very important specifications in high speed
circuits. In fact these times determine the maximum toggle rate of the part. Rise and fall times are normally
specified at 20% and 80% of the signal amplitude (60% difference). Assuming that the edges at 50% amplitude
are coming up and down like a sawtooth it is possible to calculate the maximum toggle rate but this number is
too optimistic. In practice the edges are not linear while the pulse shape is more or less a sinewave.
period period
1
2
80%
20%
V
OUT
Decision Level
Ideal Pulse Out
1
bit
0
1
0
1
0
1
0
0
Figure 31. Bit Rates
Need for Terminated Transmission Lines
During the 1980’s and 90’s, TI fabricated the 100K ECL logic family. The rise and fall time specifications were
0.75 ns, which were considered very fast. If sufficient care has not been given in designing the transmission lines
and choosing the correct terminations, then errors in digital circuits are introduced. To be helpful to designers
that use ECL with “old” PCB-techniques, the 10K ECL family was introduced with rise and fall time specifications
of 2 ns. This is much slower and easier to use. The RSPECL output signals of the LMH7324 have transition
times that extend the fastest ECL family. A careful PCB design is needed using RF techniques for transmission
and termination.
Transmission lines can be formed in several ways. The most commonly used types are the coaxial cable and the
twisted pair telephony cable. (See Figure 32.)
D
2h
d
Parallel Wire
Coax Cable
Figure 32. Cable Types
These cables have a characteristic impedance determined by their geometric parameters. Widely used
impedances for the coaxial cable are 50Ω and 75Ω. Twisted pair cables have impedances of about 120Ω to
150Ω.
Other types of transmission lines are the strip line and the microstrip line. These last types are used on PCB
boards. They have the characteristic impedance dictated by the physical dimensions of a track placed over a
metal ground plane. (See Figure 33.)
22
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SNOSAZ2G –SEPTEMBER 2007–REVISED MARCH 2013
top copper
FR4
signal line
PCB
bottom copper
stripline
signal line
Top Copper
PCB
FR4
bottom copper
Microstrip
signal lines
PCB
Top Copper
FR4
bottom copper
differential microstrip
Figure 33. PCB Lines
Differential Microstrip Line
The transmission line which is ideally suited for complementary signals is the differential microstrip line. This is a
double microstrip line with a narrow space in between. This means both lines have strong coupling and this
determines the characteristic impedance. The fact that they are routed above a copper plane does not affect
differential impedance, only CM-capacitance is added. Each of the structures above has its own geometric
parameters, so for each structure there is a different formula to calculate the right impedance. For calculations on
these transmission lines visit the TI website or order RAPIDESIGNER. At the end of the transmission line there
must be a termination having the same impedance as that of the transmission line itself. It does not matter what
impedance the line has, if the load has the same value no reflections will occur. When designing a PCB board
with transmission lines on it, space becomes an important item especially on high density boards. With a single
microstrip line, line width is fixed for a given impedance and for a specific board material. Other line widths will
result in different impedances.
Advantages of Differential Microstrip Lines
Impedances of transmission lines are always dictated by their geometric parameters. This is also true for
differential microstrip lines. Using this type of transmission line, the distance of the track determines the resulting
impedance. So, if the PCB manufacturer can produce reliable boards with low track spacing the track width for a
given impedance is also small. The wider the spacing, the wider tracks are needed for a specific impedance. For
example two tracks of 0.2 mm width and 0.1 mm spacing have the same impedance as two tracks of 0.8 mm
width and 0.4 mm spacing. With high-end PCB processes, it is possible to design very narrow differential
microstrip transmission lines. It is desirable to use these to create optimal connections to the receiving part or the
terminating resistor, in accordance to their physical dimensions. Seen from the comparator, the termination
resistor must be connected at the far end of the line. Open connections after the termination resistor (e.g. to the
input of a receiver) must be as short as possible. The allowed length of such connections varies with the
received transients. The faster the transients, the shorter the open lines must be to prevent signal degradation.
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PCB LAYOUT CONSIDERATIONS AND COMPONENT VALUE SELECTION
High frequency designs require that both active and passive components be selected from those that are
specially designed for this purpose. The LMH7324 is fabricated in a 32-pin WQFN package intended for surface
mount design. For reliable high speed design it is highly recommended to use small surface mount passive
components because these packages have low parasitic capacitance and low inductance simply because they
have no leads to connect them to the PCB. It is possible to amplify signals at frequencies of several hundreds of
MHz using standard through-hole resistors. Surface mount devices however, are better suited for this purpose.
Another important issue is the PCB itself, which is no longer a simple carrier for all the parts and a medium to
interconnect them. The PCB becomes a real component itself and consequently contributes its own high
frequency properties to the overall performance of the circuit. Good practice dictates that a high frequency design
have at least one ground plane, providing a low impedance path for all decoupling capacitors and other ground
connections. Care should be given especially that on-board transmission lines have the same impedance as the
cables to which they are connected. Most single ended applications have 50Ω impedance (75Ω for video and
cable TV applications). Such low impedance, single ended microstrip transmission lines usually require much
wider traces (2 to 3 mm) on a standard double sided PCB board than needed for a ‘normal’ trace. Another
important issue is that inputs and outputs should not ‘see’ each other. This occurs if input and output tracks are
routed in parallel over the PCB with only a small amount of physical separation, particularly when the difference
in signal level is high. Furthermore components should be placed as flat and low as possible on the surface of
the PCB. For higher frequencies a long lead can act as a coil, a capacitor or an antenna. A pair of leads can
even form a transformer. Careful design of the PCB minimizes oscillations, ringing and other unwanted behavior.
For ultra high frequency designs only surface mount components will give acceptable results. (For more
information see OA-15, literature number SNOA367).
TI suggests the following evaluation board as a guide for high frequency layout and as an aid in device testing:
Device
Package
Evaluation Board
Ordering ID
LMH7324
RTV0032A
LMH7324EVAL
This evaluation board can be shipped when a device sample request is placed with Texas Instruments.
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SNOSAZ2G –SEPTEMBER 2007–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision F (March 2013) to Revision G
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 24
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH7324SQ/NOPB
ACTIVE
WQFN
RTV
32
1000 RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
L7324SQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Nov-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH7324SQ/NOPB
WQFN
RTV
32
1000
178.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Nov-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WQFN RTV 32
SPQ
Length (mm) Width (mm) Height (mm)
208.0 191.0 35.0
LMH7324SQ/NOPB
1000
Pack Materials-Page 2
PACKAGE OUTLINE
RTV0032A
WQFN - 0.8 mm max height
S
C
A
L
E
2
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.15
4.85
A
B
PIN 1 INDEX AREA
5.15
4.85
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
SYMM
EXPOSED
THERMAL PAD
(0.1) TYP
9
16
8
17
SYMM
33
2X 3.5
3.1 0.1
28X 0.5
1
24
0.30
32X
0.18
32
25
PIN 1 ID
0.1
C A B
0.5
0.3
32X
0.05
4224386/B 04/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTV0032A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(3.1)
SYMM
SEE SOLDER MASK
DETAIL
32
25
32X (0.6)
1
24
32X (0.24)
28X (0.5)
(3.1)
33
SYMM
(4.8)
(1.3)
8
17
(R0.05) TYP
(
0.2) TYP
VIA
9
16
(1.3)
(4.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224386/B 04/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RTV0032A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.775) TYP
25
32
32X (0.6)
1
32X (0.24)
28X (0.5)
24
(0.775) TYP
(4.8)
33
SYMM
(R0.05) TYP
4X (1.35)
17
8
9
16
4X (1.35)
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 33
76% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4224386/B 04/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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