LMH5401FFK/EM [TI]
耐辐射加固保障 (RHA) 6.5GHz 超宽带全差分放大器 | FFK | 14 | 25 to 25;
| 型号： | LMH5401FFK/EM |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 耐辐射加固保障 (RHA) 6.5GHz 超宽带全差分放大器 | FFK | 14 | 25 to 25 放大器 |
| 文件： | 总56页 (文件大小：2033K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMH5401-SP
ZHCSH86B –DECEMBER 2017–REVISED FEBRUARY 2019
LMH5401-SP 6.5GHz 耐辐射低噪声低功率增益可配置
全差分放大器
1 特性
2 应用
1
•
QMLV（QML V 类）已通过 MIL-PRF-38535 认
证，SMD 5962R1721401VXC
•
•
•
•
•
•
•
平衡-非平衡变压器替代产品：直流电频率达 2GHz
GSPS ADC 驱动器
DAC 缓冲器
–
–
–
耐辐射加固保障 (RHA) 能力高达 100krad (Si)
总电离剂量 (TID)
中频、射频和基带增益块
SAW 滤波器缓冲器和驱动器
电平转换器
单粒子闩锁 (SEL) 对于
LET 的抗扰度 = 85MeV-cm2/mg
支持军用级温度范围（-55°C 至 125°C）
耐辐射应用
•
•
增益带宽积 (GBP)：6.5GHz
优异的线性性能：
直流电频率达 2GHz
3 说明
LMH5401-SP 是一款针对射频 (RF)、中频 (IF) 或高速
直流耦合时域 应用优化的高性能耐辐射差分放大器。
该器件非常适合于直流耦合或交流耦合 应用 。
LMH5401-SP 在 SE-DE 或差分至差分 (DE-DE) 模式
下运行时会产生非常低的二阶和三阶失真。
•
•
压摆率：17,500V/µs
低 HD2、HD3 失真
（500mVPP，100Ω，SE-DE，Gv = 17dB）(1)：
–
–
–
–
–
100MHz：HD2 为 -91dBc，HD3 为 -95dBc
200MHz：HD2 为 -86dBc，HD3 为 -85dBc
500MHz：HD2 为 -80dBc，HD3 为 -80dBc
1GHz：HD2 为 -53dBc，HD3 为 -70dBc
2GHz：HD2 为 -68dBc，HD3 为 -56dBc
器件信息(1)
器件型号
等级
封装
5962R1721401VXC 耐辐射加固
14 引脚 LCCC [FFK]
5.50mm × 6.00mm
5962-1721401V2C
LMH5401FFK\EM
QMLV
工程样片(2)
•
•
低 IMD2、IMD3 失真
（1VPP，100Ω，SE-DE，Gv = 17dB）(1)：
LMH5401EVMCVAL 陶瓷评估板
—
–
–
–
500MHz：IMD2 为 –90dBc，IMD3 为 –79dBc
1GHz：IMD2 为 –80dBc，IMD3 为 –61dBc
2GHz：IMD2 为 –64dBc，IMD3 为 –42dBc
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
(2) 这些部件仅适用于工程评估。部件按照不合规的流程进行加工
处理。这些部件不适用于质检、生产、辐射测试或飞行。这些
零部件无法在 –55°C 至 125°C 的完整 MIL 额定温度范围内或
运行寿命中保证其性能。
高 OIP2、OIP3。Gp = 8dB(1)
–
–
500MHz：OIP2 为 91dBm，OIP3 为 47.7dBm
1 GHz：OIP2 为 80dBm，OIP3 为 37.5dBm
•
•
•
•
输入电压噪声：1.25nV/√Hz
输入电流噪声：3.5pA/√Hz
支持单电源和双电源运行
电流消耗：60mA
•
关断特性
(1)
功率增益 (Gp) = 8dB；电压增益 (Gv) = 17dB；RL总计
=
200Ω。更多详细信息请参见输出参考节点和增益命名规则部
分。
LMH5401-SP 小信号频率响应
LMH5401-SP 驱动 ADC12D1620QML
10
Gp = 8 dB, Gv = 17 dB
25 ꢀ
RT
5
0
FB+
RF
50-ꢀ,
Single-Ended Input
OUT+ RO
RG
10 ꢀ
INœ
œ
IN+
+
+
œ
OUT_AMP
Filter
LMH5401-SP
+
RO
ADC12D1620
œ
IN+
INœ
-5
10 ꢀ
RG+RM
RF
OUTœ
FBœ
-10
-15
-20
25 ꢀ
CM
Copyright © 2017, Texas Instruments Incorporated
10
100
1k
Frequency (MHz)
10k
SBOS
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS849
LMH5401-SP
ZHCSH86B –DECEMBER 2017–REVISED FEBRUARY 2019
www.ti.com.cn
目录
8.11 Test Schematics.................................................... 23
Detailed Description ............................................ 25
9.1 Overview ................................................................. 25
9.2 Functional Block Diagram ....................................... 25
9.3 Feature Description................................................. 25
9.4 Device Functional Modes........................................ 31
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 （续）.............................................................. 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics: VS = 5 V........................... 5
7.6 Electrical Characteristics: VS = 3.3 V........................ 7
7.7 Typical Characteristics: 5 V .................................... 10
7.8 Typical Characteristics: 3.3 V ................................. 16
Parameter Measurement Information ................ 20
8.1 Output Reference Nodes and Gain Nomenclature. 20
8.2 ATE Testing and DC Measurements ...................... 21
8.3 Frequency Response.............................................. 21
8.4 S-Parameters.......................................................... 22
8.5 Frequency Response with Capacitive Load............ 22
8.6 Distortion................................................................. 22
8.7 Noise Figure............................................................ 22
9
10 Application and Implementation........................ 32
10.1 Application Information.......................................... 32
10.2 Typical Application ................................................ 36
10.3 Do's and Don'ts .................................................... 45
11 Power Supply Recommendations ..................... 46
11.1 Supply Voltage...................................................... 46
11.2 Single Supply ........................................................ 46
11.3 Split Supply ........................................................... 46
11.4 Supply Decoupling ................................................ 46
12 Layout................................................................... 47
12.1 Layout Guidelines ................................................. 47
12.2 Layout Example .................................................... 47
13 器件和文档支持 ..................................................... 48
13.1 器件支持................................................................ 48
13.2 文档支持................................................................ 48
13.3 接收文档更新通知 ................................................. 48
13.4 社区资源................................................................ 48
13.5 商标....................................................................... 49
13.6 静电放电警告......................................................... 49
13.7 术语表 ................................................................... 49
14 机械、封装和可订购信息....................................... 49
8
8.8 Pulse Response, Slew Rate, and Overdrive
Recovery.................................................................. 22
8.9 Power Down............................................................ 23
8.10 VCM Frequency Response .................................... 23
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (July 2018) to Revision B
Page
•
•
•
•
•
已更改 图 1 ........................................................................................................................................................................... 10
已添加 图 7 ........................................................................................................................................................................... 10
已添加 图 8 ........................................................................................................................................................................... 10
已添加 图 14 ......................................................................................................................................................................... 11
已添加 图 15 ......................................................................................................................................................................... 11
Changes from Original (December 2017) to Revision A
Page
•
•
•
已添加 RHA 器件 .................................................................................................................................................................... 1
Changed VS = 5 V PSRR values (–44 dB, –48 dB) from MIN : to MAX ................................................................................ 6
Changed VS = 3.3 V PSRR values (–44 dB, –48 dB) from MIN : to MAX ............................................................................. 8
2
版权 © 2017–2019, Texas Instruments Incorporated
LMH5401-SP
www.ti.com.cn
ZHCSH86B –DECEMBER 2017–REVISED FEBRUARY 2019
5 说明 （续）
此放大器针对 SE-DE 和 DE-DE 系统进行了优化。该器件具有直流到 2GHz 的超高可用带宽。LMH5401-SP 可在
广泛的 应用 （如测试与测量、宽带通信以及高速数据采集）中用于在信号链中进行 SE-DE 转换，而无需外部平衡
-非平衡变压器。
该器件提供了共模参考输入引脚，以便使放大器输出共模符合 ADC 输入要求。可选电源范围介于 3.3V 和 5V 之
间，并且可根据应用要求支持双电源供电。掉电功能还可实现节能。
当器件由 5V 电源供电且达到 300mW 超低功耗时，这一性能等级才能实现。该器件采用德州仪器 (TI) 的先进互补
BiCMOS 工艺制造，可节省空间，同时提供 LCCC-14 封装以实现更高的性能。
6 Pin Configuration and Functions
FFK Package
14-Pin LCCC
Top View
VSœ
CM
VS+
3
2
1
LMH5401-SP
25 ꢀ
FB+
INœ
IN+
FBœ
4
5
6
7
14
13
12
11
GND
10 ꢀ
10 ꢀ
OUT+
OUTœ
GND
œ
+
25 ꢀ
8
9
10
VSœ
PD
VS+
Pin Functions
PIN
I/O/P(1)
DESCRIPTION
NAME
CM
NO.
2
7
I
Input pin to set amplifier output common-mode voltage.
Negative output feedback component connection.
Positive output feedback component connection.
Printed circuit board (PCB) ground.
Negative input pin.
FB–
FB+
GND
IN–
O
O
P
I
4
11, 14
5
IN+
6
I
Positive input pin.
OUT–
OUT+
PD
12
13
9
O
O
I
Negative output pin.
Positive output pin.
Power-down (logic 1 = power down).
Negative supply voltage.
VS–
VS+
3, 8
1, 10
P
P
Positive supply voltage.
(1) I = input, O = output, P = power
Copyright © 2017–2019, Texas Instruments Incorporated
3
LMH5401-SP
ZHCSH86B –DECEMBER 2017–REVISED FEBRUARY 2019
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)(1)
MIN
MAX
5.5
UNIT
Power supply
Voltage
V
Input voltage
(VS–) – 0.7
(VS+) + 0.7
10
Input current
Current
mA
Output current (sourcing or sinking) OUT+, OUT–
100
Continuous power dissipation
See Thermal Information table
Maximum junction temperature, TJ
Temperature Maximum junction temperature, continuous operation, long-term reliability
Storage, Tstg
150
125
150
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±3500
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
3.15
–55
NOM
MAX
5.25
125
UNIT
Supply voltage (VS = VS+ – VS–)
Operating junction temperature, TJ
5
V
°C
7.4 Thermal Information
LMH5401-SP
FFK (LCCC)
14 PINS
92.1
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
106.2
71.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
64.8
ψJB
68.2
RθJC(bot)
63.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2017–2019, Texas Instruments Incorporated
LMH5401-SP
www.ti.com.cn
ZHCSH86B –DECEMBER 2017–REVISED FEBRUARY 2019
7.5 Electrical Characteristics: VS = 5 V
The specifications shown below correspond to the respectively identified subgroup temperature (see 表 1), unless otherwise
noted. VS+ = 5 V; VS– = 0 V; VCM = 2.5 V; RLtotal = 200-Ω differential(1); Gp = 8 dB (Gv = 17 dB); single-ended input,
differential output, and RS = 50 Ω (unless otherwise noted)(2)
.
PARAMETER
TEST CONDITIONS
SUBGROUP(3)
MIN
TYP
MAX
UNIT
AC PERFORMANCE
GBP
Gain bandwidth product
Gp = 8 dB
6.5
4.2
GHz
GHz
Small-signal, –3-dB
bandwidth
SSBW
VL = 100 mVPP
VL = 1.0 VPP
VL = 1.0 VPP
Large-signal, –3-dB
bandwidth
LSBW
SR
4
GHz
GHz
Bandwidth for ±0.5-dB
flatness
2.9
Slew rate
2-V step
17500
80
V/µs
ps
Rise and fall time
Overdrive recovery
Output balance error
Output impedance
0.1% settling time
1-V step, 10% to 90%
Overdrive = ±0.5 V
f = 1 GHz
300
–47
20
ps
dBc
Ω
zo
At dc, differential
[1, 2, 3]
13
25
2 V, RL = 200 Ω
1
ns
f = 100 MHz, VL = 1 VPP
f = 200 MHz, VL = 1 VPP
f = 500 MHz, VL = 1 VPP
f = 1 GHz, VL = 1 VPP
f = 2 GHz, VL = 1 VPP
f = 100 MHz, VL = 1 VPP
f = 200 MHz, VL = 1 VPP
f = 500 MHz, VL = 1 VPP
f = 1 GHz, VL = 1 VPP
f = 2 GHz, VL = 1 VPP
–91
–86
–80
–53
–68
–95
–85
–80
–70
–56
–90
–80
–64
91
Second-order harmonic
distortion
HD2
dBc
dBc
Third-order harmonic
distortion
HD3
f = 500 MHz, VL = 1 VPP per tone
IMD2
OIP2
IMD3
Second-order intermodulation f = 1 GHz, VL = 1 VPP per tone
f = 2 GHz, VL = 1 VPP per tone
dBc
dBm
dBc
f = 500 MHz, VL = 1 VPP, matched load
Second-order output intercept
f = 1000 MHz, VL = 1 VPP, matched
load
point
80
f = 500 MHz, VL = 0.25 VPP per tone
f = 1 GHz, VL = 0.25 VPP per tone
f = 2 GHz, VL = 0.25 VPP per tone
–79
–61
–42
Third-order intermodulation
f = 500 MHz, VL = 1 VPP, unmatched
load
47.7
37.5
Third-order output intercept
point
OIP3
dBm
f = 1000 MHz, VL = 1 VPP, unmatched
load
NOISE PERFORMANCE
en
in
Input voltage noise density
1.25
3.5
nV/√Hz
pA/√Hz
Input noise current
Noise figure
RS = 50 Ω, SE-DE, 200 MHz
See 图 57
NF
9.6
dB
INPUT
VIO
Input offset voltage
Input bias current
[1, 2, 3]
[1, 2, 3]
[1, 2, 3]
±0.5
70
±5
150
±20
mV
µA
µA
Ω
IIB
IIO
Input offset current
Differential resistance
±1
Open-loop
4600
Input common-mode
low voltage
(VS–) +
0.41
VICL
[1, 2, 3]
VS–
V
(1) Please see the Output Reference Nodes and Gain Nomenclature section.
(2) The input resistance and corresponding gain are obtained with the external resistance added.
(3) For subgroup definitions, please see 表 1.
Copyright © 2017–2019, Texas Instruments Incorporated
5
LMH5401-SP
ZHCSH86B –DECEMBER 2017–REVISED FEBRUARY 2019
www.ti.com.cn
Electrical Characteristics: VS = 5 V (continued)
The specifications shown below correspond to the respectively identified subgroup temperature (see 表 1), unless otherwise
noted. VS+ = 5 V; VS– = 0 V; VCM = 2.5 V; RLtotal = 200-Ω differential(1); Gp = 8 dB (Gv = 17 dB); single-ended input,
differential output, and RS = 50 Ω (unless otherwise noted)(2)
.
PARAMETER
TEST CONDITIONS
SUBGROUP(3)
MIN
TYP
MAX
UNIT
V
Input common-mode
high voltage
VICH
[1, 2, 3]
(VS+) – 1.41 (VS+) – 1.2
72
CMRR
OUTPUT
VOCRH
Common-mode rejection ratio Differential, 1-VPP input shift, dc
dBc
Output voltage range, high
Output voltage range, low
Measured single-ended
Measured single-ended
[1, 2, 3]
[1, 2, 3]
(VS+) – 1.3 (VS+) – 1.1
(VS–) + 1.3 (VS–) + 1.1
V
V
VOCRL
Differential output voltage
swing
VOD
IOD
Differential
VO = 0 V(4)
5.8
VPP
mA
Differential output current
[1, 2, 3]
40
50
POWER SUPPLY
VS
Supply voltage
[1, 2, 3]
[1, 2, 3]
[1, 2, 3]
[1, 2, 3]
[1, 2, 3]
3.15
5.25
–44
–48
78
V
VS–
–80
–82
60
PSRR
Power-supply rejection ratio
Quiescent current
dB
VS+
PD = 0
PD = 1
46
1
IQ
mA
3
6
OUTPUT COMMON-MODE CONTROL PIN (VCM
)
SSBW
Small-signal bandwidth
VCM slew rate
VOCM = 100 mVPP
1.2
2900
GHz
V/µs
V
VOCM = 500 mVPP
VCM voltage range low
VCM voltage range high
VCM gain
Differential gain shift < 1 dB
Differential gain shift < 1 dB
VCM = 0 V
[1, 2, 3]
[1, 2, 3]
[1, 2, 3]
(VS–) + 1.4
(VS–) + 2
1.01
(VS+) – 2 (VS+) – 1.4
V
0.98
1.0
–27
0.4
V/V
VOCM output common-mode
offset from VCM input voltage
VCM = 0 V
mV
mV
VOCM
POWER DOWN (PD PIN)
Enable or disable voltage
Common-mode offset voltage Output-referred
Device powers on below 0.8 V,
device powers down above 1.2 V
VT
[1, 2, 3]
0.9
1
1.1
3
1.2
V
threshold
Power-down quiescent
current
[1, 2, 3]
[1, 2, 3]
6
mA
PD bias current
PD = 2.5 V
10
10
10
±100
µA
ns
ns
Turn-on time delay
Turn-off time delay
Time to VO = 90% of final value
Time to VO = 10% of original value
(4) This test shorts the outputs to ground (mid supply) then sources or sinks 60 mA and measures the deviation from the initial condition.
6
Copyright © 2017–2019, Texas Instruments Incorporated
LMH5401-SP
www.ti.com.cn
ZHCSH86B –DECEMBER 2017–REVISED FEBRUARY 2019
7.6 Electrical Characteristics: VS = 3.3 V
The specifications shown below correspond to the respectively identified subgroup temperature (see 表 1), unless otherwise
noted. VS+ = 3.3 V; VS– = 0 V; VCM = 1.65 V; RLtotal = 200-Ω differential(1); Gp = 8 dB (Gv = 17 dB); single-ended input,
differential output, and input and output referenced to midsupply (unless otherwise noted); measured using an EVM as
discussed in the Parameter Measurement Information section.
PARAMETER
TEST CONDITIONS
SUBGROUP(2)
MIN
TYP
MAX
UNIT
AC PERFORMANCE
GBP
Gain bandwidth product
Gp = 8 dB
6.5
4
GHz
GHz
Small-signal, –3-dB
bandwidth
SSBW
VL = 100 mVPP
VL = 1 VPP
Large-signal, –3-dB
bandwidth
LSBW
SR
3.8
2.6
GHz
GHz
Bandwidth for ±0.5-dB
flatness
VL = 1 VPP
Slew rate
2-V step
17500
90
V/µs
ps
Rise and fall time
Overdrive recovery
Output balance error
Output impedance
0.1% settling time
1-V step, 10% to 90%
Overdrive = ±0.5 V
400
–47
20
ps
f = 1 GHz
dBc
Ω
zo
At dc
[1, 2, 3]
13
25
2 V, RL = 200 Ω
1
ns
f = 100 MHz, VL = 500 mVPP
f = 200 MHz, VL = 500 mVPP
f = 500 MHz, VL = 500 mVPP
f = 1 GHz, VL = 500 mVPP
f = 100 MHz, VL = 500 m VPP
f = 200 MHz, VL = 500 mVPP
f = 500 MHz, VL = 500 mVPP
f = 1 GHz, VL = 500 mVPP
f = 500 MHz, VL = 0.25 VPP per tone
f = 1 GHz, VL = 0.25 VPP per tone
f = 2 GHz, VL = 0.25 VPP per tone
–93
–87
–75.2
–58
–83
–76
–59
–53
–94
–83
–68
Second-order harmonic
distortion
HD2
dBc
dBc
Third-order harmonic
distortion
HD3
Second-order intermodulation
distortion
IMD2
OIP2
IMD3
OIP3
dBc
dBm
dBc
f = 500 MHz, VL = 1 VPP, matched
load
70
54
Second-order output intercept
point
f = 1000 MHz, VL = 1 VPP, matched
load
f = 500 MHz, VL = 0.25 VPP per tone
f = 1 GHz, VL = 0.25 VPP per tone
f = 2 GHz, VL = 0.25 VPP per tone
–74
–63
–49
Third-order intermodulation
distortion
f = 500 MHz, VL = 1 VPP, unmatched
load
33
Third-order output intercept
point
dBm
f = 1000 MHz, VL = 1 VPP, unmatched
load
26.5
NOISE PERFORMANCE
en
in
Input voltage noise density
1.25
3.5
nV/√Hz
pA/√Hz
Input noise current
Noise figure
RS = 50 Ω, SE-DE, G = 12 dB,
200 MHz
NF
11.9
dB
INPUT
VIO
IIB
Input offset voltage
Input bias current
±0.5
70
±5
150
±20
mV
µA
µA
Ω
IIO
Input offset current
Differential impedance
±1
Zid
4600
Input common-mode
low voltage
(VS–) +
0.41
VICL
[1, 2, 3]
(VS–)
V
(1) Please see the Output Reference Nodes and Gain Nomenclature section.
(2) For subgroup definitions, please see 表 1.
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Electrical Characteristics: VS = 3.3 V (continued)
The specifications shown below correspond to the respectively identified subgroup temperature (see 表 1), unless otherwise
noted. VS+ = 3.3 V; VS– = 0 V; VCM = 1.65 V; RLtotal = 200-Ω differential(1); Gp = 8 dB (Gv = 17 dB); single-ended input,
differential output, and input and output referenced to midsupply (unless otherwise noted); measured using an EVM as
discussed in the Parameter Measurement Information section.
PARAMETER
TEST CONDITIONS
SUBGROUP(2)
MIN
TYP
MAX
UNIT
Input common-mode
high voltage
VICH
[1, 2, 3]
(VS+) – 1.41 (VS+) – 1.2
–72
V
CMRR
OUTPUT
VOCRH
Common-mode rejection ratio Differential, 1-VPP input shift, dc
dBc
Output voltage range, high
Output voltage range, low
Measured single-ended
Measured single-ended
[1, 2, 3]
[1, 2, 3]
(VS+) – 1.3 (VS+) – 1.1
(VS–) + 1.3 (VS–) + 1.1
V
V
VOCRL
Differential output voltage
swing
VOD
IOD
Differential
VO = 0 V(3)
2.8
VPP
mA
Differential output current
[1, 2, 3]
30
40
POWER SUPPLY
VS
Supply voltage
[1, 2, 3]
[1, 2, 3]
[1, 2, 3]
[1, 2, 3]
[1, 2, 3]
3.15
5.25
–44
–48
63
V
VS–
–80
–84
54
PSRR
Power-supply rejection ratio
Quiescent current
dB
VS+
PD = 0
PD = 1
44
1
IQ
mA
1.6
5
OUTPUT COMMON-MODE CONTROL PIN (VCM
)
SSBW
Small-signal bandwidth
VCM voltage range low
VOCM = 200 mVPP
3
GHz
V
(VS–) +
1.35
(VS–) +
1.55
Differential gain shift < 1 dB
[1, 2, 3]
(VS+) –
1.35
VCM voltage range high
VCM gain
Differential gain shift < 1 dB
VCM = 0 V
[1, 2, 3]
[1, 2, 3]
(VS+) – 1.55
0.98
V
1
–27
0.4
1.01
V/V
mV
mV
VOCM output common-mode
offset from VCM input voltage
VCM = 0 V
VOCM
POWER DOWN (PD PIN)
Enable or disable voltage
Common-mode offset voltage Output-referred
Device powers on below 0.8 V,
device powers down above 1.2 V
VT
[1, 2, 3]
0.9
1
1.1
1.6
1.2
V
threshold
Power-down quiescent
current
[1, 2, 3]
[1, 2, 3]
6
mA
PD bias current
PD = 2.5 V
10
10
10
±100
µA
ns
ns
Turn-on time delay
Turn-off time delay
Time to VO = 90% of final value
Time to VO = 10% of original value
(3) This test shorts the outputs to ground (mid supply) then sources or sinks 60 mA and measures the deviation from the initial condition.
8
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ZHCSH86B –DECEMBER 2017–REVISED FEBRUARY 2019
表 1. Quality Conformance Inspection(1)
SUBGROUP
DESCRIPTION
Static tests at
TEMPERATURE (°C)
1
2
25
125
–55
25
Static tests at
3
Static tests at
4
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
5
125
–55
25
6
7
8A
8B
9
125
–55
25
10
11
125
–55
(1) MIL-STD-883, Method 5005 - Group A
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7.7 Typical Characteristics: 5 V
at TA = 25°C, VS+ = 5 V; VS– = 0 V; VCM = 2.5 V, RLtotal = 200-Ω differential(1) (RO = 40 Ω each), Gp = 8 dB (Gv = 17 dB),
single-ended input and differential output, and input and output pins referenced to mid supply (unless otherwise noted);
measured using an EVM as discussed in the Parameter Measurement Information section (see 图 54 to 图 57)
10
5
10
5
0
0
-5
-5
-10
-15
-20
-10
-15
-20
Gp = -6 dB, Gv = 3 dB
Gp = -3 dB, Gv = 6 dB
Gp = 0 dB, Gv = 9 dB
Gp = 3 dB, Gv = 12 dB
Gp = 3 dB, Gv = 12 dB
Gp = 5.6 dB, Gv = 14.6 dB
Gp = 8 dB, Gv = 17 dB
10
100
1k
Frequency (MHz)
10k
10
100
1k
Frequency (MHz)
10k
D051
SBOS
See Stability, Noise Gain, and Signal Gain for more details
图 1. SE-DE Small Signal Frequency Response for Low Gain
图 2. SE-DE Small Signal Frequency Response vs Gain
10
10
5
0
5
0
-5
-5
-10
-10
Rload = 70 W
Cload = No Cap
Cload = 1 pF
Rload = 100 W
Rload = 120 W
-15
-15
Cload = 2.4 pF
Cload = 4.7 pF
-20
Rload = 200 W
Rload = 400 W
-20
10
100
1k
Frequency (MHz)
10k
10
100
1k
Frequency (MHz)
10k
SBOS
SBOS
图 4. SE-DE Small Signal Frequency Response vs Cload
图 3. SE-DE Small Signal Frequency Response vs Rload
10
20
10
5
0
0
-10
-20
-30
-40
-50
-5
-10
-55èC
-40èC
-60
Sds21
-70
-80
-90
25èC
85èC
125èC
Sss11
Sdd22
Ssd12
-15
-20
10
100
1k
Frequency (MHz)
10k
10
100
1k
Frequency (MHz)
10k
SBOS
SBOS
图 5. SE-DE Small Signal Frequency Response vs
图 6. SE-DE Small Signal S-Parameters
Temperature
(1) Please see the Output Reference Nodes and Gain Nomenclature section.
10
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ZHCSH86B –DECEMBER 2017–REVISED FEBRUARY 2019
Typical Characteristics: 5 V (接下页)
at TA = 25°C, VS+ = 5 V; VS– = 0 V; VCM = 2.5 V, RLtotal = 200-Ω differential() (RO = 40 Ω each), Gp = 8 dB (Gv = 17 dB),
single-ended input and differential output, and input and output pins referenced to mid supply (unless otherwise noted);
measured using an EVM as discussed in the Parameter Measurement Information section (see 图 54 to 图 57)
20
10
10
0
5
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-5
-10
-15
-20
Sdd11
Sdd12
Sdd21
Sdd22
Gp = 6 dB, Gv = 12 dB
Gp = 10.9 dB, Gv = 16.9 dB
Gp = 12 dB, Gv = 18 dB
10
100
1k
Frequency (MHz)
10k
10
100
1k
Frequency (MHz)
10k
D052
D053
图 7. DIFF-DIFF Small Signal Frequency Response vs Gain
图 8. DIFF-DIFF Small Signal S-Parameters
15
210
200
190
180
170
160
150
10
5
0
-5
-10
-15
10
100
1k
Frequency (MHz)
10k
10
100
1k
Frequency (MHz)
10k
SBOS
SBOS
图 9. SE-DE Amplitude Imbalance
图 10. SE-DE Phase Imbalance
0
-10
-20
VOUT_AMP = 2 Vpp-diff
VOUT_AMP = 1 Vpp-diff
-10
-20
-30
-40
-50
-30
-40
-50
-60
-70
-80
-90
-100
-110
10
100
1k
10k
10
100
1k
Frequency (MHz)
Frequency (MHz)
SBOS
SBOS
图 11. SE-DE Total Imbalance
图 12. SE-DE 2nd Order Harmonic Distortion vs Frequency
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Typical Characteristics: 5 V (接下页)
at TA = 25°C, VS+ = 5 V; VS– = 0 V; VCM = 2.5 V, RLtotal = 200-Ω differential() (RO = 40 Ω each), Gp = 8 dB (Gv = 17 dB),
single-ended input and differential output, and input and output pins referenced to mid supply (unless otherwise noted);
measured using an EVM as discussed in the Parameter Measurement Information section (see 图 54 to 图 57)
-10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
VOUT_AMP = 2 Vpp-diff
VOUT_AMP = 1 Vpp-diff
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
HD2 DIFF-SE (dBc)
HD2 SE-DIFF (dBc)
10
100
1k
250
750
1250
1750
2250
2750
Frequency (MHz)
SBOS
Frequency (MHz)
D054
图 13. SE-DE 3rd Order Harmonic Distortion vs Frequency
图 14. DE-SE 2nd Order Harmonic Distortion vs Frequency
-30
0
-10
-20
-30
-40
-50
-60
-70
-80
Frequency = 500 MHz
-40
-50
-60
-70
-80
-90
-100
-110
HD3 DIFF-SE (dBc)
-90
HD3 SE-DIFF (dBc)
-100
250
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
500
750 1000 1250 1500 1750 2000 2250
VOUT_AMP (Vpp-diff)
SBOS
Frequency (MHz)
D055
图 16. SE-DE 2nd Order Harmonic Distortion vs Vout
图 15. DE-SE 3rd Order Harmonic Distortion vs Frequency
-30
-15
Frequency = 500 MHz
VOUT_AMP = 2 Vpp-diff, 500 MHz
VOUT_AMP = 1 Vpp-diff, 500 MHz
-20
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-40
-50
-60
-70
-80
-90
-100
-110
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
VOUT_AMP (Vpp-diff)
VCMOUT (V)
SBOS
SBOS
图 17. SE-DE 3rd Order Harmonic Distortion vs Vout
图 18. SE-DE 2nd Order Harmonic Distortion vs Output
Common Mode Voltage
12
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ZHCSH86B –DECEMBER 2017–REVISED FEBRUARY 2019
Typical Characteristics: 5 V (接下页)
at TA = 25°C, VS+ = 5 V; VS– = 0 V; VCM = 2.5 V, RLtotal = 200-Ω differential() (RO = 40 Ω each), Gp = 8 dB (Gv = 17 dB),
single-ended input and differential output, and input and output pins referenced to mid supply (unless otherwise noted);
measured using an EVM as discussed in the Parameter Measurement Information section (see 图 54 to 图 57)
10
-60
-65
-70
-75
-80
-85
-90
-95
-100
VOUT_AMP = 2 Vpp-diff, 500 MHz
VOUT_AMP = 1 Vpp-diff, 500 MHz
VOUT_AMP = 2 Vpp-diff, 500 MHz
VOUT_AMP = 1 Vpp-diff, 500 MHz
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
-55
-25
5
35
65
95
125
VCMOUT (V)
Temperature (èC)
SBOS
SBOS
图 19. SE-DE 3rd Order Harmonic Distortion vs Output
图 20. SE-DE 2nd Order Harmonic Distortion vs Temperature
Common Mode Voltage
-50
-10
VOUT_AMP = 2 Vpp-diff, 500 MHz
VOUT_AMP = 1 Vpp-diff, 500 MHz
VOUT_AMP = 2 Vpp-diff
VOUT_AMP = 1 Vpp-diff
-20
-55
-60
-65
-70
-75
-80
-85
-90
-30
-40
-50
-60
-70
-80
-90
-100
-110
-55
-25
5
35
65
95
125
10
100
1k
Temperature (èC)
Frequency (MHz)
SBOS
SBOS
图 21. SE-DE 3rd Order Harmonic Distortion vs Temperature
图 22. SE-DE 2nd Order Intermodulation Distortion vs
Frequency
-10
120
VOUT_AMP = 2 Vpp-diff
100 W matched to 100-W load
-20
-30
-40
-50
-60
-70
-80
-90
-100
VOUT_AMP = 1 Vpp-diff
110
100
90
80
70
60
50
40
10
100
Frequency (MHz)
1k
0
500
1000
1500
2000
2500
3000
SBOS
Frequency (MHz)
SBOS
图 23. SE-DE 3rd Order Intermodulation Distortion vs
图 24. SE-DE Output 2nd Order Intercept Point
Frequency
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Typical Characteristics: 5 V (接下页)
at TA = 25°C, VS+ = 5 V; VS– = 0 V; VCM = 2.5 V, RLtotal = 200-Ω differential() (RO = 40 Ω each), Gp = 8 dB (Gv = 17 dB),
single-ended input and differential output, and input and output pins referenced to mid supply (unless otherwise noted);
measured using an EVM as discussed in the Parameter Measurement Information section (see 图 54 to 图 57)
10
50
45
40
35
30
25
20
15
100 W matched to 100-W load
20 W unmatched to 100-W load
0
2500 MHz
2000 MHz
1750 MHz
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
1500 MHz
1000 MHz
750 MHz
500 MHz
100 MHz
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
1.1 1.2 1.3
0
250 500 750 1000 1250 1500 1750 2000 2250 2500
Vout/tone (Vpp-diff) on 100 W (Matched)*
Frequency (MHz)
SBOS
SBOS
*See Output Reference Nodes and Gain Nomenclature for more
details
图 25. SE-DE 3rd Order Intermodulation Distortion vs Vout
图 26. SE-DE Output 3rd Order Intercept Point
(Matched Load)
0
100
-10
2000 MHz
2250 MHz
-20
-30
2500 MHz
1750 MHz
1500 MHz
1000 MHz
-40
10
1
-50
750 MHz
-60
500 MHz
100 MHz
-70
-80
-90
-100
-110
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
0.1
Vout/tone (Vpp-diff) on 100 W (Unmatched)*
SBOS
100
1k
10k
100k
1M
10M
*See Output Reference Nodes and Gain Nomenclature for more
Frequency (Hz)
C023
details
图 27. SE-DE 3rd Order Intermodulation Distortion vs Vout
图 28. Input-Referred Voltage Noise
(Unmatched Load)
±1.
20
All external components included
±1ꢀ
ꢀ1.
18
16
14
12
10
8
ꢀ1ꢀ
±ꢀ1.
±±1ꢀ
±±1.
±-Vpp Pulse
2-Vpp Pulse
ꢀ
.
±ꢀ
±.
2ꢀ
10
100
1k
Frequency (MHz)
Time (ns)
SBOS
Cꢀ2.
图 29. SE-DE Noise Figure vs Frequency
图 30. SE-DE Output Signal Pulse Response
14
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ZHCSH86B –DECEMBER 2017–REVISED FEBRUARY 2019
Typical Characteristics: 5 V (接下页)
at TA = 25°C, VS+ = 5 V; VS– = 0 V; VCM = 2.5 V, RLtotal = 200-Ω differential() (RO = 40 Ω each), Gp = 8 dB (Gv = 17 dB),
single-ended input and differential output, and input and output pins referenced to mid supply (unless otherwise noted);
measured using an EVM as discussed in the Parameter Measurement Information section (see 图 54 to 图 57)
±0±4
±2ꢁ
±2.
±0±2
ꢀ2ꢁ
±0±±
ꢀ2.
.2ꢁ
±±0±2
±±0±4
±±0±6
±±0±8
.2.
±.2ꢁ
±ꢀ2.
±ꢀ2ꢁ
±±2.
1-Vpp Pulse
2-Vpp Pulse
VO
PD
±
5
1±
15
2±
.
ꢀ.
±.
3.
4.
ꢁ.
6.
7.
8.
9. ꢀ..
Time (ns)
Time (ns)
C±26
C.±7
VCM @ AMPOUT Node; VCM = (Vo+ + Vo–) / 2
图 31. SE-DE Output Common Mode Pulse Response
图 32. Power Down Timing
±
VO Ideal
ꢀ
VO Measured
ꢁ
0
±ꢁ
±ꢀ
±±
0.0
0.5
1.0
1.5
ꢁ.0
ꢁ.5
Time (ns)
C0ꢁ8
图 33. Overdrive Recovery
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7.8 Typical Characteristics: 3.3 V
at TA = 25°C, VS+ = 3.3 V; VS– = 0 V; VCM = 1.65 V, RLtotal = 200-Ω differential(1) (RO = 40 Ω each), Gp = 8 dB (Gv = 17 dB),
single-ended input and differential output, and input and output pins referenced to midsupply (unless otherwise noted);
measured using an EVM as discussed in the Parameter Measurement Information section (see 图 54 to 图 57)
10
5
10
5
0
0
-5
-5
-10
-15
-20
-10
-15
-20
Rload = 70 W
Rload = 100 W
Rload = 120 W
Rload = 200 W
Rload = 400 W
Gp = 3 dB, Gv = 12 dB
Gp = 5.6 dB, Gv = 14.6 dB
Gp = 8 dB, Gv = 17 dB
10
100
1k
Frequency (MHz)
10k
10
100
1k
Frequency (MHz)
10k
SBOS
SBOS
图 34. SE-DE Small Signal Frequency Response vs Gain
图 35. SE-DE Small Signal Frequency Response vs Rload
10
10
5
0
5
0
-5
-5
-10
-10
-55èC
-40èC
Cload = No Cap
Cload = 1 pF
Cload = 2.2 pF
Cload = 4.7 pF
25èC
85èC
125èC
-15
-20
-15
-20
10
100
1k
Frequency (MHz)
10k
10
100
1k
Frequency (MHz)
10k
SBOS
SBOS
图 36. SE-DE Small Signal Frequency Response vs Cload
图 37. SE-DE Small Signal Frequency Response vs
Temperature
20
10
-10
VOUT_AMP = 2 Vpp-diff
VOUT_AMP = 1 Vpp-diff
-20
-30
0
-10
-20
-30
-40
-50
-40
-50
-60
-70
-80
-60
Sds21
-90
-70
-80
-90
Sss11
Sdd22
Ssd12
-100
-110
10
100
1k
Frequency (MHz)
10k
10
100
1k
Frequency (MHz)
SBOS
SBOS
图 38. SE-DE Small Signal S-Parameters
图 39. SE-DE 2nd Order Harmonic Distortion vs Frequency
(1) Please see the Output Reference Nodes and Gain Nomenclature section.
16
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ZHCSH86B –DECEMBER 2017–REVISED FEBRUARY 2019
Typical Characteristics: 3.3 V (接下页)
at TA = 25°C, VS+ = 3.3 V; VS– = 0 V; VCM = 1.65 V, RLtotal = 200-Ω differential() (RO = 40 Ω each), Gp = 8 dB (Gv = 17 dB),
single-ended input and differential output, and input and output pins referenced to midsupply (unless otherwise noted);
measured using an EVM as discussed in the Parameter Measurement Information section (see 图 54 to 图 57)
-10
-30
-40
-50
-60
-70
-80
-90
VOUT_AMP = 2 Vpp-diff
VOUT_AMP = 1 Vpp-diff
Frequency = 500 MHz
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
10
100
1k
0
0.5
1
1.5
2
2.5
3
3.5
4
Frequency (MHz)
VOUT_AMP (Vpp-diff)
SBOS
SBOS
Vout = pk-pk voltage swing per tone on 100-Ω effective load
图 40. SE-DE 3rd Order Harmonic Distortion vs Frequency
图 41. SE-DE 2nd Order Harmonic Distortion vs Vout
-10
-10
Frequency = 500 MHz
VOUT_AMP = 2 Vpp-diff, 500 MHz
VOUT_AMP = 1 Vpp-diff, 500 MHz
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-20
-30
-40
-50
-60
-70
-80
-90
0
0.5
1
1.5
2
2.5
3
3.5
-1 -0.8 -0.6 -0.4 -0.2
0
0.2 0.4 0.6 0.8
1
VOUT_AMP (Vpp-diff)
VCMOUT (V)
SBOS
SBOS
Vout = pk-pk voltage swing per tone on 100-Ω effective load
图 42. SE-DE 3rd Order Harmonic Distortion vs Vout
图 43. SE-DE 2nd Order Harmonic Distortion vs Output
Common Mode Voltage
-5
-50
VOUT_AMP = 2 Vpp-diff, 500 MHz
VOUT_AMP = 1 Vpp-diff, 500 MHz
VOUT_AMP = 2 Vpp-diff, 500 MHz
VOUT_AMP = 1 Vpp-diff, 500 MHz
-10
-55
-60
-65
-70
-75
-80
-85
-90
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
-1
-0.8 -0.6 -0.4 -0.2
0
0.2
0.4
0.6
0.8
-55
-25
5
35
65
95
125
VCMOUT (V)
Temperature (èC)
SBOS
SBOS
图 44. SE-DE 3rd Order Harmonic Distortion vs Output
图 45. SE-DE 2nd Order Harmonic Distortion vs Temperature
Common Mode Voltage
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Typical Characteristics: 3.3 V (接下页)
at TA = 25°C, VS+ = 3.3 V; VS– = 0 V; VCM = 1.65 V, RLtotal = 200-Ω differential() (RO = 40 Ω each), Gp = 8 dB (Gv = 17 dB),
single-ended input and differential output, and input and output pins referenced to midsupply (unless otherwise noted);
measured using an EVM as discussed in the Parameter Measurement Information section (see 图 54 to 图 57)
-30
-35
-40
-45
-50
-55
-60
-65
-70
-32
VOUT_AMP = 2 Vpp-diff, 500 MHz
VOUT_AMP = 1 Vpp-diff, 500 MHz
VOUT_AMP = 2 Vpp-diff
VOUT_AMP = 1 Vpp-diff
-42
-52
-62
-72
-82
-92
-102
-112
-55
-25
5
35
65
95
125
10
100
Frequency (MHz)
1k
Temperature (èC)
SBOS
SBOS
图 46. SE-DE 3rd Order Harmonic Distortion vs Temperature
图 47. SE-DE 2nd Order Intermodulation Distortion vs
Frequency
-10
100
VOUT_AMP = 2 Vpp-diff
VOUT_AMP = 1 Vpp-diff
VOUT_AMP = 2 Vpp-diff
VOUT_AMP = 1 Vpp-diff
-20
90
80
70
60
50
40
30
-30
-40
-50
-60
-70
-80
-90
-100
-110
10
100
1k
0
500
1000
1500
2000
2500
3000
Frequency (MHz)
Frequency (MHz)
SBOS
SBOS
图 48. SE-DE 3rd Order Intermodulation Distortion vs
图 49. SE-DE Output 2nd Order Intercept Point
Frequency
±1.
±1ꢀ
50
VOUT_AMP = 2 Vpp-diff
VOUT_AMP = 1 Vpp-diff
40
30
20
10
0
ꢀ1.
ꢀ1ꢀ
±ꢀ1.
±±1ꢀ
±±1.
±-Vpp Pulse
2-Vpp Pulse
ꢀ
.
±ꢀ
±.
2ꢀ
0
500
1000
1500
2000
2500
3000
Frequency (MHz)
Time (ns)
Cꢀ46
SBOS
图 51. SE-DE Output Signal Pulse Response
图 50. SE-DE Output 3rd Order Intercept Point
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Typical Characteristics: 3.3 V (接下页)
at TA = 25°C, VS+ = 3.3 V; VS– = 0 V; VCM = 1.65 V, RLtotal = 200-Ω differential() (RO = 40 Ω each), Gp = 8 dB (Gv = 17 dB),
single-ended input and differential output, and input and output pins referenced to midsupply (unless otherwise noted);
measured using an EVM as discussed in the Parameter Measurement Information section (see 图 54 to 图 57)
±0±6
±0±4
±0±2
±0±±
±±0±2
±±0±4
±±0±6
±±0±8
.-Vpp Pulse
2-Vpp Pulse
±±0.±
±
5
.±
.5
2±
Time (ns)
C±47
VCM @ AMPOUT Node; VCM = (Vo+ + Vo–) / 2
图 52. SE-DE Output Common Mode Pulse Response
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8 Parameter Measurement Information
8.1 Output Reference Nodes and Gain Nomenclature
The LMH5401-SP is a decompensated, fully-differential amplifier (FDA) configurable with external resistors for
noise gain greater than 4 V/V or 12 dB (GBP = 6.5 GHz). For most of this document, data are collected for Gv =
17 dB for both single-ended-to-differential (SE-DE) and differential-to-differential (DE-DE) conversions in the
diagrams illustrated in the Test Schematics section. When matching the output to a 100-Ω load, the evaluation
module (EVM) uses external 40-Ω resistors to complete the output matching, as the device has an internal series
10 Ω on each output. Having on-chip output resistors creates two potential reference points for measuring the
output voltage. The amplifier output pins create one output reference point (OUT_AMP). The other output
reference point is OUT_LOAD at the 100-Ω load impedance, RL. These points are illustrated in 图 53; see also
the Test Schematics section.
RL
RLtotal
LMH5401
RT
FB+
IN-
25 W
RF
Single-Ended
Input
10 W
10 W
RO
RO
RG
RG
-
Test Equipment
With 50-W
Load Impedances
Test Equipment
With 50-W
Source Impedance
+
-
+
-
+
-
CO
IN+
FB-
RM
RF
25 W
OUT_AMP
OUT_LOAD
Copyright © 2017, Texas Instruments Incorporated
CM
图 53. Output Reference Nodes
Most measurements in the Electrical Characteristics tables and in the Typical Characteristics sections are
measured with reference to the OUT_AMP reference point. 公式 1 shows that the conversion between reference
points is a straightforward reduction of 3 dB for power and 6 dB for voltage in a matched condition when Ro is
set such that 20 Ω + 2 × Ro = RL. With Ro set to 40 Ω and RL set to 100 Ω-differential, the total load impedance
seen by the amplifier, RLtotal, is 200 Ω. This is considered a matched load condition as 100-Ω is driving RL of 100
Ω. The device is also capable of driving lower impedances. By setting Ro to 0 Ω, RLtotal becomes 120 Ω. This is
considered an unmatched condition since 20 Ω is driving RL of 100 Ω. As explained in the Application Curves
section, efficiency is improved (losses reduced) in a mismatched condition which is acceptable if transmission
line reflections are avoided and proper termination practices are employed. As stated previously, most
measurements in this document are referenced to OUT_AMP node. However, there are some typical
characteristic plots that are measured with a fixed signal swing with respect to the OUT_LOAD reference point;
specifically, IMD3 图 25 and 图 27 are referenced to the voltage swing at node OUT_LOAD.
VOUT_LOAD = (VOUT_AMP – 6 dB) and POUT_LOAD = (POUT_AMP – 6 dB)
(1)
This document makes references to both voltage gain, Gv, and power gain, Gp. Voltage gain is defined as the
ratio of the differential output voltage at node OUT_AMP to the differential, or single-ended, input voltage at the
node before Rg. Power gain, for the purposes of this document, is defined as the ratio of the power dissipated on
RL (100 Ω-differential) to the power transferred from a source to the input impedance of the amplifier. Whereas
voltage gain contains no input and load impedances in its calculation, power gain does depend on termination
impedances.
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8.2 ATE Testing and DC Measurements
All production testing and ensured dc parameters are measured on automated test equipment capable of dc
measurements only. Measurements such as output current sourcing and sinking are made in reference to the
device output pins. Some measurements (such as voltage gain) are referenced to the output of the internal
amplifier and do not include losses attributed to the on-chip output resistors. The Electrical Characteristics table
conditions specify these conditions. When the measurement is referred to the amplifier output, then the output
resistors are not included in the measurement. If the measurement is referred to the device pins, then the output
resistor loss is included in the measurement.
8.3 Frequency Response
This test is run with both single-ended inputs and differential inputs.
For tests with single-ended inputs, the standard EVM is used with no changes; see 图 54. In order to provide a
matched input, the unused input requires a broadband 50-Ω termination to be connected. When using a four-port
network analyzer, the unused input can either be terminated with a broadband load, or can be connected to the
unused input on the four-port analyzer. The network analyzer provides proper termination. A network analyzer is
connected to the input and output of the EVM with 50-Ω coaxial cables and is set to measure the forward transfer
function (s21). The input signal frequency is swept with the signal level set for the desired output amplitude.
The LMH5401-SP is fully symmetrical, either input (IN+ or IN–) can be used for single-ended inputs. The unused
input must be terminated. RF, RG1, and RG2 determine the gain. RT and RM enable matching to the source
resistance. See the Test Schematics section for more information on setting these resistors per gain and source
impedance requirements. Bandwidth is dependant on gain settings because this device is a voltage feedback
amplifier. With a GBP of 6.5 GHz, the approximate bandwidth can be calculated for a specific application
requirement, as shown in 公式 2. 图 55 illustrates a test schematic for differential input and output.
GBP (Hz) = BW (Hz) × Noise Gain
(2)
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Frequency Response (接下页)
For tests with differential inputs, the same setup for single-ended inputs is used except all four connectors are
connected to a network analyzer port. Measurements are made in either true differential mode on the Rohde &
Schwarz® network analyzer or in calculated differential mode. In both cases, the differential inputs are each
driven with a 50-Ω source. 表 2 and 表 3 list resistor values for various gain settings.
表 2. Differential Input/Output
AV (V/V)
RG1, RG2 (Ω)
100
RF (Total / External, Ω)
199 / 174
RT (Ω)
100
2
4
49.9
199 / 174
N/A
6
49.9
300 / 274
N/A
8
49.9
400 / 375
N/A
10
49.9
500 / 475
N/A
表 3. SE Input
AV (V/V)
RG1 (Ω)
90.9
RT (Ω)
76.8
RG2 (Ω)
121
RF (Total / External, Ω)
200 / 175
2
4
22.6
357
66.5
152 / 127
8
12.1
1100
1580
60.4
250 / 225
10
9.76
57.6
300 / 275
8.4 S-Parameters
The standard EVM is used for all s-parameter measurements. All four ports are used or are terminated with 50
Ω; see the Frequency Response section.
8.5 Frequency Response with Capacitive Load
The standard EVM is used and the capacitive load is soldered to the inside pads of the 40-Ω matching resistors
(on the DUT side). In this configuration, the on-chip, 10-Ω resistors isolate the capacitive load from the amplifier
output pins. The test schematic for capacitive load measurements is illustrated in 图 56.
8.6 Distortion
The standard EVM is used for measuring single-tone harmonic distortion and two-tone intermodulation distortion.
All distortion is measured with single-ended input signals; see 图 57. In order to interface with single-ended test
equipment, external baluns are required between the EVM output ports and the test equipment. The Typical
Characteristics plots are created with Marki™ baluns, model number BAL-0010. These baluns are used to
combine two tones in the two-tone test plots. For distortion measurements the same termination must be used on
both input pins. When a filter is used on the driven input port, the same filter and a broadband load are used to
terminate the other input. When the signal source is a broadband controlled impedance, then only a broadband-
controlled impedance is required to terminate the unused input.
8.7 Noise Figure
The standard EVM is used with a single-ended input matched to 50-Ω and the Marki balun on the output similar
to the harmonic distortion test setup.
8.8 Pulse Response, Slew Rate, and Overdrive Recovery
The standard EVM is used for time-domain measurements. The input is single-ended with the differential outputs
routed directly to the oscilloscope inputs. The differential signal response is calculated from the two separate
oscilloscope inputs (图 28 to 图 30). In addition, the common-mode response is also captured in this
configuration.
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8.9 Power Down
The standard EVM is used with the shorting block on jumper JPD removed completely. A high-speed, 50-Ω pulse
generator is used to drive the PD pin when the output signal is measured by viewing the output signal (such as a
250-MHz sine-wave input).
8.10 VCM Frequency Response
The standard EVM is used with RCM+ and RCM– removed and a new resistor installed at RTCM = 49.9 Ω. The
49.9-Ω resistor is placed at R14 on the EVM schematic. A network analyzer is connected to the VCM input of the
EVM and the EVM outputs are connected to the network analyzer with 50-Ω coaxial cables. Set the network
analyzer analysis settings to single-ended input and differential output. Measure the output common-mode with
respect to the single-ended input (Scs21). The input signal frequency is swept with the signal level set for 100
mV (–16 dBm). Note that the common-mode control circuit gain is one.
8.11 Test Schematics
RT = 1100 W
LMH5401
Differential
Load = 200 W
50-W
Single-Ended
Input
25 W
RF = 200 W
R1 = 12.1 W
10 W
40 W
40 W
OUT+
OUT-
IN-
-
1
Test Equipment
With 50-W
Inputs
+
Test Equipment
With 50-W
+
-
+
-
OUT_AMP
OUT_LOAD
IN+
-
2
Outputs
R2 = 60 W
RF = 200 W
10 W
25 W
Test Equipment
Load = 100 W
CM
PD
Copyright © 2017, Texas Instruments Incorporated
图 54. Test Schematic: Single-Ended Input, Differential Output, GV = 7 V/V
RL = 100 W
RLtotal = 200 W
RT = NA
LMH5401
Rin = 100-W diff
25 W
RF = 187 W
G1 = 50 W
10 W
40 W
40 W
R
IN-
IN+
-
1
Test Equipment
With 50-W
Inputs
Test Equipment
With 50-W
Rs = 100-W diff
+
-
+
-
+
-
OUT_AMP
RG2 = 50 W
RF = 187 W
OUT_LOAD
2
10 W
25 W
Test Equipment
Load = 100 W
RT = NA
CM
PD
Copyright © 2017, Texas Instruments Incorporated
图 55. Test Schematic: Differential Input, Differential Output, GV = 4.25 V/V
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Test Schematics (接下页)
RL
RLtotal
LMH5401
RT
FB+
IN-
25 W
RF
Single-Ended
Input
10 W
10 W
RO
RO
RG
RG
-
Test Equipment
With 50-W
Load Impedances
Test Equipment
With 50-W
Source Impedance
+
-
+
-
+
-
CO
IN+
FB-
RM
RF
25 W
OUT_AMP
OUT_LOAD
Copyright © 2017, Texas Instruments Incorporated
CM
图 56. Test Schematic: Capacitive Load, GV = 7 V/V
RLtotal = 200 W
RL = 100 W
LMH5401
1100 W
25 W
50-W
Single-Ended
200 W
40 W
40 W
Input
10 W
12.1 W
IN-
OUT+
OUT-
-
Test Equipment
With 50-W
Inputs
BAL
0010
+
-
Test Equipment
With 50-W
+
-
+
-
OUT_AMP
IN+
Outputs
60 W
10 W
OUT_LOAD
200 W
25 W
PD
CM
Copyright © 2017, Texas Instruments Incorporated
图 57. Test Schematic for Noise Figure and Single-Ended Harmonic Distortion, GV = 7 V/V
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9 Detailed Description
9.1 Overview
The LMH5401-SP is a very high-performance, differential amplifier optimized for radio frequency (RF) and
intermediate frequency (IF) or high-speed, time-domain applications for wide bandwidth applications as the GBP
is 6.5 GHz. The device is ideal for dc- or ac-coupled applications that may require a single-ended-to-differential
(SE-DE) conversion when driving an analog-to-digital converter (ADC). The necessary external feedback (RF)
and gain set (RG) resistors configure the gain of the device. For the EVM the standard gain is set to Gv = 17 dB
(for both DE and SE conversions) with RF = 200 Ω and RG = 12.1 Ω.
A common-mode reference input pin is provided to align the amplifier output common-mode with the ADC input
requirements. Power supplies between 3.3 V and 5 V can be selected and dual-supply operation is supported
when required by the application. A power-down feature is also available for power savings.
The LMH5401-SP offers two on-chip termination resistors, one for each output with values of 10 Ω each. For
most load conditions the 10-Ω resistors are only a partial termination. Consequently, external termination
resistors are required in most applications. See 表 4 for some common load values and the matching resistors.
9.2 Functional Block Diagram
V+
+FB
25 ꢀ
+OUT
10 ꢀ
œ
-IN
2.5 kꢀ
2.5 kꢀ
High-Aol
Differential I/O
Amplifier
+
œ
+IN
-FB
+
-OUT
10 ꢀ
25 ꢀ
V+
œ
Vcm
Error
Amplifier
+
VCM
PD
GND
Compa
rator
NOTE: V- and GND are isolated.
Vœ
Copyright © 2017, Texas Instruments Incorporated
NOTE: V– and GND are isolated.
9.3 Feature Description
The LMH5401-SP includes the following features:
•
•
•
•
•
•
•
Fully-differential amplifier
Flexible gain configurations using external resistors
Output common-mode control
Single- or split-supply operation
Gain bandwidth product (GBP) of 6.5 GHz
Linear bandwidth of 2 GHz (Gv = 17 dB)
Power down
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Feature Description (接下页)
9.3.1 Fully-Differential Amplifier
The LMH5401-SP is a voltage feedback (VFA)-based fully-differential amplifier (FDA) offering a GBP of 6.5 GHz
with flexible gain options using external resistors. The core differential amplifier is a slightly decompensated
voltage feedback design with a high slew rate and best-in-class linearity up to 2 GHz for Gv = 17 dB (SE-DE,
DE-DE).
As with all FDA devices, the output average voltage (common-mode) is controlled by a separate common-mode
loop. The target for this output average is set by the VCM input pin. The VOCM range extends from 1.1 V below the
midsupply voltage to 1.1 V above the midsupply voltage when using a 5-V supply. Note that on a 3.3-V supply
the output common-mode range is quite small. For applications using a 3.3-V supply voltage, the output
common-mode must remain very close to the midsupply voltage.
The input common-mode voltage offers more flexibility than the output common-mode voltage. The input
common-mode range extends from the negative rail to approximately 1 V above the midsupply voltage when
powered with a 5-V supply.
A power-down pin is included. This pin is referenced to the GND pins with a threshold voltage of approximately 1
V. Setting the PD pin voltage to more than the specified minimum voltage turns the device off, placing the
LMH5401-SP into a very low quiescent current state. Note that, when disabled, the signal path is still present
through the passive external resistors. Input signals applied to a disabled LMH5401-SP device still appear at the
outputs at some level through this passive resistor path, as with any disabled FDA device. The power-down pin
is biased to the logic low state with a 50-kΩ internal resistor.
9.3.2 Operations for Single-Ended to Differential Signals
One of the most useful features supported by the FDA device is the active balun configuration which provides an
easy conversion from a single-ended input to a differential output centered on a user-controlled, common-mode
level. Although the output side is relatively straightforward, the device input pins move in a common-mode sense
with the input signal. This feature acts to increase the apparent input impedance to be greater than the RG value.
However, this feature can cause input clipping if this common-mode signal moves beyond the input range. This
input active impedance issue applies to both ac- and dc-coupled designs, and requires somewhat more complex
solutions for the resistors to account for this active impedance, as described in this section.
9.3.2.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversion
When the signal path is ac coupled, the dc biasing for the LMH5401-SP becomes a relatively simple task. In all
designs, start by defining the output common-mode voltage. The ac-coupling issue can be separated for the
input and output sides of an FDA design. The input can be ac coupled and the output dc coupled, or the output
can be ac coupled and the input dc coupled, or they can both be ac coupled. One situation where the output can
be dc coupled (for an ac-coupled input), is when driving directly into an ADC where the VOCM control voltage
uses the ADC common-mode reference to directly bias the FDA output common-mode to the required ADC input
common-mode. The feedback path must always be dc-coupled. In any case, the design starts by setting the
desired VOCM. When an ac-coupled path follows the output pins, the best linearity is achieved by operating VOCM
at mid supply. The VOCM voltage must be within the linear range for the common-mode loop, as specified in the
headroom specifications. If the output path is also ac coupled, simply letting the VOCM control pin float is usually
preferred in order to obtain a midsupply default VOCM bias with no external elements. To limit noise, place a 0.1-
µF decoupling capacitor on the VOCM pin to ground. After VOCM is defined, check the target output voltage swing
to ensure that the VOCM positive or negative output swing on each side does not clip into the supplies. If the
desired output differential swing is defined as VOPP, divide by 4 to obtain the ±VP swing around VOCM at each of
the two output pins (each pin operates 180° out of phase with the other). Check that VOCM ±VP does not exceed
the output swing of this device. Going to the device input pins side, because both the source and balancing
resistor on the non-signal input side are dc blocked (see 图 59), no common-mode current flows from the output
common-mode voltage, thus setting the input common-mode equal to the output common-mode voltage. This
input headroom also sets a limit for higher VOCM voltages. The minimum headroom for the input pins to the
positive supply overrides the headroom limit for the output VOCM because the input VICM is the output VOCM for
ac-coupled sources. Also, the input signal moves this input VICM around the dc bias point, as described in the
Resistor Design Equations for Single-to-Differential Applications subsection of the Fully-Differential Amplifier
section.
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Feature Description (接下页)
9.3.2.2 DC-Coupled Input Signal Path Considerations for SE-DE Conversions
The output considerations remain the same as for the ac-coupled design. Again, the input can be dc coupled
when the output is ac coupled. A dc-coupled input with an ac-coupled output can have some advantages to
move the input VICM down if the source is ground referenced. When the source is dc coupled into the LMH5401-
SP (as shown in 图 58), both sides of the input circuit must be dc coupled to retain differential balance. Normally,
the non-signal input side has an RG element biased to whatever the source midrange is expected to be.
Providing this mid-scale reference gives a balanced differential swing around VOCM at the outputs. Often, RG2 is
simply grounded for dc-coupled, bipolar-input applications. This configuration gives a balanced differential output
if the source swings around ground. If the source swings from ground to some positive voltage, grounding RG2
gives a unipolar output differential swing from both outputs at VOCM (when the input is at ground) to one polarity
of swing. Biasing RG2 to an expected midpoint for the input signal creates a differential output swing around
VOCM. One significant consideration for a dc-coupled input is that VOCM sets up a common-mode bias current
from the output back through RF and RG to the source on both sides of the feedback. Without input-balancing
networks, the source must sink or source this dc current. After the input signal range and biasing on the other RG
element is set, check that the voltage divider from VOCM to VI through RF and RG (and possibly RS) establishes
an input VICM at the device input pins that is in range.
50-W Input Match, Gain of 7 V/V
from RT, Single-Ended Source to
RLtotal = 200 W
RL = 100 W
Differential Output
LMH5401
RT = 1100 W
RF = 200 W
25 W
50-W
Source
10 W
40 W
40 W
RG1 = 12.1 W
IN-
OUT+
OUT-
-
+
-
+
-
+
-
C1 = 0.1 mF
100 W
OUT_AMP
IN+
RG2 = 60 W
RF = 200 W
10 W
25 W
PD
CM
Copyright © 2017, Texas Instruments Incorporated
图 58. DC-Coupled, Single-Ended-to-Differential, Gv = 7 V/V
9.3.2.3 Resistor Design Equations for Single-to-Differential Applications
Being familiar with the FDA resistor selection criteria is still important because the LMH5401-SP gain is
configured through external resistors. The design equations for setting the resistors around an FDA to convert
from a single-ended input signal to a differential output can be approached in several ways. In this section,
several critical assumptions are made to simplify the results:
•
•
The feedback resistors are selected first and are set to be equal on the two sides of the device.
The dc and ac impedances from the summing junctions back to the signal source and ground (or a bias
voltage on the non-signal input side) are set equal to retain the feedback divider balance on each side of the
FDA.
Both of these assumptions are typical and are aimed to deliver the best dynamic range through the FDA signal
path.
After the feedback resistor values are chosen, the aim is to solve for RT (a termination resistor to ground on the
signal input side), RG1 (the input gain resistor for the signal path), and RG2 (the matching gain resistor on the
non-signal input side); see 图 59. This example uses the LMH5401-SP, an external resistor FDA. The same
resistor solutions can be applied to either ac- or dc-coupled paths. Adding blocking capacitors in the input-signal
chain is a simple option. Adding these blocking capacitors after the RT element (see 图 59) has the advantage of
removing any dc currents in the feedback path from the output VOCM to ground.
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Feature Description (接下页)
50-W Input Match, Gain of 7 V/V
from RT, Single-Ended Source to
Differential Output
RLtotal = 200 W
RL = 100 W
LMH5401-SP
RT = 1100 W
RF = 200 W
25 W
50-W
Source
10 W
40 W
40 W
RG1 = 12.1 W
IN-
OUT+
OUT-
-
+
-
+
-
+
-
C1 = 0.1 mF
100 W
OUT_AMP
IN+
RG2 = 60 W
RF = 200 W
10 W
C2 = 0.1 mF
25 W
PD
CM
图 59. AC-Coupled, Single-Ended Source to a Differential Gain of a 7-V/V
Most FDA amplifiers use external resistors and have complete flexibility in the selected RF, however the
LMH5401-SP has small on-chip feedback resistors that are fixed at 25 Ω. The equations used in this section
apply with an additional 25 Ω to be added to the external RF resistors.
After the feedback resistor values are chosen, the aim is to solve for RT (a termination resistor to ground on the
signal input side), RG1 (the input gain resistor for the signal path), and RG2 (the matching gain resistor on the
non-signal input side). The same resistor solutions can be applied to either ac- or dc-coupled paths. Adding
blocking capacitors in the input-signal chain is a simple option. Adding these blocking capacitors after the RT
element has the advantage of removing any dc currents in the feedback path from the output VOCM to ground.
Earlier approaches to the solutions for RT and RG1 (when the input must be matched to a source impedance, RS)
follow an iterative approach. This complexity arises from the active input impedance at the RG1 input. When the
FDA is used to convert a single-ended signal to differential, the common-mode input voltage at the FDA inputs
must move with the input signal to generate the inverted output signal as a current in the RG2 element. A more
recent solution is shown as 公式 3, where a quadratic in RT can be solved for an exact required value. This
quadratic emerges from the simultaneous solution for a matched input impedance and target gain. The only
inputs required are:
1. The selected RF value.
2. The target voltage gain (AV) from the input of RT to the differential output voltage.
3. The desired input impedance at the junction of RT and RG1 to match RS.
Solving this quadratic for RT starts the solution sequence, as shown in 公式 3:
RS
2
≈
’
2
2RS 2RF+
A V
2RFR 2 A V
∆
÷
«
◊
RT2 -RT
-
= 0
S
2RF 2 + A - R A (4 + A ) 2RF 2 + A - R A (4 + A V )
V
S
V
V
V
S
V
(3)
Being a quadratic, there are limits to the range of solutions. Specifically, after RF and RS are chosen, there is
physically a maximum gain beyond which 公式 3 starts to solve for negative RT values (if input matching is a
requirement). With RF selected, use 公式 4 to verify that the maximum gain is greater than the desired gain.
»
…
ÿ
Ÿ
Ÿ
Ÿ
Ÿ
RF
RS
4
RF
RS
…
Avmax = (
- 2) • 1+ 1+
…
…
…
RF
RS
(
- 2)2
Ÿ
⁄
(4)
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Feature Description (接下页)
If the achievable AVmax is less than desired, increase the RF value. After RT is derived from 公式 3, the RG1
element is given by 公式 5:
RF
2
- RS
A V
RG1
=
RS
RT
1+
(5)
Then, the simplest approach is to use a single RG2 = RT || RS + RG1 on the non-signal input side. Often, this
approach is shown as the separate RG1 and RS elements. This approach can provide a better divider match on
the two feedback paths, but a single RG2 is often acceptable. A direct solution for RG2 is given as 公式 6:
RF
2
A V
RG2
=
RS
RT
1+
(6)
This design proceeds from a target input impedance matched to RS, signal gain AV, and a selected RF value. The
nominal RF value chosen for the LMH5401-SP characterization is 225 Ω (RFExternal + RFInternal, where RFInternal is
always 25 Ω). As discussed previously, this resistance is on-chip and cannot be changed. Refer to 表 2 and 表 3
in the Frequency Response section, which list the value of resistors used for characterization in this document.
9.3.2.4 Input Impedance Calculations
The designs so far have included a source impedance, RS, that must be matched by RT and RG1. The total
impedance with respect to the input at RG1 for the circuit of 图 58 is the parallel combination of RT to ground and
ZA (active impedance) presented by the amplifier input at RG1. That expression, assuming RG2 is set to obtain a
differential divider balance, is given by 公式 7:
≈
∆
«
’≈
÷∆
◊«
’
÷
◊
RG1
RG2
RF
1+
1+
RG1
ZA = RG1
RF
2 +
RG2
(7)
For designs that do not need impedance matching (but instead come from the low-impedance output of another
amplifier, for instance), RG1 = RG2 is the single-to-differential design used without RT to ground. Setting RG1 = RG2
= RG in 公式 7 gives the input impedance of a simple input FDA driving from a low-impedance, single-ended
source to a differential output.
9.3.3 Differential-to-Differential Signals
The LMH5401-SP can also be used to amplify differential input signals to differential output signals. In many
ways, this method is a much simpler way to operate the FDA from a design equations perspective. Again,
assuming the two sides of the circuit are balanced with equal RF and RG elements, the differential input
impedance is now just the sum of the two RG elements to a differential inverting summing junction. In these
designs, the input common-mode voltage at the summing junctions does not move with the signal, but must be
dc biased in the allowable range for the input pins with consideration given to the voltage headroom required to
each supply. Slightly different considerations apply to ac- or dc-coupled, differential-in to differential-out designs,
as described in this section.
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Feature Description (接下页)
9.3.3.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
When using the LMH5401-SP with an ac-coupled differential source, the input can be coupled in through two
blocking capacitors. An optional input differential termination resistor (RM) can be included to allow the input RG
resistors to be scaled up while still delivering lower differential input impedance to the source. In 图 60, the RG
elements sum to show a 200-Ω differential impedance and the RM element combines in parallel to give a net
100-Ω, ac, differential impedance to the source. Again, the design proceeds ideally by selecting the RF element
values, then the RG to set the differential gain, then an RM element (if needed) to achieve a target input
impedance. Alternatively, the RM element can be eliminated, the RG elements set to the desired input impedance,
and RF set to the get the differential gain (= RF / RG). The dc biasing in 图 60 is very simple. The output VOCM is
set by the input control voltage and, because there is no dc current path for the output common-mode voltage,
that dc bias also sets the input pins common-mode operating points.
RF1 = 402 W
C1
RG1 = 100 W
Downconverter Mixer
Differential
Output
VOCM
RM = 200 W
FDA
RL = 200 W
RG2 = 100 W
C1
RF2 = 402 W
图 60. Downconverting Mixer AC-Coupled to the LMH5401-SP (GV = 4 V/V)
9.3.3.2 DC-Coupled, Differential-Input to Differential-Output Design Issues
Operating the LMH5401-SP with a dc-coupled input source simply requires that the input pins stay in range of
the dc common-mode operating voltage. Only RG values that are equal to the differential input impedance and
that set the correct RF values for the gain desired are required.
9.3.4 Output Common-Mode Voltage
The CM input controls the output common-mode voltage. CM has no internal biasing network and must be driven
by an external source or resistor divider network to the positive power supply. The CM input impedance is very
high and bias current is not critical. Also, the CM input has no internal reference and must be driven from an
external source. Using a bypass capacitor is also necessary. A capacitor value of 0.01 µF is recommended. For
best harmonic distortion, maintain the CM input within ±1 V of the midsupply voltage using a 5-V supply and
within ±0.5 V when using a 3.3-V supply. The CM input voltage can be operated outside this range if lower
output swing is used or distortion degradation is allowed. For more information, see 图 24 and 图 25.
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9.4 Device Functional Modes
9.4.1 Operation With a Split Supply
The LMH5401-SP can be operated using split supplies. One of the most common supply configurations is ±2.5
V. In this case, VS+ is connected to 2.5 V, VS– is connected to –2.5 V, and the GND pins are connected to the
system ground. As with any device, the LMH5401-SP is impervious to what the levels are named in the system.
In essence, using split supplies is simply a level shift of the power pins by –2.5 V. If everything else is level-
shifted by the same amount, the device does not detect any difference. With a ±2.5-V power supply, the CM
range is 0 V ±1 V; the input has a slightly larger range of –2.5 V to 1 V. This design has certain advantages in
systems where signals are referenced to ground, and as noted in the ADC Input Common-Mode Voltage
Considerations—DC-Coupled Input section, for driving ADCs with low input common-mode voltage requirements
in dc-coupled applications. With the GND pin connected to the system ground, the power-down threshold is 1.2
V, which is compatible with most logic levels from 1.5-V CMOS to 2.5-V CMOS.
As noted previously, the absolute supply voltage values are not critical. For example, using a 4-V VS+ and a
–1-V VS– still results in a 5-V supply condition. As long as the input and output common-mode voltages remain
in the optimum range, the amplifier can operate on any supply voltages from 3.3 V to 5.25 V. When considering
using supply voltages near the 3.3-V total supply, be very careful to make sure that the amplifier performance is
adequate. Setting appropriate common-mode voltages for large-signal swing conditions becomes difficult when
the supply voltage is below 4 V.
9.4.2 Operation With a Single Supply
As with split supplies, the LMH5410-SP can be operated from single-supply voltages from 3.3 V to 5.25 V.
Single-supply operation is most appropriate when the signal path is ac coupled and the input and output
common-mode voltages are set to mid supply by the CM pin and are preserved by coupling capacitors on the
input and output.
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10 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Stability, Noise Gain, and Signal Gain
Two types of gain are associated with amplifiers: noise gain (NG) and signal gain. Noise gain determines the
stability of an amplifier. The noise gain is the inverse of the voltage divider from the outputs back to the
differential inputs. This gain is calculated by NG = (RF / RIN) + 1. For the LMH5401-SP, NG > 4 creates a stable
circuit independent on how the signal gain is set. In 图 61, for optimal performance choose RF within the values
noted in this document (see the Parameter Measurement Information section for further information). Using too
large of a resistance in the feedback path adds noise and can possibly have a negative affect on bandwidth,
depending on the parasitic capacitance of the board; too low of a resistance can load the output, thus affecting
distortion performance. When low signal gain stability is needed, the noise gain can be altered with the addition
of a resistor, Rcomp. By manipulating the noise gain with this addition, the amplifier can be stabilized at lower
signal gains. In 图 61, RS and Rcomp in parallel combination also affects the noise gain of the amplifier. RG and RF
are the main gain-setting resistors and the addition of Rcomp adjusts the noise gain for stability. Much of this
stability can be simulated using the LMH5401-SP TINA model, depending on the amplifier configuration. The
example in 图 61 uses the LMH5401-SP, a signal gain of 2.8 V/V, and a noise gain of 4.75 V/V resulting in the
frequency response shown in 图 62.
RL
RLtotal
LMH5401-SP
RT = 84.5 ꢀ
RF = 200 ꢀ
RG = 68.1 ꢀ
FB+
IN-
25 ꢀ
Single-Ended
Input
10 ꢀ
RO
RO
-
Test Equipment
With 50-ꢀ
Load Impedances
Test Equipment
With 50-ꢀ
Source Impedance
+
-
+
-
+
-
RCOMP = 301 ꢀ
IN+
FB-
RG = 68.1 ꢀ
RM = 99.5 ꢀ
10 ꢀ
25 ꢀ
RF = 200 ꢀ
OUT_AMP
OUT_LOAD
CM = mid-supply
图 61. Noise Gain Compensation for Stability at Gp = 0 dB
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Application Information (接下页)
10
5
0
-5
-10
-15
Gp = 0 dB, Gv = 9 dB
100
-20
10
1k
10k
Frequency (MHz)
SBOS
图 62. SE-DE Small Signal Frequency Response for Low Gain
10.1.2 Input and Output Headroom Considerations
The starting point for most designs is to assign an output common-mode voltage. For ac-coupled signal paths,
this starting point is often the default midsupply voltage to retain the most available output swing around the
output operating point, which is centered with VCM equal to the midsupply point. For dc-coupled designs, set this
voltage considering the required minimum headroom to the supplies listed in the Electrical Characteristics tables
for VCM control. From that target output, VCM, the next step is to verify that the desired output differential VPP
stays within the supplies. For any desired differential output voltage (VOPP) check the maximum possible signal
swing for each output pin. Make sure that each pin can swing to the voltage required by the application.
For instance, when driving the ADC12D1800RF with a 1.25-V common-mode and 0.8-VPP input swing, the
maximum output swing is set by the negative-going signal from 1.25 V to 0.2 V. The negative swing of the signal
is right at the edge of the output swing capability of the LMH5401-SP. In order to set the output common-mode to
an acceptable range, a negative power supply of at least –1 V is recommended. The ideal negative supply
voltage is the ADC VCM – 2.5 V for the negative supply and the ADC VCM + 2.5 V for the input swing. In order to
use the existing supply rails, deviating from the ideal voltage may be necessary.
With the output headroom confirmed, the input junctions must also stay within their operating range. Because the
input range extends nearly to the negative supply voltage, input range limitations only appear when approaching
the positive supply where a maximum 1.5-V headroom is required.
The input pins operate at voltages set by the external circuit design, the required output VOCM, and the input
signal characteristics. The operating voltage of the input pins depends on the external circuit design. With a
differential input, the input pins operate at a fixed input VICM, and the differential input signal does not influence
this common-mode operating voltage.
AC-coupled differential input designs have a VICM equal to the output VOCM. DC-coupled differential input designs
must check the voltage divider from the source VCM to the LMH5401-SP CM setting. That result solves to an
input VICM within the specified range. If the source VCM can vary over some voltage range, the validation
calculations must include this variation.
10.1.3 Noise Analysis
The first step in the output noise analysis is to reduce the application circuit to its simplest form with equal
feedback and gain setting elements to ground (as shown in 图 63) with the FDA and resistor noise terms to be
considered.
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Application Information (接下页)
2
2
enRG
enRF
RF
RG
2
In+
+
2
eno
œ
2
Inœ
2
eni
2
2
enRG
enRF
RG
RF
图 63. FDA Noise-Analysis Circuit
The noise powers are shown in 图 63 for each term. When the RF and RG terms are matched on each side, the
total differential output noise is the root sum of squares (RSS) of these separate terms. Using NG (noise gain) ≡
1 + RF / RG, the total output noise is given by 公式 8. Each resistor noise term is a 4-kTR power.
2
2
eno
=
e NG + 2 i R
+ 2 4kTR NG
F
(
)
(
)
(
)
ni
n
F
(8)
The first term is simply the differential input spot noise times the noise gain. The second term is the input current
noise terms times the feedback resistor (and because there are two terms, the power is two times one of the
terms). The last term is the output noise resulting from both the RF and RG resistors, again times two, for the
output noise power of each side added together. Using the exact values for a 50-Ω, matched, single-ended to
differential gain, sweep with 2 Ω (plus an internal 25 Ω) and the intrinsic noise eni = 1.25 nV and in = 3.5 pA for
the LMH5401-SP, which gives an output spot noise from 公式 8. Then, dividing by the signal gain set through
internal resistors (AV), gives the input-referred, spot-noise voltage (ei) of 1.35 nV/√Hz. Note that for the
LMH5401-SP the current noise is an insignificant noise contributor because of the low value of RF.
10.1.4 Noise Figure
Noise figure (NF) is a helpful measurement in an RF system design. The basis of this calculation is to define how
much thermal noise the system (or even on the component) adds to this input signal. All systems are assumed to
have a starting thermal noise power of –174 dBm/√Hz at room temperature calculated from P(dBW) = 10 × log
(kTB), where T is temperature in Kelvin (290k), B is bandwidth in Hertz (1 Hz), and k is Boltzmann's constant
1.38 × 10–23 (J / K). Whenever an element is placed in a system, additional noise is added beyond the thermal
noise floor. The noise factor (F) helps calculate the noise figure and is the ratio between the input SNR and the
output SNR. Input SNR includes the noise contribution from the resistive part of the source impedance, ZS. NF is
relative to the source impedance used in the measurement or calculation because ideal capacitors and inductors
are known to be noiseless. NF can be calculated by 公式 9:
NF = 10 log (eno2 / enZs)
where
•
•
en(Zs) is the thermal noise of the source resistance and equal to 4 kTRS (GDT)2,
G is the voltage gain of the amplifier.
(9)
From 公式 10, NF is roughly equal to 10 dB which is the just above the actual value of 9.6 dB measured on the
bench at 200 MHz when referenced to 50 Ω and as illustrated in 图 29.
RT
DT =
RS + RT
(10)
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Application Information (接下页)
For thermal noise calculations with different source resistance, 公式 11 can be used to calculate the NF change
with a new source resistance. For example, 公式 9 uses a source resistance of 50 Ω. By using a source of 100
Ω, the new noise figure calculation (公式 11) yields an NF with a 3-dB improved. This is intuitive as the noise of
source increases, the noise of the amplifier becomes less noticeable, and, hence, the NF improves.
en(Zs) = kTRs
(11)
10.1.5 Thermal Considerations
The LMH5401-SP is packaged in a space-saving LCCC package that has a thermal coefficient (RθJC(bot)) of
63.8°C/W. Limit the total power dissipation in order to keep the device junction temperature below 150°C for
instantaneous power and below 125°C for continuous power.
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10.2 Typical Application
The LMH5401-SP is designed as a single-ended-to-differential (SE-DE) and differential-to-differential (DE-DE)
gain block configured with external resistors and gain-stable single-ended to differential for NG ≥ 2 V/V. The
LMH5401-SP has no low-end frequency cutoff and has 6.5-GHz gain product bandwidth. The LMH5401-SP is a
very attractive substitute for a balun transformer in many applications.
The resistors labeled RO serve to match the filter impedance to the 20-Ω amplifier differential output impedance.
If no filter is used, these resistors may not be required if the ADC is located very close to the LMH5401-SP. If
there is a transmission line between the LMH5401-SP and the ADC then the RO resistors must be sized to match
the transmission line impedance. A typical application driving an ADC is shown in 图 64.
25 ꢀ
RT
FB+
RF
50-ꢀ,
Single-Ended Input
RO
RO
OUT+
RG
10 ꢀ
INœ
œ
IN+
+
œ
+
œ
OUT_AMP
Filter
ADC12D1620
LMH5401-SP
+
IN+
INœ
10 ꢀ
RG+RM
RF
OUTœ
FBœ
25 ꢀ
CM
Copyright © 2017, Texas Instruments Incorporated
图 64. Single-Ended Input ADC Driver
10.2.1 Design Requirements
The main design requirements are to keep the amplifier input and output common-mode voltages compatible
with the ADC requirements and the amplifier requirements. Using split power supplies may be required.
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Typical Application (接下页)
10.2.2 Detailed Design Procedure
10.2.2.1 Driving Matched Loads
The LMH5401-SP has on-chip output resistors, however, for most load conditions additional resistance must be
added to the output to match a desired load. 表 4 lists the matching resistors for some common load conditions.
表 4. Load Component Values(1)
RO+ AND RO– FOR A MATCHED
TERMINATION
TOTAL LOAD RESISTANCE AT
LOAD (RL)
TERMINATION LOSS
AMPLIFIER OUTPUT (RLtotal
)
50 Ω
100 Ω
200 Ω
400 Ω
1 kΩ
15 Ω
40 Ω
100 Ω
200 Ω
400 Ω
800 Ω
2000 Ω
6 dB
6 dB
6 dB
6 dB
6 dB
90 Ω
190 Ω
490 Ω
(1) The total load includes termination resistors.
10.2.2.2 Driving Unmatched Loads For Lower Loss
When the LMH5401-SP and the load can be placed very close together, back-terminated transmission lines are
not required. In this case, the 6-dB loss can be reduced significantly. One example is shown in 图 65.
Low-Pass Filter
VIN
200 W
12.1 W
8.4 nF
LMH5401-SP
ADC12J4000
0.7 pF
8.4 nF
0.7 pF
1100 W
60 W
200 W
NOTE: Amplitude gain = 17 dB and net gain to ADC = 15.5 dB.
图 65. Low-Loss ADC
10.2.2.3 Driving Capacitive Loads
With high-speed signal paths, capacitive loading is highly detrimental to the signal path, as shown in 图 66.
Designers must make every effort to reduce parasitic loading on the amplifier output pins. The device on-chip
resistors are included in order to isolate the parasitic capacitance associated with the package and the PCB pads
that the device is soldered to. The LMH5401-SP is stable with most capacitive loads ≤ 10 pF; however,
bandwidth suffers with capacitive loading on the output.
10
5
0
-5
-10
Cload = No Cap
Cload = 1 pF
Cload = 2.4 pF
Cload = 4.7 pF
-15
-20
10
100
1k
Frequency (MHz)
10k
SBOS
图 66. Frequency Response with Capacitive Load
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10.2.2.4 Driving ADCs
The LMH5401-SP is designed and optimized for the highest performance to drive differential input ADCs. 图 67
shows a generic block diagram of the LMH5401-SP driving an ADC. The primary interface circuit between the
amplifier and the ADC is usually a filter of some type for antialias purposes, and provides a means to bias the
signal to the input common-mode voltage required by the ADC. Filters range from single-order real RC poles to
higher-order LC filters, depending on the requirements of the application. Output resistors (RO) are shown on the
amplifier outputs to isolate the amplifier from any capacitive loading presented by the filter.
25 ꢀ
FB+
RF
OUT+
RO
RO
10 ꢀ
OUT_AMP
10 ꢀ
RG
INœ
œ
IN+
+
œ
+
œ
100-ꢀ
Differential Input
LMH5401-SP
Filter
ADC
IN+
INœ
+
RG
OUTœ
RF
FBœ
25 ꢀ
CM
Copyright © 2017, Texas Instruments Incorporated
图 67. Differential ADC Driver Block Diagram
The key points to consider for implementation are the SNR, SFDR, and ADC input considerations as described in
this section.
10.2.2.4.1 SNR Considerations
The signal-to-noise ratio (SNR) of the amplifier and filter can be calculated from the amplitude of the signal and
the bandwidth of the filter. The noise from the amplifier is band-limited by the filter with the equivalent brick-wall
filter bandwidth. The amplifier and filter noise can be calculated using 公式 12:
V2
VO
O
SNRAMP+FILTER = 10 ´ log
= 20 ´ log
e2
eFILTEROUT
FILTEROUT
where:
•
•
•
•
eFILTEROUT = eNAMPOUT × √ENB,
eNAMPOUT = the output noise density of the LMH5401-SP,
ENB = the brick-wall equivalent noise bandwidth of the filter, and
VO = the amplifier output signal.
(12)
For example, with a first-order (N = 1) band-pass or low-pass filter with a 30-MHz cutoff, the ENB is 1.57 × f–3dB
= 1.57 × 30 MHz = 47.1 MHz. For second-order (N = 2) filters, the ENB is 1.22 × f–3dB. When filter order
increases, the ENB approaches f–3dB (N = 3 → ENB = 1.15 × f–3dB; N = 4 → ENB = 1.13 × f–3dB). Both VO and
eFILTEROUT are in RMS voltages. For example, with a 2-VPP (0.707 VRMS) output signal and a 30-MHz first-order
filter, the SNR of the amplifier and filter is 70.7 dB with eFILTEROUT = 5.81 nV/√Hz × √47.1 MHz = 39.9 μVRMS
.
The SNR of the amplifier, filter, and ADC sum in RMS fashion is as shown in 公式 13 (SNR values in dB):
-SNRAMP+FILTER
-SNRADC
10
10
SNRSYSTEM = -20 ´ log
10
+ 10
(13)
This formula shows that if the SNR of the amplifier and filter equals the SNR of the ADC, the combined SNR is 3
dB lower (worse). Thus, for minimal degradation (< 1 dB) on the ADC SNR, the SNR of the amplifier and filter
must be ≥ 10 dB greater than the ADC SNR. The combined SNR calculated in this manner is usually accurate to
within ±1 dB of the actual implementation.
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10.2.2.4.2 SFDR Considerations
The SFDR of the amplifier is usually set by the second-order or third-order harmonic distortion for single-tone
inputs, and by the second-order or third-order intermodulation distortion for two-tone inputs. Harmonics and
second-order intermodulation distortion can be filtered to some degree, but third-order intermodulation spurs
cannot be filtered. The ADC generates the same distortion products as the amplifier, but as a result of the
sampling and clock feedthrough, additional spurs (not linearly related to the input signal) are included.
When the spurs from the amplifier and filter are known, each individual spur can be directly added to the same
spur from the ADC, as shown in 公式 14, to estimate the combined spur (spur amplitudes in dBc):
-HDxAMP+FILTER
-HDxADC
20
20
HDxSYSTEM = -20 ´ log
10
+ 10
(14)
This calculation assumes the spurs are in phase, but usually provides a good estimate of the final combined
distortion.
For example, if the spur of the amplifier and filter equals the spur of the ADC, then the combined spur is 6 dB
higher. To minimize the amplifier contribution (< 1 dB) to the overall system distortion, the spur from the amplifier
and filter must be approximately 19 dB lower in amplitude than that of the converter. The combined spur
calculated in this manner is usually accurate to within ±6 dB of the actual implementation; however, higher
variations can be detected as a result of phase shift in the filter, especially in second-order harmonic
performance.
This worst-case spur calculation assumes that the amplifier and filter spur of interest is in phase with the
corresponding spur in the ADC, such that the two spur amplitudes can be added linearly. There are two phase-
shift mechanisms that cause the measured distortion performance of the amplifier-ADC chain to deviate from the
expected performance calculated using 公式 14: common-mode phase shift and differential phase shift.
Common-mode phase shift is the phase shift detected equally in both branches of the differential signal path
including the filter. Common-mode phase shift nullifies the basic assumption that the amplifier, filter, and ADC
spur sources are in phase. This phase shift can lead to better performance than predicted when the spurs
become phase shifted, and there is the potential for cancellation when the phase shift reaches 180°. However, a
significant challenge exists in designing an amplifier-ADC interface circuit to take advantage of a common-mode
phase shift for cancellation: the phase characteristic of the ADC spur sources are unknown, thus the necessary
phase shift in the filter and signal path for cancellation is also unknown.
Differential phase shift is the difference in the phase response between the two branches of the differential filter
signal path. Differential phase shift in the filter as a result of mismatched components caused by nominal
tolerance can severely degrade the even-order distortion of the amplifier-ADC chain. This effect has the same
result as mismatched path lengths for the two differential traces, and causes more phase shift in one path than
the other. Ideally, the phase response over frequency through the two sides of a differential signal path are
identical, such that even-order harmonics remain optimally out of phase and cancel when the signal is taken
differentially. However, if one side has more phase shift than the other, then the even-order harmonic
cancellation is not as effective.
Single-order RC filters cause very little differential phase shift with nominal tolerances of 5% or less, but higher-
order LC filters are very sensitive to component mismatch. For instance, a third-order Butterworth band-pass
filter with a 100-MHz center frequency and a 20-MHz bandwidth creates as much as 20° of differential phase
imbalance in a SPICE Monte Carlo analysis with 2% component tolerances. Therefore, although a prototype may
work, production variance is unacceptable. In ac-coupled applications that require second- and higher-order
filters between the LMH5401-SP and the ADC, a transformer or balun is recommended at the ADC input to
restore the phase balance. For dc-coupled applications where a transformer or balun at the ADC input cannot be
used, using first- or second-order filters is recommended to minimize the effect of differential phase shift because
of the component tolerance.
版权 © 2017–2019, Texas Instruments Incorporated
39
LMH5401-SP
ZHCSH86B –DECEMBER 2017–REVISED FEBRUARY 2019
www.ti.com.cn
10.2.2.4.3 ADC Input Common-Mode Voltage Considerations—AC-Coupled Input
The input common-mode voltage range of the ADC must be respected for proper operation. In an ac-coupled
application between the amplifier and the ADC, the input common-mode voltage bias of the ADC is
accomplished in different ways depending on the ADC. Some ADCs use internal bias networks such that the
analog inputs are automatically biased to the required input common-mode voltage if the inputs are ac-coupled
with capacitors (or if the filter between the amplifier and ADC is a band-pass filter). Other ADCs supply their
required input common-mode voltage from a reference voltage output pin (often called CM or VCM). With these
ADCs, the ac-coupled input signal can be re-biased to the input common-mode voltage by connecting resistors
from each input to the CM output of the ADC, as 图 68 shows. However, the signal is attenuated because of the
voltage divider created by RCM and RO.
RO
RCM
AIN+
Amp
ADC
CM
AIN-
RCM
RO
图 68. Biasing AC-Coupled ADC Inputs Using the ADC CM Output
The signal can be re-biased when ac coupling; thus, the output common-mode voltage of the amplifier is a don’t
care for the ADC.
10.2.2.4.4 ADC Input Common-Mode Voltage Considerations—DC-Coupled Input
DC-coupled applications vary in complexity and requirements, depending on the ADC. One typical requirement is
resolving the mismatch between the common-mode voltage of the driving amplifier and the ADC. Devices such
as the ADS5424 require a nominal 2.4-V input common-mode, whereas other devices such as the ADS5485
require a nominal 3.1-V input common-mode; still others such as the ADS6149 and the ADS4149 require 1.5 V
and 0.95 V, respectively. As shown in 图 69, a resistor network can be used to perform a common-mode level
shift. This resistor network consists of the amplifier series output resistors and pull-up or pull-down resistors to a
reference voltage. This resistor network introduces signal attenuation that may prevent the use of the full-scale
input range of the ADC. ADCs with an input common-mode closer to the typical 2.5-V LMH5401-SP output
common-mode are easier to dc-couple, and require little or no level shifting.
VREF
RP
RO
VAMP+
VADC+
ADC
CIN
Amp
RIN
VAMP-
VADC-
RO
RP
VREF
图 69. Resistor Network to DC Level-Shift Common-Mode Voltage
For common-mode analysis of the circuit in 图 69, assume that VAMP± = VCM and VADC± = VCM (the specification
for the ADC input common-mode voltage). VREF is chosen to be a voltage within the system higher than VCM
(such as the ADC or amplifier analog supply) or ground, depending on whether the voltage must be pulled up or
down, respectively; RO is chosen to be a reasonable value, such as 24.9 Ω. With these known values, RP can be
found by using 公式 15:
VADC - VREF
RP = RO
VAMP - VADC
(15)
40
版权 © 2017–2019, Texas Instruments Incorporated
LMH5401-SP
www.ti.com.cn
ZHCSH86B –DECEMBER 2017–REVISED FEBRUARY 2019
Shifting the common-mode voltage with the resistor network comes at the expense of signal attenuation.
Modeling the ADC input as the parallel combination of a resistance (RIN) and capacitance (CIN) using values
taken from the ADC data sheet, the approximate differential input impedance (ZIN) for the ADC can be calculated
at the signal frequency. The effect of CIN on the overall calculation of gain is typically minimal and can be ignored
for simplicity (that is, ZIN = RIN). The ADC input impedance creates a divider with the resistor network; the gain
(attenuation) for this divider can be calculated by 公式 16:
2RP || ZIN
GAIN =
2RO + 2RP || ZIN
(16)
With ADCs that have internal resistors that bias the ADC input to the ADC input common-mode voltage, the
effective RIN is equal to twice the value of the bias resistor. For example, the ADS5485 has a 1-kΩ resistor tying
each input to the ADC VCM; therefore, the effective differential RIN is 2 kΩ.
The introduction of the RP resistors also modifies the effective load that must be driven by the amplifier. 公式 17
shows the effective load created when using the RP resistors.
RL = 2RO + 2RP || ZIN
(17)
The RP resistors function in parallel to the ADC input such that the effective load (output current) at the amplifier
output is increased. Higher current loads limit the LMH5401-SP differential output swing.
By using the gain and knowing the full-scale input of the ADC (VADC FS), the required amplitude to drive the ADC
with the network can be calculated using 公式 18:
VADC FS
VAMP PP
=
GAIN
(18)
As with any design, testing is recommended to validate whether the specific design goals are met.
10.2.2.5 GSPS ADC Driver
The LMH5401-SP can drive the full Nyquist bandwidth of ADCs with sampling rates up to 4 GSPS, as shown in
图 70. If the front-end bandwidth of the ADC is more than 2 GHz, use a simple noise filter to improve SNR.
Otherwise, the ADC can be connected directly to the amplifier output pins. Matching resistors may not be
required, however allow space for matching resistors on the preliminary design.
LMH5401-SP
25 ꢀ
RT
RF
50-ꢀ
Single-Ended
Input
OUT+
RO
RO
RG
10 ꢀ
OUT_AMP
10 ꢀ
INœ
œ
IN+
+
+
œ
Filter
ADC12D1620QML-SP
IN+
œ
INœ
+
RG
OUTœ
RF
RM
25 ꢀ
CM
Copyright © 2017, Texas Instruments Incorporated
图 70. GSPS ADC Driver
版权 © 2017–2019, Texas Instruments Incorporated
41
LMH5401-SP
ZHCSH86B –DECEMBER 2017–REVISED FEBRUARY 2019
www.ti.com.cn
10.2.2.6 Common-Mode Voltage Correction
The LMH5401-SP can set the output common-mode voltage to within a typical value of ±30 mV. If greater
accuracy is desired, a simple circuit can improve this accuracy by an order of magnitude. A precision, low-power
operational amplifier is used to sense the error in the output common-mode of the LMH5401-SP and corrects the
error by adjusting the voltage at the CM pin. In 图 71, the precision of the op amp replaces the less accurate
precision of the LMH5401-SP common-mode control circuit while still using the LMH5401-SP common-mode
control circuit speed. The op amp in this circuit must have better than a 1-mV input-referred offset voltage and
low noise. Otherwise the specifications are not very critical because the LMH5401-SP is responsible for the
entire differential signal path.
OUT+
œ
INœ
FB+
5 kꢀ
5 kꢀ
+
CM
LMH5401-SP
œ
FBœ
IN+
+
OUTœ
10 nF
œ
LMV771
Desired
VOCM
+
Copyright © 2017, Texas Instruments Incorporated
图 71. Common-Mode Correction Circuit
42
版权 © 2017–2019, Texas Instruments Incorporated
LMH5401-SP
www.ti.com.cn
ZHCSH86B –DECEMBER 2017–REVISED FEBRUARY 2019
10.2.2.7 Active Balun
The LMH5401-SP is designed to convert single-ended signals to a differential output with very high bandwidth
and linearity, as shown in 图 72. The LMH5401-SP can support dc coupling as well as ac coupling. The
LMH5401-SP is smaller than any balun with low-frequency response and has excellent amplitude and phase
balance over a wide frequency range. As shown in 图 73, the LMH5401-SP amplitude imbalance is near 0 dB up
to 1 GHz when used with a 5-V supply. 图 75 plots all S-parameters showing superior wideband input and output
return loss compared to many baluns.
25 ꢀ
LMH5401-SP
FB+
RT
RF
RO
RO
OUT+
RG
10 ꢀ
OUT_AMP
10 ꢀ
Single-Ended Input
INœ
œ
+
œ
+
œ
Differential
Output
IN+
OUTœ
RG
RM
RF
FBœ
25 ꢀ
CM
Copyright © 2017, Texas Instruments Incorporated
图 72. Active Balun
15
10
5
210
200
190
180
170
160
150
0
-5
-10
-15
10
100
1k
10k
10
100
1k
Frequency (MHz)
10k
Frequency (MHz)
SBOS
SBOS
图 73. SE-DE Amplitude Imbalance
图 74. SE-DE Phase Imbalance
版权 © 2017–2019, Texas Instruments Incorporated
43
LMH5401-SP
ZHCSH86B –DECEMBER 2017–REVISED FEBRUARY 2019
www.ti.com.cn
20
10
0
-10
-20
-30
-40
-50
-60
-70
-80
Sds21
Sss11
Sdd22
Ssd12
-90
10
100
1k
Frequency (MHz)
10k
SBOS
图 75. SE-DE Small Signal S-Parameters
44
版权 © 2017–2019, Texas Instruments Incorporated
LMH5401-SP
www.ti.com.cn
ZHCSH86B –DECEMBER 2017–REVISED FEBRUARY 2019
10.2.3 Application Curves
The LMH5401-SP has on-chip series output resistors to isolate the output of the amplifier. These resistors
provide the LMH5401-SP extra phase margin in most applications. When the amplifier is used to drive a
terminated transmission line or a controlled impedance filter, additional external resistance is required to match
the transmission line of the filter. In these matched applications, there is a 6-dB loss of gain. When the
LMH5401-SP is used to drive loads that are not back-terminated or matched, there is a loss in gain resulting
from the on-chip resistors. 图 76 shows that loss for different load conditions. In most cases the loads are
between 50 Ω and 200 Ω, where the on-chip resistor losses are 1.6 dB and 0.42 dB, respectively. As an
example, if the LMH5401-SP were to drive an ADC with a differential input impedance of 100 Ω without any
matching components the signal loss would be 0.83 dB compared to 6 dB in a matched configuration. Of course,
this is only feasible if the LMH5401-SP and the ADC are placed in close proximity (< 1/4 wavelength of the
frequency of interest) so as to avoid standing waves from reflections due to the mismatch in impedances). 图 77
shows the net gain realized by the amplifier for a large range of load resistances when the LMH5401-SP is
configured for 16-dB gain.
7
6
5
4
3
2
1
0
17
16
15
14
13
12
11
10
9
10
100
1k
10k
10
100
1k
10k
External Load (Ω)
External Load (Ω)
C072
C073
图 76. Gain Loss Resulting from On-Chip Output Resistors
图 77. Net Gain versus Load Resistance
10.3 Do's and Don'ts
10.3.1 Do:
•
•
•
•
•
Include a thermal design at the beginning of the project.
Use well-terminated transmission lines for all signals.
Use solid metal layers for the power supplies.
Keep signal lines as straight as possible.
Use split supplies where required.
10.3.2 Don't:
•
•
•
Use a lower supply voltage than necessary.
Use thin metal traces to supply power.
Forget about the common-mode response of filters and transmission lines.
版权 © 2017–2019, Texas Instruments Incorporated
45
LMH5401-SP
ZHCSH86B –DECEMBER 2017–REVISED FEBRUARY 2019
www.ti.com.cn
11 Power Supply Recommendations
The LMH5401-SP can be used with either split or single-ended power supplies. The ideal supply voltage is a
5-V total supply, split around the desired common-mode of the output signal swing. For example, if the
LMH5401-SP is used to drive an ADC with a 1-V input common mode, then the ideal supply voltages are 3.5 V
and –1.5 V. The GND pin can then be connected to the system ground and the PD pin is ground referenced.
11.1 Supply Voltage
Using a 5-V power supply gives the best balance of performance and power dissipation. If power dissipation is a
critical design criteria, a power supply as low as 3.3 V (±1.65) can be used. When using a lower power supply,
the input common-mode and output swing capabilities are drastically reduced. Make sure to study the common-
mode voltages required before deciding on a lower-voltage power supply. In most cases the extra performance
achieved with 5-V supplies is worth the power.
11.2 Single Supply
Single-supply voltages from 3.3 V to 5 V are supported. When using a single supply check both the input and
output common-mode voltages that are required by the system.
11.3 Split Supply
In general, split supplies allow the most flexibility in system design. To operate as split supply, apply the positive
supply voltage to VS+, the negative supply voltage to VS–, and the ground reference to GND. Note that supply
voltages do not need to be symmetrical. Provided the total supply voltage is between 3.3 V and 5.25 V, any
combination of positive and negative supply voltages is acceptable. This feature is often used when the output
common-mode voltage must be set to a particular value. For best performance, the power-supply voltages are
symmetrical around the desired output common-mode voltage. The input common-mode voltage range is much
more flexible than the output.
11.4 Supply Decoupling
Power-supply decoupling is critical to high-frequency performance. Onboard bypass capacitors are used on the
LMH5401-SPEVM; however, the most important component of the supply bypassing is provided by the PCB. As
illustrated in 图 78, there are multiple vias connecting the LMH5401-SP power planes to the power-supply traces.
These vias connect the internal power planes to the LMH5401-SP. Both VS+ and VS– must be connected to the
internal power planes with several square centimeters of continuous plane in the immediate vicinity of the
amplifier. The capacitance between these power planes provides the bulk of the high-frequency bypassing for
the LMH5401-SP.
46
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LMH5401-SP
www.ti.com.cn
ZHCSH86B –DECEMBER 2017–REVISED FEBRUARY 2019
12 Layout
12.1 Layout Guidelines
With a GBP of 6.5 GHz, layout for the LMH5401-SP is critical and nothing can be neglected. In order to simplify
board design, the LMH5401-SP has on-chip resistors that reduce the affect of off-chip capacitance. For this
reason, TI recommends that the ground layer below the LMH5401-SP not be cut. The recommendation not to cut
the ground plane under the amplifier input and output pins is different than many other high-speed amplifiers, but
the reason is that parasitic inductance is more harmful to the LMH5401-SP performance than parasitic
capacitance. By leaving the ground layer under the device intact, parasitic inductance of the output and power
traces is minimized. The DUT portion of the evaluation board layout is illustrated in 图 78.
The EVM uses long-edge capacitors for the decoupling capacitors, which reduces series resistance and
increases the resonant frequency. Vias are also placed to the power planes before the bypass capacitors.
Although not evident in the top layer, two vias are used at the capacitor in addition to the two vias underneath the
device.
The output matching resistors are 0402 size and are placed very close to the amplifier output pins, which
reduces both parasitic inductance and capacitance. The use of 0603 output matching resistors produces a
measurable decrease in bandwidth.
When the signal is on a 50-Ω controlled impedance transmission line, the layout then becomes much less critical.
The transition from the 50-Ω transmission line to the amplifier pins is the most critical area.
The CM pin also requires a bypass capacitor. Place this capacitor near the device. Refer to the user guide
LMH5401EVM-CVAL evaluation module, (SLOU478) for more details on board layout and design.
12.2 Layout Example
图 78. Layout Example
版权 © 2017–2019, Texas Instruments Incorporated
47
LMH5401-SP
ZHCSH86B –DECEMBER 2017–REVISED FEBRUARY 2019
www.ti.com.cn
13 器件和文档支持
13.1 器件支持
13.1.1 器件命名规则
Pin 1
YQ = DIFF DATE
B = DIE REV. '–'FOR NO REV
F = F/E CODE (2 DIGITS MAX)
THA = COUNTRY CODE
Q = QML
YQFB THA
5962–
Q
SRN
1721401VXC
LMH5401
SRN = SERIAL NUMBER
YYWW = SEAL DATE
LL = LOT WINDOW
Z = B/I SPLIT LOT
YYWWLLZ
\T/
\T/ = TI LOGO
图 79. 器件标识信息
13.2 文档支持
13.2.1 相关文档
请参阅如下相关文档：
•
•
•
•
•
ADC12D1x00 12 位、2.0/3.2 GSPS 超高速 ADC，SNAS480
ADC12D1620QMP-SP 12 位单通道或双通道 3200MSPS 或 1600MSPS 射频取样 ADC，SNAS717
抗辐射 V 类宽带全差分放大器，SLOS538
抗辐射 V 类宽带全差分放大器，SLOS539
LMH5401-SP TINA 模型
13.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
48
版权 © 2017–2019, Texas Instruments Incorporated
LMH5401-SP
www.ti.com.cn
ZHCSH86B –DECEMBER 2017–REVISED FEBRUARY 2019
13.5 商标
E2E is a trademark of Texas Instruments.
Marki is a trademark of Marki Microwave, Inc.
Rohde & Schwarz is a registered trademark of Rohde & Schwarz.
All other trademarks are the property of their respective owners.
13.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。
版权 © 2017–2019, Texas Instruments Incorporated
49
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2022
PACKAGING INFORMATION
Orderable Device
5962-1721401VXC
5962R1721401VXC
LMH5401FFK/EM
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
-55 to 125
-55 to 125
25 to 25
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ACTIVE
LCCC
LCCC
LCCC
FFK
14
14
14
1
RoHS-Exempt
& Green
Call TI
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
5962-
Samples
Samples
Samples
1721401VXC
LMH5401
ACTIVE
ACTIVE
FFK
FFK
1
1
RoHS-Exempt
& Green
Call TI
Call TI
5962R
1721401VXC
LMH5401
RoHS-Exempt
& Green
LMH5401FFK
/EM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LMH5401-SP :
Catalog : LMH5401
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
5962-1721401VXC
5962R1721401VXC
LMH5401FFK/EM
FFK
FFK
FFK
LCCC
LCCC
LCCC
14
14
14
1
1
1
506.98
506.98
506.98
26.16
26.16
26.16
6220
6220
6220
NA
NA
NA
Pack Materials-Page 1
PACKAGE OUTLINE
FFK0014A
LCCC - 1.87 mm max height
S
C
A
L
E
2
.
2
0
0
LEADLESS CERAMIC CHIP CARRIER
6.25
5.75
4X (R0.15)
4.75
4.25
5.75
5.25
(R0.4) TYP
5.25
4.75
(0.364)
1.87 MAX
(0.6) TYP
NOTE 3
TYP
3
0.2
8X
(R0.15) TYP
(45 X0.4)
4
7
NOTE 3
TYP
(0.15) TYP
10X 1.27 0.1
3
1
8
15
2X
2.54 0.1
2.5 0.2
10
PIN 1 ID
(45 X0.4)
14
11
14X 1.1 0.12
14X 0.64 0.07
2X 3.81 0.1
4223813/B 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The terminals are gold-plated.
www.ti.com
EXAMPLE BOARD LAYOUT
FFK0014A
LCCC - 1.87 mm max height
LEADLESS CERAMIC CHIP CARRIER
(3)
SYMM
14X (0.64)
11
14
(
0.2) TYP VIA
1
10
8X (45 X0.4)
10X (1.27)
15
(4.95)
SYMM
(2.5)
(1)
14X (1.65)
3
8
(R0.05) TYP
4
7
(1.25)
(5.45)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 14X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED
METAL
METAL UNDER
SOLDER MASK
METAL
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4223813/B 04/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
FFK0014A
LCCC - 1.87 mm max height
LEADLESS CERAMIC CHIP CARRIER
14X (1.65)
11
14X (0.64)
SYMM
14
1
15
10
8X (45 X0.4)
10X (1.27)
SYMM
(4.95)
(0.65)
TYP
4X (1.1)
3
8
(R0.05) TYP
4
7
(0.75) TYP
4X (1.3)
(5.45)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 15:
76% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE: 14X
4223813/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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