LMH5485-SP [TI]
Radiation-hardness-assured (RHA) 850-MHz fully differential amplifier;
| 型号： | LMH5485-SP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Radiation-hardness-assured (RHA) 850-MHz fully differential amplifier |
| 文件： | 总34页 (文件大小：2050K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMH5485-SP
ZHCSLH1A –SEPTEMBER 2021 –REVISED DECEMBER 2021
LMH5485-SP 耐Hardened 辐射(RHA) 型负轨输入、轨至轨输出高精度850MHz
全差分放大器
1 特性
3 说明
• 已通过QMLV（QML V 级）MIL-PRF-38535 认
证，SMD 5962R1920401VXC
LMH5485-SP 是一款辐射、低功耗、电压反馈、全差
分放大器 (FDA)，输入共模范围低于负电源轨和轨至轨
输出。专为功耗敏感型数据采集系统而设计，在这些系
统中，高密度对于高性能模数转换器 (ADC) 或数模转
换器(DAC) 接口设计至关重要。
– 辐射加固保障(RHA) 能力高达100krad (Si) 总
电离剂量(TID)
– 单粒子闩锁(SEL) 对于LET 的
抗扰度= 85MeV-cm2/mg
LMH5485-SP 具有所需的负电源轨输入，可用于连接
直流耦合、以接地为中心的源信号。此负电源轨输入搭
配轨至轨输出，只需使用一个 2.7V 至 5.1V 的电源，
即可轻松将单端接地基准双极信号源与各种逐次逼近寄
存器 (SAR) 、Δ-Σ 或流水线 ADC 相连接。
LMH5485-SP 还为此类 ADC 驱动应用提供出色的直流
精度，并可在 –55°C 至 +125°C 的宽温度范围内运
行。
– 支持军用级温度范围：..-55°C 至125°C
• 全差分放大器(FDA) 架构
• 带宽：490MHz (G = 2V/V)
• 增益带宽积（GBWP）：850MHz
• 压摆率：1400V/µs
• HD2、HD3：–79dBc、–97dBc（10MHz、2
VPP
）
• 输入电压噪声：2.4nV/√Hz (f > 100kHz)
• 输入失调电压、温漂：±100µV、±0.5µV/°C
• 负轨输入(NRI)、轨到轨输出(RRO)
• 输出共模控制
器件信息
器件型号(1)
等级
耐辐射加固保障(RHA)
QMLV
封装
陶瓷CFP
HKX (8)
6.5mm × 6.5mm
5962R1920401VXC
5962-1920401VXC
LMH5485HKX/EM
• 电源：
工程样片(2)
– 电源电压范围：2.7V 至5.1V
– 静态电流：10.1mA（5V 电源）
– 断电能力：2µA（典型值）
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
(2) 这些器件仅适用于工程评估。器件按照不合规的流程进行加工
处理。这些器件不适用于质检、生产、辐射测试或飞行。这些
零器件无法在–55°C 至125°C 的完整MIL 额定温度范围内或
运行寿命中保证其性能。
2 应用
• 低功耗高性能ADC 驱动器：
– SAR、ΔΣ和流水线
• 差分DAC 输出驱动器
• 命令和数据处理
• 运载火箭系统
• 空间成像系统：
– 光学成像有效载荷
– 雷达成像有效载荷
– 热成像摄像机
LMH5485 Wideband,
Fully-Differential Amplifier
50- Input Match,
Gain of 2 V/V from Rt,
Single-Ended Source to
Differential Output
Rf1
402
C1
100 nF
Vcc
Rg1
191
50-
Source
–
Output
Measurement
Point
+
Rload
500
Rt
60.2
Vocm
FDA
–
+
PD
Rg2
221
Vcc
C2
100 nF
Rf2
402
简化版原理图
单端到差分增益为2 的100mVPP 输出
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOSA33
LMH5485-SP
ZHCSLH1A –SEPTEMBER 2021 –REVISED DECEMBER 2021
www.ti.com.cn
Table of Contents
9 Detailed Description......................................................18
9.1 Overview...................................................................18
9.2 Functional Block Diagram.........................................20
9.3 Feature Description...................................................20
9.4 Device Functional Modes..........................................21
10 Power Supply Recommendations..............................29
11 Layout...........................................................................29
11.1 Layout Guidelines................................................... 29
12 Device and Documentation Support..........................30
12.1 Documentation Support.......................................... 30
12.2 Receiving Notification of Documentation Updates..30
12.3 支持资源..................................................................30
12.4 Trademarks.............................................................30
12.5 Electrostatic Discharge Caution..............................30
12.6 术语表..................................................................... 30
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................4
7.5 Electrical Characteristics: VS+ –VS– = 5 V...............5
7.6 Electrical Characteristics: VS+ –VS– = 3 V...............8
7.7 Quality Conformance Inspection...............................10
7.8 Typical Characteristics: 5 V Single Supply................11
7.9 Typical Characteristics: 3 V Single Supply................12
7.10 Typical Characteristics: 3 V to 5 V Supply Range...13
8 Parameter Measurement Information..........................16
8.1 Example Characterization Circuits............................16
Information.................................................................... 30
13.1 Tube Information.....................................................32
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (September 2021) to Revision A (December 2021)
Page
• Added clarifying text to note 1 in Pin Functions table.........................................................................................3
• Changed 0.9 V to 0.91 V in second paragraph of 节9.1 section......................................................................18
• Changed 0.9 V to 0.91 V in first paragraph of 节9.4.1.1 section..................................................................... 22
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5 Device Comparison Table
INPUT NOISE
(nV/√Hz)
GBWP
(MHz)
IQ
(mA)
HD2 / HD3 (dBc)
2 VPP AT 10 MHz
DEVICE
RAD TOLERANCE
RAIL-TO-RAIL
100 kRad TID
30 kRad TID
150 kRad TID
100 kRad TID
LMH5485-SP
LMH5485-SEP
THS4513-SP
LMH5401-SP
850
850
10.1
10.1
37.7
60
2.4
2.4
NRI/Out
NRI/Out
No
–79 / –97
–90 / –102
–106 / –108
–99 / –100
3000
6500
2.2
1.25
No
6 Pin Configuration and Functions
OUT–
Vs–
1
2
3
4
8
7
6
5
OUT+
Vs+
PD
Vocm
IN–
IN+
图6-1. Top View
HKX Package
8-Pin CFP
表6-1. Pin Functions
PIN
NAME
IN+
NO.
4
TYPE(1)
DESCRIPTION
I
I
Noninverting (positive) amplifier input
Inverting (negative) amplifier input
Noninverted (positive) amplifier output
Inverted (negative) amplifier output
5
IN–
OUT+
OUT–
PD
8
O
O
I
1
3
Power down. PD = logic low = power off mode; PD = logic high = normal operation.
Common-mode voltage input
Vocm
Vs+
6
I
7
P
P
Positive power-supply input
2
Negative power-supply input
Vs–
(1) I = input, O = output, P = power
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
5.25
UNIT
V
Supply voltage, (Vs+) –Vs–
Voltage
Input-output voltage range
Differential input voltage
Continuous input current
Continuous output current
(Vs+) + 0.5
±1
V
(Vs–) –0.5
V
±20
mA
mA
±80
Current
See Thermal Information table and Thermal Analysis
Continuous power dissipation
section
Maximum junction temperature
Operating free-air temperature range
Storage temperature, Tstg
150
125
150
°C
°C
°C
Temperature
–55
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
7.2 ESD Ratings
VALUE
TBD
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
TBD
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
NOM
5
MAX
5.1
UNIT
Vs+
TA
Single-supply voltage
Ambient temperature
V
25
125
°C
–55
7.4 Thermal Information
LMH5485-SP
HKX (CFP)
8 PINS
145.7
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
67.6
128.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
61.1
ψJT
122.1
ψJB
RθJC(bot)
55.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics: VS+ –VS– = 5 V
The specifications shown below correspond to the respectively identified subgroup temperature (see 节7.7), unless
otherwise noted. VOCM = open (defaults midsupply), VOUT = 2 VPP, Rf = 402 Ω, Rload = 499 Ω, 50-Ωinput match, G = 2
V/V, single-ended input, differential output, and PD = +Vs, unless otherwise noted. See 图8-1 for an AC-coupled gain of a
2-V/V test circuit, and 图8-3 for a DC-coupled gain of a 2-V/V test circuit.
PARAMETER
TEST CONDITIONS
SUBGROUP(1)
MIN
TYP
MAX UNIT
AC PERFORMANCE
Small-signal bandwidth
Small-signal bandwidth
Small-signal bandwidth
Small-signal bandwidth
GBWP Gain-bandwidth product
Large-signal bandwidth
Bandwidth for 0.1-dB flatness
Slew rate(2)
Vout = 100 mVPP, G = 1
Vout = 100 mVPP, G = 2
Vout = 100 mVPP, G = 5
Vout = 100 mVPP, G = 10
Vout = 100 mVPP, G = 20
Vout = 2 VPP
530
490
240
125
850
315
50
MHz
MHz
MHz
MHz
MHz
MHz
MHz
V/µs
ns
Vout = 2 VPP
Vout = 2-VPP, FPBW
Vout = 2-V step, input ≤0.5 ns tr
1400
1.4
Rise/fall time
To 1%
5.4
ns
Vout = 2-V step,
tr = 2 ns
Settling time
To 0.1%
10
ns
Overshoot and undershoot
100-kHz harmonic distortion
24%
Vout = 2-V step, input ≤0.3 ns tr
HD2
Vout = 2 VPP
HD3
dBc
dBc
dBc
dBc
–111
–149
–79
HD2
Vout = 2 VPP
HD3
10-MHz harmonic distortion
–97
2nd-order intermodulation
distortion
dBc
dBc
–90
–85
2.4
f = 10 MHz, 100-kHz tone
spacing, Vout envelope = 2 VPP
(1 VPP per tone)
3rd-order intermodulation
distortion
nV/√
Hz
Input voltage noise
Input current noise
Overdrive recovery time
f > 100 kHz
f > 1 MHz
pA/√
Hz
1.9
2x output overdrive, either
polarity
20
ns
Closed-loop output impedance f = 10 MHz (differential)
DC PERFORMANCE
0.1
Ω
AOL
Open-loop voltage gain
Input-referred offset voltage
Input offset voltage drift(3)
Input bias current
[1, 2, 3]
[1, 2, 3]
97
–900
–2.5
1.7
119
±100
±0.5
10
dB
900
2.5 µV/°C
15 µA
15 nA/°C
µV
Positive out of node
[1, 2, 3]
[1, 2, 3]
Input bias current drift(3)
6
Input offset current
±150
±0.3
650
nA
–650
–1.5
Input offset current drift(3)
1.5 nA/°C
INPUT
< 3-dB degradation in CMRR
from midsupply
(Vs–) –
Common-mode input low
Common-mode input high
[1, 2, 3]
V
Vs–
0.2
< 3-dB degradation in CMRR
from midsupply
(Vs+) –
[1, 2, 3]
[1, 2, 3]
V
(Vs+) –1.2
1.3
Common-mode rejection ratio Input pins at midsupply
82
100
dB
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7.5 Electrical Characteristics: VS+ –VS– = 5 V (continued)
The specifications shown below correspond to the respectively identified subgroup temperature (see 节7.7), unless
otherwise noted. VOCM = open (defaults midsupply), VOUT = 2 VPP, Rf = 402 Ω, Rload = 499 Ω, 50-Ωinput match, G = 2
V/V, single-ended input, differential output, and PD = +Vs, unless otherwise noted. See 图8-1 for an AC-coupled gain of a
2-V/V test circuit, and 图8-3 for a DC-coupled gain of a 2-V/V test circuit.
PARAMETER
TEST CONDITIONS
SUBGROUP(1)
MIN
TYP
MAX UNIT
Input impedance differential
mode
kΩ||
pF
Input pins at midsupply
110 || 1.25
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7.5 Electrical Characteristics: VS+ –VS– = 5 V (continued)
The specifications shown below correspond to the respectively identified subgroup temperature (see 节7.7), unless
otherwise noted. VOCM = open (defaults midsupply), VOUT = 2 VPP, Rf = 402 Ω, Rload = 499 Ω, 50-Ωinput match, G = 2
V/V, single-ended input, differential output, and PD = +Vs, unless otherwise noted. See 图8-1 for an AC-coupled gain of a
2-V/V test circuit, and 图8-3 for a DC-coupled gain of a 2-V/V test circuit.
PARAMETER
TEST CONDITIONS
SUBGROUP(1)
MIN
TYP
MAX UNIT
OUTPUT
(Vs–) +
(Vs–) +
Output voltage low
[1, 2, 3]
V
0.2
0.25
(Vs+) –
(Vs+) –
Output voltage high
Output current drive
[1, 2, 3]
[1, 2, 3]
V
0.25
0.2
±75
±100
mA
POWER SUPPLY
Specified operating voltage
[1, 2, 3]
[1, 2, 3]
2.7
9.2
5
5.1
11
V
Quiescent operating current
±PSRR Power-supply rejection ratio
POWER DOWN
10.1
mA
Either supply pin to differential
Vout
[1, 2, 3]
82
100
dB
(Vs–) +
Enable voltage threshold
[1, 2, 3]
[1, 2, 3]
V
V
1.7
(Vs–) +
Disable voltage threshold
Disable pin bias current
0.7
[1, 2, 3]
[1, 2, 3]
[1, 2, 3]
20
6
50
30
8
nA
µA
µA
PD = Vs–→Vs+
PD = (Vs–) + 0.7 V
PD = Vs–
Power-down quiescent current
2
Time from PD = low to
Vout = 90% of final value
Turnon-time delay
Turnoff time delay
100
60
ns
ns
Time from PD = low to
Vout = 10% of final value
OUTPUT COMMON-MODE VOLTAGE CONTROL(4)
Small-signal bandwidth
Slew rate(2)
Vocm = 100 mVPP
Vocm = 2-V step
150
400
MHz
V/µs
Gain
[1, 2, 3]
0.975
0.982
0.1
0.995 V/V
Input bias current
Considered positive out of node [1, 2, 3]
Vocm input driven to midsupply
0.8
µA
–0.8
kΩ||
pF
Input impedance
47 || 1.2
±8
Default voltage offset from
midsupply
Vocm pin open
[1, 2, 3]
[1, 2, 3]
45
8
mV
mV
–45
CM Vos Common-mode offset voltage Vocm input driven to midsupply
±2
±4
–8
CM VOS drift(3)
Vocm input driven to midsupply
+20 mV/°C
V
–20
Common-mode loop supply
headroom to negative supply
< ±15-mV shift from midsupply
CM Vos
[1, 2, 3]
[1, 2, 3]
0.94
1.2
Common-mode loop supply
headroom to positive supply
< ±15-mV shift from midsupply
CM Vos
V
(1) For subgroup definitions, please see 节7.7
(2) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (VP / √2) · 2π· f–3dB
.
(3) Input offset voltage drift, input bias current drift, input offset current drift, and Vocm drift are average values calculated by taking data at
the at the maximum-range ambient-temperature end-points, computing the difference, and dividing by the temperature range.
(4) Specifications are from the input Vocm pin to the differential output average voltage.
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7.6 Electrical Characteristics: VS+ –VS– = 3 V
The specifications shown below correspond to the respectively identified subgroup temperature (see 节7.7), unless
otherwise noted. Vocm = open (defaults midsupply), VOUT = 2 VPP, Rf = 402 Ω, Rload = 499 Ω, 50-Ωinput match, G = 2
V/V, single-ended input, differential output, and PD = +Vs, unless otherwise noted. See 图8-1 for an AC-coupled gain of a
2-V/V test circuit, and 图8-3 for a DC-coupled gain of a 2-V/V test circuit.
PARAMETER
TEST CONDITIONS
SUBGROUP(1)
MIN
TYP
MAX UNIT
AC PERFORMANCE
Vout = 100 mVPP, G = 1
Vout = 100 mVPP, G = 2
Vout = 100 mVPP, G = 5
Vout = 100 mVPP, G = 20
Vout = 2 VPP
510
475
240
850
300
50
MHz
MHz
MHz
MHz
MHz
MHz
V/µs
ns
Small-signal bandwidth
GBWP Gain-bandwidth product
Large-signal bandwidth
Bandwidth for 0.1-dB flatness
Slew rate(2)
Vout = 2 VPP
Vout = 2-V step, FPBW
Vout = 2-V step, input ≤0.5 ns tr
1200
1.6
5
Rise/fall time
To 1%
ns
Vout = 2-V step,
tr = 2 ns
Settling time
To 0.1%
9
ns
Overshoot and undershoot
100-kHz harmonic distortion
25%
Vout = 2-V step, input ≤0.3 ns tr
HD2
Vout = 2 VPP
HD3
dBc
dBc
dBc
dBc
–111
–150
–80
HD2
Vout = 2 VPP
HD3
10-MHz harmonic distortion
–96
2nd-order intermodulation
distortion
dBc
dBc
–89
–87
2.4
f = 10 MHz, 100-kHz tone
spacing, Vout envelope = 2 VPP
(1 VPP per tone)
3rd-order intermodulation
distortion
nV/√
Hz
Input voltage noise
Input current noise
Overdrive recovery time
f > 100 kHz
f > 1 MHz
pA/√
Hz
1.9
2X output overdrive, either
polarity
20
ns
Closed-loop output impedance f = 10 MHz (differential)
DC PERFORMANCE
0.1
Ω
AOL
Open-loop voltage gain
Input-referred offset voltage
Input offset voltage drift(3)
Input bias current
[1, 2, 3]
[1, 2, 3]
97
–900
–2.5
1.7
119
±100
±0.5
9
dB
900
2.5 µV/°C
15 µA
15 nA/°C
µV
Positive out of node
[1, 2, 3]
[1, 2, 3]
Input bias current drift(3)
5
Input offset current
±150
±0.3
650
nA
–650
–1.5
Input offset current drift(3)
1.5 nA/°C
INPUT
< 3-dB degradation in CMRR
from midsupply
(Vs–) –
Common-mode input low
Common-mode input high
[1, 2, 3]
V
Vs–
0.2
< 3-dB degradation in CMRR
from midsupply
(Vs+) –
[1, 2, 3]
[1, 2, 3]
V
(Vs+) –1.2
100
1.3
Common-mode rejection ratio Input pins at midsupply
82
dB
Input impedance differential
Input pins at midsupply
mode
kΩ||
pF
110 || 1.25
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7.6 Electrical Characteristics: VS+ –VS– = 3 V (continued)
The specifications shown below correspond to the respectively identified subgroup temperature (see 节7.7), unless
otherwise noted. Vocm = open (defaults midsupply), VOUT = 2 VPP, Rf = 402 Ω, Rload = 499 Ω, 50-Ωinput match, G = 2
V/V, single-ended input, differential output, and PD = +Vs, unless otherwise noted. See 图8-1 for an AC-coupled gain of a
2-V/V test circuit, and 图8-3 for a DC-coupled gain of a 2-V/V test circuit.
PARAMETER
TEST CONDITIONS
SUBGROUP(1)
MIN
TYP
MAX UNIT
OUTPUT
(Vs–) +
(Vs–) +
Output voltage low
[1, 2, 3]
V
0.2
0.25
(Vs+) –
(Vs+) –
Output voltage high
Output current drive
[1, 2, 3]
[1, 2, 3]
V
0.25
0.2
±55
±60
mA
POWER SUPPLY
Specified operating voltage
[1, 2, 3]
[1, 2, 3]
2.7
9
3
5.1
V
Quiescent operating current
±PSRR Power-supply rejection ratio
POWER DOWN
9.7
10.6
mA
Either supply pin to differential
Vout
[1, 2, 3]
82
100
dB
(Vs–) +
Enable voltage threshold
[1, 2, 3]
[1, 2, 3]
V
V
1.7
(Vs–) +
Disable voltage threshold
Disable pin bias current
0.7
[1, 2, 3]
[1, 2, 3]
[1, 2, 3]
20
2
50
30
8
nA
µA
µA
PD = Vs–→Vs+
PD = (Vs–) + 0.7 V
PD = Vs–
Power-down quiescent current
1
Time from PD = low to
Vout = 90% of final value
Turnon-time delay
Turnoff time delay
100
60
ns
ns
Time from PD = low to
Vout = 10% of final value
OUTPUT COMMON-MODE VOLTAGE CONTROL(4)
Small-signal bandwidth
Slew rate(2)
Vocm = 100 mVPP
Vocm = 1-V step
140
350
MHz
V/µs
Gain
[1, 2, 3]
0.975
0.987
0.1
0.990 V/V
Input bias current
Considered positive out of node [1, 2, 3]
Vocm input driven to midsupply
0.7
µA
–0.7
kΩ||
pF
Input impedance
47 || 1.2
±10
Default voltage offset from
midsupply
Vocm pin open
[1, 2, 3]
[1, 2, 3]
45
8
mV
mV
–45
CM Vos Common-mode offset voltage Vocm input driven to midsupply
±2
±4
–8
CM VOS drift(3)
Vocm input driven to midsupply
20 mV/°C
V
–20
Common-mode loop supply
headroom to negative supply
< ±15-mV shift from midsupply
CM Vos
[1, 2, 3]
[1, 2, 3]
0.94
1.2
Common-mode loop supply
headroom to positive supply
< ±15-mV shift from midsupply
CM Vos
V
(1) For subgroup definitions, please see 节7.7
(2) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (VP / √2) · 2π· f–3dB
.
(3) Input offset voltage drift, input bias current drift, input offset current drift, and Vocm drift are average values calculated by taking data at
the at the maximum-range ambient-temperature end-points, computing the difference, and dividing by the temperature range.
Maximum drift set by distribution of a large sampling of devices. Drift is not specified by test or QA sample test.
(4) Specifications are from input Vocm pin to differential output average voltage.
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7.7 Quality Conformance Inspection
SUBGROUP
DESCRIPTION
TEMPERATURE (℃)
1
2
3
4
5
6
7
Static tests at
25
Static tests at
125
–55
25
Static tests at
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
125
–55
25
8A
8B
125
–55
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7.8 Typical Characteristics: 5 V Single Supply
at Vs+ = 5 V, Vs– = GND, RF= 402 Ω, Vocm is open, 50 Ω single-ended input to differential output, gain = 2 V/V, Rload =
500 Ω, and TA ≈25°C (unless otherwise noted)
3
0
-3
-6
-9
10
100
1000
Frequency (MHz)
Vo = 100 mVpp, see 图8-1 and 表9-1 for resistor values
图7-1. Small-Signal Frequency Response vs Gain
VO = 2 Vpp, see 图8-1 and 表9-1 for resistor values
.
图7-2. Large-Signal Frequency Response
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
0
2
4
6
8
10 12 14 16 18 20 22 24
Time (ns)
2 VPP output, see 图8-1
50 MHz input, 0.5-ns input edge rate, single-ended to
.
differential output, split supply, DC-coupled, see 图8-3
图7-4. Harmonic Distortion Over Frequency
图7-3. Large-Signal Step Response
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7.9 Typical Characteristics: 3 V Single Supply
at Vs+ = 3 V, Vs–= GND, Vocm is open, 50 Ωsingle-ended input to differential output, gain = 2 V/V, Rload = 500 Ω, and TA
≈25°C (unless otherwise noted)
6
3
G=1
G=2
G=5
3
0
0
-3
-6
-9
-3
-6
-9
10
20 30 40 50 70 100
200 300 500 7001000
10
100
1000
Frequency (MHz)
Frequency (MHz)
Rf = 402 Ω, Vout = 100 mVPP, see 图8-1 and 表9-1 for
Rf = 402 Ω, Vout = 2 VPP, see 图8-1 and 表9-1 for resistor
resistor values
values
图7-5. Small-Signal Frequency Response vs Gain
图7-6. Large-Signal Frequency Response
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
0
2
4
6
8
10 12 14 16 18 20 22 24
Time (ns)
2 VPP output, see 图8-1 with Vs+ = 3 V, Vocm = 1.5 V
50 MHz input, 0.5-ns input edge rate, single-ended input to
.
differential output, split supply, DC coupled, see 图8-3
图7-8. Harmonic Distortion Over Frequency
图7-7. Large-Signal Step Response
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7.10 Typical Characteristics: 3 V to 5 V Supply Range
at Vs+ = 3 V and 5 V, Vs–= GND, Vocm is open, 50 Ωsingle-ended input to differential output, gain = 2 V/V, Rload = 500
Ω, and TA ≈25°C (unless otherwise noted)
10
Gain=2, +3 V
Gain=2, +5 V
Gain=5, +3 V
1
Gain=5, +5 V
0.1
0.01
0.001
0.0001
1k
10k
100k 1M
Frequency (Hz)
10M
100M
D038
.
.
Single-ended input to differential output, simulated differential
output impedance, see 图8-1
图7-9. Main Amplifier Differential Open-Loop Gain and Phase
图7-10. Closed-Loop Output Impedance
vs Frequency
50
-50
+5 V EN
+5 V IN
+3 V EN
+3 V IN
+3 V supply
+5 V supply
-55
-60
-65
-70
-75
-80
10
1
1k
10k
100k
Frequency (Hz)
1M
10M
1k
10k
100k 1M
Frequency (Hz)
10M
100M
.
.
D040
Single-ended input to differential output, gain of 2 (see 图8-1),
simulated with 1% resistor, worst-case mismatch
图7-11. Input Spot Noise Over Frequency
图7-12. Output Balance Error Over Frequency
110
100
90
90
+3 V +Vs
+5 V +Vs
+3 V -Vs
+5 V -Vs
85
80
75
70
65
60
55
50
45
40
80
70
60
50
1k
10k
100k 1M
Frequency (Hz)
10M
100M
10k
100k
1M
Frequency (Hz)
10M
100M
D041
D042
Common-mode in to differential out, gain of 2 simulation
.
Single-ended to differential, gain of 2 (see 图8-1) PSRR
simulated to differential output
图7-13. CMRR Over Frequency
图7-14. PSRR Over Frequency
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7.10 Typical Characteristics: 3 V to 5 V Supply Range (continued)
at Vs+ = 3 V and 5 V, Vs–= GND, Vocm is open, 50 Ωsingle-ended input to differential output, gain = 2 V/V, Rload = 500
Ω, and TA ≈25°C (unless otherwise noted)
1000
100
10
10
8
+5 V Vocm driven
+5 V Vocm floating
+3 V Vocm driven
+3 V Vocm floating
+5 V supply
+3 V supply
6
4
2
0
-2
-4
-6
-8
-10
1
100
1k
10k 100k
Frequency (Hz)
1M
10M
0.8
1.2
1.6
2
2.4
2.8
Vocm Input Voltage (V)
3.2
3.6
4
D045
D046
Vocm input either driven to mid-supply by low impedance
source, or allowed to float and default to mid-supply
Average Vocm output offset of 37 units, Standard deviation
< 2.5 mV, see 图8-3
图7-15. Output Common-Mode Noise
图7-16. Vocm Offset vs Vocm Setting
100
100
+3 V supply
+5 V supply
95
95
90
85
80
90
85
80
75
70
75
+3 V supply
+5 V supply
70
0.85
0.85
1.35
1.85
2.35
Vocm (V)
2.85
3.35
3.85
1.35
1.85
2.35
Vocm (V)
2.85
3.35 3.85
D047
D048
Single-ended to differential gain of 2 (see 图8-1), PSRR for
Single-ended to differential gain of 2 (see 图8-1), PSRR for
negative supply to differential output (1-kHz simulation)
positive supply to differential output (1-kHz simulation)
图7-17. –PSRR vs Vocm Approaching Vs–
图7-18. +PSRR vs Vocm Approaching Vs+
1400
+5 V Supply
+3 V Supply
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
Input Offset Current (nA)
Total of 4618 units for each supply. For Vs = 5 V: μ= -35.1
μV, σ= 38.9 μV
Total of 4618 units for each supply. For Vs = 5 V: μ= 16.7 nA,
σ= 62.3 nA
图7-19. Input Offset Voltage
图7-20. Input Offset Current
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7.10 Typical Characteristics: 3 V to 5 V Supply Range (continued)
at Vs+ = 3 V and 5 V, Vs–= GND, Vocm is open, 50 Ωsingle-ended input to differential output, gain = 2 V/V, Rload = 500
Ω, and TA ≈25°C (unless otherwise noted)
10
9
8
7
6
5
4
3
2
1
0
11
10.5
10
9.5
9
5 V supply
3 V supply
5 V supply
3 V supply
8.5
8
7.5
7
10
100
Differential Load (W)
1000
0
1
2
3
Disable Pin Voltage (PD) Volts
4
5
D055
D056
Maximum differential output swing, Vocm at mid-supply
.
图7-21. Maximum Vopp vs Rload
图7-22. Supply Current vs PD Voltage
2500
1600
+5 V Supply
+3 V Supply
+5 V Supply
+3 V Supply
2250
2000
1750
1500
1250
1000
750
1400
1200
1000
800
600
400
200
0
500
250
0
Vocm Offset Voltage (mV)
Vocm Offset Voltage (mV)
Vocm input floating. Total of 4618 units for each supply.
Total of 4618 units for each supply. For Vs = 5 V: μ= 0.3 mV,
For Vs = 5 V: μ= 6.8 mV, σ= 3.9 mV
σ= 1.3 mV
.
图7-23. Common-Mode Output Offset from Vs+ / 2 Default Value
图7-24. Common-Mode Output Offset from Driven Vocm
5
5
PD 3 V
Out 3 V
Out 5 V
PD 5 V
PD 3 V
4
4
3
PD 5 V
3
2
1
3-V Supply
2
1
5-V Supply
0
-1
-2
0
-1
-2
0.04
0.06
0.08
0.1
Time (µs)
0.12
0.14
0.16
0.18
0.28
0.3
0.32
Time (µs)
0.34
0.36
D059
D060
10 MHz, 1 Vpp input single to differential gain of 2,
10 MHz, 1 VPP input single to differential gain of 2,
see 图8-3
see 图8-3
图7-25. PD Turn On Waveform
图7-26. PD Turn Off Waveform
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8 Parameter Measurement Information
8.1 Example Characterization Circuits
The LMH5485-SP offers the advantages of a fully differential amplifier (FDA) design, with the trimmed input
offset voltage of a precision op amp. The FDA is an extremely flexible device that provides a purely differential
output signal centered on a settable output common-mode level. The primary options revolve around the choices
of single-ended or differential inputs, AC-coupled or DC-coupled signal paths, gain targets, and resistor Value
selections. Differential sources can certainly be supported and are often simpler to both implement and analyze.
Because most lab equipment is single-ended, the characterization circuits typically operate with a single-ended,
matched, 50 Ω input termination to a differential output at the FDA output pins. That output is then translated
back to single-ended through a variety of baluns (or transformers) depending on the test and frequency range.
DC-coupled, step-response testing uses two 50 Ω scope inputs with trace math. The starting point for any
single-ended-to-differential, AC-coupled characterization plot is shown in 图8-1.
LMH5485 Wideband,
Fully-Differential Amplifier
50- Input Match,
Gain of 2 V/V from Rt,
Single-Ended Source to
Differential Output
Rf1
402
C1
100 nF
Vcc
Rg1
191
50-
Source
–
Output
Measurement
Point
+
Rload
500
Rt
60.2
Vocm
FDA
–
+
PD
Rg2
221
Vcc
C2
100 nF
Rf2
402
图8-1. AC-Coupled, Single-Ended Source to a Differential Gain of a 2 V/V Test Circuit
图 8-1 shows how most characterization plots fix the Rf (Rf1 = Rf2) value at 402 Ω. This element value is
completely flexible in application, but the 402 Ω provides a good compromise for the parasitic issues linked to
this value, specifically:
• Added output loading. The FDA appears like an inverting op amp design with both feedback resistors as an
added load across the outputs (approximate total differential load in 图8-1 is 500 Ω|| 804 Ω= 308 Ω).
• Noise contributions because of the resistor values. The resistors contribute both a 4kTR term and provide
gain for the input current noise.
• Parasitic feedback pole at the input summing nodes. This pole created by the feedback R value and the
1.25-pF 0.9-pF differential input capacitance (as well as any board layout parasitic) introduces a zero in the
noise gain, decreasing the phase margin in most situations. This effect must be managed for best frequency
response flatness or step response overshoot. The 402 Ωvalue selected does degrade the phase margin
slightly over a lower value, but does not decrease the loading significantly from the nominal 500 Ωvalue
across the output pins.
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The frequency domain characterization curves start with the selections of 图 8-1. Then, various elements are
modified to show their impact over a range of design targets, specifically:
• Gain setting is changed by adjusting Rt and the 2 –Rg elements (holding a 50 Ωinput match).
• Output loading, including both resistive and capacitive load testing.
• Power-supply settings. Most often, a single +5 V test uses a ±2.5 V supply, and a +3 V test uses ±1.5 V
supplies.
• The disable control pin is tied to Vs+ for any active channel test.
Because most network and spectrum analyzers are a single-ended input, the output network on the LMH5485-
SP characterization tests typically show the desired load connected through a balun to a single-ended, 50 Ω
load, while presenting a 50 Ω source from the balun output back into the balun. For instance, 图 8-2 shows a
wideband MA/Com balun used for 图 8-1. This network shows a 500 Ωdifferential load to the LMH5485-SP, but
an AC-coupled, 50 Ω source to the network analyzer. Distortion testing typically uses a lower-frequency, DC-
isolated balun (such as the TT1-6T) that is rotated 90° from the wider band interface of 图8-2.
C10
100 nF
Ro1
237
ETC1-1-13
50- Load
N1
500-
Differential
Load
LMH5485
Output
R9
56.2
Ro2
237
N2
C9
100 nF
图8-2. Example 500 ΩLoad to a Single-Ended, Doubly-Terminated, AC-Coupled, 50 ΩInterface
This approach allows a higher differential load, but with a wideband 50 Ω output match at the cost of
considerable signal-path insertion loss. This loss is acceptable for characterization, and is normalized out to
show the characterization curves.
图8-3 shows the circuit used as a starting point for time-domain or DC-coupled testing.
LMH5485 Wideband,
Fully-Differential Amplifier
50- Input Match,
Gain of 5 V/V from Rt,
Single-Ended Source to
Rf1
402
Differential Step-Response Test
Vcc
Rg1
68.1
50-
–
Source
Output
Measurement
Point
+
–
R1
500
Rt
80.6
Vocm
FDA
+
PD
Rg2
100
Vcc
Rf2
402
图8-3. DC-Coupled, Single-Ended-to-Differential, Basic Test Circuit Set for a Gain of 5 V/V
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In this case, the input is DC-coupled, showing a 50 Ω input match to the source, gain of 5 V/V to a differential
output, again driving a nominal 500 Ω load. Using a single supply, the Vocm control input can either be floated
(defaulting to mid-supply) or be driven within the allowed range for the Vocm loop (see the headroom limits on
Vocm in the Electrical Characteristics: VS+ −VS = 5 V tables). To use this circuit for step-response
measurements, load each of the two outputs with a 250 Ω network, translating to a 50 Ω source impedance
driving into two 50 Ω scope inputs. Then, difference the scope inputs to generate the step responses. 图 8-4
shows the output interface circuit. This grounded interface pulls a DC load current from the output Vocm voltage
for single-supply operation. Running this test with balanced bipolar power supplies eliminates this DC load
current and gives similar waveform results.
Ro1
221
50-
Scope
Rm1
64.9
LMH5485
Output
Rm1
Ro2
64.9
221
50-
Scope
图8-4. Example 500 ΩLoad to Differential, Doubly-Terminated, DC-Coupled 50 ΩScope Interface
9 Detailed Description
9.1 Overview
The LMH5485-SP is a voltage-feedback (VFA) based, fully-differential amplifier (FDA) offering greater than 490
MHz, small-signal bandwidth at a gain of 2 V/V with trimmed supply current and input offset voltage. The core
differential amplifier is a slightly decompensated voltage-feedback design with a high slew-rate, precision input
stage. This design gives the 490 495 MHz gain of 2 V/V small-signal bandwidth shown in the characterization
curves, with a 1400 1300 V/µs slew rate, yielding approximately a 315 295 MHz, 2 VPP, large-signal bandwidth
in the same circuit configuration.
The outputs offer near rail-to-rail output swing (0.2 V headroom to either supply), while the device inputs are
negative rail inputs with approximately 1.2 V of headroom required to the positive supply. 图 8-3 shows how this
negative rail input directly supports a bipolar input around ground in a DC-coupled, single-supply design. Similar
to all FDA devices, the output average voltage (common-mode) is controlled by a separate common-mode loop.
The target for this output average is set by the Vocm input pin that can be either floated to default near mid-
supply or driven to a desired output common-mode voltage. The Vocm range extends from a very low 0.91 V
above the negative supply to 1.1 V below the positive supply, supporting a wide range of modern analog-to-
digital converter (ADC) input common-mode requirements using a single 2.7 V to 5.1 V supply range for the
LMH5485-SP.
A power-down pin (PD) is included. Pull the PD pin voltage to the negative supply to turn the device off, putting
the LMH5485-SP into a very-low quiescent current state. For normal operation, the PD pin must be asserted
high. When the device is disabled, remember that the signal path is still present through the passive external
resistors. Input signals applied to a disabled LMH5485-SP still appear at the outputs at some level through this
passive resistor path as they would for any disabled FDA device.
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9.1.1 Terminology and Application Assumptions
Like all widely-used devices, numerous common terms have developed that are unique to this type of device.
These terms include:
• Fully differential amplifier (FDA)—In this document, this term is restricted to devices offering what appears
similar to a differential inverting op amp design element that requires an input resistor (not high-impedance
input) and includes a second internal control-loop setting the output average voltage (Vocm) to a default or
set point. This second loop interacts with the differential loop in some configurations.
• The desired output signal at the two output pins is a differential signal swinging symmetrically around a
common-mode voltage where that is the average voltage for the two outputs.
• Single-ended to differential—always use the outputs differentially in an FDA; however, the source signal can
be either a single-ended source or differential, with a variety of implementation details for either. When the
FDA operation is single-ended to differential, only one of the two input resistors receives the source signal
with the other input resistor connected to a DC reference (often ground) or through a capacitor to ground.
To simplify, several features in the application of the LMH5485-SP are not explicitly stated, but are necessary for
correct operation. These requirements include:
• Although not always stated, make sure to tie the power disable pin to the positive supply when only an
enabled channel is desired.
• Virtually all AC characterization equipment expects a 50 Ωtermination from the 50 Ωsource, and a 50 Ω
single-ended source impedance from the device outputs to the 50 Ωsensing termination. This termination is
achieved in all characterizations (often with some insertion loss), but is not necessary for most applications.
Matching impedance is most often required when transmitting over longer distances. Tight layouts from a
source, through the LMH5485-SP, and on to an ADC input do not require doubly-terminated lines or filter
designs; the exception is if the source requires a defined termination impedance for correct operation (for
example, a SAW filter source).
• External element values are normally assumed to be accurate and matched. In an FDA, match the feedback
resistor values and also match the (DC and AC) impedance from the summing junctions to the source on one
side and the reference or ground on the other side. Unbalancing these values introduces nonidealities in the
signal path. For the signal path, imbalanced resistor ratios on the two sides create a common-mode to
differential conversion. Also, mismatched Rf values and feedback ratios create some added differential output
error terms from any common-mode DC, ac signal, or noise terms. Snapping to standard 1% resistor values
is a typical approach and generally leads to some nominal feedback ratio mismatch. Mismatched resistors or
ratios do not in themselves degrade harmonic distortion. If there is meaningful CM noise or distortion coming
in, those errors are converted to a differential error through element or ratio mismatch.
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9.2 Functional Block Diagram
Vs+
OUT+
OUT–
–
IN–
IN+
2.5 k
2.5 k
High-Aol
Differential I/O
Amplifier
+
–
+
Vs+
100 k
–
Vcm
Error
Amplifier
+
Vocm
CMOS
Buffer
PD
100 k
Vs–
9.3 Feature Description
9.3.1 Differential I/O
The LMH5485-SP combines a core differential I/O, high-gain block with an output common-mode sense that is
compared to a reference voltage and then fed back into the main amplifier block to control the average output to
that reference. The differential I/O block is a classic, high open-loop gain stage with a dominant pole at
approximately 900 Hz. This voltage feedback structure projects a single-pole, unity-gain Aol at 850 MHz (gain
bandwidth product). The high-speed differential outputs include an internal averaging resistor network to sense
the output common-mode voltage. This voltage is compared by a separate Vcm error amplifier to the voltage on
the Vocm pin. If floated, this reference is at half the total supply voltage across the device using two 100-kΩ
resistors. This Vcm error amplifier transmits a correction signal into the main amplifier to force the output
average voltage to meet the target voltage on the Vocm pin. The bandwidth of this error amplifier is
approximately the same bandwidth as the main differential I/O amplifier.
The differential outputs are collector outputs to obtain the rail-to-rail output swing. These outputs are relatively
high-impedance, open-loop sources; however, closing the loop provides a very low output impedance for load
driving. No output current limit or thermal shutdown features are provided in this lower-power device. The
differential inputs are PNP inputs to provide a negative-rail input range.
To operate the LMH5485-SP connect the OUT– pin to the IN+ pin through an Rf, and the OUT+ pin to the IN–
pin through the same value of Rf. Bring in the inputs through additional resistors to the IN+ and IN– pins. The
differential I/O op amp operates similarly to an inverting op amp structure where the source must drive the input
resistor and the gain is the ratio of the feedback to the input resistor.
9.3.2 Power-Down Control Pin (PD)
The LMH5485-SP includes a power-down control pin, PD. This pin must be asserted high for correct amplifier
operation. The PD pin cannot be floated because there is no internal pullup or pulldown resistor on this pin to
reduce disabled power consumption. Asserting this pin low (within 0.7 V of the negative supply) puts the
LMH5485-SP into a very low quiescent state (approximately 2 µA). Switches in the default Vocm resistor string
open to eliminate the fixed bias current (25 µA) across the supply in this 200-kΩvoltage divider to mid-supply.
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9.3.2.1 Operating the Power Shutdown Feature
When the PD pin is asserted high, close to the positive supply, the device will be in normal active mode of
operation. To disable the device for reduced power consumption, PD pin must be asserted low, close to the
negative supply. 图 7-22 shows the PD pin voltage and the corresponding quiescent current drawn. For
applications that require the device to only be powered on when the supplies are present, tie the PD pin to the
positive supply voltage.
The disable operation is referenced from the negative supply (normally, ground). For split-supply operation, with
the negative supply below ground, a disable control voltage below ground is required to turn the LMH5485-SP
off when the negative supply exceeds –0.7 V.
For single-supply operation, a minimum of 1.7 V above the negative supply (ground, in this case) is required to
assure operation. This minimum logic-high level allows for direct operation from 1.8 V supply logic.
9.3.3 Input Overdrive Operation
The LMH5485-SP input stage architecture is intrinsically robust to input overdrives with the series input resistor
required by all applications. High input overdrives cause the outputs to limit into their maximum swings with the
remaining input current through the Rg resistors absorbed by internal, back-to-back protection diodes across the
two inputs. These diodes are normally off in application, and only turn on to absorb the currents that a large input
overdrive might produce through the source impedance and or the series Rg elements required by all designs.
The internal input diodes can safely absorb up to ±15 mA in an overdrive condition. For designs that require
more current to be absorbed, consider adding an external protection diode such as BAV99.
9.4 Device Functional Modes
This wideband FDA requires external resistors for correct signal-path operation. When configured for the desired
input impedance and gain setting with these external resistors, the amplifier can be either on with the PD pin
asserted to a voltage greater than (Vs–) + 1.7 V or turned off by asserting PD low. Disabling the amplifier shuts
off the quiescent current and stops the correct amplifier operation. The signal path is still present for the source
signal through the external resistors.
The Vocm control pin sets the output average voltage. Left open, Vocm defaults to an internal mid-supply value.
Driving this high-impedance input with a voltage reference within its valid range sets a target for the internal Vcm
error amplifier.
9.4.1 Operation from Single-Ended Sources to Differential Outputs
One of the most useful features supported by the FDA device is an easy conversion from a single-ended input to
a differential output centered on a user-controlled, common-mode level. While the output side is relatively
straightforward, the device input pins move in a common-mode sense with the input signal. This common-mode
voltage at the input pins moving with the input signal acts to increase the apparent input impedance to be
greater than the Rg value. This input active impedance issue applies to both AC- and DC-coupled designs, and
requires somewhat more complex solutions for the resistors to account for this active impedance, as shown in
the following subsections.
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9.4.1.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversion
When the signal path can be AC-coupled, the DC biasing for the LMH5485-SP becomes a relatively simple task.
In all designs, start by defining the output common-mode voltage. The AC-coupling issue can be separated for
the input and output sides of an FDA design. The input can be AC coupled and the output DC coupled, or the
output can be AC coupled and the input DC coupled, or they can both be AC coupled. One situation where the
output might be DC coupled (for an AC-coupled input), is when driving directly into an ADC where the Vocm
control voltage uses the ADC common-mode reference to directly bias the FDA output common-mode to the
required ADC input common-mode. In any case, the design starts by setting the desired Vocm. When an AC-
coupled path follows the output pins, the best linearity is achieved by operating Vocm at mid-supply. The Vocm
voltage must be within the linear range for the common-mode loop, as specified in the headroom specifications
(approximately 0.91 V greater than the negative supply and 1.1 V less than the positive supply). If the output
path is also AC coupled, simply letting the Vocm control pin float is usually preferred in order to get a mid-supply
default Vocm bias with minimal elements. To limit noise, place a 0.1 µF decoupling capacitor on the Vocm pin to
ground.
After Vocm is defined, check the target output voltage swing to ensure that the Vocm plus the positive or
negative output swing on each side does not clip into the supplies. If the desired output differential swing is
defined as Vopp, divide by 4 to obtain the ±Vp swing around Vocm at each of the two output pins (each pin
operates 180° out of phase with the other). Check that Vocm ±Vp does not exceed the absolute supply rails for
this rail-to-rail output (RRO) device.
Going to the device input pins side, because both the source and balancing resistor on the nonsignal input side
are DC blocked (see 图 8-1), no common-mode current flows from the output common-mode voltage, thus
setting the input common-mode equal to the output common-mode voltage.
This input headroom also sets a limit for higher Vocm voltages. Because the input Vicm is the output Vocm for
AC-coupled sources, the 1.2 V minimum headroom for the input pins to the positive supply overrides the 1.1 V
headroom limit for the output Vocm. Also, the input signal moves this input Vicm around the DC bias point, as
described in the Resistor Design Equations for the Single-Ended to Differential Configuration of the FDA section.
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9.4.1.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversion
The output considerations remain the same as for the AC-coupled design. Again, the input can be DC-coupled
while the output is AC-coupled. A DC-coupled input with an AC-coupled output might have some advantages to
move the input Vicm down if the source is ground referenced. 图8-3 shows how when the source is DC-coupled
into the LMH5485-SP, both sides of the input circuit must be DC coupled to retain differential balance. Normally,
the nonsignal input side has an Rg element biased to whatever the source midrange is expected to be. Providing
this midscale reference gives a balanced differential swing around Vocm at the outputs. Often, Rg2 is simply
grounded for DC-coupled, bipolar-input applications. This configuration gives a balanced differential output if the
source is swinging around ground. If the source swings from ground to some positive voltage, grounding Rg2
gives a unipolar output differential swing from both outputs at Vocm (when the input is at ground) to one polarity
of swing. Biasing Rg2 to an expected midpoint for the input signal creates a differential output swing around
Vocm.
One significant consideration for a DC-coupled input is that Vocm sets up a common-mode bias current from the
output back through Rf and Rg to the source on both sides of the feedback. Without input balancing networks,
the source must sink or source this DC current. After the input signal range and biasing on the other Rg element
is set, check that the voltage divider from Vocm to Vin through Rf and Rg (and possibly Rs) establishes an input
Vicm at the device input pins that is in range. If the average source is at ground, the negative rail input stage for
the LMH5485-SP is in range for applications using a single positive supply and a positive output Vocm setting
because this DC current lifts the average FDA input summing junctions up off of ground to a positive voltage (the
average of the V+ and V–input pin voltages on the FDA).
9.4.1.3 Resistor Design Equations for the Single-Ended to Differential Configuration of the FDA
The design equations for setting the resistors around an FDA to convert from a single-ended input signal to
differential output can be approached from several directions. Here, several critical assumptions are made to
simplify the results:
• The feedback resistors are selected first and set equal on the two sides.
• The DC and AC impedances from the summing junctions back to the signal source and ground (or a bias
voltage on the nonsignal input side) are set equal to retain feedback divider balance on each side of the FDA
Both of these assumptions are typical and aimed to delivering the best dynamic range through the FDA signal
path.
图 8-1 and 图 8-3 shows how after the feedback resistor values are chosen, the aim is to solve for the Rt (a
termination resistor to ground on the signal input side), Rg1 (the input gain resistor for the signal path), and Rg2
(the matching gain resistor on the nonsignal input side). The same resistor solutions can be applied to either AC-
or DC-coupled paths. Adding blocking capacitors in the input-signal chain is a simple option. 图 8-1 shows how
adding these blocking capacitors after the Rt element has the advantage of removing any DC currents in the
feedback path from the output Vocm to ground.
Earlier approaches to the solutions for Rt and Rg1 (when the input must be matched to a source impedance, Rs)
follow an iterative approach. This complexity arises from the active input impedance at the Rg1 input. When the
FDA is used to convert a single-ended signal to differential, the common-mode input voltage at the FDA inputs
must move with the input signal to generate the inverted output signal as a current in the Rg2 element. 方程式
1shows a more recent solution, where a quadratic in Rt can be solved for an exact required value. This quadratic
emerges from the simultaneous solution for a matched input impedance and target gain. The only inputs
required are the following:
1. The selected Rf value.
2. The target voltage gain (Av) from the input of Rt to the differential output voltage.
3. The desired input impedance at the junction of Rt and Rg1 to match Rs.
As 方程式1 shows, solving this quadratic for Rt starts the solution sequence.
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Rs
≈
«
’
◊
2Rs 2Rf +
Av2
2RfRs2Av
∆
÷
2
Rt2 - Rt
-
= 0
2Rf 2 + Av - RsAv(4 + Av) 2Rf 2 + Av - RsAv(4 + Av)
(1)
Being a quadratic, there are limits to the range of solutions. Specifically, after Rf and Rs are chosen, there is
physically a maximum gain beyond which 方程式 1 starts to solve for negative Rt values (if input matching is a
requirement). With Rf selected, use 方程式2 to verify that the maximum gain is greater than the desired gain.
»
…
ÿ
Ÿ
Ÿ
Ÿ
Rf
4
Rf
Rs
…
Avmax = (
- 2) • 1+ 1+
Rf
Rs
…
…
(
- 2)2
Ÿ
⁄
Rs
(2)
If the achievable Avmax is less than desired, increase the Rf value. After Rt is derived from 方程式 1, the Rg1
element is given by 方程式3:
Rf
2
- Rs
Av
Rg1 =
Rs
Rt
1+
(3)
Then, the simplest approach is to use a single Rg2 = Rt || Rs + Rg1 on the nonsignal input side. Often, this
approach is shown as the separate Rg1 and Rs elements. Using these separate elements provide a better
divider match on the two feedback paths, but a single Rg2 is often acceptable. A direct solution for Rg2 is given
as 方程式4:
Rf
2
Av
Rg2 =
Rs
1+
Rt
(4)
This design proceeds from a target input impedance matched to Rs, signal gain Av from the matched input to the
differential output voltage, and a selected Rf value. The nominal Rf value chosen for the LMH5485-SP
characterization is 402 Ω. As discussed previously, going lower improves noise and phase margin, but reduces
the total output load impedance possibly degrading harmonic distortion. Going higher increases the output noise,
and might reduce the loop-phase margin because of the feedback pole to the input capacitance, but reduces the
total loading on the outputs. Using 方程式 2 to 方程式 4 to sweep the target gain from 1 to Avmax < 14.3 V/V
gives 表 9-1, which shows exact values for Rt, Rg1, and Rg2, where a 50 Ω source must be matched while
setting the two feedback resistors to 402 Ω. One possible solution for 1% standard values is shown along with
the resulting actual input impedance and gain with % errors to the targets in 表9-1.
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表9-1. Required Resistors for a Single-Ended to Differential FDA Design Stepping Gain from
1 V/V to 14 V/V
Rg1,
EXACT
(Ω)
Rg2,
EXACT
(Ω)
Rt, EXACT
ACTUAL %ERR TO ACTUAL %ERR TO
Av(1)
Rt 1%
Rg1 1%
Rg2 1%
ZIN
Rs
GAIN
Av
(Ω)
1
2
55.2
60.1
65.6
72.0
79.7
89.1
101
117
54.9
60.4
64.9
71.5
80.6
88.7
102
118
395
193
392
191
421
220
422
221
49.731
50.171
49.572
49.704
50.451
49.909
50.179
50.246
49.605
50.009
49.815
50.051
49.926
50.079
1.006
2.014
2.983
4.005
5.014
6.008
7.029
7.974
9.016
9.961
11.024
11.995
12.967
13.986
0.62%
0.72%
–0.54%
0.34%
3
123
124
151
150
–0.86%
–0.59%
0.90%
–0.57%
0.14%
4
88.9
68.4
53.7
43.5
35.5
28.8
23.5
18.8
14.7
10.9
7.26
88.7
68.1
53.6
43.2
35.7
28.7
23.7
18.7
14.7
11.0
7.32
118
118
5
99.2
85.7
77.1
70.6
65.4
62.0
59.6
57.9
56.7
56.2
100
0.28%
6
86.6
76.8
69.8
64.9
61.9
59.0
57.6
56.2
56.2
0.14%
–0.18%
0.36%
7
0.42%
8
0.49%
–0.32%
0.18%
9
138
170
220
313
545
2209
137
169
221
316
549
2210
–0.79%
0.02%
10
11
12
13
14
–0.39%
0.22%
–0.37%
0.10%
–0.04%
–0.25%
–0.10%
–0.15%
0.16%
(1) Rf = 402 Ω, Rs = 50 Ω, and AvMAX = 14.32 V/V.
These equations and design flow apply to any FDA. Using the feedback resistor value as a starting point is
particularly useful for current-feedback-based FDAs such as the LMH6554, where the value of these feedback
resistors determines the frequency response flatness. Similar tables can be built using the equations provided
here for other source impedances, Rf values, and gain ranges.
Note the extremely low Rg1 values at the higher gains. For instance, at a gain of 14 V/V, that 7.32 Ω standard
value is transformed by the action of the common-mode loop moving the input common-mode voltage to appear
like a 50 Ω input match. This active input impedance provides an improved input-referred noise at higher gains.
The TINA model correctly shows this actively-set input impedance in the single-ended to differential
configuration, and is a good tool to validate the gains, input impedances, response shapes, and noise issues.
9.4.1.4 Input Impedance for the Single-Ended to Differential FDA Configuration
The designs so far have included a source impedance, Rs, that must be matched by Rt and Rg1. The total
impedance at the junction of Rt and Rg1 for the circuit of 图 8-3 is the parallel combination of Rt to ground, and
the ZA (active impedance) presented by Rg1. The expression for ZA, assuming Rg2 is set to obtain the
differential divider balance, is given by 方程式5:
≈
∆
«
’≈
÷∆
◊«
’
÷
◊
Rg1
Rg2
Rf
1+
1+
Rg1
ZA = Rg1
Rf
2 +
Rg2
(5)
For designs that do not need impedance matching, but instead come from the low impedance output of another
amplifier for instance, Rg1 = Rg2 is the single-to-differential design used without an Rt to ground. Setting Rg1 =
Rg2 = Rg in 方程式 5 gives the input impedance of a simple input FDA driving from a low-impedance, single-
ended source to a differential output as shown in 方程式6:
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Rf
1+
Rg
Rf
ZA = 2Rg
2 +
Rg
(6)
In this case, setting a target gain as Rf / Rg ≡ α, and then setting the desired input impedance, allows the Rg
element to be resolved first, and then the required Rf to get the gain. For example, targeting an input impedance
of 200 Ω with a gain of 4 V/V, 方程式 7 gives the physical Rg element. Multiplying this required Rg value by a
gain of 4 gives the Rf value and the design of 图9-1.
2 +
2 1+
a
a
Rg = ZA
(7)
LMH5485 Wideband,
Fully-Differential Amplifier
Rf1
480
200- Input Impedance,
Gain of 4 V/V Design
Vcc
Rg1
120
–
Output
Measurement
Point
+
R1
500
+
Vocm
FDA
Vs
–
–
+
PD
Rg2
120
Vcc
Rf2
480
图9-1. 200 ΩInput Impedance, Single-Ended to Differential DC-Coupled Design with Gain of 4 V/V
After being designed, this circuit can also be AC-coupled by adding blocking caps in series with the two 120 Ω
Rg resistors. This active input impedance has the advantage of increasing the apparent load to the prior stage
using lower resistors values, leading to lower output noise for a given gain target.
9.4.2 Differential-Input to Differential-Output Operation
In many ways, this method is a much simpler way to operate the FDA from a design equations perspective.
Again, assuming the two sides of the circuit are balanced with equal Rf and Rg elements, the differential input
impedance is now just the sum of the two Rg elements to a differential inverting summing junction. In these
designs, the input common-mode voltage at the summing junctions does not move with the signal, but must be
DC biased in the allowable range for the input pins with consideration given to the voltage headroom required
from each supply. Slightly different considerations apply to AC- or DC-coupled, differential-in to differential-out
designs, as described in the following sections.
9.4.2.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
There are two typical ways to use the LMH5485-SP with an AC-coupled differential source. In the first method,
the source is differential and can be coupled in through two blocking capacitors. The second method uses either
a single-ended or a differential source and couples in through a transformer (or balun). 图 9-2 shows a typical
blocking capacitor approach to a differential input. An optional input differential termination resistor (Rm) is
included in this design. This Rm element allows the input Rg resistors to be scaled up while still delivering lower
differential input impedance to the source. In this example, the Rg elements sum to show a 200 Ω differential
impedance, while the Rm element combines in parallel to give a net 100 Ω, AC-coupled, differential impedance
to the source. Again, the design proceeds ideally by selecting the Rf element values, then the Rg to set the
differential gain, then an Rm element (if needed) to achieve a target input impedance. Alternatively, the Rm
element can be eliminated, the Rg elements set to the desired input impedance, and Rf set to the get the
differential gain (= Rf / Rg).
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LMH5485 Wideband,
Fully-Differential Amplifier
Rf1
402
C1
100 nF
Vcc
Rg1
100
–
Output
Measurement
Point
+
R1
500
Vocm
FDA
–
Downconverter
Differential
Output
Rm
200
+
PD
C2
100 nF
Rg2
100
Vcc
Rf2
402
图9-2. Down-Converting Mixer Delivering an AC-Coupled Differential Signal to the LMH5485-SP
The DC biasing here is very simple. The output Vocm is set by the input control voltage. Because there is no DC
current path for the output common-mode voltage, that DC bias also sets the input pins common-mode operating
points.
Transformer input coupling allows either a single-ended or differential source to be coupled into the LMH5485-
SP, which also improves the input-referred noise figure. These designs assume a source impedance that must
be matched in the balun interface. 图9-3 shows the simplest approach where an example 1:2 turns ratio step-up
transformer is used from a 50 Ωsource.
LMH5485 Wideband,
Fully-Differential Amplifier
Rf1
402
Pulse
CX2047LNL
1:2 Turns Ratio
Vcc
Balun
Rg1
100
C1
100 nF
Rs
50
M1
–
+
90.4
H
Output
Measurement
Point
+
–
R1
500
Vocm
FDA
+
–
PD
VG1
N1
N2
Rg2
100
Vcc
Rf2
402
图9-3. Input Balun Interface Delivers a Differential Input to the LMH5485-SP
In this example, this 1:2 turns ratio step-up transformer provides a source and load match from the 50 Ω source
if the secondary is terminated in 200 Ω (turns-ratio squared is the impedance ratio across a balun). The two Rg
elements provide that termination as they sum to the differential virtual ground at the FDA summing junctions.
The input blocking cap (C1) is optional and included only to eliminate DC shorts to ground from the source. This
solution often improves the input-referred noise figure more so than just the FDA using this passive (zero power
dissipation) input balun. Defining a few ratios allows a noise figure expression to be written as 方程式8:
2
2
≈
∆
∆
’
÷
÷
÷
÷
n • i • Rs
≈
∆
«
’
÷
◊
(
)
eni
1
2
1
1
2
≈
’
◊
n
•
+
+
∆
«
÷
(1+ b2
)
8
ab2
4
b2
b
n
a
NF = 10 • Log 1+
+
+
+
2
∆
b2
(
ab
)
kTRs
∆
∆
÷
«
◊
(8)
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where
• n ≡turns ratio (the ohms ratio is then n2)
• α≡differential gain in the FDA = Rf / Rg
• β≡transformer insertion loss in V/V (from a dB insertion loss, convert to linear attenuation = β)
• kT = 4e-21J at 290 K (17°C)
One way to use 方程式 8 is to fix the input balun selection, and then sweep the FDA gain by stepping up the Rf
value. The lowest-noise method uses just the two Rg elements for termination matching (no Rm element, such
as in 图 9-3) and sweep the Rf values up to assess the resulting input-referred noise figure. While this method
can be used with all FDAs and a wide range of input baluns, relatively low-frequency input baluns are an
appropriate choice here because the LMH5485-SP holds exceptional SFDR for less than 40 MHz applications.
Two representative selections, with their typical measured spans and resulting model elements, are shown in 表
9-2. For these two selections, the critical inputs for the noise figures are the turns ratio and the insertion loss (the
0.2 dB for the CX2014LNL becomes a β= 0.977 in the NF expression).
表9-2. Example Input Step-Up Baluns and Associated Parameters
–1-dB
FREQUENCY (MHz)
–3-dB
FREQUENCY (MHz)
NO. OF DECADES
MODEL ELEMENTS
PART
NUMBER
INSERTION
LOSS (dB)
TURNS
RATIO
MFR
Rs (Ω)
–1-dB
–3-dB
MIN
MAX
MIN
MAX
L1 (µH)
L2 (µH)
k
M (µH)
POINTS POINTS
ADT2-1T
50
50
0.1
463
270
0.3
0.2
MiniCircuits
Pulse Eng
3.67
3.51
4.22
3.93
0.05
825
372
1.41
2
79.57747 158.50797 0.99988 112.19064
90.42894 361.71578 0.99976 180.81512
CX2047LNL
0.083
0.044
Using the typical input referred noise terms for the LMH5485-SP (eni = 2.2 nV and in = 1.9 pA) and sweeping the
total gain from the input of the balun to the differential output over a 10-dB to 24-dB span, gives the input noise
figure shown in 图9-4.
14
ADT2-1T
CX2047LNL
13
12
11
10
9
8
7
10
12
14
16
18
20
22
24
Total Gain (dB)
图9-4. Noise Figure vs Total Gain with the Two Input Baluns of Table 9-2
The 50 Ω referred noise figure estimates show a decreasing input-referred noise for either balun as the gain
increases through 24 dB. The only elements changing in these sweeps are the feedback-resistor values, to
achieve the total target gain after the step up from the input balun. The example of 图9-3 is a gain of
7.86 V/V, or a 17.9-dB gain where a 10.0-dB input noise figure is predicted from 图 9-4. Another advantage for
this method is that the effective noise gain (NG) is reduced by the source impedance appearing as part of the
total Rg element in the design. The example of 图9-3 operates with a NG = 1 + 402 / (100 + 100) = 3 V/V, giving
greater than 300 MHz SSBW in the LMH5485-SP portion of the design. Combining that with the 372 MHz in the
balun itself gives greater than 200 MHz in this 18-dB gain stage; or an equivalent greater than 1.6-GHz gain
bandwidth product in a low-power, high dynamic range interface.
Added features and considerations for the balun input of 图9-3 include:
• Many of these baluns offer a secondary centertap. Leave the centertap unconnected for the best HD2
suppression and DC biasing (do not include a capacitor from this centertap to ground).
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• With a floating secondary centertap, the input pins common-mode voltage again equals the output Vocm
setting because there is no DC path for the output common-mode voltage to create a common-mode current
(ICM).
10 Power Supply Recommendations
The LMH5485-SP is principally intended to operate with a nominal single-supply voltage of +3 V to +5 V. Supply
decoupling is required, as described in the Layout Guidelines. The amplifier signal path is flexible for single or
split-supply operation. Most applications are intended to be single supply, but any split-supply design can be
used, as long as the total supply across the LMH5485-SP is less than 5.25 V and the required input, output, and
common-mode pin headrooms to each supply are observed. Left open, the Vocm pin defaults to near mid-supply
for any combination of split or single supplies used. The disable pin is negative-rail referenced. Using a negative
supply requires the disable pin to be pulled down to within 0.7 V of the negative supply to disable the amplifier.
11 Layout
11.1 Layout Guidelines
Similar to all high-speed devices, best system performance is achieved with a close attention to board layout.
The LMH5485-SP evaluation module (EVM) shows a good example of high frequency layout techniques as a
reference. This EVM includes numerous extra elements and features for characterization purposes that may not
apply to some applications. General high-speed, signal-path layout suggestions include the following:
• Continuous ground planes are preferred for signal routing with matched impedance traces for longer runs;
however, ground and power planes around the capacitive sensitive input and output device pins should be
open. After the signal is sent into a resistor, the parasitic capacitance becomes more of a band limiting issue
and less of a stability issue.
• Use good, high-frequency decoupling capacitors (0.1 µF) on the ground plane at the device power pins.
Higher value capacitors (2.2 µF) are required, but may be placed further from the device power pins and
shared among devices. A supply decoupling capacitor across the two power supplies (for bipolar operation)
should also be added. For best high-frequency decoupling, consider X2Y supply-decoupling capacitors that
offer a much higher self-resonance frequency over standard capacitors.
• For each LMH5485-SP, attach a separate 0.1 µF capacitor to a nearby ground plane. With cascaded or
multiple parallel channels, including ferrite beads from the larger capacitor is often useful to the local high-
frequency decoupling capacitor.
• When using differential signal routing over any appreciable distance, use microstrip layout techniques with
matched impedance traces.
• The input summing junctions are very sensitive to parasitic capacitance. Connect any Rg elements into the
summing junction with minimal trace length to the device pin side of the resistor. The other side of the Rg
elements can have more trace length if needed to the source or to ground.
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Design for a Wideband, Differential Transimpedance DAC Output application report
• Texas Instruments, Extending Rail-to-Rail Output Range for Fully Differential Amplifiers to Include True Zero
Volts reference guide
• Texas Instruments, LMH6554 2.8-GHz Ultra Linear Fully Differential Amplifier data sheet
• Texas Instruments, LMH5485-SP-EVM user guide
• Texas Instruments, Maximizing the dynamic range of analog front ends having a transimpedance amplifier
technical brief
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
HKX0008A
CFP - 2.785 mm max height
S
C
A
L
E
1
.
0
0
0
CERAMIC FLATPACK
B
6X 1.27
1
8
6.725
6.225
2X 3.81
4
5
0.52
8X
0.42
6.735
6.235
A
0.2
C A B
2.785 MAX
0.20
0.12
0.95 MAX
(4.445)
C
4
5
8
1
PIN 1 ID
24 MAX
4223439/C 08/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermetically sealed with a metal lid.
4. The leads are gold plated.
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13.1 Tube Information
Package
Type
L
W
(mm)
T
(µm)
B
(mm)
Device
Package Name
Pins
SPQ
(mm)
LMH5485HKX/EM
CFP
HKX
8
1
506.98
26.16
6220
NA
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PACKAGE OPTION ADDENDUM
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12-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PLMH5485HKX/EM
ACTIVE
CFP
HKX
8
25
TBD
Call TI
Call TI
25 to 25
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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