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LM5169PQDDARQ1 [TI]

LM5169-Q1/LM5168-Q1 0.65-A/0.3-A, 120-V, Step-Down Converter with Fly-Buck™ Converter Capability;
LM5169PQDDARQ1
型号： LM5169PQDDARQ1
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

LM5169-Q1/LM5168-Q1 0.65-A/0.3-A, 120-V, Step-Down Converter with Fly-Buck™ Converter Capability
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LM5168-Q1, LM5169-Q1  
SNVSBZ3 – JUNE 2021  
LM5169-Q1/LM5168-Q1 0.65-A/0.3-A, 120-V, Step-Down Converter with Fly-Buck™  
Converter Capability  
1 Features  
3 Description  
•
AEC-Q100-qualified for automotive applications  
– Device temperature grade 1: –40°C to +125°C,  
ambient temperature range  
The LM5169-Q1 and LM5168-Q1 synchronous buck  
converters are designed to regulate over a wide input  
voltage range, minimizing the need for external surge  
suppression components. A minimum controllable on  
time of 50 ns facilitates large step-down conversion  
ratios, enabling the direct step-down from a 48-  
V nominal input to low-voltage rails for reduced  
system complexity and solution cost. The LM5169-Q1  
operates during input voltage dips as low as 6 V,  
at nearly 100% duty cycle if needed, making it an  
excellent choice for wide input supply range industrial  
and high cell count battery pack applications.  
•
Designed for reliable and rugged applications  
– Wide input voltage range of 6 V to 120 V  
– Junction temperature range: –40°C to +150°C  
– Fixed 3-ms internal soft-start timer  
– Peak and valley current-limit protection  
– Input UVLO and thermal shutdown protection  
Suited for scalable automotive HEV/EV power  
supplies  
– Low minimum on and off times of 50 ns  
– Adjustable switching frequency up to 1 MHz  
– Diode emulation for high light-load efficiency  
– Auto mode with low-quiescent current (< 10 µA)  
– FPWM mode enables fly-buck capability  
– 3-µA shutdown quiescent current  
•
With integrated high-side and low-side power  
MOSFETs, the LM5169-Q1 delivers up to 0.65-A  
of output current and the LM5168-Q1 delivers up  
to 0.3-A of output current. A constant on time  
(COT) control architecture provides nearly constant  
switching frequency with excellent load and line  
transient response. The LM5169-Q1 is available in  
FPWM or Auto mode operation. FPWM mode ensures  
forced CCM operation across the entire load range  
supporting isolated Fly-buck operation. Auto mode  
enables ultra-low IQ and diode emulation mode  
operation for high light-load efficiency.  
– Pin-to-pin compatible with LM5164-Q1,  
LM5163-Q1, LM5017, and LM34927  
Integration reduces solution size and cost  
•
– COT mode control architecture  
– Integrated 1.9-Ω NFET buck switch  
– Integrated 0.71-Ω NFET synchronous rectifier  
– 1.2-V internal voltage reference  
– No loop compensation components  
– Internal VCC bias regulator and boot diode  
– Open-drain power-good indicator  
– 8-pin SOIC package with PowerPAD™ with  
30°C/W RθJA (EVM)  
Device Information  
PART NUMBER  
LM5169-Q1  
PACKAGE(1)  
BODY SIZE (NOM)  
SO PowerPAD (8)  
4.89 mm × 3.90 mm  
LM5168-Q1  
(1) For all available packages, see the orderable addendum at  
the end of the data sheet.  
2 Applications  
•
•
•
•
Communications – brick power module  
Industrial battery pack (≥ 10 S)  
Battery pack – e-bike/e-scooter/LEV  
HEV/EV – battery management system  
D1  
LO  
VIN  
VOUT  
VOUT2  
VIN  
SW  
COUT2  
CA  
RA  
CBST  
CIN  
RFB1  
T1  
EN/UVLO  
RT  
BST  
FB  
VIN  
VOUT1  
COUT  
VIN  
SW  
CB  
CA  
RA  
CBST  
CIN  
RFB1  
EN/UVLO  
RT  
BST  
FB  
RT  
RFB2  
COUT1  
CB  
PGOOD  
GND  
RT  
RFB2  
GND  
PGOOD  
Typical Buck Application Circuit  
Typical Fly-Buck Application Circuit  
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change  
without notice.  
 
 
 
LM5168-Q1, LM5169-Q1  
SNVSBZ3 – JUNE 2021  
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Table of Contents  
1 Features............................................................................1  
2 Applications.....................................................................1  
3 Description.......................................................................1  
4 Revision History.............................................................. 2  
5 Device Comparison Table...............................................3  
6 Pin Configuration and Functions...................................4  
7 Specifications.................................................................. 5  
7.1 Absolute Maximum Ratings ....................................... 5  
7.2 ESD Ratings .............................................................. 5  
7.3 Recommended Operating Conditions ........................5  
7.4 Thermal Information ...................................................6  
7.5 Electrical Characteristics ............................................6  
8 Detailed Description........................................................8  
8.1 Overview.....................................................................8  
8.2 Functional Block Diagram...........................................9  
8.3 Feature Description.....................................................9  
8.4 Device Functional Modes..........................................14  
9 Application and Implementation..................................15  
9.1 Application Information............................................. 15  
9.2 Typical Application.................................................... 16  
10 Power Supply Recommendations..............................25  
11 Layout...........................................................................26  
11.1 Layout Guidelines................................................... 26  
11.2 Layout Example...................................................... 28  
12 Device and Documentation Support..........................29  
12.1 Device Support....................................................... 29  
12.2 Documentation Support.......................................... 29  
12.3 Receiving Notification of Documentation Updates..30  
12.4 Support Resources................................................. 30  
12.5 Trademarks.............................................................30  
12.6 Electrostatic Discharge Caution..............................30  
12.7 Glossary..................................................................30  
13 Mechanical, Packaging, and Orderable  
Information.................................................................... 30  
4 Revision History  
DATE  
REVISION  
NOTES  
June 2021  
*
Initial release  
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5 Device Comparison Table  
LIGHT  
LOAD  
MODE  
DEVICE  
NAME  
OUTPUT  
CURRENT  
SAMPLES  
AVAILABLE?  
DESCRIPTION  
LM5169-Q1  
LM5169-Q1  
LM5168-Q1  
LM5168-Q1  
LM5169FQDDARQ1  
LM5169PQDDARQ1  
LM5168FQDDARQ1  
LM5168PQDDARQ1  
0.65 A  
0.65 A  
0.3 A  
FPWM  
PFM  
Contact TI  
Contact TI  
Available  
FPWM  
PFM  
0.3 A  
Contact TI  
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6 Pin Configuration and Functions  
GND  
SW  
VIN  
BST  
EP  
EN/UVLO  
PGOOD  
RT  
FB  
Figure 6-1. 8-Pin SO PowerPAD DDA Package (Top View)  
Table 6-1. Pin Functions  
PIN  
I/O(1)  
DESCRIPTION  
NO.  
NAME  
1
GND  
G
Ground connection for internal circuits  
Regulator supply input pin to the high-side power MOSFET and internal bias regulator. Connect  
directly to the input supply of the buck converter with short, low impedance paths.  
2
3
VIN  
P/I  
Precision enable and undervoltage lockout (UVLO) programming pin. If the EN/UVLO rising voltage  
is below 1.1 V, the converter is in Shutdown mode with all functions disabled. If the UVLO voltage  
is greater than 1.1 V and below 1.5 V, the converter is in Standby mode with the internal VCC  
regulator operational and no switching. If the EN/UVLO voltage is above 1.5 V, the start-up  
sequence begins.  
EN/UVLO  
I
4
5
RT  
FB  
I
I
On-time programming pin. A resistor between this pin and GND sets the buck switch on time.  
Feedback input of voltage regulation comparator  
Power-good indicator. This pin is an open-drain output pin. Connect to a source voltage through an  
external pullup resistor between 10 kΩ to 100 kΩ. Connect to GND if the PGOOD feature is not  
needed.  
6
PGOOD  
BST  
O
P/I  
P
Bootstrap gate-drive supply. Required to connect a high-quality 2.2-nF X7R ceramic capacitor  
between BST and SW to bias the internal high-side gate driver.  
7
Switching node that is internally connected to the source of the high-side NMOS buck switch and  
the drain of the low-side NMOS synchronous rectifier. Connect to the switching node of the power  
inductor.  
8
SW  
Exposed pad of the package. No internal electrical connection. Solder the EP to the GND pin and  
connect to a large copper plane to reduce thermal resistance.  
—
EP  
—
(1) G = Ground, I = Input, O = Output, P = Power  
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7 Specifications  
7.1 Absolute Maximum Ratings  
Over operating junction temperature range (unless otherwise noted) (1)  
MIN  
–0.3  
–1.5  
–3  
MAX  
120  
UNIT  
VIN  
SW, DC  
120  
SW, transient < 20 ns  
BOOT  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
125.5  
5.5  
Pin voltage  
BOOT – SW  
EN  
V
120  
5.5  
FB  
RT  
5.5  
PGOOD  
14  
Bootstrap  
External BST to SW capacitance  
2.5  
nF  
capacitor(2)  
TJ  
Operating junction temperature  
Storage temperature  
–40  
–65  
150  
150  
°C  
°C  
Tstg  
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply  
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.  
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully  
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.  
(2) Specification applies to FPWM and fly-buck operation.  
7.2 ESD Ratings  
VALUE  
UNIT  
Human-body model (HBM), per ANSI/ESDA/JEDEC  
JS-001 (1)  
±2000  
V(ESD)  
Electrostatic discharge  
V
Charged-device model (CDM), per JEDEC specification  
JESD22-C101 (2)  
±500  
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.  
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.  
7.3 Recommended Operating Conditions  
Over operating junction temperature range (unless otherwise noted)  
MIN  
NOM  
MAX  
115  
UNIT  
V
VIN  
Pin voltage  
Pin voltage  
VIN  
6
VEN  
EN  
115  
V
LM5169  
LM5168  
FPWM Mode  
0.65  
0.3  
A
IOUT  
Output current range  
A
CBST  
FSW  
External BST to SW capacitance  
Switching frequency  
2.2  
nF  
kHz  
100  
1000  
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UNIT  
SNVSBZ3 – JUNE 2021  
7.4 Thermal Information  
LM516x-Q1  
DDA (SOIC)  
8 PINS  
22  
THERMAL METRIC(1)  
RθJA(EVM)  
RθJA  
RθJC(top)  
ψJT  
Junction-to-ambient thermal resistance for LM5169QEVM(2)  
Junction-to-ambient thermal resistance  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
38.9  
Junction-to-case (top) thermal resistance  
Junction-to-top characterization parameter  
Junction-to-board thermal resistance  
51.7  
2.9  
RθJB  
14.1  
ψJB  
Junction-to-board characterization parameter  
Junction-to-case (bottom) thermal resistance  
14.1  
RθJC(bot)  
3.3  
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics  
(2) This value is obtained on the LM5169FQEVM with approximaetly 49 cm2 of copper area. See the LM5169FQEVM user guide for more  
information.  
7.5 Electrical Characteristics  
TJ = –40°C to +150°C, VIN = 4.5 V to 120 V. Typical values are at TJ = 25°C and VIN = 24 V (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
SUPPLY  
VEN = 2.5 V, PWM operation  
VEN = 2.5 V, PFM operation  
VEN = 1.25 V  
420  
10  
17  
3
880  
25  
µA  
µA  
µA  
µA  
IQ(VIN)  
VIN quiescent current  
IQ(STANDBY)  
ISD(VIN)  
VIN standby current – LDO only  
VIN shutdown supply current  
35  
VEN = 0 V  
15  
ENABLE  
VEN(R)  
EN voltage rising threshold  
EN voltage falling threshold  
EN rising, enable switching  
EN falling, disable switching  
1.45  
1.35  
1.5  
1.4  
1.55  
1.44  
V
V
VEN(F)  
EN rising, enable internal LDO, no  
switching.  
VSD(R)  
EN standby rising threshold  
EN standby falling threshold  
1.1  
V
V
VSD(F)  
REFERENCE VOLTAGE  
EN falling, disable internal LDO  
0.45  
1.181  
1.75  
VFB  
FB voltage  
VFB falling  
1.2  
3
1.218  
4.75  
V
STARTUP  
tSS  
Internal fixed soft-start time  
ms  
POWER STAGE  
RDSON(HS)  
RDSON(LS)  
tON(min)  
High-side MOSFET on-resistance  
Low-side MOSFET on-resistance  
Minimum ON pulse width  
On time1  
ISW = –100 mA  
ISW = 100 mA  
1.85  
0.75  
50  
Ω
Ω
ns  
ns  
ns  
ns  
ns  
ns  
tON(1)  
VVIN = 6 V, RRT = 75 kΩ  
VVIN = 6 V, RRT = 25 kΩ  
VVIN = 12 V, RRT = 75 kΩ  
VVIN = 12 V, RRT = 25 kΩ  
5000  
1650  
2550  
830  
tON(2)  
On time2  
tON(3)  
On time3  
tON(4)  
On time4  
tOFF(min)  
BOOT CIRCUIT  
VBOOT-SW(UV_R)  
Minimum OFF pulse width  
50  
BOOT-SW UVLO rising threshold  
VBOOT-SW rising  
2.7  
3.4  
V
OVERCURRENT PROTECTION  
LM5168  
LM5169  
LM5168  
LM5169  
LM5168  
LM5169  
0.356  
0.71  
0.42  
0.84  
0.484  
0.94  
A
A
A
A
A
A
IHS_PK(OC)  
ILS_PK(OC)  
IDELTA(OC)  
High-side peak current limit  
0.356  
0.71  
0.42  
0.484  
0.94  
Low-side peak current limit  
0.84  
0.084  
0.168  
Min of IHS_PK(OC) or ILS_PK(OC) minus  
ILS_V(OC)  
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TJ = –40°C to +150°C, VIN = 4.5 V to 120 V. Typical values are at TJ = 25°C and VIN = 24 V (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
1.5  
0.75  
0
MAX  
UNIT  
A
LM5169  
LM5168  
1.25  
1.75  
ILS(NOC)  
Low-side negative current limit  
0.635  
0.865  
A
IZC  
Zero-cross detection current threshold  
Hiccup time before re-start  
A
TW  
64  
ms  
POWER GOOD  
FB falling, PG high to low  
FB rising, PG low to high  
VFB = 1 V  
1.055  
1.105  
1.08  
1.14  
7
1.1  
V
V
Ω
VPGTH  
Power-good threshold  
1.175  
RPG  
Power-good on-resistance  
THERMAL SHUTDOWN  
TJ(SD)  
Thermal shutdown threshold (1)  
Thermal shutdown hysteresis (1)  
Temperature rising  
175  
10  
°C  
°C  
TJ(HYS)  
(1) Ensured by design.  
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8 Detailed Description  
8.1 Overview  
The LM5169-Q1 and LM5168-Q1 are easy-to-use, ultra-low IQ constant on-time (COT) synchronous step-down  
buck regulators. With integrated high-side and low-side power MOSFETs, the LM516x-Q1 is a low-cost, highly  
efficient buck converter that operates from a wide input voltage of 6 V to 120 V, delivering up to 0.65-A or  
0.3-A DC load current. The LM516x-Q1 is available in an 8-pin SO PowerPAD™ package with 1.27-mm pin pitch  
for adequate spacing in high-voltage applications. This constant on-time (COT) converter is ideal for low-noise,  
high-current, and fast load transient requirements, operating with a predictive on-time switching pulse. Over  
the input voltage range, input voltage feedforward is employed to achieve a quasi-fixed switching frequency. A  
controllable on time as low as 50 ns permits high step-down ratios and a minimum forced off time of 50 ns  
provides extremely high duty cycles, allowing VIN to drop close to VOUT before frequency foldback occurs. The  
LM516x-Q1 implements a smart peak and valley current limit detection circuit to ensure robust protection during  
output short circuit conditions. Control loop compensation is not required for this regulator, reducing design time  
and external component count.  
The LM5169-Q1 and LM5168-Q1 are pre-programmed to operate in Auto mode or FPWM mode. When  
configured to operate in Auto mode, at light loads, the device transitions into an ultra-low IQ mode to maintain  
high efficiency and prevent draining battery cells connected to the input when the system is in standby. When  
configured in FPWM Mode, at light loads the device will maintain CCM operation enabling Fly-buck operation.  
The Fly-buck configuration can be used to generate both a non-isolated primary output and an isolated  
secondary output.  
The LM5169-Q1 and LM5168-Q1 incorporates additional features for comprehensive system requirements,  
including an open-drain power-good circuit for the following:  
•
•
•
•
•
•
Power-rail sequencing and fault reporting  
Internally fixed soft start  
Monotonic start-up into prebiased loads  
Precision enable for programmable line undervoltage lockout (UVLO)  
Smart cycle-by-cycle current limit for optimal inductor sizing  
Thermal shutdown with automatic recovery  
The LM5169-Q1 and LM5168-Q1 support a wide range of end equipment requiring a regulated output from  
a high input supply where the transient voltage deviates from its DC level. Examples of such end equipment  
systems are the following:  
•
•
•
•
48-V automotive systems  
High cell-count battery-pack systems  
24-V industrial systems  
48-V telecom and PoE voltage ranges  
The pin arrangement is designed for a simple layout that requires only a few external components.  
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8.2 Functional Block Diagram  
VIN  
VIN  
VDD  
BIAS  
REGULATOR  
CIN  
VDD UVLO  
RUV1  
EN/UVLO  
STANDBY  
œ
+
THERMAL  
SHUTDOWN  
RUV2  
1.5 V  
œ
+
SHUTDOWN  
BST  
LOGIC  
.45 V  
VIN  
CBST  
RT  
ON/OFF  
TIMERS  
DISABLE  
CONSTANT  
ON-TIME  
CONTROL  
LOGIC  
VOUT  
LO  
VOUT  
SW  
VCC  
RFB1  
FEEDBACK  
COMPARATOR  
SLEEP  
COUT  
FB  
DETECT  
œ
+
RT  
VREF  
PGOOD  
LS SENSE  
RFB2  
PEAK/VALLEY  
CURRENT LIMIT  
FB  
œ
+
GND  
PGOOD  
COMPARATOR  
0.9*VREF  
8.3 Feature Description  
8.3.1 Control Architecture  
The LM516x-Q1 step-down switching converter employs a constant on-time (COT) control scheme. The COT  
control scheme sets a fixed on time, tON, of the high-side FET using a timing resistor (RT). tON is adjusted as  
VIN changes and is inversely proportional to the input voltage to maintain a fixed frequency when in Continuous  
Conduction mode (CCM). After expiration of tON, the high-side FET remains off until the feedback pin is equal  
or below the reference voltage of 1.2 V. To maintain stability, the feedback comparator requires a minimal ripple  
voltage that is in-phase with the inductor current during the off time. Furthermore, this change in feedback  
voltage during the off time must be large enough to dominate any noise present at the feedback node. The  
minimum recommended ripple voltage is 20 mV. See Table 8-1 for different types of ripple injection schemes that  
ensure stability over the full input voltage range.  
During a rapid start-up or a positive load step, the regulator operates with minimum off times until regulation is  
achieved. This feature enables extremely fast load transient response with minimum output voltage undershoot.  
When regulating the output in steady-state operation, the off time automatically adjusts itself to produce the  
SW pin duty cycle required for output voltage regulation to maintain a fixed switching frequency. In CCM, the  
switching frequency FSW is programmed by the RT resistor. Use Equation 1 to calculate the switching frequency.  
2500*V  
V
OUT  
kΩ  
F
kHz =  
(1)  
SW  
R
T
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Table 8-1. Ripple Generation Methods  
TYPE 1  
TYPE 2  
TYPE 3  
Lowest Cost  
Reduced Ripple  
Minimum Ripple  
LO  
LO  
VOUT  
VIN  
VOUT  
LO  
VIN  
VOUT  
VIN  
VIN  
SW  
VIN  
SW  
VIN  
SW  
RA  
CA  
CBST  
CBST  
CFF  
CIN  
CIN  
CBST  
RFB1  
RFB1  
RESR  
RESR  
EN/UVLO  
RT  
BST  
FB  
EN/UVLO  
RT  
BST  
FB  
EN/UVLO  
RT  
BST  
RFB1  
COUT  
CB  
FB  
RFB2  
COUT  
RFB2  
COUT  
RT  
RT  
RT  
RFB2  
PGOOD  
GND  
PGOOD  
GND  
PGOOD  
GND  
10  
20mV  
CA  
í
RESR  
í
FSW ∂(RFB1 || RFB2  
)
DIL(nom)  
(7)  
20mV ∂ VOUT  
VFB1 ∂ DIL(nom)  
(4)  
RESR  
í
RACA  
Ç
(2)  
VOUT  
V
- VOUT ∂ t  
(
)
20mV  
RESR  
í
IN-nom  
ON @V  
(
)
IN-nom  
2∂ VIN ∂FSW ∂COUT  
(5)  
(8)  
VOUT  
RESR  
í
2∂ VIN ∂FSW ∂COUT  
(3)  
1
tTR-settling  
CFF  
í
CB í  
2p ∂FSW ∂(RFB1 || RFB2  
)
3∂RFB1  
(6)  
(9)  
Table 8-1 presents three different methods for generating appropriate voltage ripple at the feedback node.  
The Type-1 ripple generation method uses a single resistor, RESR, in series with the output capacitor. The  
generated voltage ripple has two components: capacitive ripple caused by the inductor ripple current charging  
and discharging the output capacitor and resistive ripple caused by the inductor ripple current flowing into the  
output capacitor and through series resistance RESR. The capacitive ripple component is out of phase with the  
inductor current and does not decrease monotonically during the off time. The resistive ripple component is  
in-phase with the inductor current and decreases monotonically during the off time. The resistive ripple must  
exceed the capacitive ripple at VOUT for stable operation. If this condition is not satisfied, unstable switching  
behavior is observed in COT converters, with multiple on-time bursts in close succession followed by a long off  
time. Equation 2 and Equation 3 define the value of the series resistance RESR to ensure sufficient in-phase  
ripple at the feedback node.  
Type-2 ripple generation uses a CFF capacitor in addition to the series resistor. As the output voltage ripple is  
directly AC-coupled by CFF to the feedback node, the RESR and ultimately the output voltage ripple, are reduced  
by a factor of VOUT / VFB1  
.
Type-3 ripple generation uses an RC network consisting of RA and CA, and the switch node voltage to  
generate a triangular ramp that is in-phase with the inductor current. This triangular wave is the AC-coupled  
into the feedback node with capacitor CB. Since this circuit does not use output voltage ripple, it is suited for  
applications where low output voltage ripple is critical. The AN-1481 Controlling Output Ripple and Achieving  
ESR Independence in Constant On-time (COT) Regulator Designs Application Note provides additional details  
on this topic.  
Light load mode operation can be set to PFM and DEM operation or FPWM operation as a factory option.  
Diode Emulation mode (DEM) prevents negative inductor current, and pulse skipping maintains the highest  
efficiency at light load currents by decreasing the effective switching frequency. DEM operation occurs when the  
synchronous power MOSFET switches off as inductor valley current reaches zero. Here, the load current is less  
than half of the peak-to-peak inductor current ripple in CCM. Turning off the low-side MOSFET at zero current  
reduces switching loss, and prevents negative current conduction reduces conduction loss. Power conversion  
efficiency is higher in a DEM converter than an equivalent Forced-PWM CCM converter. With DEM operation,  
the duration that both power MOSFETs remain off progressively increases as load current decreases. When this  
idle duration exceeds 15 μs, the converter transitions into an ultra-low IQ mode, consuming only 10-μA quiescent  
current from the input. In FPWM operation, the DEM feature is turned off. This means that the device remains in  
CCM under light loads, and the device is capable of operating in a fly-buck configuration.  
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8.3.2 Internal VCC Regulator and Bootstrap Capacitor  
The LM516x-Q1 contains an internal linear regulator that is powered from VIN with a nominal output of 5  
V, eliminating the need for an external capacitor to stabilize the linear regulator. The internal VCC regulator  
supplies current to internal circuit blocks, including the synchronous FET driver and logic circuits. The input pin  
(VIN) can be connected directly to line voltages up to 120 V. Since the power MOSFET has a low total gate  
charge, use a low bootstrap capacitor value to reduce the stress on the internal regulator. It is required to select  
a high-quality 2.2-nF 50-V X7R ceramic bootstrap capacitor as specified in the Absolute Maximum Ratings.  
Selecting a higher value capacitance stresses the internal VCC regulator and damages the device. A lower  
capacitance than required is not sufficient to drive the internal gate of the power MOSFET. An internal diode  
connects from the VCC regulator to the BST pin to replenish the charge in the high-side gate drive bootstrap  
capacitor when the SW voltage is low.  
8.3.3 Internal Soft Start  
The LM516x-Q1 employs an internal soft-start control ramp that allows the output voltage to gradually reach  
a steady-state operating point, thereby reducing start-up stresses and current surges. The soft-start feature  
produces a controlled, monotonic output voltage start-up. The soft-start time is internally set to 3 ms.  
8.3.4 On-Time Generator  
The on time of the LM516x-Q1 high-side FET is determined by the RT resistor and is inversely proportional to  
the input voltage, VIN. The inverse relationship with VIN results in a nearly constant frequency as VIN is varied.  
Use Equation 10 to calculate the on time.  
R
kΩ  
T
t
µs =  
(10)  
ON  
V
V *2.5  
IN  
Use Equation 11 to determine the RT resistor to set a specific switching frequency in CCM.  
2500*V  
V
OUT  
kHz  
R
kΩ =  
(11)  
T
F
SW  
Select RT for a minimum on time (at maximum VIN) greater than 50 ns for proper buck operation and greater  
than 100 ns for proper fly-buck operation. In addition to this minimum on time, the maximum frequency for this  
device is limited to 1 MHz.  
8.3.5 Current Limit  
The PFM variant of the LM516x-Q1 manages overcurrent conditions with cycle-by-cycle current limiting of the  
peak inductor current. The current sensed in the high-side MOSFET is compared every switching cycle to the  
current limit threshold (0.84 A or 0.42 A). To protect the converter from potential current runaway conditions,  
the LM516x-Q1 includes a foldback valley current limit feature, set at 0.67 A for the LM5169-Q1 and 0.34 A for  
LM5168-Q1, that is enabled if a peak current limit is detected. As shown in Figure 8-1, if the peak current in  
the high-side MOSFET exceeds 0.84 A for the LM5169-Q1 and 0.42 A for the LM5168-Q1 (typical), the present  
cycle is immediately terminated regardless of the programmed on time (tON), the high-side MOSFET is turned  
off and the foldback valley current limit is activated. The low-side MOSFET remains on until the inductor current  
drops below this foldback valley current limit, after which the next on-pulse is initiated. This method folds back  
the switching frequency to prevent overheating and limits the average output current to less than 0.65 A for  
LM5169-Q1 and 0.3 A for LM5168-Q1 to ensure proper short-circuit and heavy-load protection.  
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vFB  
VREF  
iL  
Peak ILIM  
Valley ILIM  
IAVG(ILIM)  
IAVG1  
t
tON  
tSW  
< tON  
> tSW  
Figure 8-1. Current Limit Timing Diagram  
Current is sensed after a leading-edge blanking time following the high-side MOSFET turnon transition. The  
propagation delay of the current limit comparator is 100 ns. During high step-down conditions when the on-time  
is less than 100 ns, a back-up peak current limit comparator in the low-side FET also set at 0.84 A, or 0.42 A  
enables the foldback valley current limit set at 0.67 A or 0.34 A. This innovative current limit scheme enables  
ultra-low duty-cycle operation, permitting large step-down voltage conversions while ensuring robust protection  
of the converter.  
The FPWM variant of the device implements a current limit off-timer and hiccup protection. If the current in the  
high-side MOSFET exceeds IHS_PK(OC), the high-side MOSFET is immediately turned off and a non-resettable  
off-timer is initiated. The length of the off time is controlled by the feedback voltage and the input voltage. The  
off-timer ensures safe short circuit operation in fly-buck configuration. An overload current on the secondary  
output can result in the secondary voltage collapsing while the primary voltage remains in regulation. This results  
in a possible condition where the secondary output voltage will not recover after the overload condition. Hiccup  
protection ensures a soft-start counter will enable both the secondary and primary output voltages to recover  
properly after an overcurrent event is detected for 16 consecutive current limit cycles. After four cycles without  
current limit detection, restart the hiccup protection counter. The LM516x-Q1 will attempt soft start after a "hiccup  
period" of 64 ms.  
8.3.6 N-Channel Buck Switch and Driver  
The LM516x-Q1 integrates an N-channel buck switch and associated floating high-side gate driver. The gate-  
driver circuit works in conjunction with an external bootstrap capacitor and an internal high-voltage bootstrap  
diode. A high-quality 2.2-nF, 50-V X7R ceramic capacitor connected between the BST and SW pins provides the  
voltage to the high-side driver during the buck switch on time. See Section 8.3.2 for limitations. During the off  
time, the SW pin is pulled down to approximately 0 V, and the bootstrap capacitor charges from the internal VCC  
through the internal bootstrap diode. The minimum off-timer, set to 50 ns (typical), ensures a minimum time each  
cycle to recharge the bootstrap capacitor. When the on time is less than 300 ns, the minimum off-timer is forced  
to 250 ns to ensure that the BST capacitor is charged in a single cycle. This is vital during wakeup from Sleep  
mode when the BST capacitor is most likely discharged.  
8.3.7 Synchronous Rectifier  
The LM516x-Q1 provides an internal low-side synchronous rectifier N-channel MOSFET. This MOSFET provides  
a low-resistance path for the inductor current to flow when the high-side MOSFET is turned off.  
The synchronous rectifier operates in a Diode Emulation mode. Diode emulation enables the regulator to  
operate in a Pulse-skipping mode during light load conditions. This mode leads to a reduction in the average  
switching frequency at light loads. Switching losses and FET gate driver losses, both of which are proportional to  
switching frequency, are significantly reduced at very light loads and efficiency is improved. This Pulse-skipping  
mode also reduces the circulating inductor current and losses associated with conventional CCM at light loads.  
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8.3.8 Enable/Undervoltage Lockout (EN/UVLO)  
The LM516x-Q1 contains a dual-level EN/UVLO circuit. When the EN/UVLO voltage is below 1.1 V (typical), the  
converter is in a low-current Shutdown mode and the input quiescent current (IQ) is dropped down to 3 µA. When  
the voltage is greater than 1.1 V but less than 1.5 V (typical), the converter is in Standby mode. In Standby  
mode, the internal bias regulator is active while the control circuit is disabled. When the voltage exceeds the  
rising threshold of 1.5 V (typical), normal operation begins. Install a resistor divider from VIN to GND to set  
the minimum operating voltage of the regulator. Use Equation 12 and Equation 13 to calculate the input UVLO  
turn-on and turn-off voltages, respectively.  
≈
’
÷
◊
RUV1  
RUV2  
V
= 1.5V ∂ 1+  
∆
IN(on)  
«
(12)  
≈
’
÷
◊
RUV1  
RUV2  
V
= 1.4V ∂ 1+  
∆
IN(off)  
«
(13)  
TI recommends selecting RUV1 in the range of 1 MΩ for most applications. A larger RUV1 consumes less DC  
current, which is mandatory if light-load efficiency is critical. If input UVLO is not required, the power-supply  
designer can either drive EN/UVLO as an enable input driven by a logic signal or connect it directly to VIN.  
If EN/UVLO is directly connected to VIN, the regulator begins switching as soon as the internal bias rails are  
active.  
8.3.9 Power Good (PGOOD)  
The LM516x-Q1 provides a PGOOD flag pin to indicate when the output voltage is within the regulation level.  
Use the PGOOD signal for start-up sequencing of downstream converters or for fault protection and output  
monitoring. PGOOD is an open-drain output that requires a pullup resistor to a DC supply not greater than 14  
V. The typical range of pullup resistance is 10 kΩ to 100 kΩ. If necessary, use a resistor divider to decrease the  
voltage from a higher voltage pullup rail. When the FB voltage exceeds 95% of the internal reference VREF, the  
internal PGOOD switch turns off and PGOOD can be pulled high by the external pullup. If the FB voltage falls  
below 90% of VREF, an internal 7-Ω PGOOD switch turns on and PGOOD is pulled low to indicate that the output  
voltage is out of regulation. The rising edge of PGOOD has a built-in deglitch delay of 5 µs.  
8.3.10 Thermal Protection  
The LM516x-Q1 includes an internal junction temperature monitor to protect the device in the event of a higher  
than normal junction temperature. If the junction temperature exceeds 175°C (typical), thermal shutdown occurs  
to prevent further power dissipation and temperature rise. The LM516x-Q1 initiates a restart sequence when  
the junction temperature falls to 165°C, based on a typical thermal shutdown hysteresis of 10°C. This is a  
non-latching protection, so the device cycles into and out of thermal shutdown if the fault persists.  
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8.4 Device Functional Modes  
8.4.1 Shutdown Mode  
EN/UVLO provides ON and OFF control for the LM516x-Q1. When VEN/UVLO is below approximately 0.45 V,  
the device is in Shutdown mode. Both the internal linear regulator and the switching regulator are off. The  
quiescent current in Shutdown mode drops to 3 µA at VIN = 24 V. The LM516x-Q1 also employs internal bias rail  
undervoltage protection. If the internal bias supply voltage is below the UV threshold, the regulator remains off.  
8.4.2 Active Mode  
The LM516x-Q1 is in Active mode when VEN/UVLO is above the precision enable threshold and the internal bias  
rail is above its UV threshold. In COT Active mode, the LM516x-Q1 is in one of the following modes depending  
on the load current:  
1. CCM with fixed switching frequency when load current is above half of the peak-to-peak inductor current  
ripple  
2. Auto Mode – Light Load Operation: Pulse skipping and Diode Emulation mode (DEM) when the load current  
is less than half of the peak-to-peak inductor current ripple in CCM operation  
3. FPWM Mode – Light Load Operation: Continuous Conduction mode (CCM) throughout the entire load  
current range, including when the load current is lower than half of the inductor current ripple  
4. Current limit CCM with peak and valley current limit protection when an overcurrent condition is applied at  
the output  
8.4.3 Sleep Mode  
Section 8.3.1 gives a brief introduction to the LM516x-Q1 diode emulation (DEM) feature. The converter enters  
DEM during light-load conditions when the inductor current decays to zero and the synchronous MOSFET is  
turned off to prevent negative current in the system. In the DEM state, the load current is lower than half of the  
peak-to-peak inductor current ripple and the switching frequency decreases when the load is further decreased  
as the device operates in a pulse skipping mode. A switching pulse is set when VFB drops below 1.2 V.  
As the frequency of operation decreases and VFB remains above 1.2 V (VREF) with the output capacitor sourcing  
the load current for greater than 15 µs, the converter enters an ultra-low IQ sleep mode to prevent draining the  
input power supply. The input quiescent current (IQ) required by the LM516x-Q1 decreases to 10 µA in Sleep  
mode, improving the light-load efficiency of the regulator. In this mode, all internal controller circuits are turned  
off to ensure very low current consumption by the device. Such low IQ renders the LM516x-Q1 as the best option  
to extend operating lifetime for off-battery applications. The FB comparator and internal bias rail are active to  
detect when the FB voltage drops below the internal reference VREF and the converter transitions out of Sleep  
mode into Active mode. There is a 9-µs wake-up delay from sleep to active states.  
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9 Application and Implementation  
Note  
Information in the following applications sections is not part of the TI component specification,  
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for  
determining suitability of components for their purposes, as well as validating and testing their design  
implementation to confirm system functionality.  
9.1 Application Information  
The LM516x-Q1 requires only a few external components to create a buck converter to step down from a wide  
range of supply voltages to a fixed output voltage. Several features are integrated in the device to meet system  
design requirements, including the following:  
•
•
•
•
•
Precision enable  
Input voltage UVLO  
Internal soft start  
Programmable switching frequency  
A PGOOD indicator  
To expedite and streamline the process of designing a LM516x-based converter, a comprehensive LM516x-Q1  
quick-start calculator tool is available for download to assist the designer with component selection for a given  
application. This tool is complemented by the availability of an evaluation module, PSPICE models, as well as  
TI’s WEBENCH® Power Designer.  
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9.2 Typical Application  
The LM516x-Q1 "F" version is designed for fly-buck applications by operating in FPWM mode. Figure 9-1 shows  
the schematic for a 10-V output fly-buck regulator with a 10-V auxiliary output, capable of delivering 300 mA from  
each output, used as an example application. Note that the secondary output ground can be floating with respect  
to the input supply ground. See Table 9-1 for a description of fly-buck terminology used in the this example.  
VOUT2  
COUT2  
22 µF  
RPL  
1 k  
T1  
LM5169  
1:1  
VIN  
EN  
VIN  
SW  
VOUT1  
33 µ H  
CA  
118 k  
CIN  
2.2 µF  
COUT1  
22µF  
RA  
BST  
RFBT  
56 pF  
CB  
453 k  
FB  
RT  
RFBB  
RT  
33.2 k  
GND  
PGOOD  
61.9 k  
Figure 9-1. Example Application Circuit  
Table 9-1. Fly-buck Terminology  
TERM  
DESCRIPTION  
Primary output voltage, as for a buck regulator. This output is tightly  
regulated by the LM516x-Q1.  
VOUT1  
Secondary output voltage from couple inductor secondary winding.  
This voltage is not tightly regulated, but depends on parasitic voltage  
drops on the primary and secondary sides.  
VOUT2  
IOUT1  
IOUT2  
Primary output current, as for a buck regulator  
Secondary output current from coupled inductor secondary winding  
Note  
In this data sheet, the effective value of capacitance is defined as the actual capacitance under  
D.C. bias and temperature, not the rated or nameplate values. Use high-quality, low ESR, ceramic  
capacitors with an X5R or better dielectric throughout. All high value ceramic capacitors have a  
large voltage coefficient in addition to normal tolerances and temperature effects. Under D.C. bias,  
the capacitance drops considerably. Large case sizes and higher voltage ratings are better in this  
regard. To help mitigate these effects, multiple capacitors can be used in parallel to bring the minimum  
effective capacitance up to the required value. This can also ease the RMS current requirements on  
a single capacitor. A careful study of bias and temperature variation of any capacitor bank must be  
made to ensure that the minimum value of effective capacitance is provided.  
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9.2.1 Design Requirements  
Table 9-2 lists the design requirements for this typical fly-buck application.  
Table 9-2. Detailed Design Parameters  
DESIGN PARAMETER  
EXAMPLE VALUE  
24 V  
Nominal input voltage  
Input voltage range  
Primary output voltage  
Secondary output voltage  
Primary output current  
Secondary output current  
Switching frequency  
20 V to 60 V (operational to 115 V)  
10 V  
10 V  
0.3 A  
0.3 A  
750 kHz  
9.2.2 Detailed Design Procedure  
9.2.2.1 Switching Frequency (RT)  
The switching frequency of the LM516x-Q1 is set by the on-time programming resistor connected to the RT pin.  
Equation 14 is used to calculate RT based on the desired switching frequency. For this example of 750 kHz, 33.2  
kΩ is used.  
VOUT 2500  
RT(K )=  
F
SW (kHz)  
(14)  
Note that at very low duty cycles, the 50-ns minimum controllable on time of the high-side MOSFET, tON(min)  
,
limits the maximum switching frequency. In CCM, tON(min) limits the voltage conversion step-down ratio for a  
given switching frequency. Use Equation 15 to calculate the minimum controllable duty cycle.  
DMIN = tON(min) ∂FSW  
(15)  
Ultimately, the choice of switching frequency for a given output voltage affects the available input voltage range,  
solution size, and efficiency. Use Equation 16 to calculate the maximum supply voltage for a given tON(min) to  
maintain the full switching frequency.  
VOUT  
V
=
IN(max)  
tON(min) ∂FSW  
(16)  
9.2.2.2 Transformer Selection  
For this fly-buck application, a coupled inductor (sometimes called a transformer) is required. The first step is to  
decide upon the turns ratio. In a fly-buck, the secondary output voltage is slightly less than the reflected primary  
output voltage scaled by the turns ratio. Equation 17 can be used to calculate the turns ratio for a given VOUT1  
and VOUT2. The nearest integer ratio should be selected. VOUT2 will be slightly less than calculated due to the  
secondary diode drop and other parasitic voltage drops in the secondary. Also, keep in mind that the secondary  
voltage is not fed back to the controller, and is, therefore, not well regulated. For this example, it is required that  
VOUT2 is equal to VOUT1, therefore, use a 1:1 turns ratio.  
VOUT2 N2  
≅
VOUT1 N1  
(17)  
Next, the primary inductance must be calculated. This is the same as calculating the inductance for an ordinary  
buck regulator, and is based on the desired primary ripple current. Typically, a ripple current of between 20% and  
40% of the primary current is used. Equation 18 gives the primary current in a fly-buck and Equation 19 gives  
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the required primary inductance. Using an input voltage of 24 V and the other parameters in Table 9-2, the user  
arrives at a value of 38 μH. A standard value of 33 μH for this example is selected. Although the inductance  
can be selected based on the maximum input voltage and lower values of K, a somewhat smaller value of  
inductance is used in this example to save space on the PCB.  
N2  
IPRI=IOUT1+IOUT2  
N1  
(18)  
(19)  
(VIN-VOUT1) VOUT1  
K IPRI FSW VIN  
L=  
where  
•
K = ripple current factor = 20% to 40%  
Finally, the maximum currents in the transformer must be checked. A transformer with a saturation current equal  
to or greater than the device current limit must be selected. Also, the maximum primary current, and, therefore,  
the output current, is limited by the current limit if the device. Equation 20 can be used to calculate the maximum  
output current for a given inductance and application parameters.  
The magnitude of the ripple current and peak current in the transformer are required to select the output  
capacitors. These are calculated using Equation 21 and Equation 22, respectively.  
1 (VIN-VOUT1) VOUT1  
IPRI-max= ICL  
-
2
L FSW  
VIN  
(20)  
where  
•
ICL = device current limit = IHS_PK(OC)  
(VIN-VOUT1) VOUT1  
ΔI=  
∙
L∙FSW  
VIN  
(21)  
(22)  
(VIN-VOUT1) VOUT1  
IPK=IPRI  
+
L FSW  
VIN  
9.2.2.3 Output Capacitor Selection  
The primary output capacitor, COUT1, can be selected using either Equation 23 or Equation 24. For this design,  
an output voltage ripple of 5 mV and a load transient of 0.2 V is used. From this, a ripple current of 0.34 A at 60  
V input, and a peak transformer current of 0.77 A at full load is calculated. The two output capacitor equations  
give values of 11 μF and 5 μF. Because of the large derating of ceramic capacitors, COUT1 = 1 × 22 μF is used.  
Keep in mind that the equations give the minimum capacitance value and in no case should the capacitance of  
COUT1 be less than 2.2 μF. More output capacitance can be used to improve load transient response. Also note  
that when using type III ripple injection, the actual ripple voltage appearing on the output can be kept small.  
I2PK  
2 VOUT1 ΔVO  
L
COUT  
>
(23)  
where  
•
•
IPK = peak transformer current from Equation 22  
ΔVO = output voltage load transient  
I
COUT  
>
8 FSW Vripple  
(24)  
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where  
•
•
ΔI = ripple current from Equation 21  
Vripple = ripple voltage on primary output  
COUT2 is selected using Equation 25. In this case, a ripple voltage on the secondary otuput of 20 mV is chosen.  
The minimum input voltage should be used in this equation. A value of 10 μF is calculated and 1 × 22 μF  
for COUT2 is selected. Again, the equation gives the minimum capacitance value and in no case should the  
capacitance of COUT2 be less than 2.2 μF.  
IOUT2 VOUT1  
COUT2  
>
Vripple2 VIN FSW  
(25)  
Both output capacitors should be X7R ceramics in a 1206 or 1210 case size, and rated for at least twice the  
output voltage.  
9.2.2.4 Secondary Output Diode  
The secondary output diode must block the maximum input voltage reflected to the secondary by the transformer  
turns ratio. Equation 26 is used to determine the maximum reverse voltage on the diode. For this example, a  
value of 70 V is calculated and a 100-V diode is chosen. The diode current rating should be at least equal to  
the secondary output current with an appropriate factor of safety. Schottky diodes are the best choice for this  
application. Ultra-fast recovery diodes can also be used. In any case, choose a diode with the lowest turn-off  
time.  
N2  
VR>VIN  
+VOUT2  
N1  
(26)  
9.2.2.5 Regulation Comparator  
The LM516x-Q1 voltage regulation loop regulates the output voltage by maintaining the FB voltage equal to the  
internal reference voltage, VREF = 1.2 V (typ). A resistor divider programs the ratio from the output voltage VOUT1  
to VREF  
.
Equation 27 is used to calculate RFBT based on a selected RFBB  
.
VREF  
RFBT  
=
∙RFBB  
VOUT1-VREF  
(27)  
TI recommends selecting RFBB in the range of 10 kΩ to 1 MΩ for most applications. A larger RFBB consumes  
less DC current, which is mandatory if light-load efficiency is critical. RFBB larger than 1 MΩ is not recommended  
as the feedback path becomes more susceptible to noise. For this example, RFBB = 61.9 kΩ is chosen. This  
gives RFBT = 453 kΩ. It is important to route the feedback trace away from the noisy area of the PCB and keep  
the feedback resistors close to the FB pin.  
Note that in some schematics, the user may see RFB1 and RFB2; the correlation is as follows: RFB1 = RFBB and  
RFB2 = RFBT  
.
9.2.2.6 Input Capacitor  
The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying the ripple  
current and isolating switching noise from other circuits. A minimum of 2.2 µF of ceramic capacitance is required  
on the input of the LM516x-Q1 regulator, connected directly between VIN and GND. This must be rated for  
at least the maximum input voltage that the application requires; preferably twice the maximum input voltage.  
This capacitance can be increased to help reduce input voltage ripple and maintain the input voltage during  
load transients. More input capacitance is required for larger output currents. Keep in mind that the value of 2.2  
µF is the actual value after all derating is applied. For this example, 4 × 1-µF, 100-V, X7R (or better) ceramic  
capacitors are chosen due to voltage derating. If larger case size, higher voltage capacitors, or both can be  
used, then the total number may be reduced.  
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Many times, it is desirable to use an electrolytic capacitor on the input in parallel with the ceramics. This is  
especially true if long leads or traces (greater than about 5 cm) are used to connect the input supply to the  
regulator. The moderate ESR of this capacitor can help damp any ringing on the input supply caused by the  
long power leads. The use of this additional capacitor also helps with voltage dips caused by input supplies with  
unusually high impedance.  
Most of the input switching current passes through the ceramic input capacitor or capacitors. Use Equation 28  
to calculate the approximate RMS current. This value must be checked against the manufacturers' maximum  
ratings.  
IPRI  
IRMS  
2
(28)  
9.2.2.7 Type-3 Ripple Network  
A Type-3 ripple generation network uses an RC filter consisting of RA and CA across SW and VOUT1 to generate  
a triangular ramp that is in phase with the inductor current. This triangular ramp is then AC-coupled into the  
feedback node through capacitor CB. Type-3 ripple injection is suited for applications where low output voltage  
ripple is crucial, and is chosen for this example.  
Equation 29 is used to calculate CA. With the values used in this example, CA > 245 pF. A value of 3300 pF is  
selected to keep RA within practical limits. In general, the user needs 20 mV of ripple at the feedback pin for  
reliable operation, calculated at nominal input voltage. The minimum value of ripple should not be less than 12  
mV at minimum input voltage. Using Equation 30 with nominal input voltage, a value of RA > 117 kΩ was found  
and a value of 118 kΩ is selected.  
10  
CA  
FSW RFBB||RFBT  
(29)  
(VIN-VOUT1) VOUT1  
0.02 VIN FSW CA  
RA  
(30)  
While the magnitude of the generated ripple does not affect the output voltage ripple, it produces a DC error  
of approximately half the amplitude of the generated ripple, scaled by the feedback divider ratio. Therefore, the  
amount of DC offset, tolerable in the output voltage, imposes an upper bound on the feed-back ripple.  
Finally, Equation 31 is used to calculate the coupling capacitance CB. In the equation, TR is the approximate  
settling time of the control loop to a load transient disturbance. This was taken as 50 μs.  
TR  
CB  
3 RFBT  
(31)  
where  
TR = 50 μs (typ)  
•
In this example, a value of > 37 pF was calculated for CB and a value of 56 pF is selected. This value avoids  
excessive coupling capacitor discharge by the feedback resistors during sleep intervals when operating at light  
loads.  
9.2.2.8 Minimum Secondary Output Load  
The secondary output should have a "dummy" load connected at all times to prevent the output voltage from  
rising too high under certain conditions. Since the secondary output is not tightly regulated by the control  
loop, and because of transformer and diode parasitics, COUT2 can charge to high levels unless the energy is  
dissipated in the secondary output load. In this example, a 1-kΩ resistor is used as a minimum load on the  
secondary output. A Zener diode can also be used to clamp the secondary output voltage, if desired.  
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9.2.2.9 Example Design Summary  
The preceding design procedure is typical of the steps needed to create a fly-buck regulator with LM516x-Q1.  
Please see the LM5169FQEVM User's Guide for a more detailed BOM example. Also, the Designing an Isolated  
Fly-buck Converter Using the LMR36520 Application Note provides more information about designing fly-buck  
power stages.  
9.2.2.10 Thermal Considerations  
As with any power conversion device, the LM516x-Q1 dissipates internal power while operating. The effect  
of this power dissipation is to raise the internal temperature of the converter above ambient. The internal die  
temperature (TJ) is a function of the following:  
•
•
•
•
Ambient temperature  
Power loss  
Effective thermal resistance, RθJA, of the device  
PCB combination  
The maximum internal die temperature for the LM516x-Q1 must be limited to 150°C. This establishes a limit  
on the maximum device power dissipation and, therefore, the load current. Equation 32 shows the relationships  
between the important parameters. It is easy to see that larger ambient temperatures (TA) and larger values  
of RθJA reduce the maximum available output current. The converter efficiency can be estimated by using  
the curves provided in this data sheet. Note that these curves include the power loss in the inductor. If the  
desired operating conditions cannot be found in one of the curves, then interpolation can be used to estimate  
the efficiency. Alternatively, the EVM can be adjusted to match the desired application requirements and the  
efficiency can be measured directly. The correct value of RθJA is more difficult to estimate. As stated in the  
Semiconductor and IC Package Thermal Metrics Application Report, the value of RθJA given in the Thermal  
Information is not valid for design purposes and must not be used to estimate the thermal performance of the  
application. The values reported in that table were measured under a specific set of conditions that are rarely  
obtained in an actual application. The data given for RθJC(bott) and ΨJT can be useful when determining thermal  
performance. See the Semiconductor and IC Package Thermal Metrics Application Report for more information  
and the resources given at the end of this section.  
(
TJ - TA  
RqJA  
)
∂
h
1- h  
1
IOUT  
=
∂
MAX  
(
)
VOUT  
(32)  
where  
η = efficiency  
The effective RθJA is a critical parameter and depends on many factors such as the following:  
•
•
•
•
•
•
•
Power dissipation  
Air temperature/flow  
PCB area  
Copper heat-sink area  
Number of thermal vias under the package  
Adjacent component placement  
The LM516x-Q1 features a die attach paddle, or "thermal pad" (EP), to provide a place to solder down to the  
PCB heat-sinking copper. This provides a good heat conduction path from the regulator junction to the heat sink  
and must be properly soldered to the PCB heat sink copper. Typical examples of RΘJA can be found in Figure  
9-2. The copper area given in the graph is for each layer. The top and bottom layers are 2-oz. copper each, while  
the inner layers are 1 oz. Remember that the data given in this graph is for illustration purposes only, and the  
actual performance in any given application depends on all of the previously mentioned factors.  
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65  
60  
55  
50  
45  
40  
35  
30  
25  
20  
15  
2L  
4L  
0
10  
20  
30  
40  
50  
60  
70  
80  
90  
100  
110  
Copper Area (cm2)  
Figure 9-2. Typical RΘJA Versus Copper Area  
To continue with the design example, assume that the user has an ambient temperature of 70ºC and wishes  
to estimate the required copper area to keep the device junction temperature below 125ºC, at full load. From  
the curves in Section 9.2.3, an efficiency of about 81% was found at an input voltage of 24 V and 0.3 A from  
both primary and secondary outputs. The efficiency will be somewhat less at high junction temperatures, so an  
efficiency of approximately 79% is assumed. This gives a total loss of about 1.59 W. Subtract out the copper loss  
of the inductor, and arrive at a device dissipation of about 1.37 W. With this information, the user can calculate  
the required RθJA of about 40ºC/W. Based on Figure 9-2 the required copper area is about 18 cm2 to 20 cm2, for  
a two-layer PCB. For details of this calculation, please see the PCB Thermal Design Tips for Automotive DC/DC  
Converters Application Note.  
The following resources can be used as a guide to optimal thermal PCB design and estimating RθJA for a given  
application environment:  
•
•
•
•
•
Semiconductor and IC Package Thermal Metrics Application Report  
AN-2020 Thermal Design By Insight, Not Hindsight Application Report  
A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages Application Report  
Using New Thermal Metrics Application Report  
PCB Thermal Design Tips for Automotive DC/DC Converters Application Report  
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9.2.3 Application Curves  
The curves in this section we taken on the LM5169FQEVM. Unless otherwise specified the following conditions  
apply: VIN = 24 V, TA = 25°C. For a detailed schematic and BOM, see the LM5169FQEVM User's Guide.  
10.08  
10.078  
10.076  
10.074  
10.072  
10.07  
10.24  
10.2  
10.16  
10.12  
10.08  
10.04  
10  
100  
95  
90  
85  
80  
75  
70  
65  
60  
55  
10.068  
10.066  
10.064  
10.062  
10.06  
9.96  
9.92  
9.88  
9.84  
Primary Output  
Secondary Output  
24V  
48V  
60V  
0
0.05  
0.1  
0.15  
0.2  
0.25  
0.3  
0.35  
0.4  
Primary Output Current (A)  
0
0.05  
0.1  
0.15  
0.2  
0.25  
0.3  
0.35  
0.4  
Output Current (A)  
VOUT1 = VOUT2 = 10 V  
Primary DCR = 0.62A  
IOUT1 = IOUT2 FSW = 750 kHz  
VIN = 24 V  
IOUT2 = 10 mA  
Figure 9-4. Load Regulation vs Primary Load  
Current  
Figure 9-3. Efficiency  
10.11  
10.105  
10.1  
10.2  
10  
10.128  
10.126  
10.124  
10.122  
10.12  
9.7  
9.6  
9.5  
9.4  
9.3  
9.2  
9.1  
9
9.8  
9.6  
9.4  
9.2  
9
10.095  
10.09  
10.085  
10.08  
10.075  
10.07  
10.118  
10.116  
10.114  
10.112  
10.11  
8.9  
8.8  
8.7  
Primary Output Voltage  
Secondary Output Voltage  
8.8  
8.6  
Primary Output Voltage  
Secondary Output Voltage  
10.108  
0
0.05  
0.1  
0.15  
0.2  
0.25  
0.3  
0.35  
20  
30  
40  
50  
60  
70  
80  
90  
100 110  
Secondary Output Current (A)  
Input Voltage (V)  
VIN = 24 V  
IOUT1 =0.3 A  
VIN = 24 V  
IOUT1 = IOUT2 = 0.3 A  
Figure 9-5. Load Regulation vs Secondary Load  
Current  
Figure 9-6. Line Regulation  
EN  
EN  
0
0
Primary Output  
Primary Output  
5V/div  
5V/div  
Secondary Output  
Secondary Output  
10V/div  
10V/div  
0
0
Inductor  
Current  
0.5A/div  
Inductor  
Current  
1A/div  
800µ s/div  
2ms/div  
0
0
VIN = 24 V  
IOUT1 = IOUT2 = 10 mA  
VIN = 24 V  
IOUT1 = IOUT2 = 10 mA  
Figure 9-7. Light Load Start-Up from EN  
Figure 9-8. Full Load Start-Up from EN  
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Secondary  
Output  
500mV/div  
Secondary  
Output  
2V/div  
0
0
0
0
Primary  
Output  
50mV/div  
Primary  
Output  
100mV/div  
Primary  
Output  
Current  
Secondary  
Output  
Current  
200mA/div  
200mA/div  
200µs/div  
200µs/div  
0
0
VIN = 24 V  
IOUT2 = 10 mA  
VIN = 24 V  
IOUT1 = 10 mA  
Figure 9-9. Load Transient on Primary Output  
Figure 9-10. Load Transient on Secondary Output  
Short Removed  
Short Trigger  
Short Removed  
Short Trigger  
0
0
0
Primary  
Output  
5V/div  
Primary  
Output  
5V/div  
Secondary  
Output  
10V/div  
Secondary  
Output  
10V/div  
0
Inductor  
Current  
1A/div  
Inductor  
Current  
500mA/div  
0
40ms/div  
40ms/div  
0
VIN = 24 V  
IOUT2 = 10 mA  
VIN = 24 V  
IOUT1 = 0.3 A  
Figure 9-11. Short Circuit on Primary Output  
Figure 9-12. Short Circuit on Secondary Output  
SW, 20V/div  
Primary Output  
20mV/div  
0
SEC, 20V/div  
0
Secondary Output  
20mV/div  
Pri. Current, 500mA/div  
0
400ns/div  
1µ s/div  
VIN = 24 V  
IOUT = IOUT2 = 0.2 A  
VIN = 24 V  
IOUT = IOUT2 = 0.2 A  
Figure 9-13. Typical Switching Waveforms  
Figure 9-14. Typical Output Ripple  
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10 Power Supply Recommendations  
The LM516x-Q1 buck converter is designed to operate from a wide input voltage range between 6 V and  
120 V. The characteristics of the input supply must be compatible with the Absolute Maximum Ratings and  
Recommended Operating Conditions tables. In addition, the input supply must be capable of delivering the  
required input current to the fully loaded regulator. Use Equation 33 to estimate the average input current.  
VOUT ∂IOUT  
IIN  
=
V ∂ h  
IN  
(33)  
where  
•
η = efficiency  
If the converter is connected to an input supply through long wires or PCB traces with a large impedance,  
take special care to achieve stable performance. The parasitic inductance and resistance of the input cables  
can have an adverse affect on converter operation. The parasitic inductance in combination with the low-ESR  
ceramic input capacitors form an under-damped resonant circuit. This circuit can cause overvoltage transients  
at VIN each time the input supply is cycled ON and OFF. The parasitic resistance causes the input voltage to  
dip during a load transient. If the converter is operating close to the minimum input voltage, this dip can cause  
false UVLO fault triggering and a system reset. The best way to solve such issues is to reduce the distance from  
the input supply to the regulator and use an aluminum electrolytic input capacitor in parallel with the ceramics.  
The moderate ESR of the electrolytic capacitor helps to damp the input resonant circuit and reduce any voltage  
overshoots. A 10-μF electrolytic capacitor with a typical ESR of 0.5 Ω provides enough damping for most input  
circuit configurations.  
An EMI input filter is often used in front of the regulator that, unless carefully designed, can lead to instability as  
well as some of the effects mentioned above. The Simple Success with Conducted EMI for DC-DC Converters  
Application Report provides helpful suggestions when designing an input filter for any switching regulator.  
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11 Layout  
11.1 Layout Guidelines  
PCB layout is a critical portion of good power supply design. There are several paths that conduct high slew-rate  
currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise and EMI or  
degrade the power supply performance.  
1. To help eliminate these problems, bypass the VIN pin to GND with a low-ESR ceramic bypass capacitor with  
a high-quality dielectric. Place CIN as close as possible to the LM516x-Q1 VIN and GND pins. Grounding for  
both the input and output capacitors must consist of localized top-side planes that connect to the GND pin  
and GND PAD.  
2. Minimize the loop area formed by the input capacitor connections to the VIN and GND pins.  
3. Locate the inductor close to the SW pin. Minimize the area of the SW trace or plane to prevent excessive  
capacitive coupling.  
4. Tie the GND pin directly to the power pad under the device and to a heat-sinking PCB ground plane.  
5. Use a ground plane in one of the middle layers as a noise shielding and heat dissipation path.  
6. Have a single-point ground connection to the plane. Route the ground connections for the feedback, and  
enable components to the ground plane. This prevents any switched or load currents from flowing in analog  
ground traces. If not properly handled, poor grounding results in degraded load regulation or erratic output  
voltage ripple behavior.  
7. Make VIN, VOUT, and ground bus connections as wide as possible. This reduces any voltage drops on the  
input or output paths of the converter and maximizes efficiency.  
8. Minimize trace length to the FB pin. Place both feedback resistors, RFB1 and RFB2, close to the FB pin. Place  
CFF (if used) directly in parallel with RFB1. If output set-point accuracy at the load is important, connect the  
VOUT sense at the load. Route the VOUT sense path away from noisy nodes and preferably through a layer  
on the other side of a grounded shielding layer.  
9. The RT pin is sensitive to noise. Thus, locate the RT resistor as close as possible to the device and route  
with minimal lengths of trace. The parasitic capacitance from RT to GND must not exceed 20 pF.  
10. Provide adequate heat sinking for the LM516x-Q1 to keep the junction temperature below 150°C. For  
operation at full rated load, the top-side ground plane is an important heat-dissipating area. Use an array  
of heat-sinking vias to connect the exposed pad to the PCB ground plane. If the PCB has multiple copper  
layers, these thermal vias must also be connected to inner layer heat-spreading ground planes.  
11.1.1 Compact PCB Layout for EMI Reduction  
Radiated EMI generated by high di/dt components relates to pulsing currents in switching converters. The larger  
the area covered by the path of a pulsing current, the more electromagnetic emission is generated. The key  
to minimizing radiated EMI is to identify the pulsing current path and minimize the area of that path. Figure  
11-1 denotes the critical switching loop of the buck converter power stage in terms of EMI. The topological  
architecture of a buck converter means that a particularly high di/dt current path exists in the loop comprising  
the input capacitor and the integrated MOSFETs of the LM516x-Q1, and it becomes mandatory to reduce the  
parasitic inductance of this loop by minimizing the effective loop area.  
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VIN  
VIN  
2
CIN  
LM516x  
High  
di/dt  
loop  
BST  
High-side  
NMOS  
Q1  
LO  
gate driver  
SW  
VOUT  
8
1
CO  
Q2  
Low-side  
NMOS  
gate driver  
GND  
GND  
Figure 11-1. Critical Current Loops in the Buck Converter  
The input capacitor provides the primary path for the high di/dt components of the current of the high-side  
MOSFET. Placing a ceramic capacitor as close as possible to the VIN and GND pins is the key to EMI reduction.  
Keep the trace connecting SW to the inductor as short as possible and just wide enough to carry the load  
current without excessive heating. Use short, thick traces or copper pours (shapes) for current conduction path  
to minimize parasitic resistance. Place the output capacitor close to the VOUT side of the inductor, and connect  
the return terminal of the capacitor to the GND pin and exposed PAD of the LM516x-Q1.  
11.1.2 Feedback Resistors  
Reduce noise sensitivity of the output voltage feedback path by placing the resistor divider close to the FB pin,  
rather than close to the load. This reduces the trace length of FB signal and noise coupling. The FB pin is the  
input to the feedback comparator, and as such, is a high impedance node sensitive to noise. The output node is  
a low impedance node, so the trace from VOUT to the resistor divider can be long if a short path is not available.  
Route the voltage sense trace from the load to the feedback resistor divider, keeping away from the SW node,  
the inductor, and VIN to avoid contaminating the feedback signal with switch noise, while also minimizing the  
trace length. This is most important when high feedback resistances greater than 100 kΩ are used to set the  
output voltage. Also, route the voltage sense trace on a different layer from the inductor, SW node, and VIN so  
there is a ground plane that separates the feedback trace from the inductor and SW node copper polygon. This  
provides further shielding for the voltage feedback path from switching noise sources.  
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11.2 Layout Example  
Figure 11-2 shows an example layout for the PCB top layer of a 2-layer board with essential components placed  
on the top side.  
Type 3 ripple  
injection  
Connect BST cap  
close to BST and SW  
Place FB resistors very  
close to FB & GND pins  
PGOOD  
connection  
Thermal vias under PAD  
Place resistor R8  
close to the RON pin  
GND  
Optional RC  
VOUT  
connection  
Connect ceramic  
input cap close to  
VIN and GND  
EN/UVLO  
connection  
connection snubber to  
reduce SW  
node ringing  
Figure 11-2. LM516x-Q1 PCB Layout Example  
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12 Device and Documentation Support  
12.1 Device Support  
12.1.1 Third-Party Products Disclaimer  
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT  
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES  
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER  
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.  
12.2 Documentation Support  
12.2.1 Related Documentation  
For related documentation see the following:  
•
•
•
•
•
Stability Analysis of COT Type-III Ripple Circuit  
Designing an Isolated Fly-buck Converter  
Design a Fly-buck Solution with Opto-coupler  
Designing an Isolated Fly-buck Converter Using the LMR36520  
Texas Instruments, Selecting an Ideal Ripple Generation Network for Your COT Buck Converter Application  
Report  
•
Texas Instruments, Valuing Wide VIN, Low-EMI Synchronous Buck Circuits for Cost-Effective, Demanding  
Applications White Paper  
•
•
•
Texas Instruments, An Overview of Conducted EMI Specifications for Power Supplies White Paper  
Texas Instruments, An Overview of Radiated EMI Specifications for Power Supplies White Paper  
Texas Instruments, 24-V AC Power Stage with Wide VIN Converter and Battery Gauge for Smart Thermostat  
Design Guide  
•
Texas Instruments, Accurate Gauging and 50-μA Standby Current, 13S, 48-V Li-ion Battery Pack Reference  
Design Guide  
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•
Texas Instruments, AN-2162: Simple Success with Conducted EMI from DC/DC Converters Application  
Report  
•
•
Texas Instruments, Powering Drones with a Wide VIN DC/DC Converter Application Report  
Texas Instruments, Using New Thermal Metrics Application Report  
12.3 Receiving Notification of Documentation Updates  
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on  
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For  
change details, review the revision history included in any revised document.  
12.4 Support Resources  
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight  
from the experts. Search existing answers or ask your own question to get the quick design help you need.  
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do  
not necessarily reflect TI's views; see TI's Terms of Use.  
12.5 Trademarks  
PowerPAD™ and TI E2E™ are trademarks of Texas Instruments.  
All trademarks are the property of their respective owners.  
12.6 Electrostatic Discharge Caution  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled  
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may  
be more susceptible to damage because very small parametric changes could cause the device not to meet its published  
specifications.  
12.7 Glossary  
TI Glossary  
This glossary lists and explains terms, acronyms, and definitions.  
13 Mechanical, Packaging, and Orderable Information  
The following pages include mechanical packaging and orderable information. This information is the most  
current data available for the designated devices. This data is subject to change without notice and revision of  
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.  
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PACKAGE OPTION ADDENDUM  
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PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
PLM5168FQDDARQ1  
ACTIVE SO PowerPAD  
DDA  
8
2500  
Non-RoHS &  
Non-Green  
Call TI  
Call TI  
-40 to 150  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
GENERIC PACKAGE VIEW  
DDA 8  
PowerPADTM SOIC - 1.7 mm max height  
PLASTIC SMALL OUTLINE  
Images above are just a representation of the package family, actual package may vary.  
Refer to the product data sheet for package details.  
4202561/G  
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY  
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD  
PARTY INTELLECTUAL PROPERTY RIGHTS.  
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate  
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standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you  
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TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either  
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Copyright © 2021, Texas Instruments Incorporated  

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