LM5175-Q1 [TI]

符合 AEC-Q100 标准的 42V 宽输入电压 4 开关同步降压/升压控制器;


型号：	LM5175-Q1
厂家：	TEXAS INSTRUMENTS
描述：	符合 AEC-Q100 标准的 42V 宽输入电压 4 开关同步降压/升压控制器开关控制器
文件：	总37页 (文件大小：1421K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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LM5175-Q1

ZHCSEX5 –APRIL 2016

LM5175-Q1 42V 宽 V_IN同步 4 开关降压-升压控制器

1 特性

3 说明

•

适用于汽车电子应用

具有符合 AEC-Q100 标准的下列结果：

LM5175-Q1 是一款同步四开关降压-升压 DC/DC 控制

器，能够将输出电压稳定在输入电压、高于输入电压或

者低于输入电压的某一电压值上。LM5175-Q1 可在

3.5V 至 42V 的宽输入电压范围内运行（最大值为

60V），支持各类应用。

–

器件温度 1 级：-40℃ 至 +125℃ 的环境运行温

度范围

器件人体模型 (HBM) 静电放电 (ESD) 分类等级

LM5175-Q1 在降压和升压工作模式下均采用电流模式

控制，以提供出色的负载和线路调节性能。开关频率可

通过外部电阻进行编程，并且可与外部时钟信号同步。

器件组件充电模式 (CDM) ESD 分类等级 C4B

•

单电感降压-升压控制器，用于升压/降压 DC/DC 转

换

•

宽 V_IN范围：3.5V 至 42V，最大值为 60V

灵活的 V_OUT范围：0.8V 至 55V

该器件还具有可编程软启动功能，并且提供诸如逐

周期电流限制、输入欠压锁定 (UVLO)、输出过压保护

(OVP) 和热关断等各类保护特性。此外，LM5175-Q1

特有可选择的连续导通模式 (CCM) 或断续导通模式

(DCM)、可选平均输入或输出电流限制、可降低峰值电

磁干扰 (EMI) 的可选扩展频谱以及应对持续过载情况

的可选断续模式保护。

V_OUT短路保护

高效降压-升压转换

可调开关频率

可选频率同步和抖动

集成 2A 金属氧化物半导体场效应晶体管

(MOSFET) 栅极驱动器

器件信息⁽¹⁾

•

逐周期电流限制和可选断续模式

可选输入或输出平均电流限制

可编程的输入欠压闭锁 (UVLO) 和软启动

电源正常和输出过压保护

订货编号

LM5175-Q1

封装

封装尺寸

HTSSOP-28

9.7mm x 4.4mm

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

可利用脉冲跳跃来选择连续导通模式 (CCM) 或断

续导通模式 (DCM)

4 简化电路原理图

V_IN

•

薄型小外形尺寸 (HTSSOP)-28 封装

VCC

V_OUT

BOOT1

HDRV1

EN/UVLO

Enable

2 应用

Power Good

PGOOD

•

汽车起停系统

SW1

LDRV1

备用电池和超级电容充电

工业 PC 用电源

USB 供电

SLOPE

CSG

LM5175-Q1

RT/SYNC

LDRV2

COMP

LED 照明

SW2

AGND

PGND

VCC

BOOT2

HDRV2

VOSNS

VCC

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNVSAD9

LM5175-Q1

ZHCSEX5 –APRIL 2016

www.ti.com.cn

8.3 Feature Description................................................. 14

8.4 Device Functional Modes........................................ 19

Application and Implementation ........................ 20

9.1 Application Information............................................ 20

9.2 Typical Application .................................................. 20

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

简化电路原理图........................................................ 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

7.1 Absolute Maximum Ratings ...................................... 4

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 6

7.6 Typical Characteristics.............................................. 9

Detailed Description ............................................ 12

8.1 Overview ................................................................. 12

8.2 Functional Block Diagram ....................................... 13

10 Power Supply Recommendations ..................... 27

11 Layout................................................................... 27

11.1 Layout Guidelines ................................................. 27

11.2 Layout Example .................................................... 28

12 器件和文档支持 ..................................................... 29

12.1 文档支持................................................................ 29

12.2 社区资源................................................................ 29

12.3 商标....................................................................... 29

12.4 静电放电警告......................................................... 29

12.5 Glossary................................................................ 29

13 机械、封装和可订购信息....................................... 29

13.1 Package Option Addendum .................................. 30

5 修订历史记录

日期

修订版本

注释

2016 年 4 月

最初发布版本

LM5175-Q1

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ZHCSEX5 –APRIL 2016

6 Pin Configuration and Functions

HTSSOP-28

PWP Package

Top View

EN/UVLO

VIN

SW1

HDRV1

BOOT1

LDRV1

BIAS

VISNS

MODE

DITH

RT/SYNC

SLOPE

VCC

PGND

LDRV2

BOOT2

HDRV2

SW2

LM5175-Q1

HTSSOP-28

COMP

AGND

VOSNS

ISNS(œ)

ISNS(+)

PGOOD

CSG

Pin Functions

DESCRIPTION

NO.

NAME

Enable pin. For EN/UVLO < 0.4 V, the LM5175-Q1 is in a low current shutdown mode. For 0.7 V < EN/UVLO <

1.23 V, the controller operates in standby mode in which the VCC regulator is enabled but the PWM controller is

not switching. For EN/UVLO > 1.23 V, the PWM function is enabled, provided VCC exceeds the VCC UV

threshold.

EN/UVLO

VIN

The input supply pin to the IC. Connect V_INto a supply voltage between 3.5 V and 42 V.

V_INsense input. Connect to the input capacitor.

VISNS

Mode = GND, DCM, Hiccup Disabled (Set R_MODEresistor

to GND = 0 Ω)

Mode = 1.00 V, DCM, Hiccup Enabled (Set R_MODEresistor

to GND = 49.9 kΩ)

MODE

Mode = 1.85 V, CCM, Hiccup Enabled (Set R_MODEresistor

to GND = 93.1 kΩ)

Mode = VCC, CCM, Hiccup Disabled (Set R_MODEresistor

to VCC = 0 Ω)

A capacitor connected between the DITH pin and AGND is charged and discharged with a 10 uA current source.

As the voltage on the DITH pin ramps up and down the oscillator frequency is modulated between –5% and +5%

of the nominal frequency set by the RT resistor. Grounding the DITH pin will disable the dithering feature. In the

external Sync mode, the DITH pin voltage is ignored.

DITH

Switching frequency programming pin. An external resistor is connected to the RT/SYNC pin and AGND to set

the switching frequency. This pin can also be used to synchronize the PWM controller to an external clock.

RT/SYNC

A capacitor connected between the SLOPE pin and AGND provides the slope compensation ramp for stable

current mode operation in both buck and boost mode.

SLOPE

Soft-start programming pin. A capacitor between the SS pin and AGND pin programs soft-start time.

Output of the error amplifier. An external RC network connected between COMP and AGND compensates the

regulator feedback loop.

COMP

AGND

Analog ground of the IC.

Feedback pin for output voltage regulation. Connect a resistor divider network from the output of the converter to

the FB pin.

LM5175-Q1

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Pin Functions (continued)

DESCRIPTION

NO.

NAME

VOSNS

V_OUTsense input. Connect to the output capacitor.

Input or Output Current Sense Amplifier inputs. An optional current sense resistor connected between ISNS(+)

and ISNS(–) can be located either on the input side or on the output side of the converter. If the sensed voltage

across the ISNS(+) and ISNS(-) pins reaches 50 mV, a slow Constant Current (CC) control loop becomes active

and starts discharging the soft-start capacitor to regulated the drop across ISNS(+) and ISNS(-) to 50 mV. Short

ISNS(+) and ISNS(-) together to disable this feature.

ISNS(–)

ISNS(+)

The negative or ground input to the PWM current sense amplifier. Connect directly to the low-side (ground) of

the current sense resistor.

CSG

The positive input to the PWM current sense amplifier.

PGOOD

Power Good open drain output. PGOOD is pulled low when FB is outside a 0.8 V ±10% regulation window.

SW2

SW1

The boost and the buck side switching nodes respectively.

HDRV2

HDRV1

Output of the high-side gate drivers. Connect directly to the gates of the high-side MOSFETs.

BOOT2

BOOT1

An external capacitor is required between the BOOT1, BOOT2 pins and the SW1, SW2 pins respectively to

provide bias to the high-side MOSFET gate drivers.

LDRV2

LDRV1

Output of the low-side gate drivers. Connect directly to the gates of the low-side MOSFETs.

PGND

VCC

Power ground of the IC. The high current ground connection to the low-side gate drivers.

Output of the VCC bias regulator. Connect capacitor to ground.

Optional input to the VCC bias regulator. Powering VCC from an external supply instead of V_INcan reduce

power loss at high V_IN. For V_BIAS> 8 V, the VCC regulator draws power from the BIAS pin. The BIAS pin voltage

must not exceed 40 V.

BIAS

The PowerPAD should be soldered to the analog ground. If possible, use thermal vias to connect to a PCB

ground plane for improved power dissipation.

PowerPAD™

7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾

MIN

–0.3

-0.3

–1

MAX

UNIT

VIN, EN/UVLO, VISNS, VOSNS, ISNS(+), ISNS(–)

BIAS

FB, SS, DITH, SLOPE, COMP

RT/SYNC

3.6

SW1, SW2

SW1, SW2 (20 ns transient)

VCC, MODE, PGOOD

LDRV1, LDRV2

–3.0

–0.3

–40

-65

8.5

BOOT1, HDRV1 with respect to SW1

BOOT2, HDRV2 with respect to SW2

BOOT1, BOOT2

CS, CSG

Maximum junction temperature⁽²⁾

0.3

150

°C

Storage temperature, T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

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7.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

±2000

±500

±750

V_(ESD)Electrostatic discharge

All pins

Corner pins

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

3.5

NOM

MAX

UNIT

V_IN

Input voltage range

BIAS

Bias supply voltage range

Output voltage range

V_OUT

0.8

EN/UVLO

Enable voltage range

ISNS(+), ISNS(-)

Average current sense common mode range

Operating temperature range⁽²⁾

Operating frequency range

T_J

–40

100

150

600

°C

F_sw

kHz

(1) Recommended Operating Conditions are conditions under the device is intended to be functional. For specifications and test conditions,

see Electrical Characteristics .

(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

7.4 Thermal Information

LM5175-Q1

THERMAL METRIC⁽¹⁾

HTSSOP (PWP)

UNIT

28 PINS

33.1

17.7

14.9

0.4

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

R_θJC(top)

R_θJB

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

14.7

1.1

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

LM5175-Q1

ZHCSEX5 –APRIL 2016

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7.5 Electrical Characteristics

Typical values correspond to T_J= 25°C. Minimum and maximum limits apply over the T_J= –40°C to 125°C junction

temperature range unless otherwise stated. V_IN= 24 V unless otherwise stated.⁽¹⁾⁽²⁾

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

SUPPLY CURRENT

I_Q

V_INshutdown current

V_INoperating current

V_EN/UVLO= 0 V

1.4

µA

V_EN/UVLO= 2 V, V_FB= 0.9 V

1.65

VCC

V_VCC(VIN)

V_UV(VCC)

Regulation voltage

V_BIAS= 0 V, VCC open

VCC increasing

6.95

3.11

7.35

3.27

160

7.88

3.43

VCC Undervoltage lockout

Undervoltage hysteresis

VCC current limit

I_VCC

V_VCC= 0 V

R_OUT(VCC)

BIAS

VCC regulator output impedance

I_VCC= 30 mA, V_IN= 3.5 V

9.3

V_BIAS(SW)

EN/UVLO

V_EN(STBY)

I_EN(STBY)

V_EN(OP)

ΔI_HYS(OP)

BIAS switchover voltage

V_IN= 24 V

7.25

8.75

Standby threshold

EN/UVLO rising

V_EN/UVLO= 1.1 V

EN/UVLO rising

V_EN/UVLO= 1.5 V

0.55

0.79

0.97

µA

Standby source current

Operating threshold

1.15

1.5

1.23

3.5

1.29

5.5

Operating hysteresis current

µA

I_SS

Soft-start pull up current

SS clamp voltage

FB to SS offset

V_SS= 0 V

SS open

V_SS= 0 V

4.0

5.65

1.27

-15

7.25

µA

V_SS(CL)

V_FB– V_SS

EA (ERROR AMPLIFIER)

V_REF

Feedback reference voltage

Error amplifier gm

FB = COMP

0.788

0.800

1.27

280

0.812

gm_EA

µA

I_SINK/I_SOURCECOMP sink/source current

V_FB=V_REF± 300 mV

R_OUT

Amplifier output resistance

Unity gain bandwidth

MΩ

MHz

I_BIAS(FB)

FREQUENCY

f_SW(1)

Feedback pin input bias current

FB in regulation

100

Switching Frequency 1

Switching Frequency 2

RT = 133 kΩ

RT = 47 kΩ

180

430

200

500

220

565

kHz

f_SW(2)

(1) All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and

applying statistical process control.

(2) The junction temperature (T_Jin °C) is calculated from the ambient temperature (T_Ain °C) and power dissipation (P_Din Watts) as follows:

T_J= T_A+ (P_D• R_θJA) where R_θJA(in °C/W) is the package thermal impedance provided in the Thermal Information section.

LM5175-Q1

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ZHCSEX5 –APRIL 2016

Electrical Characteristics (continued)

Typical values correspond to T_J= 25°C. Minimum and maximum limits apply over the T_J= –40°C to 125°C junction

temperature range unless otherwise stated. V_IN= 24 V unless otherwise stated.⁽¹⁾⁽²⁾

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

DITHER

I_DITHER

Dither source/sink current

Dither high threshold

Dither low threshold

10.5

1.27

1.16

µA

V_DITHER

SYNC

V_SYNC

Sync input high threshold

Sync input low threshold

Sync input pulse width

2.1

1.2

PW_SYNC

500

CURRENT LIMIT

V_CS(BUCK)

Buck current limit threshold (Valley)

V_IN= V_VISNS= 24 V, V_VOSNS= 12 V,

V_SLOPE= 0 V, T_J= 25°C

53.2

114

µA

V_CS(BOOST)

Boost current limit threshold (Peak)

V_IN= V_VISNS= 12 V, V_VOSNS= 24 V,

V_SLOPE= 0 V, T_J= 25°C

160

–75

202

I_BIAS(CS/CSG)

CS/CSG pin bias current

V_CS= V_CSG= 0 V

I_OFFSET(CS/CSCSG pin bias current

CONSTANT CURRENT LOOP

V_SNS

Average current loop regulation target

V_ISNS(-)= 24 V, sweep ISNS(+), V_SS

0.8 V

µA

I_SNS

ISNS(+)/ISNS(–) pin bias currents

gm of soft-start pull down amplifier

V_ISNS(+)= V_ISNS(–)= V_IN= 24 V

V_ISNS(+)–V_ISNS(–)= 50 mV, V_SS= 0.5

SLOPE

I_SLOPE

Buck adaptive slope current

Boost adaptive slope current

Slope compensation amplifier gm

V_VISNS= 24 V, V_VOSNS= 12 V, V_SLOPE

= 0 V

µA

V_VISNS= 12 V, V_VOSNS= 18 V, V_SLOPE

= 0 V

gm_SLOPE

MODE

µS

µA

I_MODE

Source current out of MODE pin

DCM with hiccup threshold

CCM with hiccup threshold

CCM no hiccup threshold

0.60

1.18

2.22

0.7

0.76

1.38

2.6

V_{DCM_HIC}

V_{CCM_HIC}

V_CCM

1.28

2.4

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Electrical Characteristics (continued)

Typical values correspond to T_J= 25°C. Minimum and maximum limits apply over the T_J= –40°C to 125°C junction

temperature range unless otherwise stated. V_IN= 24 V unless otherwise stated.⁽¹⁾⁽²⁾

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

PGOOD

V_PGD

PGOOD trip threshold for falling FB

PGOOD trip threshold for rising FB

Hysteresis

Measured with respect to V_REF

–9%

10%

I_LEAK(PGD)

I_SINK(PGD)

OUTPUT OVP

V_OVP

PGOOD leakage current

PGOOD sink current

100

6.5

V_PGOOD= 0.4 V

At the FB pin

4.2

Output overvoltage threshold

Hysteresis

0.86

NMOS DRIVERS

I_HDRV1,2

Driver peak source current

V_BOOT– V_SW= 7 V

1.8

2.2

Driver peak sink current

I_LDRV1,2

Driver peak source current

Driver peak sink current

1.8

2.2

R_HDRV1,2

Driver pull up resistance

V_BOOT– V_SW= 7 V

V_BOOT- V_SW= 7 V

HDRV1,2 shut off

1.9

Ω

Driver pull down resistance

BOOT1,2 to SW1,2 UVLO threshold

BOOT1,2 to SW1,2 UVLO hysteresis

1.3

V_UV(BOOT1,2)

2.73

280

HDRV1,2 start switching

BOOT1,2 to SW1,2 threshold for refresh

pulse

4.45

R_LDRV1,2

Driver pull up resistance

1.5

Ω

Driver pull down resistance

t_DT1

t_DT2

Dead time HDRV1,2 off to LDRV1,2 on

Dead time LDRV1,2 off to HDRV1,2 on

°C

THERMAL SHUTDOWN

T_SD

Thermal shutdown temperature

Thermal shutdown hysteresis

165

T_SD(HYS)

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ZHCSEX5 –APRIL 2016

7.6 Typical Characteristics

At T_A= 25°C, unless otherwise stated.

100

V_IN=6V

V_IN=12V

V_IN=24V

V_IN(V)

LOAD CURRENT (A)

D009

D008

V_OUT=12 V

I_OUT=3 A

Fsw=300 kHz

L1=4.7 μH

V_OUT=12 V

Fsw=300 kHz

L1=4.7 μH

Figure 1. Efficiency vs V_IN

Figure 2. Efficiency vs Load

600

500

400

300

200

100

150

R_T(kW)

200

250

300

VIN (V)

D002

D004

Figure 4. VCC vs V_IN

Figure 3. Oscillator Frequency

0.8

0.6

0.4

0.2

2.4

2.2

1.8

1.6

1.4

BIAS = 12V

BIAS = 0V

BIAS = 12V

BIAS = 0V

V_IN(V)

D006

D007

Figure 5. I_INStandby

Figure 6. I_INOperating vs V_IN

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Typical Characteristics (continued)

At T_A= 25°C, unless otherwise stated.

1.30

1.26

1.22

1.18

1.14

1.10

3.2

2.4

1.6

0.8

-40 °C

25 °C

125 °C

-40

-20

100 120 140

V_IN(V)

TEMPERATURE (°C)

D010

D013

Figure 7. I_INShutdown vs V_IN

Figure 8. ENABLE/UVLO Rising Threshold vs Temperature

110

100

200

190

180

170

160

150

140

-40

-20

100 120 140

-40

-20

100 120 140

TEMPERATURE (èC)

TEMPERATURE (°C)

D012

D011

Figure 9. Buck Current Limit vs Temperature

Figure 10. Boost Current Limit vs Temperature

0.805

{í1 (20ë/div)

0.803

0.801

0.799

0.797

0.795

{í2 (10ë/div)

ëhÜÇ (200më/div ac)

L[ (5!/div)

5 µs/div

-40

-20

100 120 140

VOUT=12 V

VIN=24 V

TEMPERATURE (°C)

D014

Figure 12. Forced CCM Operation (Buck)

Figure 11. V_REFvs Temperature

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Typical Characteristics (continued)

At T_A= 25°C, unless otherwise stated.

{í1 (20ë/div)

{í2 (10ë/div)

{í1 (20ë/div)

{í2 (10ë/div)

ëhÜÇ (200më/div ac)

L[ (5!/div)

ëhÜÇ (200më/div ac)

L[ (5!/div)

5 µs/div

500 µs/div

5 µs/div

VOUT=12 V

VIN=6 V

VOUT=12 V

VIN=12 V

Figure 13. Forced CCM Operation (Boost)

Figure 14. Forced CCM Operation (Buck-Boost)

ëhÜÇ (500më/div)

ëhÜÇ (500 më/div ac)

L[ (5!/div)

500 µs/div

VIN=6 V

VOUT=12 V

Load 2A to 4A

VIN=24 V

VOUT=12 V

Load 2A to 4A

Figure 16. Load Step (Boost)

Figure 15. Load Step (Buck)

ëhÜÇ (500më/div)

L[ (5!/div)

ëhÜÇ (1ë/div)

ꢀhat (1ë/div)

ëLb (10ë/div)

L[ (5!/div)

5ms/div

VIN=12 V

VOUT=12 V

Load 2A to 4A

VIN=8 V to 24 V

VOUT=12 V

I_OUT=1A

Figure 17. Load Step (Buck-Boost)

Figure 18. Line Transient

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Typical Characteristics (continued)

At T_A= 25°C, unless otherwise stated.

ëhÜÇ (5ë/div)

welease

hverload

Iiccup

L[ (5!/div)

20ms/div

VIN=24 V

VOUT=12 V

Hiccup Enabled

Figure 19. Hiccup Mode Current Limit

8 Detailed Description

8.1 Overview

The LM5175-Q1 is a wide input voltage four-switch buck-boost controller IC with integrated drivers for N-channel

MOSFETs. It operates in the buck mode when V_INis greater than V_OUTand in the boost mode when V_INis less

than V_OUT. When V_INis close to V_OUT, the device operates in a proprietary transition buck or boost mode. The

control scheme provides smooth operation for any input/output combination within the specified operating range.

The buck or boost transition control scheme provides a low ripple output voltage when V_INequals V_OUTwithout

compromising the efficiency.

The LM5175-Q1 integrates four N-Channel MOSFET drivers including two low-side drivers and two high-side

drivers, eliminating the need for external drivers or floating bias supplies. The internal VCC regulator supplies

internal bias rails as well as the MOSFET gate drivers. The VCC regulator is powered either from the input

voltage through the VIN pin or from the output or an external supply through the BIAS pin for improved efficiency.

The PWM control scheme is based on valley current mode control for buck operation and peak current mode

control for boost operation. The inductor current is sensed through a single sense resistor in series with the low-

side MOSFETs. The sensed current is also monitored for cycle-by-cycle current limit. The behavior of the

LM5175-Q1 during an overload condition is dependent on the MODE pin programming (see MODE Pin

Configuration). If hiccup mode fault protection is selected, the controller turns off after a fixed number of

switching cycles in cycle-by-cycle current limit and restarts after another fixed number of clock cycles. The hiccup

mode reduces the heating in the power components in a sustained overload condition. If hiccup mode is disabled

through the MODE pin, the controller remains in a cycle-by-cycle current limit condition until the overload is

removed. The MODE pin also selects continuous conduction mode (CCM) for noise sensitive applications or

discontinuous conduction mode (DCM) for higher light load efficiency.

In addition to the cycle-by-cycle current limiting, the LM5175-Q1 also provides an optional average current

regulation loop that can be configured for either input or output current limiting. This is useful for battery charging

or other applications where a constant current behavior may be required.

The soft-start time of LM5175-Q1 is programmed by a capacitor connected to the SS pin to minimize the inrush

current and overshoot during startup.

The precision EN/UVLO pin supports programmable input undervoltage lockout (UVLO) with hysteresis. The

output overvoltage protection (OVP) feature turns off the high-side drivers when the voltage at the FB pin is 7.5%

above the nominal 0.8-V V_REF. The PGOOD output indicates when the FB voltage is inside a ±10% regulation

window centered at V_REF

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8.2 Functional Block Diagram

VIN

BIAS

3.5 µA

EN/UVLO

VCC

1.23 V

OPERATING

STANDBY

EN & BIAS

LOGIC

1.5 µA

0.7 V

THERMAL

SHUTDOWN

45 mV

1.2 V

PGOOD

5 µA

0.88 V

0.86 V

ISNS(+)

ISNS(-)

0.72 V

1 mA/V

CONSTANT

CURRENT LOOP

BOOT1

HDRV1

3.3 V

GM ERROR

AMPLIFIER

PWM

COMPARATOR

1.6 V

0.8 V

SW1

VCC

LDRV1

COMP

AMPLIFIER

CLK

BUCK-BOOST CONTROLLER

LOGIC

BOOT2

HDRV2

A=5

ꢀ

ILIMIT

COMPARATOR

CSG

SW2

VCC

LDRV2

VISNS

VOSNS

SLOPE

ILIM

SLOPE

COMP

CCM/DCM

MODE

HICCUP CURRENT

LIMIT

RT/SYNC

DITH

OSC/SYNC

CLK

PGND

AGND

LM5175-Q1

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8.3 Feature Description

8.3.1 Fixed Frequency Valley/Peak Current Mode Control with Slope Compensation

The LM5175-Q1 implements a fixed frequency current mode control of both the buck and boost switches. The

output voltage, scaled down by the feedback resistor divider, appears at the FB pin and is compared to the

internal reference (V_REF) by an internal error amplifier. The error amplifier produces an error voltage by driving

the COMP pin. An adaptive slope compensation signal based on V_IN, V_OUT, and the capacitor at the SLOPE pin

is added to the current sense signal measured across the CS and CSG pins. The result is compared to the

COMP error voltage by the PWM comparator.

The LM5175-Q1 regulates the output using valley current mode control in buck mode and peak current mode

control in boost mode. For valley current mode control, the high-side buck MOSFET controlled by HDRV1 is

turned on by the PWM comparator at the valley of the inductor ripple current and turned off by the oscillator clock

signal. Valley current mode control is advantageous for buck converters where the PWM controller must resolve

very short on-times. For peak current mode control in the boost mode, the low-side boost MOSFET controlled by

LDRV2 is turned on by the clock signal in each switching cycle and turned off by the PWM comparator at the

peak of the inductor ripple current.

The low-side gate drive LDRV1, complementary to the HDRV1 drive signal, controls the synchronous rectification

MOSFET of the buck stage. The high-side gate drive HDRV2, complementary to the low-side gate drive LDRV2,

controls the high-side synchronous rectifier of the boost stage. For operation with V_INclose to V_OUT, the LM5175-

Q1 uses a proprietary buck or boost transition scheme to achieve smooth, low ripple transition zone behavior.

Peak and valley current mode controllers require slope compensation for stable current loop operation at duty

cycle greater than 50% in peak current mode control and less than 50% in valley current mode control. The

LM5175-Q1 provides a SLOPE pin to program optimum slope for any V_INand V_OUTcombination using an

external capacitor.

8.3.2 VCC Regulator and Optional BIAS Input

The VCC regulator provides a regulated 7.5-V bias supply to the gate drivers. When EN/UVLO is above the 0.7-

V (typical) standby threshold, the VCC regulator is turned on. For V_INless than 7.5 V, the VCC voltage tracks V_IN

with a small voltage drop as shown in Figure 4. If the EN/UVLO input is above the 1.23 V operating threshold

and VCC exceeds the 3.3 V (typical) VCC UV threshold, the controller is enabled and switching begins.

The VCC regulator draws power from V_INwhen there is no supply voltage connected to the BIAS pin. If the BIAS

pin is connected to an external voltage source that exceeds VCC by one diode drop, the VCC regulator draws

power from the BIAS input instead of V_IN. Connecting the BIAS pin to V_OUTin applications with V_OUTgreater than

8.5 V improves the efficiency of the regulator in the buck mode. The BIAS pin voltage should not exceed 36 V.

For low V_INoperation, ensure that the VCC voltage is sufficient to fully enhance the MOSFETs. Use an external

bias supply if V_INdips below the voltage required to sustain the VCC voltage. For these conditions, use a series

blocking diode between the input supply and the VIN pin (Figure 20). This prevents VCC from back-feeding into

V_INthrough the body diode of the VCC regulator.

A 1-µF capacitor to PGND is required to supply the VCC regulator load transients.

Series Blocking

Diode

VIN

C_VIN

LM5175-Q1

Optional

Bias Supply/

VOUT

BIAS

C_BIAS

VCC

C_VCC

Figure 20. VCC Regulator

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Feature Description (continued)

8.3.3 Enable/UVLO

The LM5175-Q1 has a dual function enable and undervoltage lockout (UVLO) circuit. The EN/UVLO pin has

three distinct voltage ranges: shutdown, standby, and operating (see Shutdown, Standby, and Operating Modes).

When the EN/UVLO pin is below the standby threshold (0.7 V typical), the converter is held in a low power

shutdown mode. When EN/UVLO voltage is greater than the standby threshold but less than the 1.23 V

operating threshold, the internal bias rails and the VCC regulator are enabled but the soft-start (SS) pin is held

low and the PWM controller is disabled. A 1.5 µA pull-up current is sourced out of the EN/UVLO pin in standby

mode to provide hysteresis between the shutdown mode and the standby mode. When EN/UVLO is greater than

the 1.23 V operating threshold, the controller commences operation if VCC is above VCC UV threshold (3.3 V). A

hysteresis current of 3.5 µA is sourced into the EN/UVLO pin when the EN/UVLO input exceeds the 1.23 V

operation threshold to provide hysteresis that prevents on/off chattering in the presence of noise with a slowly

changing input voltage.

The V_INundervoltage lockout turn-on threshold is typically set by a resistor divider from the VIN pin to AGND with

the mid-point of the divider connected to EN/UVLO. The turn-on threshold VIN_UVis calculated using Equation 1

where R_UV2is the upper resistor and R_UV1is the lower resistor in the EN/UVLO resistor divider:

≈

’

◊

R_UV2

R_UV1

= 1.23 V ì 1+

-R_UV2ì1.5 mA

∆

IN(UV)

(1)

The hysteresis between the UVLO turn-on threshold and turn-off threshold is set by the upper resistor in the

EN/UVLO resistor divider and is given by:

DV_HYS(UV)= 3.5 mA ìR_UV2

(2)

V_IN

LM5175-Q1

R_UV2

EN/UVLO

R_UV1

Figure 21. UVLO Threshold Programming

8.3.4 Soft-Start

The LM5175-Q1 soft-start time is programmed using a soft-start capacitor from the SS pin to AGND. When the

converter is enabled, an internal 5-µA current source charges the soft-start capacitor. When the SS pin voltage is

below the 0.8-V feedback reference voltage V_REF, the soft-start pin controls the regulated FB voltage. Once SS

exceeds V_REF, the soft-start interval is complete and the error amplifier is referenced to V_REF. The soft-start time

is given by Equation 3:

C_SSì 0.8 V

t_ss

5 mA

(3)

The soft-start capacitor is internally discharged when the converter is disabled because of EN/UVLO falling

below the operation threshold or VCC falling below the VCC UV threshold. The soft-start pin is also discharged

when the converter is in hiccup mode current limiting or in thermal shutdown. When average input or output

current limiting is active, the soft-start capacitor is discharged by the constant current loop transconductance

(gm) amplifier to limit either input or output current.

LM5175-Q1

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Feature Description (continued)

8.3.5 Overcurrent Protection

The LM5175-Q1 provides cycle-by-cycle current limit to protect against overcurrent and short circuit conditions.

In buck operation, the sensed valley voltage across the CSG and CS pins is limited to 76 mV. The high-side

buck switch skips a cycle if the sensed voltage does not fall below this threshold during the buck switch off time.

In boost operation, the maximum peak voltage across CS and CSG is limited to 160 mV. If the peak current in

the low-side boost switch causes the CS pin to exceed this threshold voltage, the boost switch is turned off for

the remainder of the clock cycle.

Applying the appropriate voltage to the MODE pin of the LM5175-Q1 enables hiccup mode fault protection (see

MODE Pin Configuration). In the hiccup mode, the controller shuts down after detecting cycle-by-cycle current

limiting for 128 consecutive cycles and the soft-start capacitor is discharged. The soft-start capacitor is

automatically released after 4000 oscillator clock cycles and the controller restarts. If hiccup mode protection is

not enabled through the MODE pin, the LM5175-Q1 will operate in cycle-by-cycle current limiting as long as the

overload condition persists.

8.3.6 Average Input/Output Current Limiting

The LM5175-Q1 provides optional average current limiting capability to limit either the input or the output current

of the DC/DC converter. The average current limiting circuit uses an additional current sense resistor connected

in series with the input supply or output voltage of the converter. A current sense gm amplifier with inputs at the

ISNS(+) and ISNS(-) pins monitors the voltage across the sense resistor and compares it with an internal 50 mV

reference. If the drop across the sense resistor is greater than 50 mV, the gm amplifier gradually discharges the

soft-start capacitor. When the soft-start capacitor discharges below the 0.8-V feedback reference voltage V_REF

the output voltage of the converter decreases to limit the input or output current. The average current limiting

feature can be used in applications requiring a regulated current from the input supply or into the load. The target

constant current is given by Equation 4:

50 mV

I_CL(AVG)

R_SNS

(4)

The average current loop can be disabled by shorting the ISNS(+) and ISNS(-) pins together.

8.3.7 CCM/DCM Operation

The LM5175-Q1 allows selection of continuous conduction mode (CCM) or discontinuous conduction mode

(DCM) operation using the MODE pin (see MODE Pin Configuration). In CCM operation the inductor current can

flow in either direction and the controller switches at a fixed frequency regardless of the load current. This mode

is useful for noise-sensitive applications where a fixed switching eases filter design. In DCM operation the

synchronous rectifier MOSFETs emulate diodes as LDRV1 or HDRV2 turn-off for the remainder of the PWM

cycle when the inductor current reaches zero. The DCM mode results in reduced frequency operation at light

loads, which lowers switching losses and increases light load efficiency of the converter.

8.3.8 Frequency and Synchronization (RT/SYNC)

The LM5175-Q1 switching frequency can be programmed between 100 kHz and 600 kHz using a resistor from

the RT/SYNC pin to AGND. The R_Tresistor is related to the nominal switching frequency (F_sw) by the following

equation:

≈

∆

’

- 200 ns

^sw◊

R_T

37 pF

(5)

Figure 3 in the Typical Characteristics shows the relationship between the programmed switching frequency (F_sw)

and the R_Tresistor.

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Feature Description (continued)

The RT/SYNC pin can also be used for synchronizing the internal oscillator to an external clock signal. The

external synchronization pulse is ac coupled using a capacitor to the RT/SYNC pin. The voltage at the RT/SYNC

pin must not exceed 3.3 V peak. The external synchronization pulse frequency should be higher than the

internally set oscillator frequency and the pulse width should be between 75 ns and 500 ns.

LM5175-Q1

RT/SYNC

external SYNC

C_SYNC

R_T

Figure 22. Using External SYNC

8.3.9 Frequency Dithering

The LM5175-Q1 provides an optional frequency dithering function that is enabled by connecting a capacitor from

DITH to AGND. Figure 23 illustrates the dithering circuit. A triangular waveform centered at 1.22 V is generated

across the C_DITHcapacitor. This triangular waveform modulates the oscillator frequency by ±5% of the nominal

frequency set by the R_Tresistor. The C_DITHcapacitance value sets the rate of the low frequency modulation. A

lower C_DITHcapacitance will modulate the oscillator frequency at a faster rate than a higher capacitance. For the

dithering circuit to effectively reduce peak EMI, the modulation rate must be much less than the oscillator

frequency (F_sw). Equation 6 calculates the DITH pin capacitance required to set the modulation frequency, F_MOD

Connecting the DITH pin directly to AGND disables frequency dithering, and the internal oscillator operates at a

fixed frequency set by the RT resistor. Dither is disabled when external SYNC is used.

10 mA

F_MODì0.24 V

C_DITH

(6)

1.22 V + 5%

1.22 V

LM5175-Q1

1.22 V œ 5%

DITH

C_DITH

Figure 23. Dither Operation

8.3.10 Output Overvoltage Protection (OVP)

The LM5175-Q1 provides an output overvoltage protection (OVP) circuit that turns off the gate drives when the

feedback voltage is 7.5% above the 0.8 V feedback reference voltage V_REF. Switching resumes once the output

falls within 5% of V_REF

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Feature Description (continued)

8.3.11 Power Good (PGOOD)

PGOOD is an open drain output that is pulled low when the voltage at the FB pin is outside –9% / +10% of the

nominal 0.8-V reference voltage. The PGOOD internal N-Channel MOSFET pull-down strength is typically 4.2

mA. This pin can be connected to a voltage supply of up to 8 V through a pull-up resistor.

8.3.12 Gm Error Amplifier

The LM5175-Q1 has a gm error amplifier for loop compensation. The gm amplifier output (COMP) range is 0.3 V

to 3 V. Connect an R_c1-C_c1compensation network between COMP and ground for type II (PI) compensation (see

Figure 24). Another pole is usually added using C_c2to suppress higher frequency noise.

The COMP output voltage (V_COMP) range limits the possible V_INand I_OUTrange for a given design. In buck mode,

the maximum V_INfor which the converter can regulate the output at no load is when V_COMPreaches 0.3 V.

Equation 7 gives V_COMPas a function of V_INat no load in CCM buck mode:

2 mS∂ V - V

+ 6 mA

V_OUT

(

)

OUT

V_COMP(BUCK)= 1.6 V - A_CS∂R_SENSE

∂

∂ 1-D

(

∂ 1-D

(

BUCK

)

BUCK

2∂L1∂F

C_SLOPE∂F

(7)

(8)

Where D_BUCKin the equation Equation 7 is the buck duty cycle given by:

V_OUT

D_BUCK

A larger L1, lower slope ripple (higher C_SLOPE), smaller sense resistor (R_SENSE), and higher frequency can

increase the maximum V_INrange for buck operation.

For boost mode, the minimum V_INfor which the converter can regulate the output at full load is when V_COMP

reaches 3 V. Equation 9 gives V_COMPas a function of V_INin boost mode:

2mS∂ V

- V + 5mA

≈

’

◊

V_OUT

(

)

OUT

V_COMP(BOOST)= 1.6V + A_CS∂R_SENSE∂ I

∂

∂D_BOOST

∆

OUT

2∂L1∂F

C_SLOPE∂F

(9)

Where D_BOOSTin the Equation 9 is the boost duty cycle given by:

D_BOOST= 1-

V_OUT

(10)

A larger L1, lower slope ripple (higher C_SLOPE), smaller sense resistor (R_SENSE), and higher frequency can extend

the minimum V_INrange for boost operation.

8.3.13 Integrated Gate Drivers

The LM5175-Q1 provides four N-channel MOSFET gate drivers: two floating high-side gate drivers at the HDRV1

and HDRV2 pins, and two ground referenced low-side drivers at the LDRV1 and LDRV2 pins. Each driver is

capable of sourcing 1.5 A and sinking 2 A peak current. In buck operation, LDRV1 and HDRV1 are switched by

the PWM controller while HDRV2 remains continuously on. In boost operation, LDRV2 and HDRV2 are switched

while HDRV1 remains continuously on.

In DCM buck operation, LDRV1 and HDRV2 turn off when the inductor current drops to zero (diode emulation).

In a DCM boost operation, HDRV2 turns off when inductor current drops to zero.

The gate drive output HDRV2 remains off during soft-start to prevent reverse current flow from a pre-biased

output.

The low-side gate drivers are powered from VCC and the high-side gate drivers HDRV1 and HDRV2 are

powered from bootstrap capacitors C_BOOT1(between BOOT1 and SW1) and C_BOOT2(between BOOT2 and SW2)

respectively. The C_BOOT1and C_BOOT2capacitors are charged through external Schottky diodes connected to the

VCC pin as shown in Figure 24.

LM5175-Q1

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ZHCSEX5 –APRIL 2016

Feature Description (continued)

8.3.14 Thermal Shutdown

The LM5175-Q1 is protected by a thermal shutdown circuit that shuts down the device when the internal junction

temperature exceeds 165°C (typical). The soft-start capacitor is discharged when thermal shutdown is triggered

and the gate drivers are disabled. The converter automatically restarts when the junction temperature drops by

the thermal shutdown hysteresis of 15°C below the thermal shutdown threshold.

8.4 Device Functional Modes

Please refer to Enable/UVLO section for the description of EN/UVLO pin function. Shutdown, Standby, and

Operating Modes section lists the shutdown, standby, and operating modes for LM5175-Q1 as a function of

EN/UVLO and VCC voltages.

8.4.1 Shutdown, Standby, and Operating Modes

EN/UVLO

VCC

DEVICE MODE

EN/UVLO < 0.7 V

0.7 V < EN/UVLO < 1.23 V

EN/UVLO > 1.23 V

—

Shutdown: VCC off, No switching

Standby: VCC on, No switching

Operating: VCC on, Switching enabled

—

VCC < 3.3 V

VCC > 3.3 V

8.4.2 MODE Pin Configuration

The MODE pin is used to select CCM/DCM operation and hiccup mode current limit. Mode is latched at startup.

MODE PIN CONNECTION

Connect to VCC

LIGHT LOAD MODE

HICCUP FAULT PROTECTION

No Hiccup

CCM

DCM

RMODE to AGND = 93.1 kΩ

RMODE to AGND = 49.9 kΩ

Connect to AGND

Hiccup Enabled

No Hiccup

LM5175-Q1

ZHCSEX5 –APRIL 2016

www.ti.com.cn

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The LM5175-Q1 is a four-switch buck-boost controller. A quick-start tool on the LM5175-Q1 product webpage

can be used to design a buck-boost converter using the LM5175-Q1. Alternatively, Webench^®software can

create a complete buck-boost design using the LM5175-Q1 and generate bill of materials, estimate efficiency,

solution size, and cost of the complete solution. The following sections describe a detailed step-by-step design

procedure for a typical application circuit.

9.2 Typical Application

A typical application example is a buck-boost converter operating from a wide input voltage range of 6 V to 36 V

and providing a stable 12 V output voltage with current capability of 6 A.

R_SNS

0 Ω

V_IN

V_OUT

0.1 µF

C_VIN

C_IN

4.7 µF

C_OUT

10 µF

C_OUT

180 µF

R_UV2

249 kΩ

68 µF

10 Ω

100 Ω

1 µF

100 Ω

R_UV1

59.0 kΩ

QH1

QH2

QL2

EN/UVLO VISNS

VIN

ISNS(-) ISNS(+)

HDRV1

BOOT1

4.7 µH

QL1

10 kΩ

VCC

PGOOD

C_BOOT1

0.1 µF

R_MODE

SW1

MODE

93.1 kΩ

LDRV1

100 Ω

RT/SYNC

C_SYNC

1 nF

R_SENSE

8 mΩ

47 pF

R_T

CSG

84.5 kΩ

100 Ω

LM5175-Q1

C_SS

0.1 µF

LDRV2

BOOT2

V_OUT

BIAS

VCC

C_BIAS

C_BOOT2

0.1 µF

SW2

AGND

PGND

HDRV2

VOSNS

VCC

DITH

COMP

SLOPE

C_VCC

1 µF

C_SLOPE

100 pF

C_c1

22 nF

R_RB2

R_RB1

20 kΩ

280 kΩ

C_c2

R_c1

10 kΩ

100 pF

Figure 24. LM5175-Q1 Four-Switch Buck Boost Application Schematic

LM5175-Q1

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ZHCSEX5 –APRIL 2016

Typical Application (continued)

9.2.1 Design Requirements

For this design example, the following are used as the input parameters.

DESIGN PARAMETER

Input Voltage Range

Output

EXAMPLE VALUE

6 V to 36 V

12 V

Load Current

6 A

Switching Frequency

Mode

300 kHz

CCM, Hiccup

9.2.2 Detailed Design Procedure

9.2.2.1 Frequency

The switching frequency of LM5175-Q1 is set by an R_Tresistor connected from RT/SYNC pin to AGND. The R_T

resistor required to set the desired frequency is calculated using Equation 5 or Figure 3 . A 1% standard resistor

of 84.5 kΩ is selected for F_sw= 300 kHz.

9.2.2.2 V_OUT

The output voltage is set using a resistor divider to the FB pin. The internal reference voltage is 0.8 V. Normally

the bottom resistor in the resistor divider is selected to be in the 1 kΩ to 100 kΩ range. Select

R_FB1= 20 kW

(11)

The top resistor in the feedback resistor divider is selected using Equation 12:

V_OUT- 0.8 V

R_FB2

ìR_FB1= 280 kW

0.8 V

(12)

9.2.2.3 Inductor Selection

The inductor selection is based on consideration of both buck and boost modes of operation. For the buck mode,

inductor selection is based on limiting the peak to peak current ripple ΔI_Lto ~40% of the maximum inductor

current at the maximum input voltage. The target inductance for the buck mode is:

- V_OUT)ì V_OUT

IN(MAX)

L_BUCK

= 11.1mH

0.4ìI_OUT(MAX)ìF ì V

IN(MAX)

(13)

For the boost mode, the inductor selection is based on limiting the peak to peak current ripple ΔI_Lto ~40% of the

maximum inductor current at the minimum input voltage. The target inductance for the boost mode is:

V_I²_N(MIN)ì(V_OUT- V

)

IN(MIN)

L_BOOST

= 2.1mH

0.4ìI_OUT(MAX)ìF ì V_O²_UT

(14)

In this particular application, the buck inductance is larger. Choosing a larger inductance reduces the ripple

current but also increases the size of the inductor. A larger inductor also reduces the achievable bandwidth of the

converter by moving the right half plane zero to lower frequencies. Therefore a judicious compromise should be

made based on the application requirements. For this design a 4.7-µH inductor is selected. With this inductor

selection, the inductor current ripple is 5.7 A, 4.3 A, and 2.1 A, at V_INof 36 V, 24 V, and 6 V respectively.

The maximum average inductor current occurs at the minimum input voltage and maximum load current:

V_OUTìI_OUT(MAX)

I_L(MAX)

= 13.3 A

0.9ì V

IN(MIN)

(15)

where a 90% efficiency is assumed. The peak inductor current occurs at minimum input voltage and is given by:

_IN(MIN)ì(V_OUT- V

)

IN(MIN)

I_L(PEAK)= I_L(MAX)

= 14.4 A

2ìL1ìF ì V_OUT

(16)

LM5175-Q1

ZHCSEX5 –APRIL 2016

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To ensure sufficient output current, the current limit threshold must be set to allow the maximum load current in

boost operation. To ensure that the inductor does not saturate in current limit, the peak saturation current of the

inductor should be higher than the maximum current limit. Adjusting for a ±20% current limit threshold tolerance,

the peak inductor current limit is:

1.2ìI_L(PEAK)

I_L(SAT)

= 21.6 A

0.8

(17)

Therefore, the inductor saturation current should be greater than 21.6 A. If hiccup mode protection is not

enabled, the RMS current rating of the inductor should be sufficient to tolerate continuous operation in cycle-by-

cycle current limiting.

9.2.2.4 Output Capacitor

In the boost mode, the output capacitor conducts high ripple current. The output capacitor RMS ripple current is

given by Equation 18 where the minimum V_INcorresponds to the maximum capacitor current.

V_OUT

I_COUT(RMS)= I_OUT

-1

(18)

In this example the maximum output ripple RMS current is I_COUT(RMS)= 6 A. A 5-mΩ output capacitor ESR

causes an output ripple voltage of 60 mV as given by:

I_OUTì V_OUT

DV_RIPPLE(ESR)

ìESR

IN(MIN)

(19)

A 400 µF output capacitor causes a capacitive ripple voltage of 25 mV as given by:

≈

’

◊

IN(MIN)

I_OUTì 1-

∆

V_OUT

DV_RIPPLE(COUT)

C_OUTìF

(20)

Typically a combination of ceramic and bulk capacitors is needed to provide low ESR and high ripple current

capacity. The complete schematic in Figure 24 at the end of this section shows a good starting point for C_OUTfor

typical applications.

9.2.2.5 Input Capacitor

In the buck mode, the input capacitor supplies high ripple current. The RMS current in the input capacitor is given

by:

I_CIN(RMS)= I_OUTDì(1-D)

(21)

The maximum RMS current occurs at D = 0.5, which gives I_CIN(RMS)= I_OUT/2 = 3 A. A combination of ceramic and

bulk capacitors should be used to provide short path for high di/dt current and to reduce the output voltage ripple.

The complete schematic in Figure 24 is a good starting point for C_INfor typical applications.

9.2.2.6 Sense Resistor (R_SENSE

)

The current sense resistor between the CS and CSG pins should be selected to ensure that current limit is set

high enough for both buck and boost modes of operation. For the buck operation, the current limit resistor is

given by:

76 mV ì70%

I_OUT(MAX)

R_SENSE(BUCK)

= 8.8 mW

(22)

For the boost mode of operation, the current limit resistor is given by:

160 mV ì70%

R_SENSE(BOOST)

= 7.7 mW

I_L(PEAK)

(23)

The closest standard value of R_SENSE= 8 mΩ is selected based on the boost mode operation.

LM5175-Q1

www.ti.com.cn

ZHCSEX5 –APRIL 2016

The maximum power dissipation in R_SENSEhappens at V_IN(MIN)

≈

’

≈

∆

’

160 mV

IN(MIN)

P_RSENSE(MAX)

∂R_SENSE∂ 1-

= 1.7 W

∆

R_{SENSE ◊}

V_OUT

◊

(24)

Based on this, select the current sense resistor with power rating of 2 W or higher.

For some application circuits, it may be required to add a filter network to attenuate noise in the CS and CSG

sense lines. Please see Figure 24 for typical values. The filter resistance should not exceed 100 Ω.

9.2.2.7 Slope Compensation

For stable current loop operation and to avoid sub-harmonic oscillations, the slope capacitor should be selected

based on Equation 25:

4.7 mH

8 mWì5

C_SLOPE= gm_SLOPE

= 2 mSì

= 235 pF

R_SENSEì A_CS

(25)

This slope compensation results in “dead-beat” operation, in which the current loop disturbances die out in one

switching cycle. Theoretically a current mode loop is stable with half the “dead-beat” slope (twice the calculated

slope capacitor value in Equation 25). A smaller slope capacitor results in larger slope signal which is better for

noise immunity in the transition region (V_IN~V_OUT). A larger slope signal, however, restricts the achievable input

voltage range for a given output voltage, switching frequency, and inductor. For this design C_SLOPE= 100 pF is

selected for better transition region behavior while still providing the required V_INrange. This selection of slope

capacitor, inductor, switching frequency, and inductor satisfies the COMP range limitation explained in Gm Error

Amplifier section.

9.2.2.8 UVLO

The UVLO resistor divider must be designed for turn-on below 6V. Selecting a R_UV2= 249 kΩ gives a UVLO

hysteresis of 0.8 V. The lower UVLO resistor is the selected using Equation 26:

R_UV2ì1.23 V

+1.5 mA ìR_UV2-1.23 V

R_UV1

= 59.5 kW

(

)

(26)

A standard value of 59.0 kΩ is selected for R_UV1

When programming the UVLO threshold for lower input voltage operation, it is important to choose MOSFETs

with gate (Miller) plateau voltage lower than the minimum V_IN.

9.2.2.9 Soft-Start Capacitor

The soft-start time is programmed using the soft-start capacitor. The relationship between C_SSand the soft-start

time is given by:

0.8 V ìC_SS

t_ss

5 mA

(27)

C_SS= 0.1 µF gives a soft-start time of 16 ms.

9.2.2.10 Dither Capacitor

The dither capacitor sets the modulation frequency of the frequency dithering around the nominal switching

frequency. A larger C_DITHresults in lower modulation frequency. For proper operation the modulation frequency

(F_MOD) must be much lower than the switching frequency. Use Equation 28 to select C_DITHfor the target

modulation frequency.

10 mA

F_MODì0.24 V

C_DITH

(28)

For the current design dithering is not being implemented. Therefore a 0 Ω resistor from the DITH pin to AGND

disables this feature.

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ZHCSEX5 –APRIL 2016

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9.2.2.11 MOSFETs QH1 and QL1

The input side MOSFETs QH1 and QL1 need to withstand the maximum input voltage of 36 V. In addition they

must withstand the transient spikes at SW1 during switching. Therefore QH1 and QL1 should be rated for 60 V.

The gate plateau voltages of the MOSFETs should be smaller than the minimum input voltage of the converter,

otherwise the MOSFETs may not fully enhance during startup or overload conditions.

The power loss in QH1 in the boost mode of operation is approximated by:

≈

’

V_OUT

P_COND(QH1)= I

∂

∂R_DSON(QH1)

∆

OUT

^IN◊

(29)

The power loss in QH1 in the buck mode of operation consists of both conduction and switching loss

components given by Equation 30 and Equation 31 respectively:

≈

∆

’

V_OUT

P_COND(QH1)

∂I

²∂R_DSON(QH1)

OUT

^IN◊

(30)

(31)

P_SW(QH1)

∂ V_IN∂I_OUT∂ t + t ∂F

r f sw

(

)

The rise (t_r) and the fall (t_f) times are based on the MOSFET datasheet information or measured in the lab.

Typically a MOSFET with smaller R_DSON(smaller conduction loss) will have longer rise and fall times (larger

switching loss).

The power loss in QL1 in the buck mode of operation is given by the following equation:

≈

’

V_OUT

P_COND(QL1)= 1-

∂I

²∂R_DSON(QL1)

OUT

∆

^IN◊

(32)

9.2.2.12 MOSFETs QH2 and QL2

The output side MOSFETs QH2 and QL2 see the output voltage of 12 V and additional transient spikes at SW2

during switching. Therefore QH2 and QL2 should be rated for 20 V or more. The gate plateau voltages of the

MOSFETs should be smaller than the minimum input voltage of the converter, otherwise the MOSFETs may not

fully enhance during startup or overload conditions.

The power loss in QH2 in the buck mode of operation is approximated by:

P_COND(QH2)= I_OUT²∂R_DSON(QH2)

(33)

The power loss in QL2 in the boost mode of operation consists of both conduction and switching loss

components given by Equation 34 and Equation 35 respectively:

≈

’ ≈

’

V_OUT

P_COND(QL2)= 1-

∂ I

÷ ∆ _OUT

∂

∂R_DSON(QL2)

∆

V_{OUT ◊ «}

^IN◊

(34)

(35)

≈

’

V_OUT

P_SW(QL2)

∂ V_OUT∂ I

∂

∂ t + t ∂F

r f sw

(

)

∆

OUT

IN ◊

The rise (t_r) and the fall (t_f) times can be based on the MOSFET datasheet information or measured in the lab.

Typically a MOSFET with smaller R_DSON(lower conduction loss) has longer rise and fall times (larger switching

loss).

The power loss in QH2 in the boost mode of operation is given by the following equation:

≈

’

V_OUT

P_COND(QH2)

∂ I

∂

∂R_DSON(QH2)

∆

OUT

V_{OUT «}

^IN◊

(36)

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9.2.2.13 Frequency Compensation

This section presents the control loop compensation design procedure for the LM5175-Q1 buck-boost controller.

The LM5175-Q1 operates mainly in buck or boost modes, separated by a transition region, and therefore the

control loop design is done for both buck and boost operating modes. Then a final selection of compensation is

made based on the mode that is more restrictive from a loop stability point of view. Typically for a converter

designed to go deep into both buck and boost operating regions, the boost compensation design is more

restrictive due to the presence of a right half plane zero (RHPZ) in the boost mode.

The boost power stage output pole location is given by:

≈

∆

’

ƒ_p1(boost)

= 398 Hz

2p R_OUTìC_{OUT ◊}

(37)

where R_OUT= 2 Ω corresponds to the maximum load of 6 A.

The boost power stage ESR zero location is given by:

≈

∆

’

ƒ_z1

= 79.6 kHz

2p R_ESRìC_{OUT ◊}

(38)

(39)

The boost power stage RHP zero location is given by:

≈

’

R_OUTì(1-D_MAX

)

ƒ_RHP

= 16.9 kHz

∆

◊

where D_MAXis the maximum duty cycle at the minimum V_IN.

The buck power stage output pole location is given by:

≈

∆

’

ƒ_p1(buck)

= 199 Hz

2p R_OUTìC_{OUT ◊}

(40)

The buck power stage ESR zero location is the same as the boost power stage ESR zero.

It is clear from Equation 39 that RHP zero is the main factor limiting the achievable bandwidth. For a robust

design the crossover frequency should be less than 1/3 of the RHP zero frequency. Given the position of the

RHP zero, a reasonable target bandwidth in boost operation is around 4 kHz:

ƒ_bw= 4 kHz

(41)

For some power stages, the boost RHP zero might not be as restrictive. This happens when the boost maximum

duty cycle (D_MAX) is small, or when a really small inductor is used. In those cases, compare the limits posed by

the RHP zero (f_RHP/3) with 1/20 of the switching frequency and use the smaller of the two values as the

achievable bandwidth.

The compensation zero can be placed at 1.5 times the boost output pole frequency. Keep in mind that this

locates the zero at 3 times the buck output pole frequency which results in approximately 30 degrees of phase

loss before crossover of the buck loop and 15 degrees of phase loss at intermediate frequencies for the boost

loop:

ƒ_zc= 600 Hz

(42)

If the crossover frequency is well below the RHP zero and the compensation zero is placed well below the

crossover, the compensation gain resistor R_c1is calculated using the approximation:

2pì ƒ_bwR_FB1+R_FB2A_CSìR_SENSEìC_OUT

R_c1

= 9.49 kW

gm_EA

R_FB1

1-D_MAX

(43)

where D_MAXis the maximum duty cycle at the minimum V_INin boost mode and A_CSis the current sense amplifier

gain. The compensation capacitor C_c1is then calculated from:

C_c1

= 27.9 nF

2ì pì ƒ_zcìR_c1

(44)

The standard values of compensation components are selected to be R_c1= 10 kΩ and C_c1= 22 nF.

LM5175-Q1

ZHCSEX5 –APRIL 2016

www.ti.com.cn

A high frequency pole is added to suppress switching noise using a 100 pF capacitor (C_c2) in parallel with R_c1

and C_c1. These values provide a good starting point for the compensation design. Each design should be tuned

in the lab to achieve the desired balance between stability margin across the operating range and transient

response time.

9.2.3 Application Curves

100

V_IN=6V

V_IN=12V

V_IN=24V

LOAD CURRENT (A)

Figure 26. Output Voltage Ripple

D008

Figure 25. Efficiency vs Load

Figure 27. Load Transient Response

Figure 28. Line Transient Response (8 V – 24 V, I_OUT= 2 A)

LM5175-Q1

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10 Power Supply Recommendations

The LM5175-Q1 is a power management device. The power supply for the device is any dc voltage source within

the specified input range. The supply should also be capable of supplying sufficient current based on the

maximum inductor current in boost mode operation. The input supply should be bypassed with additional

electrolytic capacitor at the input of the application board to avoid ringing due to parasitic impedance of the

connecting cables.

11 Layout

11.1 Layout Guidelines

The basic PCB board layout requires separation of sensitive signal and power paths. The following checklist

should be followed to get good performance for a well designed board.

•

Place the power components including the input filter capacitor C_IN, the power MOSFETs QL1 and QH1, and

the sense resistor R_SENSEclose together to minimize the loop area for input switching current in buck

operation.

Place the power components including the output filter capacitor C_OUT, the power MOSFETs QL2 and QH2,

and the sense resistor R_SENSEclose together to minimize the loop area for output switching current in boost

operation.

Use a combination of bulk capacitors and smaller ceramic capacitors with low series impedance for the input

and output capacitors. Place the smaller capacitors closer to the IC to provide a low impedance path for high

di/dt switching currents.

•

Minimize the SW1 and SW2 loop areas as these are high dv/dt nodes.

Layout the gate drive traces and return paths as directly as possible. Layout the forward and return traces

close together, either running side by side or on top of each other on adjacent layers to minimize the

inductance of the gate drive path.

•

Use Kelvin connections to R_SENSEfor the current sense signals CS and CSG and run lines in parallel from the

R_SENSEterminals to the IC pins. Avoid crossing noisy areas such as SW1 and SW2 nodes or high-side gate

drive traces. Place the filter capacitor for the current sense signal as close to the IC pins as possible.

•

Place the C_IN, C_OUT, and R_SENSEground pins as close as possible with thick ground trace and/or planes on

multiple layers.

Place the VCC bypass capacitor close to the controller IC, between the VCC and PGND pins. A 1-µF ceramic

capacitor is typically used.

Place the BIAS bypass capacitor close to the controller IC, between the BIAS and PGND pins. A 0.1-µF

ceramic capacitor is typically used.

•

Place the BOOT1 bootstrap capacitor close to the IC and connect directly to the BOOT1 to SW1 pins.

Place the BOOT2 bootstrap capacitor close to the IC and connect directly to the BOOT2 to SW2 pins.

Bypass the V_INpin to AGND with a low ESR ceramic capacitor located close to the controller IC. A 0.1 µF

ceramic capacitor is typically used. When using external BIAS, use a diode between input rails and V_INpins to

prevent reverse conduction when V_IN< VCC.

•

Connect the feedback resistor divider between the C_OUTpositive terminal and AGND pin of the IC. Place the

components close to the FB pin.

Use care to separate the power and signal paths so that no power or switching current flows through the

AGND connections which can either corrupt the COMP, SLOPE, or SYNC signals, or cause dc offset in the

FB sense signal. The PGND and AGND traces can be connected near the PGND pin, near the VCC

capacitor PGND connection, or near the PGND connection of the CS, CSG pin current sense resistor.

•

When using the average current loop, divide the overall capacitor (C_INor C_OUT) between the two sides of the

sense resistor to ensure small cycle-by-cycle ripple. Place the average current loop filter capacitor close to

the IC between the ISNS(+) and ISNS(-) pins.

LM5175-Q1

ZHCSEX5 –APRIL 2016

www.ti.com.cn

11.2 Layout Example

SW1

SW2

VOUT

VIN

QL1

QL2

QH1

QH2

R_ISNS

COUT

CIN

R_SENSE

COUT

LM5175-Q1

GND

Figure 29. LM5175-Q1 Power Stage Layout

LM5175-Q1

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12 器件和文档支持

12.1 文档支持

12.1.1 相关文档ꢀ

请访问德州仪器 (TI) 主页以获取最新技术文档，包括应用笔记、用户指南和参考设计。

应用报告《IC 封装热指标》，SPRA953.

12.2 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.3 商标

PowerPAD, E2E are trademarks of Texas Instruments.

Webench is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.4 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

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13.1 Package Option Addendum

13.1.1 Packaging Information

Package

Type

Package

Drawing

Package

Qty

(1)

(2)

(3)

Orderable Device

LM5175QPWPRQ1

LM5175QPWPTQ1

Status

Pins

Eco Plan

Lead/Ball Finish MSL Peak Temp

Op Temp (°C)

-40 to 125

Device Marking⁽⁴⁾⁽⁵⁾

Green (RoHS

& no Sb/Br)

Level-3-260C-168

PREVIEW

HTSSOP

PWP

2000

250

CU NIPDAU

LM5175Q

Green (RoHS

& no Sb/Br)

Level-3-260C-168

HTSSOP

-40 to 125

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

space

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest

availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the

requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified

lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used

between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by

weight in homogeneous material)

space

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

space

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device

space

(5) Multiple Device markings will be inside parentheses. Only on Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief

on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third

parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for

release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LM5175QPWPRQ1

LM5175QPWPTQ1

ACTIVE

HTSSOP

PWP

2000 RoHS & Green

250 RoHS & Green

NIPDAU

Level-3-260C-168 HR

-40 to 125

LM5175Q

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE OUTLINE

PWP0028C

PowerPAD^TMTSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

6.6

6.2

TYP

0.1 C

PIN 1 INDEX

AREA

SEATING

PLANE

26X 0.65

9.8

9.6

8.45

NOTE 3

0.30

0.19

28X

4.5

4.3

0.1

C A B

SEE DETAIL A

(0.15) TYP

2X 0.95 MAX

NOTE 5

2X 0.2 MAX

NOTE 5

0.25

GAGE PLANE

1.2 MAX

5.18

4.48

THERMAL

PAD

0.15

0.05

0.75

0.50

0 -8

DETAIL A

TYPICAL

3.1

2.4

4223582/A 03/2017

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

5. Features may differ or may not be present.

www.ti.com

EXAMPLE BOARD LAYOUT

PWP0028C

PowerPAD^TMTSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

(3.4)

NOTE 9

(3.1)

METAL COVERED

BY SOLDER MASK

SYMM

28X (1.5)

28X (0.45)

SEE DETAILS

(R0.05) TYP

(5.18)

(0.6)

26X (0.65)

SYMM

(9.7)

NOTE 9

SOLDER MASK

DEFINED PAD

(1.2) TYP

(

0.2) TYP

VIA

(1.2) TYP

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 8X

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

15.000

(PREFERRED)

SOLDER MASK DETAILS

4223582/A 03/2017

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged

or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

PWP0028C

PowerPAD^TMTSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

(3.1)

BASED ON

0.125 THICK

STENCIL

28X (1.5)

METAL COVERED

BY SOLDER MASK

28X (0.45)

(R0.05) TYP

26X (0.65)

SYMM

(5.18)

BASED ON

0.125 THICK

STENCIL

SYMM

(5.8)

SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 8X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

3.47 X 5.79

3.10 X 5.18 (SHOWN)

2.83 X 4.73

0.125

0.15

0.175

2.62 X 4.38

4223582/A 03/2017

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

12. Board assembly site may have different recommendations for stencil design.

www.ti.com

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LM5175-Q1 [TI]

相关型号：

LM5175PWPR

LM5175PWPT

LM5175QPWPRQ1

LM5175QPWPTQ1

LM5175RHFR

LM5175RHFT

LM5176

LM5176-Q1

LM5176PWPR

LM5176PWPT

LM5176QPWPRQ1

LM5176QPWPTQ1