LM5117 [TI]
Wide Input Range Synchronous Buck Controller with Analog Current Monitor; 宽输入范围同步降压控制器具有模拟电流监控器
| 型号： | LM5117 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Wide Input Range Synchronous Buck Controller with Analog Current Monitor |
| 文件： | 总33页 (文件大小：702K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 10, 2012
LM5117/LM5117Q
Wide Input Range Synchronous Buck Controller with
Analog Current Monitor
General Description
Features
The LM5117 is a synchronous buck controller intended for
step-down regulator applications from a high voltage or widely
varying input supply. The control method is based upon cur-
rent mode control utilizing an emulated current ramp. Current
mode control provides inherent line feed-forward, cycle-by-
cycle current limiting and ease of loop compensation. The use
of an emulated control ramp reduces noise sensitivity of the
pulse-width modulation circuit, allowing reliable control of
very small duty cycles necessary in high input voltage appli-
cations.
LM5117Q is an Automotive Grade product that is AEC-
■
Q100 grade 1 qualified (-40°C to +125°C operating
junction temperature)
Emulated peak current mode control
■
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■
■
■
■
■
■
■
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■
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Wide operating range from 5.5V to 65V
Robust 3.3A peak gate drives
Adaptive dead-time output driver control
Free-run or synchronizable clock up to 750kHz
Optional diode emulation mode
The operating frequency is programmable from 50 kHz to 750
kHz. The LM5117 drives external high-side and low-side
NMOS power switches with adaptive dead-time control. A us-
er-selectable diode emulation mode enables discontinuous
mode operation for improved efficiency at light load condi-
tions. A high voltage bias regulator that allows external bias
supply further improves efficiency. The LM5117’s unique ana-
log telemetry feature provides average output current infor-
mation. Additional features include thermal shutdown, fre-
quency synchronization, hiccup mode current limit and
adjustable line under-voltage lockout.
Programmable output from 0.8V
Precision 1.5% voltage reference
Analog current monitor
Programmable current limit
Hiccup mode over current protection
Programmable soft-start and tracking
Programmable line under-voltage lockout
Programmable switch-over to external bias supply
Thermal shutdown
Packages
TSSOP-20EP (Thermally enhanced)
■
■
LLP-24 (4mmx4mm)
Typical Application
30143201
© 2012 Texas Instruments Incorporated
301432 SNVS698D
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Connection Diagram
30143202
30143279
Top View
LLP-24 (4mmx4mm)
Top View
20-Lead TSSOP EP
Ordering Information
NSC Package
Drawing
Order Number
Package Type
Supplied As
Feature
LM5117QPMH
LM5117QPMHE
LM5117QPMHX
LM5117QPSQ
LM5117QPSQE
LM5117QPSQX
LM5117PMH
TSSOP-20EP
TSSOP-20EP
TSSOP-20EP
LLP-24
MXA20A
MXA20A
MXA20A
SQA24A
SQA24A
SQA24A
MXA20A
MXA20A
MXA20A
SQA24A
SQA24A
SQA24A
73 Units Per Rail
AEC-Q100 Grade 1
qualified. Automotive
Grade Production
Flow*
250 Units on Tape and Reel
2500 Units on Tape and Reel
1000 Units on Tape and Reel
250 Units on Tape and Reel
4500 Units on Tape and Reel
73 Units Per Rail
LLP-24
LLP-24
TSSOP-20EP
TSSOP-20EP
TSSOP-20EP
LLP-24
LM5117PMHE
LM5117PMHX
LM5117PSQ
250 Units on Tape and Reel
2500 Units on Tape and Reel
1000 Units on Tape and Reel
250 Units on Tape and Reel
4500 Units on Tape and Reel
LM5117PSQE
LM5117PSQX
LLP-24
LLP-24
*Automotive Grade (Q) product incorporates enhanced manufacturing and support processes for the automotive market, including defect detection methodologies.
Reliability qualification is compliant with the requirements and temperature grades defined in the AEC-Q100 standard. Automotive Grade products are identified
with the letter Q. For more information, go to http://www.national.com/automotive.
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Pin Descriptions
TSSOP
Pin
LLP
Pin
Name Description
1
24
UVLO Under-voltage lockout programming pin. If the UVLO pin voltage is below 0.4V, the regulator is in the
shutdown mode with all functions disabled. If the UVLO pin voltage is greater than 0.4V and less than
1.25V, the regulator is in standby mode with the VCC regulator operational, the SS pin grounded, and
no switching at the HO and LO outputs. If the UVLO pin voltage is above 1.25V, the SS pin is allowed
to ramp and pulse width modulated gate drive signals are delivered to the HO and LO pins. A 20μA
current source is enabled when UVLO exceeds 1.25V and flows through the external UVLO resistors
to provide hysteresis.
2
3
1
2
DEMB Optional logic input that enables diode emulation when in the low state. In diode emulation mode, the
low-side NMOS is latched off for the remainder of the PWM cycle after detecting reverse current flow
(current flow from output to ground through the low-side NMOS). When DEMB is high, diode emulation
is disabled allowing current to flow in either direction through the low-side NMOS. A 50kΩ pull-down
resistor internal to the LM5117 holds DEMB pin low and enables diode emulation if the pin is left
floating.
RES
The restart timer pin that configures the hiccup mode current limiting. A capacitor on the RES pin
determines the time the controller remains off before automatically restarting. The hiccup mode
commences when the controller experiences 256 consecutive PWM cycles of cycle-by-cycle current
limiting. After this occurs, an 10μA current source charges the RES pin capacitor to the 1.25V threshold
and restarts LM5117.
4
5
3
4
SS
RT
An external capacitor and an internal 10μA current source set the ramp rate of the error amplifier
reference during soft-start. The SS pin is held low when VCC< 5V, UVLO < 1.25V or during thermal
shutdown.
The internal oscillator is programmed with a single resistor between RT and the AGND. The
recommended maximum oscillator frequency is 750kHz. The internal oscillator can be synchronized
to an external clock by coupling a positive pulse into the RT pin through a small coupling capacitor.
6
7
5
7
AGND Analog ground. Return for the internal 0.8V voltage reference and analog circuits.
VCCDIS Optional input that disables the internal VCC regulator. If VCCDIS>1.25V, the internal VCC regulator
is disabled. VCCDIS has an internal 500kΩ pull-down resistor to enable the VCC regulator when the
pin is left floating. The internal 500kΩ pull-down resistor can be overridden by pulling VCCDIS above
1.25V with a resistor divider connected to an external bias supply.
8
9
8
9
FB
Feedback. Inverting input of the internal error amplifier. A resistor divider from the output to this pin
sets the output voltage level. The regulation threshold at the FB pin is 0.8V.
COMP Output of the internal error amplifier. The loop compensation network should be connected between
this pin and the FB pin.
10
11
10
11
CM
Current monitor output. Average of the sensed inductor current is provided. Monitor directly between
CM and AGND. CM should be left floating when the pin is not used.
RAMP PWM ramp signal. An external resistor and capacitor connected between the SW pin, the RAMP pin
and the AGND pin sets the PWM ramp slope. Proper selection of component values produces a RAMP
signal that emulates the AC component of the inductor with a slope proportional to input supply voltage.
12
13
12
13
CS
Current sense amplifier input. Connect to the high-side of the current sense resistor.
CSG
Kelvin ground connection to the current sense resistor. Connect directly to the low-side of the current
sense resistor.
14
15
16
17
14
15
16
18
PGND Power ground return pin for low-side NMOS gate driver. Connect directly to the low-side of the current
sense resistor.
LO
VCC
SW
Low-side NMOS gate drive output. Connect to the gate of the low-side synchronous NMOS transistor
through a short, low inductance path.
Bias supply pin. Locally decouple to PGND using a low ESR/ESL capacitor located as close to
controller as possible.
Switching node of the buck regulator. Connect to the bootstrap capacitor, the source terminal of the
high-side NMOS transistor and the drain terminal of the low-side NMOS through a short, low
inductance path.
3
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TSSOP
Pin
LLP
Pin
Name Description
18
19
HO
HB
High-side NMOS gate drive output. Connect to the gate of the high-side NMOS transistor through a
short, low inductance path.
19
20
High-side driver supply for the bootstrap gate drive. Connect to the cathode of the external bootstrap
diode and to the bootstrap capacitor. The bootstrap capacitor supplies current to charge the high-side
NMOS gate and should be placed as close to controller as possible.
20
22
VIN
EP
Supply voltage input source for the VCC regulator.
EP
EP
Exposed pad of the package. Electrically isolated. Should be soldered to the ground plane to reduce
thermal resistance.
6
NC
NC
NC
NC
No electrical contact.
No electrical contact.
No electrical contact.
No electrical contact.
17
21
23
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SS, RAMP, RT to AGND
CS, CSG, PGND, to AGND
ESD Rating HBM (Note 4)
Storage Temperature
-0.3 to 7V
-0.3 to 0.3V
2kV
Absolute Maximum Ratings (Note 1)
VIN to AGND
SW to AGND
HB to SW
-0.3 to 75V
-3.0 to 75V
-0.3 to 15V
-55°C to +150°C
+150°C
Junction Temperature
VCC to AGND (Note 2)
HO to SW
LO to AGND
FB, DEMB, RES, VCCDIS,
UVLO to AGND
-0.3 to 15V
Operating Ratings (Note 1)
-0.3 to HB+0.3V
-0.3 to VCC+0.3V
-0.3 to 15V
VIN (Note 5)
VCC
5.5V to 65V
5.5V to 14V
5.5V to 14V
HB to SW
CM, COMP to AGND(Note 3)
-0.3 to 7V
Junction Temperature
-40°C to +125°C
Electrical Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the
junction temperature range of -40°C to +125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical
correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
Unless otherwise specified, the following conditions apply: VVIN = 48V, VVCCDIS = 0V, RT = 25kΩ, no load on LO & HO.
Symbol Parameter
VIN Supply
Conditions
Min
Typ
Max
Units
IBIAS
VIN Operating Current (Note 6)
VSS = 0V
4.8
0.4
16
6.2
0.55
40
mA
mA
µA
VSS = 0V, VVCCDIS = 2V
VSS = 0V, VUVLO = 0V
ISHUTDOWN VIN Shutdown Current
VCC Regulator
VCC(REG) VCC Regulation
VCC Dropout (VIN to VCC)
No Load
6.85
30
7.6
0.05
0.4
42
8.2
0.14
0.5
V
V
VVIN = 5.5V, No external load
VVIN = 6.0V, ICC = 20mA
VVCC = 0V
V
VCC Sourcing Current Limit
mA
mA
mA
V
IVCC
VCC Operating Current (Note 6)
VSS = 0V, VVCCDIS = 2V
VSS = 0V, VVCCDIS = 2V, VVCC = 14V
VCC Rising
4.0
5.8
4.9
0.2
5.0
7.3
VCC Under-voltage Threshold
VCC Under-voltage Hysteresis
4.7
5.15
V
VCC Disable
VCCDIS Threshold
VCCDIS Rising
VVCCDIS = 0V
1.22
1.25
0.06
-20
1.29
V
V
VCCDIS Hysteresis
VCCDIS Input Current
VCCDIS Pull-down Resistance
nA
500
kΩ
UVLO
UVLO Threshold
UVLO Rising
VUVLO = 1.4V
UVLO Falling
1.22
15
1.25
20
1.29
25
V
µA
V
UVLO Hysteresis Current
UVLO Shutdown Threshold
UVLO Shutdown Hysteresis
0.23
0.3
0.1
V
Soft Start
ISS
SS Current Source
VSS = 0V
7
10
13
12
24
µA
SS Pull-down Resistance
Ω
Error Amplifier
VREF
FB Reference Voltage
Measured at FB, FB = COMP
VFB = 0.8V
788
2.8
800
1
812
mV
nA
V
FB Input Bias Current
COMP Output High Voltage
COMP Output Low Voltage
DC Gain
VOH
VOL
AOL
fBW
ISOURCE = 3mA
ISINK = 3mA
0.26
V
80
3
dB
MHz
Unity Gain Bandwidth
PWM Comparator
tHO(OFF) Forced HO Off-time
260
320
440
ns
5
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Symbol Parameter
Conditions
Min
Typ
100
1.2
Max
Units
ns
tON(MIN)
Minimum HO On-time
VVIN = 65V
COMP to PWM comparator offset
V
Oscillator
fSW1
Frequency 1
Frequency 2
180
430
200
480
220
530
kHz
kHz
RT = 25kΩ
RT = 10kΩ
fSW2
RT Output Voltage
1.25
3.2
V
V
RT Sync Positive Threshold
Sync Pulse Width
2.6
3.95
135
100
ns
Current Limit
VCS(TH) Cycle-by-cycle Sense Voltage
VRAMP = 0, CSG to CS
106
120
mV
Threshold
CS Input Bias Current
CSG Input Bias Current
Current Sense Amplifier Gain
Hiccup Mode Fault Timer
VCS = 0V
-100
-100
-66
-66
10
µA
µA
VCSG = 0V
V/V
256
Cycles
RES
IRES
RES Current Source
RES Threshold
10
µA
V
VRES
RES Rising
1.22
2.95
1.25
1.285
1.65
Diode Emulation
VIL
VIH
DEMB Input Low Threshold
2.0
2.5
-5
V
V
DEMB Input High Threshold
SW Zero Cross Threshold
mV
kΩ
DEMB Input Pull-down Resistance
50
Current Monitor
Current Monitor Amplifier Gain
CS to CM
17.5
-2
20.5
0
23.5
+2
V/V
%
Current Monitor Amplifier Gain
Zero Input Offset
Drift over Temperature
25
120
mV
HO Gate Driver
VOHH
VOLH
HO High-state Voltage Drop
HO Low-state Voltage Drop
HO Rise Time
IHO = –100mA, VOHH = VHB - VHO
IHO = 100mA, VOLH = VHO - VSW
C-load = 1000pF (Note 7)
C-load = 1000pF (Note 7)
VHO = 0V, SW = 0V, HB = 7.6V
VHO = VHB = 7.6V
0.17
0.1
6
0.3
0.2
V
V
ns
ns
A
HO Fall Time
5
IOHH
IOLH
Peak HO Source Current
Peak HO Sink Current
HB to SW Under-voltage
HB DC Bias Current
2.2
3.3
2.9
65
A
2.56
3.32
100
V
HB - SW = 7.6V
µA
LO Gate Driver
VOHL
VOLL
LO High-state Voltage Drop
ILO = –100mA, VOHL = VCC-VLO
ILO = 100mA, VOLL = VLO
C-load = 1000pF (Note 7)
C-load = 1000pF (Note 7)
VLO = 0V
0.17
0.1
6
0.27
0.2
V
V
LO Low-state Voltage Drop
LO Rise Time
ns
ns
A
LO Fall Time
5
IOHL
IOLL
Peak LO Source Current
Peak LO Sink Current
2.5
3.3
VLO = 7.6V
A
Switching Characteristics
TDLH
LO Fall to HO Rise Delay
No load
No load
72
71
ns
ns
HO Fall to LO Rise Delay
Thermal
TSD
Thermal Shutdown
Temperature Rising
165
25
°C
°C
Thermal Shutdown Hysteresis
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Symbol Parameter
Conditions
Min
Typ
Max
Units
Junction to Ambient
TSSOP-20EP
40
°C/W
θJA
θJC
θJA
θJC
Junction to Case
Junction to Ambient
Junction to Case
TSSOP-20EP
4
40
6
°C/W
°C/W
°C/W
LLP-24 (4mmx4mm)
LLP-24 (4mmx4mm)
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the
device is intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test conditions see the Electrical
Characteristics Table.
Note 2: See Application Information when input supply voltage is less than the VCC voltage.
Note 3: These pins are output pins. As such they are not specified to have an external voltage applied.
Note 4: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.
Note 5: Minimum VIN operating voltage is defined with VCC supplied by the internal HV startup regulator and no external load on VCC. When VCC is supplied
by an external source, minimum VIN operating voltage is 4.5V.
Note 6: Operating current does not include the current into the RT resistor.
Note 7: High and low reference are 80% and 20% of the pulse amplitude respectively.
7
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Typical Performance Characteristics
HO Peak Driver Current vs Output Voltage
LO Peak Driver Current vs Output Voltage
30143203
30143204
Driver Dead Time vs VVCC
Driver Dead Time vs Temperature
30143206
30143205
Forced HO Off-time vs Temperature
Switching Frequency vs RT
30143207
30143208
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VVCC vs IVCC
VVCC vs VVIN
30143209
30143269
VCS(TH) vs Temperature
VREF vs Temperature
30143270
30143271
VVCC vs Temperature
Error Amp Gain and Phase vs Frequency
301432162
30143273
9
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VCM vs IOUT
VCM vs VCSG-CS
30143272
30143278
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Block Diagram and Typical Application Circuit
30143210
FIGURE 1. Block Diagram and Typical Application Circuit
11
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externally supplied bias should be coupled to the VCC pin
through a diode, preferably a Schottky diode. If the VCCDIS
pin voltage exceeds the VCCDIS threshold, the internal VCC
regulator is disabled. VCCDIS has a 500kΩ internal pull-down
resistor to ground for normal operation with no external bias.
Functional Description
The LM5117 high voltage switching controller features all of
the functions necessary to implement an efficient high voltage
buck regulator that operates over a very wide input voltage
range. This easy to use controller integrates high-side and
low-side NMOS drivers. The regulator control method is
based upon peak current mode control utilizing an emulated
current ramp. Peak current mode control provides inherent
line feed-forward, cycle-by-cycle current limiting and ease of
loop compensation. The use of an emulated control ramp re-
duces noise sensitivity of the PWM circuit, allowing reliable
processing of the very small duty cycles necessary in high
input voltage applications.
The VCC regulator series pass transistor includes a diode
between VCC (Anode) and VIN (Cathode) that should not be
forward biased in normal operation. If the voltage of the ex-
ternal bias supply is greater than the VIN pin voltage, an
external blocking diode is required from the input power sup-
ply to the VIN pin to prevent the external bias supply from
passing current to the input supply through VCC.
The switching frequency is user programmable up to 750 kHz.
The RT pin allows the switching frequency to be programmed
by a single resistor or synchronized to an external clock. Fault
protection features include cycle-by-cycle and hiccup mode
current limiting, thermal shutdown and remote shutdown ca-
pability by pulling down UVLO pin. The UVLO input enables
the regulator when the input voltage reaches a user selected
threshold and provides a very low quiescent shutdown current
when pulled low. A unique analog telemetry feature provides
averaged output current information, allowing various appli-
cations that need either a current monitor or current control.
The functional block diagram and typical application circuit of
the LM5117 are shown in Figure 1
30143211
FIGURE 2. VIN Configuration for VVIN<VVCC
The device is available in TSSOP-20EP and LLP24 package
featuring an exposed pad to aid in thermal dissipation.
For VOUT between 6V and 14.5V, the output can be connected
directly to VCC through a diode.
High Voltage Startup Regulator and
VCC Disable
The LM5117 contains an internal high voltage bias regulator
that provides the VCC bias supply for the PWM controller and
NMOS gate drivers. The VIN pin can be connected to an input
voltage source as high as 65V. The output of the VCC regu-
lator is set to 7.6V. When the input voltage is below the VCC
set-point level, the VCC output tracks the VIN with a small
dropout voltage. The output of the VCC regulator is current
limited at 30mA minimum.
30143212
FIGURE 3. External VCC Supply for 6V< VOUT<14.5V
Upon power-up, the regulator sources current into the capac-
itor connected to the VCC pin. The recommended capaci-
tance range for the pin VCC is 0.47µF to 10µF. When the VCC
pin voltage exceeds the VCC UV threshold and the UVLO pin
is greater than UVLO threshold, the HO and LO drivers are
enabled and a soft-start sequence begins. The HO and LO
drivers remain enabled until either the VCC pin voltage falls
below VCC UV threshold, the UVLO pin voltage falls below
UVLO threshold, hiccup mode is activated or the die temper-
ature exceeds the thermal shutdown threshold. Enabling/
Disabling the IC by controlling UVLO is recommended in most
of cases.
For VOUT < 6V, a bias winding on the output inductor can be
added to generate the external VCC supply voltage.
An output voltage derived bias supply can be applied to the
VCC pin to reduce the controller power dissipation at higher
input voltage. The VCCDIS input can be used to disable the
internal VCC regulator when external biasing is supplied. The
30143257
FIGURE 4. External VCC Supply for VOUT <6V
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12
For 14.5V <VOUT, the external supply voltage can be regulat-
ed by using a series Zener diode from the output to VCC.
the minimum input operating voltage of the regulator. The di-
vider must be designed such that the voltage at the UVLO pin
is greater than 1.25V and never exceeds 15V when the input
voltage is in the desired operating range. If necessary, the
UVLO pin can be clamped with a Zener diode.
UVLO hysteresis is accomplished with an internal 20μA cur-
rent source that is switched on or off into the impedance of
the UVLO set-point divider. When the UVLO pin voltage ex-
ceeds the 1.25V threshold, the current source is enabled to
quickly raise the voltage at the UVLO pin. When the UVLO
pin voltage falls below the 1.25V threshold, the current source
is disabled causing the voltage at the UVLO pin to quickly fall.
The use of a CFT capacitor in parallel with RUV1 helps to min-
imize switching noise injection into UVLO pin, but it may slow
down the falling speed of the UVLO pin when the 20μA current
source is disabled. The recommended range for CFT is 10pF
to 220pF.
30143259
FIGURE 5. External VCC Supply for 14.5V <VOUT
In high input voltage applications, extra care should be taken
to ensure the VIN pin does not exceed the absolute maximum
voltage rating of 75V. During line or load transients, voltage
ringing on the VIN that exceeds the Absolute Maximum Rat-
ing can damage the IC. Both careful PC board layout and the
use of quality bypass capacitors located close to the VIN and
AGND pin are essential. Adding an R-C filter (RVIN, CVIN) on
VIN is optional and helps to prevent faulty operation caused
by poor PC board layout and high frequency switching noise
injection. The recommended capacitance and resistance
range are 0.1µF to 10µF and 1Ω to 10Ω.
The values of RUV1 and RUV2 can be determined from the fol-
lowing equations:
(1)
(2)
UVLO
Where VHYS is the desired UVLO hysteresis and
VIN(STARTUP) is the desired startup voltage of the regulator
during turn-on.
The LM5117 contains a dual level UVLO (under-voltage lock-
out) circuit. When the UVLO is less than 0.4V, the LM5117 is
in shutdown mode. The shutdown comparator provides
100mV of hysteresis to avoid chatter during transitions. When
the UVLO pin voltage is greater than 0.4V but less than 1.25V,
the controller is in standby mode. In the standby mode, the
VCC bias regulator is active but the HO and LO drivers are
disabled and the SS pin is held low. This feature allows the
UVLO pin to be used as a remote shutdown function by pulling
the UVLO pin down below 0.4V with an external open collec-
tor or open drain device. When the VCC pin exceeds its
under-voltage lockout threshold and the UVLO pin voltage is
greater than 1.25V, the HO and LO drivers are enabled and
normal operation begins.
Oscillator and Sync Capability
The LM5117 switching frequency is programmed by a single
external resistor connected between the RT pin and the
AGND pin. The resistor should be located very close to the
device and connected directly to the RT and AGND pins. To
set a desired switching frequency (fSW), the resistor value can
be calculated from the following equation:
(3)
The RT pin can be used to synchronize the internal oscillator
to an external clock. The internal oscillator can be synchro-
nized by AC coupling a positive edge into the RT pin. The
voltage at the RT pin is nominally 1.25V and the voltage at
the RT pin must exceed the RT Sync Positive Threshold to
trip the internal synchronization pulse detector. A 5V ampli-
tude pulse signal coupled through 100pF capacitor is a good
starting point. The frequency of the external synchronization
pulse is recommended to be within +/-10% of the frequency
programmed by the RT resistor but will operate to +100/-40%
of the programmed frequency. Care should be taken to guar-
antee that the RT pin voltage does not go below -0.3V at the
falling edge of the external pulse. This may limit the duty cycle
of external synchronization pulse.
30143268
FIGURE 6. UVLO Configuration
The RT resistor is always required, whether the oscillator is
free running or externally synchronized.
The UVLO pin should not be left floating. An external UVLO
set-point voltage divider from the VIN to AGND is used to set
13
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Ramp Generator and Emulated
Current Sense
The ramp signal used in the pulse width modulator for tradi-
tional current mode control is typically derived directly from
the high-side switch current. This switch current corresponds
to the positive slope portion of the inductor current. Using this
signal for the PWM ramp simplifies the control loop transfer
function to a single pole response and provides inherent input
voltage feed-forward compensation.
The disadvantage of using the high-side switch current signal
for PWM control is the large leading edge spike due to circuit
parasitics that must be filtered or blanked. Minimum achiev-
able pulse width is limited by the filtering, blanking time and
propagation delay with a high-side current sensing scheme.
30143213
FIGURE 8. RAMP Generator and Current Limit Circuit
In the applications where the input voltage may be relatively
large in comparison to the output voltage, controlling small
pulse widths and duty cycles are necessary for regulation.
The LM5117 utilizes a unique ramp generator which does not
actually measure the high-side switch current but rather re-
constructs the signal. Representing or emulating the inductor
current provides a ramp signal to the PWM comparator that
is free of leading edge spikes and measurement or filtering
delays, while maintaining the advantages of traditional peak
current mode control.
The positive slope inductor current ramp is emulated by
CRAMP connected between RAMP and AGND and RRAMP con-
nected between SW and RAMP. RRAMP should not be con-
nected to VIN directly because the RAMP pin absolute
maximum voltage rating could be exceeded under high input
voltage conditions. CRAMP is discharged by an internal switch
during the off-time and must be fully discharged during the
minimum off-time. This limits the ramp capacitor to be less
than 2nF. A good quality, thermally stable ceramic capacitor
The current reconstruction is comprised of two elements: a
sample-and-hold DC level and the emulated inductor current
ramp as shown in Figure 7. The sample-and-hold DC level is
derived from a measurement of the recirculating current flow-
ing through the current sense resistor. The voltage across the
sense resistor is sampled and held just prior to the onset of
the next conduction interval of the high-side switch. The cur-
rent sense amplifier with a gain of 10 and sample-and-hold
circuit provide the DC level of the reconstructed current signal
as shown in Figure 8.
is recommended for CRAMP
.
The selection of RRAMP and CRAMP can be simplified by adopt-
ing a K factor, which is defined as:
(4)
Where AS is the current sense amplifier gain which is normally
10. By choosing 1 as the K factor, the regulator removes any
error after one switching cycle and the design procedure is
simplified. See Application Information for detailed informa-
tion.
Error Amplifier and PWM
Comparator
The internal high-gain error amplifier generates an error sig-
nal proportional to the difference between the FB pin voltage
and the internal precision 0.8V reference. The output of error
amplifier is connected to the COMP pin allowing the user to
provide Type 2 loop compensation components, RCOMP
CCOMP and optional CHF
,
.
30143216
FIGURE 7. Composition of Emulated Current Sense
Signal
30143217
FIGURE 9. Feedback Configuration and PWM
Comparator
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14
RCOMP, CCOMP and CHF configure the error amplifier gain and
phase characteristics to achieve a stable voltage loop gain.
This network creates a pole at DC (FP1), a mid-band zero
(FZ) for phase boost, and a high frequency pole (FP2). The
recommended range of RCOMP is 2kΩ to 40kΩ. See Applica-
tion Information for detailed information.
Soft-Start
The soft-start feature allows the regulator to gradually reach
the steady state operating point, thus reducing startup stress-
es and surges. The LM5117 regulates the FB pin to the SS
pin voltage or the internal 0.8V reference, whichever is lower.
The internal 10µA soft-start current source gradually increas-
es the voltage on an external soft-start capacitor connected
to the SS pin. This results in a gradual rise of the output volt-
age. Soft-start time (tss) can be calculated from the following
equation:
(5)
(6)
(8)
The LM5117 can track the output of a master power supply
during soft-start by connecting a voltage divider from the out-
put of master power supply to the SS pin. At the beginning of
the soft-start sequence, VSS should be allowed to go below
25mV by the internal SS pull-down switch. During soft-start
period, when SS pin voltage is less than 0.8V, the LM5117
forces diode emulation for startup into a pre-biased load. If
the tracking feature is desired, connect the DEMB pin to GND
or leave the pin floating.
(7)
The PWM comparator compares the emulated current sense
signal from Ramp Generator to the voltage at the COMP pin
through a 1.2V internal voltage drop and terminates the
present cycle when the emulated current sense signal is
greater than VCOMP - 1.2V.
Diode Emulation
A fully synchronous buck regulator implemented with a free-
wheeling NMOS rather than a diode has the capability to sink
current from the output in certain conditions such as light load,
over-voltage or pre-bias startup. The LM5117 provides a
diode emulation feature that can be enabled to prevent re-
verse current flow in the low-side NMOS device. When con-
figured for diode emulation, the low-side NMOS driver is
disabled when SW pin voltage is greater than -5mV during the
off-time of the high-side NMOS driver, preventing reverse
current flow.
Cycle-by-Cycle Current Limit
The LM5117 contains a current limit monitoring scheme to
protect the regulator from possible over-current conditions as
shown in Figure 8. If the emulated ramp signal exceeds 1.2V,
the present cycle is terminated. For the case where the switch
current overshoots when the inductor is saturated or the out-
put is shorted to ground, the sample-and-hold circuit detects
the excess recirculating current before the high-side NMOS
driver is turned on again. The high-side NMOS driver is dis-
abled and will skip pulses until the current has decayed below
the current limit threshold. This approach prevents current
runaway conditions since the inductor current is forced to de-
cay to a controlled level following any current overshoot.
Maximum peak inductor current can be calculated as:
A benefit of the diode emulation is lower power loss at no load
or light load conditions. The negative effect of diode emulation
is degraded light load transient response.
The diode emulation feature is configured with the DEMB pin.
To enable diode emulation, connect the DEMB pin to GND or
leave the pin floating. If continuous conduction operation is
desired, the DEMB pin should be tied to a voltage greater than
3V and may be connected to VCC. The LM5117 forces the
regulator to operate in diode emulation mode when SS pin
voltage is less than the internal 0.8V reference, allowing for
startup into a pre-biased load with the continuous conduction
configuration.
(9)
(10)
Where IPP represents inductor peak to peak ripple current in
Figure 10, and is defined as:
(11)
15
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30143215
FIGURE 10. Inductor Current
During an output short condition, the worst case peak inductor
current is limited to:
30143218
FIGURE 11. Hiccup Mode Current Limit Timing Diagram
(12)
Where tON(MIN) is the minimum HO on-time.
In most cases, especially if the output voltage is relatively
high, it is recommended that a soft-saturating inductor such
as a powder core device is used. If a sharp-saturating inductor
is used, the inductor saturation level must be above ILIM_PK
.
The temperatures of the NMOS devices, RS and inductor
should be checked under this output short condition.
Hiccup Mode Current Limiting
To further protect the regulator during prolonged current limit
conditions, LM5117 provides a hiccup mode current limit. An
internal hiccup mode fault timer counts the PWM clock cycles
during which cycle-by-cycle current limiting occurs. When the
hiccup mode fault timer detects 256 consecutive cycles of
current limiting, an internal restart timer forces the controller
to enter a low power dissipation standby mode and starts
sourcing 10μA current into the RES pin capacitor CRES. In this
standby mode, HO and LO outputs are disabled and the soft-
start capacitor CSS is discharged.
30143219
FIGURE 12. Hiccup Mode Current Limit Circuit
The RES pin can also be configured for latch-off mode current
limiting or non-hiccup mode cycle-by-cycle current limiting. If
the RES pin is tied to VCC or a voltage greater than the RES
threshold at initial power-on, the restart timer is disabled and
the regulator operates with non-hiccup mode cycle-by-cycle
current limit. If the RES pin is tied to GND, the regulator enters
into the standby mode after 256 consecutive cycles of current
limiting and then never restarts until UVLO shutdown is cy-
cled. The restart timer is configured during initial power-on
when UVLO is above the UVLO threshold and VCC is above
the VCC UV threshold.
CRES is connected from RES pin to AGND and determines the
time (tRES) in which the LM5117 remains in the standby before
automatically restarting. When the RES pin voltage exceeds
the 1.25V RES threshold, RES capacitor is discharged and a
soft-start sequence begins. tRES can be calculated from the
following equation:
(13)
30143220
FIGURE 13. RES Configurations
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16
The average of CM output can be calculated by:
HO and LO Drivers
The LM5117 contains high current NMOS drivers and an as-
sociated high-side level shifter to drive the external high-side
NMOS device. This high-side gate driver works in conjunction
with an external diode DHB, and bootstrap capacitor CHB. A
0.1μF or larger ceramic capacitor, connected with short traces
between the HB and SW pin, is recommended. During the off-
time of the high-side NMOS driver, the SW pin voltage is
approximately 0V and the CHB is charged from VCC through
the DHB. When operating with a high PWM duty cycle, the
high-side NMOS device is forced off each cycle for 320ns to
ensure that CHB is recharged.
(14)
The current monitor output is only valid in continuous con-
duction operation. The current monitor has a limited band-
width of approximately one tenth of fSW. Adding an R-C filter,
RCM and CCM, on the output of current monitor with the cut off
frequency below one tenth of fSW is recommended to attenu-
ate sampling noise.
Maximum Duty Cycle
When operating with a high PWM duty cycle, the high-side
NMOS device is forced off each cycle for 320ns to ensure that
CHB is recharged and to allow time to sample and hold the
current in the low-side NMOS FET. This forced off-time limits
the maximum duty cycle of the controller. When designing a
regulator with high switching frequency and high duty cycle
requirements, a check should be made of the required maxi-
mum duty cycle against the graph shown in Figure 15. The
actual maximum duty cycle varies with the switching frequen-
cy as follows:
The LO and HO outputs are controlled with an adaptive dead-
time methodology which insures that both outputs are never
enabled at the same time. When the controller commands HO
to be enabled, the adaptive dead-time logic first disables LO
and waits for the LO voltage to drop. HO is then enabled after
a small delay (LO Fall to HO Rise Delay). Similarly, the LO
turn-on is delayed until the HO voltage has discharged. LO is
then enabled after a small delay (HO Fall to LO Rise Delay).
This technique insures adequate dead-time for any size
NMOS device, especially when VCC is supplied by a higher
external voltage source. The adaptive dead-time circuitry
monitors the voltages of HO and LO outputs and insures the
dead-time between the HO and LO outputs. Adding a gate
resister, RGH or RGL, may decrease the effective dead-time.
Care should be exercised in selecting an output NMOS device
with the appropriate threshold voltage, especially if VCC is
supplied by an external bias supply voltage below the VCC
regulation level. During startup at low input voltages, the low-
side NMOS device gate plateau voltage should be lower than
the VCC under-voltage lockout threshold. Otherwise, there
may be insufficient VCC voltage to completely enhance the
NMOS device as the VCC under-voltage lockout is released
during startup. If the high-side NMOS drive voltage is lower
than the high-side NMOS device gate plateau voltage during
startup, the regulator may not start or it may hang up mo-
mentarily in a high power dissipation state. This condition can
be addressed by selecting an NMOS device with a lower
threshold voltage. This situation can be avoided if the mini-
mum input voltage programmed by the UVLO resistor is
above the VCC regulation level.
30143214
FIGURE 15. Maximum Duty Cycle vs Switching
Frequency
Current Monitor
The LM5117 provides average output current information,
enabling various applications requiring monitoring or control
of the output current.
Thermal Protection
Internal thermal shutdown circuitry is provided to protect the
controller in the event the maximum junction temperature is
exceeded. When activated, typically at 165°C, the controller
is forced into a low power shutdown mode, disabling the out-
put drivers and the VCC regulator. This feature is designed to
prevent overheating and destroying the device.
30143280
FIGURE 14. Current Monitor
17
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The pole at the origin minimizes output steady state error. The
low frequency zero should be placed to cancel the load pole
of the modulator. The high frequency pole can be used to
cancel the zero created by the output capacitor ESR or to
decrease noise susceptibility of the error amplifier. By placing
the low frequency zero an order of magnitude less than the
crossover frequency, the maximum amount of phase boost
can be achieved at the crossover frequency. The high fre-
quency pole should be placed well beyond the crossover
frequency since the addition of CHF adds a pole in the feed-
back transfer function.
Application Information
FEEDBACK COMPENSATION
Open loop response of the regulator is defined as the product
of modulator transfer function and feedback transfer function.
When plotted on a dB scale, the open loop gain is shown as
the sum of modulator gain and feedback gain.
The modulator transfer function includes a power stage trans-
fer function with an embedded current loop and can be sim-
plified as one pole and one zero system as shown in equation
(15).
The crossover frequency (loop bandwidth) is usually selected
between one twentieth and one fifth of the fSW. In a simplified
formula, the crossover frequency can be defined as:
(17)
(15)
For higher crossover frequency, RCOMP can be increased,
while proportionally decreasing CCOMP. Conversely, decreas-
ing RCOMP while proportionally increasing CCOMP, results in
lower bandwidth while keeping the same zero frequency in
the feedback transfer function.
The sampled gain inductor pole is inversely proportional to
the K factor, which is defined as:
(18)
The maximum achievable loop bandwidth, in fact, is limited
by this sampled gain inductor pole. In traditional current mode
control, the maximum achievable loop bandwidth varies with
input voltage. With the LM5117’s unique slope compensation
scheme, the sampled gain inductor pole is independent of
changes to the input voltage. This frees the user from addi-
tional concerns in wide varying input range applications and
is an advantage of the LM5117.
If the ESR of COUT (RESR) is very small, the modulator transfer
function can be further simplified to a one pole system and
the voltage loop can be closed with only two loop compensa-
tion components, RCOMP and CCOMP, leaving a single pole
response at the crossover frequency. A single pole response
at the crossover frequency yields a very stable loop with 90
degrees of phase margin.
The feedback transfer function includes the feedback resistor
If the sampled gain inductor pole or the ESR zero is close to
the crossover frequency, it is recommended that the compre-
hensive formulas in Table 1 be used and the stability should
be checked by a network analyzer. The modulator transfer
function can be measured and the feedback transfer function
can be configured for the desired open loop transfer function.
If a network analyzer is not available, step load transient tests
can be performed to verify acceptable performance. The step
load goal is minimum overshoot/undershoot with a damped
response.
divider and loop compensation of the error amplifier. RCOMP
,
CCOMP and optional CHF configure the error amplifier gain and
phase characteristics and create a pole at origin, a low fre-
quency zero and a high frequency pole. This is shown math-
ematically in equation (16).
(16)
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18
SUB-HARMONIC OSCILLATION
turbation results in sub-harmonic oscillation. If K=1, any initial
perturbation will be removed in one switching cycle. This is
known as one-cycle damping. When -1<dl1/dl0<0, any initial
perturbation will be under-damped. Any perturbation will be
over-damped when 0<dl1/dl0<1.
Peak current mode regulators can exhibit unstable behavior
when operating above 50% duty cycle. This behavior is
known as sub-harmonic oscillation and is characterized by
alternating wide and narrow pulses at the SW pin. Sub-har-
monic oscillation can be prevented by adding an additional
voltage ramp (slope compensation) on top of the sensed in-
ductor current shown in Figure 7. By choosing K≥1, the
regulator will not be subject to sub-harmonic oscillation
caused by a varying input voltage.
In the frequency-domain, Q, the quality factor of the sampling
gain term in the modulator transfer function, is used to predict
the tendency for sub-harmonic oscillation, which is defined
as:
In time-domain analysis, the steady-state inductor current
starts and ends at the same value during one clock cycle. If
the magnitude of the end-of-cycle current error, dI1, caused
by an initial perturbation, dI0, is less than the magnitude of
dI0 or dI1/dI0 > -1, the perturbation naturally disappears after
a few cycles. When dI1/dI0 < -1, the initial perturbation does
not disappear, resulting in sub-harmonic oscillation in steady-
state operation.
(20)
The relationship between Q and K factor is illustrated graph-
ically in Figure 18.
30143281
30143277
FIGURE 16. Effect of Initial Perturbation when dl1/dl0 < -1
FIGURE 18. Sampling gain Q vs K Factor
dI1/dI0 can be calculated by:
The minimum value of K is 0.5 again. This is the same as time
domain analysis result. When K<0.5, the regulator is unsta-
ble. High gain peaking at 0.5 results in sub-harmonic oscilla-
tion at FSW/2. When K=1, one-cycle damping is realized. Q is
equal to 0.673 at this point. A higher K factor may introduce
additional phase shift by moving the sampled gain inductor
pole closer to the crossover frequency, but will help reduce
noise sensitivity in the current loop. The maximum allowable
value of K factor can be calculated by the Maximum
Crossover Frequency equation in Table 1.
(19)
The relationship between dI1/dI0 and K factor is illustrated
graphically in Figure 17.
PC BOARD LAYOUT RECOMMENDATION
In a buck regulator the primary switching loop consists of the
input capacitor, NMOS power switches and current sense re-
sistor. Minimizing the area of this loop reduces the stray
inductance and minimizes noise and possible erratic opera-
tion. High quality input capacitors should be placed as close
as possible to the NMOS power switches, with the VIN side of
the capacitor connected directly to the high-side NMOS drain
and the ground side of the capacitor connected as close as
possible to the current sense resistor ground connection.
Connect all of the low power ground connections (RUV1, RT,
RFB1, CSS, CRES, CCM, CVIN, CRAMP) directly to the regulator
AGND pin. Connect CVCC directly to the regulator PGND pin.
Note that CVIN and CVCC must be as physically close as pos-
sible to the IC. AGND and PGND must be directly connected
together through a top-side copper pattern connected to the
exposed pad. Ensure no high current flows beneath the un-
derside exposed pad.
30143276
FIGURE 17. dl1/dl0 vs K Factor
The minimum value of K is 0.5. When K<0.5, the amplitude
of dI1 is greater than the amplitude of dI0 and any initial per-
19
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The LM5117 has an exposed thermal pad to aid power dissi-
pation. Adding several vias under the exposed pad helps
conduct heat away from the IC. The junction to ambient ther-
mal resistance varies with application. The most significant
variables are the area of copper in the PC board, the number
of vias under the exposed pad and the amount of forced air
cooling. The integrity of the solder connection from the IC ex-
posed pad to the PC board is critical. Excessive voids greatly
decrease the thermal dissipation capacity.
The highest power dissipating components are the two power
switches. Selecting NMOS switches with exposed pads aids
the power dissipation of these devices.
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20
TABLE 1. LM5117 Frequency Analysis Formulas
SIMPLE FORMULA
COMPREHENSIVE FORMULA*
MODULATOR
TRANSFER
FUNCTION
Modulator DC
Gain
ESR Zero
ESR Pole
Not considered
Dominant
Load Pole
Sampled Gain
Inductor Pole
Not considered
Not considered
Not considered
Quality Factor
Sub-harmonic
Double Pole
K Factor
FEEDBACK
TRANSFER
FUNCTION
Feedback DC
Gain
Mid-band Gain
Low
Frequency
Zero
High
Frequency
Pole
OPEN-LOOP
RESPONSE
21
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SIMPLE FORMULA
COMPREHENSIVE FORMULA*
Cross Over
Frequency
(Open Loop
Bandwidth)
Maximum
Cross Over
Frequency
The frequency at which 45° phase shift occurs in modulator phase charac-
teristics.
* Comprehensive Equation includes an inductor pole and a gain peaking at fSW/2, which caused by sampling effect of the current mode control. Also it assumes
that a ceramic capacitor COUT2 (No ESR) is connected in parallel with COUT1. RESR1 represents ESR of COUT1
.
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22
CURRENT SENSE RESISTOR RS
Design Example
The performance of the converter will vary depending on the
K value. For this example, K=1 was chosen to control sub-
harmonic oscillation and achieve one-cycle damping. The
maximum output current capability (IOUT(MAX)) should be
20~50% higher than the required output current, to account
for tolerances and ripple current. For this example, 130% of
9A was chosen. The current sense resistor value can be cal-
culated from the equation (9), (10) as follows:
OPERATING CONDITIONS
•
•
•
•
•
•
•
Output Voltage
Full Load Current
Minimum Input Voltage
Maximum Input Voltage
Switching Frequency
Diode Emulation
VOUT = 12V
IOUT = 9A
VIN(MIN) = 15V
VIN(MAX) = 55V
fSW = 230kHz
Yes
External VCC Supply
Yes
TIMING RESISTOR RT
Generally, higher frequency applications are smaller but have
higher losses. Operation at 230 kHz was selected for this ex-
ample as a reasonable compromise between small size and
high efficiency. The value of RT for 230 kHz switching fre-
quency can be calculated from the equation (3) as follows:
A value of 7.41mΩ was realized for RS by placing an addi-
tional 0.1Ω sense resistor in parallel with 8mΩ. The sense
resistor must be rated to handle the power dissipation at max-
imum input voltage when current flows through the low-side
NMOS for the majority of the PWM cycle. The maximum pow-
er dissipation of RS can be calculated as:
A standard value of 22.1kΩ was chosen for RT.
OUTPUT INDUCTOR LO
The maximum inductor ripple current occurs at the maximum
input voltage. Typically, 20% to 40% of the full load current is
a good compromise between core loss and copper loss of the
inductor. Higher ripple current allows for a smaller inductor
size, but places more of a burden on the output capacitor to
smooth the ripple voltage on the output. For this example, a
ripple current of 40% of 9A was chosen. Knowing the switch-
ing frequency, maximum ripple current, maximum input volt-
age and the nominal output voltage, the inductor value can
be calculated as follows:
The worst case peak inductor current under the output short
condition can be calculated from the equation (12) as follows:
Where tON(MIN) is normally 100ns.
CURRENT SENSE FILTER RCS and CCS
The closest standard value of 10μH was chosen for LO. Using
the value of 10μH for LO, calculate IPP again. This step is nec-
essary if the chosen value of LO differs significantly from the
calculated value.
The LM5117 itself is not affected by the large leading edge
spike because it samples valley current just prior to the onset
of the high-side switch. A current sense filter is used to mini-
mize a noise injection from any external noise sources. In
general, a current sense filter is not necessary. In this exam-
ple, a current sense filter is not used
From the equation (11),
Adding RCS resistor changes the current sense amplifier gain
which is defined as AS=10k / (1k+RCS). A small value of RCS
resistor below 100Ω is recommended to minimize the gain
change which is caused by the temperature coefficient differ-
ence between internal and external resistors.
At the minimum input voltage, this value is 1.04A
RAMP RESISTOR RRAMP and RAMP CAPACITOR CRAMP
DIODE EMULATION FUNCTION
The positive slope of the inductor current ramp signal is em-
ulated by RRAMP and CRAMP. For this example, the value of
CRAMP was set at the standard capacitor value of 820pF. With
the inductor, sense resistor and the K factor selected, the val-
ue of RRAMP can be calculated from the equation (4) as
follows:
The DEMB pin is left floating since this example uses diode
emulation to reduce the power loss under no load or light load
conditions.
23
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NMOS device turns on and off. During the transition period
both current and voltage are present in the channel of the
NMOS device. The switching loss can be approximated as:
tR and tF are the rise and fall times of the high-side NMOS
device. The rise and fall times are usually mentioned in the
MOSFET datasheet or can be empirically observed with an
oscilloscope. Switching loss is calculated for the high-side
NMOS device only. Switching loss in the low-side NMOS de-
vice is negligible because the body diode of the low-side
NMOS device turns on before and after the low-side NMOS
device switches. For this example, the maximum drain-to-
source voltage applied to either NMOS device is 55V. The
selected NMOS devices must be able to withstand 55V plus
any ringing from drain to source and must be able to handle
at least the VCC voltage plus any ringing from gate to source.
The standard value of 165 kΩ was selected for RRAMP
.
UVLO DIVIDER RUV2, RUV1 AND CFT
The desired startup voltage and the hysteresis are set by the
voltage divider RUV1 and RUV2. Capacitor CFT provides filter-
ing for the divider. For this design, the startup voltage was set
to 14V, 1V below VIN(MIN). VHYS was set to 2V. The value of
RUV1, RUV2 can be calculated from equations (1) and (2) as
follows:
SNUBBER COMPONENTS RSNB AND CSNB
A resistor-capacitor snubber network across the low-side
NMOS device reduces ringing and spikes at the switching
node. Excessive ringing and spikes can cause erratic opera-
tion and can couple noise to the output voltage. Selecting the
values for the snubber is best accomplished through empirical
methods. First, make sure the lead lengths for the snubber
connections are very short. Start with a resistor value be-
tween 5 and 50Ω. Increasing the value of the snubber capac-
itor results in more damping, but higher snubber losses.
Select a minimum value for the snubber capacitor that pro-
vides adequate damping of the spikes on the switch waveform
at heavy load. A snubber may not be necessary with an op-
timized layout.
The standard value of 100kΩ was selected for RUV2. RUV1 was
selected to be 9.76kΩ. A value of 47pF was chosen for CFT
.
VCC DISABLE AND EXTERNAL VCC SUPPLY
The 12V output voltage allows the external VCC supply con-
figuration as shown in Figure 3. In this example, VCCDIS can
be left floating since VOUT is higher than VCC regulator set-
point level.
BOOTSTRAP CAPACITOR CHB AND BOOTSTRAP DIODE
DHB
POWER SWITCHES QH and QL
Selection of the power NMOS devices is governed by the
same trade-offs as switching frequency. Breaking down the
losses in the high-side and low-side NMOS devices is one
way to compare the relative efficiencies of different devices.
Losses in the power NMOS devices can be broken down into
conduction loss, gate charging loss, and switching loss.
The bootstrap capacitor between the HB and SW pin supplies
the gate current to charge the high-side NMOS device gate
during each cycle’s turn-on and also supplies recovery charge
for the bootstrap diode. These current peaks can be several
amperes. The recommended value of the bootstrap capacitor
is at least 0.1μF. CHB should be a good quality, low ESR, ce-
ramic capacitor located at the pins of the IC to minimize
potentially damaging voltage transients caused by trace in-
ductance. The absolute minimum value for the bootstrap
capacitor is calculated as:
Conduction loss PDC is approximately:
Where D is the duty cycle and the factor of 1.3 accounts for
the increase in the NMOS device on-resistance due to heat-
ing. Alternatively, the factor of 1.3 can be eliminated and the
high temperature on-resistance of the NMOS device can be
estimated using the RDS(ON) vs Temperature curves in the
MOSFET datasheet.
Where Qg is the high-side NMOS gate charge and ΔVHB is
the tolerable voltage droop on CHB, which is typically less than
5% of VCC or 0.15V conservatively. A value of 0.47μF was
selected for this design.
Gate charging loss (PGC) results from the current driving the
gate capacitance of the power NMOS devices and is approx-
imated as:
VCC CAPACITOR CVCC
The primary purpose of the VCC capacitor (CVCC) is to supply
the peak transient currents of the LO driver and bootstrap
diode as well as provide stability for the VCC regulator. These
peak currents can be several amperes. The recommended
value of CVCC should be no smaller than 0.47μF, and should
be a good quality, low ESR, ceramic capacitor. CVCC should
be placed at the pins of the IC to minimize potentially dam-
aging voltage transients caused by trace inductance. A value
of 1μF was selected for this design.
Qg refers to the total gate charge of an individual NMOS de-
vice, and ‘n’ is the number of NMOS devices. Gate charge
loss differs from conduction and switching losses in that the
actual dissipation occurs in the controller IC. Switching loss
(PSW) occurs during the brief transition period as the high-side
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24
OUTPUT CAPACITOR CO
jection into the VIN pin. 0.47μF ceramic capacitor is used for
CVIN in the example. RVIN is selected to be 3.9Ω
The output capacitors smooth the output voltage ripple
caused by inductor ripple current and provide a source of
charge during transient loading conditions. For this design
example, a 470μF electrolytic capacitor with maximum
20mΩ ESR was selected as the main output capacitor. The
fundamental component of the output ripple voltage with max-
imum ESR is approximated as:
SOFT-START CAPACITOR CSS
The capacitor at the SS pin (CSS) determines the soft-start
time (tSS), which is the time for the output voltage to reach the
final regulated value. The tSS for a given CSS can be calculated
from equation (8) as follows:
For this example, a value of 0.1μF was chosen for a soft-start
time of 8ms.
RESTART CAPACITOR CRES
The capacitor at the RES pin (CRES) determines tRES, which
is the time the LM5117 remains off before a restart attempt is
made in hiccup mode current limiting. tRES for a given CRES
can be calculated from equation (13) as follows:
Additional low ERS / ESL ceramic capacitors can be placed
in parallel with the main output capacitor to further reduce the
output voltage ripple and spikes. In this example, two 22μF
capacitors were added.
INPUT CAPACITOR CIN
The regulator input supply voltage typically has high source
impedance at the switching frequency. Good quality input ca-
pacitors are necessary to limit the ripple voltage at the VIN
pin while supplying most of the switch current during the on-
time. When the high-side NMOS device turns on, the current
into the device steps to the valley of the inductor current
waveform, ramps up to the peak value, and then drops to the
zero at turnoff. The input capacitor should be selected for
RMS current rating and minimum ripple voltage. A good ap-
proximation for the required ripple current rating necessary is
IRMS > IOUT / 2.
For this example, a value of 0.47μF was chosen for a restart
time of 59ms.
OUTPUT VOLTAGE DIVIDER RFB2 and RFB1
RFB1 and RFB2 set the output voltage level. The ratio of these
resistors is calculated as:
In this example, seven 3.3μF ceramic capacitors were used.
With ceramic capacitors, the input ripple voltage will be trian-
gular. The input ripple voltage can be approximated as:
The ratio between RCOMP and RFB2 determines the mid-band
gain, AFB_MID. A larger value for RFB2 may require a corre-
sponding larger value for RCOMP. RFB2 should be large enough
to keep the total divider power dissipation small. 4.99kΩ was
chosen for RFB2 in this example, which results in a RFB1 value
of 357Ω for 12V output.
LOOP COMPENSATION COMPONENTS CCOMP, RCOMP
and CHF
RCOMP, CCOMP and CHF configure the error amplifier gain and
phase characteristics to produce a stable voltage loop. For a
quick start, follow the 4 steps listed below. For detailed infor-
mation, see Application Information.
Capacitors connected in parallel should be evaluated for RMS
current rating. The current will split between the input capac-
itors based on the relative impedance of the capacitors at the
switching frequency.
STEP1: Select fCROSS
By selecting one tenth of the switching frequency, fCROSS is
calculated as follows:
VIN FILTER RVIN, CVIN
An R-C filter (RVIN, CVIN) on VIN is optional. The filter helps to
prevent faults caused by high frequency switching noise in-
25
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STEP2: Determine required RCOMP
Knowing fCROSS, RCOMP is calculated as follows:
The standard value of 22nF was selected for CCOMP
STEP4: Determine CHF to cancel ESR zero
Knowing RCOMP and CCOMP, CHF is calculated as follows:
The standard value of 27.4kΩ was selected for RCOMP
STEP3: Determine CCOMP to cancel load pole
Knowing RCOMP, CCOMP is calculated as follows:
Half of the maximum ESR is assumed as a typical ESR. The
standard value of 180pF was selected for CHF
.
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26
Application Circuit
30143221
FIGURE 19. 12V, 9A Typical Application Schematic
27
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When the VCCDIS pin voltage is greater than the VCCDIS
threshold, the controller disables the VCC regulator and the
VCC pin voltage decays. When the VCC pin voltage is less
than the VCC UV threshold, both HO and LO outputs stop
switching. Due to the time delay required for VCC to decay
below the VCC UV threshold, the over-voltage protection op-
erates in hiccup mode. See Figure 20.
Example of Constant Current
Regulator
The LM5117 can be configured as a constant current regula-
tor by using the current monitor feature (CM) as the feedback
input. A voltage divider at the VCCDIS pin from VOUT to
AGND can be used to protect against output over-voltage.
30143282
FIGURE 20. Constant Current Regulator with Hiccup Mode Output OVP
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28
The LM5117 also can be configured as a constant voltage
and constant current regulator, known as CV+CC regulator.
In this configuration, there is much less variation in the current
limiting as compared to peak cycle-by-cycle current limiting of
the inductor current. The LMV431 and the PNP transistor cre-
ate a voltage-to-current amplifier in the current loop. This
amplifier circuitry does not affect the normal operation when
the output current is less than the current limit set-point. When
the output current is greater than the set-point, the PNP tran-
sistor sources a current into CRAMP and increases the positive
slope of emulated inductor current ramp until the output cur-
rent is less than or equal to the current limit set-point. See
Figure 21 and Figure 22.
30143283
FIGURE 21. Constant Voltage Regulator with Accurate Current Limit
301432145
FIGURE 22. Current Limit Comparison
29
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Physical Dimensions inches (millimeters) unless otherwise noted
20 Pin TSSOP with Exposed Pad
NS Package Number MXA20A
24 Pin LLP
NS Package Number SQA24A
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30
Notes
31
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Notes
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