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LM5117, LM5117-Q1

SNVS698F –APRIL 2011–REVISED AUGUST 2015

LM5117/Q1 Wide Input Range Synchronous Buck Controller with Analog Current Monitor

1 Features

3 Description

The LM5117 is

a synchronous buck controller

1

•

LM5117-Q1 is Qualified for Automotive

Applications

intended for step-down regulator applications from a

high voltage or widely varying input supply. The

control method is based upon current mode control

utilizing an emulated current ramp. Current mode

control provides inherent line feed-forward, cycle-by-

cycle current limiting and ease of loop compensation.

The use of an emulated control ramp reduces noise

sensitivity of the pulse-width modulation circuit,

allowing reliable control of very small duty cycles

necessary in high input voltage applications.

•

AEC-Q100 Qualified With the Following Results:

–

Device Temperature Grade 1: -40°C to 125°C

Ambient Operating Temperature Range

•

Emulated Peak Current Mode Control

Wide Operating Range from 5.5 V to 65 V

Robust 3.3-A Peak Gate Drives

Adaptive Dead-Time Output Driver Control

Free-Run or Synchronizable Clock up to 750 kHz

Optional Diode Emulation Mode

The operating frequency is programmable from 50

kHz to 750 kHz. The LM5117 drives external high-

side and low-side NMOS power switches with

adaptive dead-time control. A user-selectable diode

emulation mode enables discontinuous mode

operation for improved efficiency at light load

conditions. A high voltage bias regulator that allows

external bias supply further improves efficiency. The

LM5117’s unique analog telemetry feature provides

average output current information. Additional

features include thermal shutdown, frequency

synchronization, hiccup mode current limit, and

adjustable line undervoltage lockout.

Programmable Output from 0.8 V

Precision 1.5% Voltage Reference

Analog Current Monitor

Programmable Current Limit

Hiccup Mode Overcurrent Protection

Programmable Soft-Start and Tracking

Programmable Line Undervoltage Lockout

Programmable Switchover to External Bias Supply

Thermal Shutdown

Device Information⁽¹⁾

2 Applications

PART NUMBER

LM5117

LM5117-Q1

PACKAGE

HTSSOP (20) PWP 6.50 mm × 4.40 mm

WQFN (24) RTW 4.00 mm × 4.00 mm

BODY SIZE (NOM)

•

Automotive Infotainment

Industrial DC-DC Motor Drivers

Automotive USB Power

Telecom Server

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

Typical Application

V

IN

UVLO

VIN

DEMB

VCC

HB

SW

RAMP

LM5117

V

OUT

HO

SW

LO

V

OUT

VCCDIS

COMP

FB

CS

CM

CSG

RT RES SS AGND PGND

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM5117, LM5117-Q1

SNVS698F –APRIL 2011–REVISED AUGUST 2015

www.ti.com

Table of Contents

7.3 Feature Description................................................. 13

7.4 Device Functional Modes........................................ 21

Application and Implementation ........................ 22

8.1 Application Information............................................ 22

8.2 Typical Applications ............................................... 22

8.3 Detailed Design Procedure ..................................... 22

8.4 Application Curves .................................................. 32

Power Supply Recommendations...................... 35

1

2

3

4

5

6

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ..................................... 5

6.2 ESD Ratings (LM5117)............................................. 5

6.3 ESD Ratings (LM5117-Q1) ....................................... 5

6.4 Recommended Operating Conditions....................... 6

6.5 Thermal Information.................................................. 6

6.6 Electrical Characteristics........................................... 7

6.7 Switching Characteristics.......................................... 8

6.8 Typical Characteristics.............................................. 9

Detailed Description ............................................ 11

7.1 Overview ................................................................. 11

7.2 Functional Block Diagram ....................................... 12

8

9

10 Layout................................................................... 35

10.1 Layout Guideline ................................................... 35

11 Device and Documentation Support ................. 36

11.1 Related Links ........................................................ 36

11.2 Community Resources.......................................... 36

11.3 Trademarks........................................................... 36

11.4 Electrostatic Discharge Caution............................ 36

11.5 Glossary................................................................ 36

7

12 Mechanical, Packaging, and Orderable

Information ........................................................... 36

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision E (March 2013) to Revision F

Page

•

Added Device Information and Pin Configuration and Functions sections, ESD Rating table, Feature Description,

Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and

Documentation Support , and Mechanical, Packaging, and Orderable Information sections ................................................ 1

•

Changed µH into µF ............................................................................................................................................................ 29

Changes from Revision D (March 2013) to Revision E

Page

•

Changed layout of National Data Sheet to TI format ........................................................................................................... 34

2

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SNVS698F –APRIL 2011–REVISED AUGUST 2015

5 Pin Configuration and Functions

PWP Package

20-Pin HTSSOP

Top View

UVLO

DEMB

RES

1

2

3

4

5

6

7

8

9

20

19

18

17

16

15

14

13

12

11

VIN

HB

HO

SS

SW

RT

VCC

LO

EP

AGND

VCCDIS

FB

PGND

CSG

CS

COMP

10

CM

RAMP

RTW Package

24-Pin WQFN

Top View

24

23

22

21

20

19

DEMB

RES

SS

1

2

3

4

5

6

18

17

16

15

14

13

SW

NC

VCC

LO

EP

RT

AGND

NC

PGND

CSG

7

8

9

10

11

12

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SNVS698F –APRIL 2011–REVISED AUGUST 2015

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Pin Functions

(1)

TYPE

DESCRIPTION

HTSSOP WQFN

NAME

1

24

UVLO

Undervoltage lockout programming pin. If the UVLO pin voltage is below 0.4 V, the

regulator is in the shutdown mode with all functions disabled. If the UVLO pin voltage is

greater than 0.4 V and less than 1.25 V, the regulator is in standby mode with the VCC

regulator operational, the SS pin grounded, and no switching at the HO and LO outputs.

If the UVLO pin voltage is above 1.25 V, the SS pin is allowed to ramp and pulse width

modulated gate drive signals are delivered to the HO and LO pins. A 20μA current

source is enabled when UVLO exceeds 1.25 V and flows through the external UVLO

resistors to provide hysteresis.

I

2

3

1

2

DEMB

RES

Optional logic input that enables diode emulation when in the low state. In diode

emulation mode, the low-side NMOS is latched off for the remainder of the PWM cycle

after detecting reverse current flow (current flow from output to ground through the low-

side NMOS). When DEMB is high, diode emulation is disabled allowing current to flow in

either direction through the low-side NMOS. A 50-kΩ pull-down resistor internal to the

LM5117 holds DEMB pin low and enables diode emulation if the pin is left floating.

I

The restart timer pin that configures the hiccup mode current limiting. A capacitor on the

RES pin determines the time the controller remains off before automatically restarting.

The hiccup mode commences when the controller experiences 256 consecutive PWM

cycles of cycle-by-cycle current limiting. After this occurs, a 10-μA current source

charges the RES pin capacitor to the 1.25 V threshold and restarts LM5117.

O

I

4

5

3

4

SS

RT

An external capacitor and an internal 10-μA current source set the ramp rate of the error

amplifier reference during soft-start. The SS pin is held low when VCC< 5 V, UVLO <

1.25 V or during thermal shutdown.

The internal oscillator is programmed with a single resistor between RT and the AGND.

The recommended maximum oscillator frequency is 750kHz. The internal oscillator can

be synchronized to an external clock by coupling a positive pulse into the RT pin through

a small coupling capacitor.

I

6

7

5

7

AGND

G

Analog ground. Return for the internal 0.8 V voltage reference and analog circuits.

VCCDIS

Optional input that disables the internal VCC regulator. If VCCDIS>1.25 V, the internal

VCC regulator is disabled. VCCDIS has an internal 500-kΩ pulldown resistor to enable

the VCC regulator when the pin is left floating. The internal 500-kΩ pull-down resistor can

be overridden by pulling VCCDIS above 1.25 V with a resistor divider connected to an

external bias supply.

I

8

9

8

9

FB

Feedback. Inverting input of the internal error amplifier. A resistor divider from the output

to this pin sets the output voltage level. The regulation threshold at the FB pin is 0.8 V.

I

COMP

CM

Output of the internal error amplifier. The loop compensation network should be

connected between this pin and the FB pin.

O

10

11

10

11

Current monitor output. Average of the sensed inductor current is provided. Monitor

directly between CM and AGND. CM should be left floating when the pin is not used.

RAMP

PWM ramp signal. An external resistor and capacitor connected between the SW pin, the

RAMP pin and the AGND pin sets the PWM ramp slope. Proper selection of component

values produces a RAMP signal that emulates the AC component of the inductor with a

slope proportional to input supply voltage.

I

12

13

12

13

CS

I

Current sense amplifier input. Connect to the high-side of the current sense resistor.

CSG

Kelvin ground connection to the current sense resistor. Connect directly to the low-side of

the current sense resistor.

G

14

15

16

17

14

15

16

18

PGND

LO

Power ground return pin for low-side NMOS gate driver. Connect directly to the low-side

of the current sense resistor.

O

Low-side NMOS gate drive output. Connect to the gate of the low-side synchronous

NMOS transistor through a short, low inductance path.

P/O/I

I/O

VCC

SW

Bias supply pin. Locally decouple to PGND using a low ESR/ESL capacitor located as

close to controller as possible.

Switching node of the buck regulator. Connect to the bootstrap capacitor, the source

terminal of the high-side NMOS transistor and the drain terminal of the low-side NMOS

through a short, low inductance path.

O

P

18

19

HO

High-side NMOS gate drive output. Connect to the gate of the high-side NMOS transistor

through a short, low inductance path.

(1) I = Input, O = Output, G = Ground, P = Power

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SNVS698F –APRIL 2011–REVISED AUGUST 2015

Pin Functions (continued)

HTSSOP WQFN

(1)

TYPE

DESCRIPTION

NAME

19

20

HB

High-side driver supply for the bootstrap gate drive. Connect to the cathode of the

external bootstrap diode and to the bootstrap capacitor. The bootstrap capacitor supplies

current to charge the high-side NMOS gate and should be placed as close to controller

as possible.

P/I

20

22

VIN

EP

P/I

-

Supply voltage input source for the VCC regulator.

EP

Exposed pad of the package. Electrically isolated. Should be soldered to the ground

plane to reduce thermal resistance.

6

NC

-

No electrical contact.

17

21

23

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–3.0

–0.3

–55

MAX

UNIT

V

VIN to AGND

SW to AGND

HB to SW

75

V

15

V

(2)

VCC to AGND

15

V

HO to SW

HB + 0.3

V

LO to AGND

VCC + 0.3

V

FB, DEMB, RES, VCCDIS, UVLO to AGND

CM, COMP to AGND⁽³⁾

SS, RAMP, RT to AGND

CS, CSG, PGND, to AGND

Storage Temperature, T_stg

Junction temperature

15

7

V

7

V

0.3

150

V

°C

–40

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) See Application and Implementation when input supply voltage is less than the VCC voltage.

(3) These pins are output pins. As such they are not specified to have an external voltage applied.

6.2 ESD Ratings (LM5117)

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

V

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per JEDEC specification JESD22- V

C101⁽²⁾

±750

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 ESD Ratings (LM5117-Q1)

VALUE

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

±2000

±750

V

V_(ESD)

Electrostatic discharge

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

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6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

5.5

-40

MAX

65

UNIT

V

VIN⁽²⁾

VCC

14

V

HB to SW

Junction temperature

14

V

125

°C

(1) Recommended Operating Conditions are conditions under which operation of the device is intended to be functional, but does not

ensure specific performance limits. For specifications and test conditions see Electrical Characteristics.

(2) Minimum VIN operating voltage is defined with VCC supplied by the internal HV startup regulator and no external load on VCC. When

VCC is supplied by an external source, minimum VIN operating voltage is 4.5 V.

6.5 Thermal Information

LM5117, LM5117-Q1

THERMAL METRIC⁽¹⁾

PWP (HTSSOP) RTW (WQFN)

UNIT

20 PINS

24 PINS

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

40

4

40

6

°C/W

R_θJC(top)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6

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6.6 Electrical Characteristics

Typical limits are for T_J= 25°C only, represent the most likely parametric norm at T_J= 25°C, and are provided for reference

purposes only; minimum and maximum limits apply over the junction temperature range of –40°C to +125°C. Unless

otherwise specified, the following conditions apply: V_VIN= 48 V, V_VCCDIS= 0 V, R_T= 25 kΩ, no load on LO and HO.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIN SUPPLY

V_SS= 0 V

4.8

0.4

16

6.2

0.55

40

mA

µA

(1)

I_BIAS

V_INoperating current

V_SS= 0 V, V_VCCDIS= 2 V

V_SS= 0 V, V_UVLO= 0 V

I_SHUTDOWNV_INshutdown current

VCC REGULATOR

V_CC(REG)

VCC regulation

No load

6.85

30

7.6

0.05

0.4

42

8.2

0.14

0.5

V

V_VIN= 5.5 V, No external load

V_VIN= 6 V, I_CC= 20 mA

V_VCC= 0 V

VCC dropout (VIN to VCC)

VCC sourcing current limit

V

mA

V_SS= 0 V, V_VCCDIS= 2 V

4

5

7.3

(1)

I_VCC

VCC operating current

V_SS= 0 V, V_VCCDIS= 2 V, V_VCC= 14

V

5.8

mA

VCC undervoltage threshold

VCC undervoltage hysteresis

VCC rising

4.7

4.9

0.2

5.15

V

VCC DISABLE

VCCDIS threshold

VCCDIS rising

V_VCCDIS= 0 V

1.22

1.25

0.06

-20

1.29

V

VCCDIS hysteresis

VCCDIS input current

VCCDIS pulldown resistance

nA

kΩ

500

UVLO

UVLO threshold

UVLO rising

V_UVLO= 1.4 V

UVLO falling

1.22

15

1.25

20

1.29

25

V

µA

V

UVLO hysteresis current

UVLO shutdown threshold

UVLO shutdown hysteresis

0.23

0.3

0.1

V

SOFT START

I_SSSS current source

SS pulldown resistance

ERROR AMPLIFIER

V_SS= 0 V

7

10

13

12

24

µA

Ω

V_REF

FB reference voltage

Measured at FB, FB = COMP

V_FB= 0.8 V

788

2.8

800

1

812

mV

nA

V

FB input bias current

COMP output high voltage

COMP output low voltage

DC gain

V_OH

V_OL

A_OL

ƒ_BW

I_SOURCE= 3 mA

I_SINK= 3 mA

0.26

V

80

3

dB

MHz

Unity gain bandwidth

PWM COMPARATOR

t_HO(OFF)Forced HO Off-time

t_ON(MIN)

260

320

100

1.2

440

ns

V

Minimum HO On-time

V_VIN= 65 V

COMP to PWM comparator offset

OSCILLATOR

ƒ_SW1

ƒ_SW2

Frequency 1

R_T= 25 kΩ

R_T= 10 kΩ

180

430

200

480

1.25

3.2

220

530

kHz

V

Frequency 2

RT output voltage

RT sync positive threshold

Sync pulse width

2.6

3.95

V

100

ns

(1) Operating current does not include the current into the R_Tresistor.

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Electrical Characteristics (continued)

Typical limits are for T_J= 25°C only, represent the most likely parametric norm at T_J= 25°C, and are provided for reference

purposes only; minimum and maximum limits apply over the junction temperature range of –40°C to +125°C. Unless

otherwise specified, the following conditions apply: V_VIN= 48 V, V_VCCDIS= 0 V, R_T= 25 kΩ, no load on LO and HO.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CURRENT LIMIT

Cycle-by-cycle sense voltage

threshold

V_CS(TH)

V_RAMP= 0 V, CSG to CS

106

120

135

mV

CS input bias current

V_CS= 0 V

–100

-66

10

µA

CSG input bias current

Current sense amplifier gain

Hiccup mode fault timer

V_CSG= 0 V

V/V

256

Cycles

RES

I_RES

RES Current Source

RES Threshold

10

µA

V

V_RES

RES Rising

1.22

2.95

1.25

1.285

1.65

DIODE EMULATION

V_IL

V_IH

DEMB input low threshold

2

2.5

–5

V

DEMB input high threshold

SW zero cross threshold

mV

kΩ

DEMB input pulldown resistance

50

CURRENT MONITOR

Current monitor amplifier gain

CS to CM

17.5

–2

20.5

0

23.5

2

V/V

%

Current monitor amplifier gain

Zero input offset

Drift over Temperature

25

120

mV

HO GATE DRIVER

V_OHH

V_OLH

HO High-state voltage drop

HO Low-state voltage drop

HO rise time

I_HO= –100 mA, V_OHH= V_HB– V_HO

I_HO= 100 mA, V_OLH= V_HO– V_SW

C-load = 1000 pF⁽²⁾

0.17

0.1

6

0.3

0.2

V

ns

A

HO fall time

C-load = 1000pF⁽²⁾

5

I_OHH

I_OLH

Peak HO source current

Peak HO sink current

HB to SW undervoltage

HB DC bias current

V_HO= 0 V, SW = 0 V, HB = 7.6 V

V_HO= V_HB= 7.6 V

2.2

3.3

2.9

65

A

2.56

3.32

100

V

HB – SW = 7.6 V

µA

LO GATE DRIVER

V_OHL

V_OLL

LO High-state Voltage Drop

I_LO= –100 mA, V_OHL= V_CC-V_LO

I_LO= 100 mA, V_OLL= V_LO

C-load = 1000 pF⁽²⁾

V_LO= 0 V

0.17

0.1

6

0.27

0.2

V

LO Low-state Voltage Drop

LO rise time

ns

A

LO fall time

5

I_OHL

Peak LO source current

Peak LO sink current

2.5

3.3

I_OLL

V_LO= 7.6 V

A

THERMAL

T_SD

Thermal shutdown

Temperature rising

165

25

°C

Thermal shutdown hysteresis

(2) High and low reference are 80% and 20% of the pulse amplitude, respectively.

6.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

72

MAX

UNIT

ns

T_DLH

T_DHL

LO fall to HO rise delay

HO fall to LO rise delay

No load

71

ns

8

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6.8 Typical Characteristics

Figure 1. HO Peak Driver Current vs Output Voltage

Figure 2. LO Peak Driver Current vs Output Voltage

Figure 4. Driver Dead Time vs Temperature

Figure 6. Switching Frequency vs R_T

Figure 3. Driver Dead Time vs V_VCC

Figure 5. Forced HO Off-time vs Temperature

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Typical Characteristics (continued)

Figure 7. V_VCCvs I_VCC

Figure 8. V_VCCvs V_VIN

Figure 9. V_CS(TH)vs Temperature

Figure 10. V_REFvs Temperature

Figure 12. Error Amp Gain and Phase vs Frequency

Figure 11. V_VCCvs Temperature

10

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Typical Characteristics (continued)

Figure 13. V_CMvs I_OUT

Figure 14. V_CMvs V_CSG-CS

7 Detailed Description

7.1 Overview

The LM5117 high voltage switching controller features all of the functions necessary to implement an efficient

high voltage buck regulator that operates over a very wide input voltage range. This easy to use controller

integrates high-side and low-side NMOS drivers. The regulator control method is based upon peak current mode

control utilizing an emulated current ramp. Peak current mode control provides inherent line feed-forward, cycle-

by-cycle current limiting and ease of loop compensation. The use of an emulated control ramp reduces noise

sensitivity of the PWM circuit, allowing reliable processing of the very small duty cycles necessary in high input

voltage applications.

The switching frequency is user programmable up to 750 kHz. The RT pin allows the switching frequency to be

programmed by a single resistor or synchronized to an external clock. Fault protection features include cycle-by-

cycle and hiccup mode current limiting, thermal shutdown and remote shutdown capability by pulling down UVLO

pin. The UVLO input enables the regulator when the input voltage reaches a user selected threshold and

provides a very low quiescent shutdown current when pulled low. A unique analog telemetry feature provides

averaged output current information, allowing various applications that need either a current monitor or current

control. The functional block diagram and typical application circuit of the LM5117 are shown in Functional Block

Diagram.

The device is available in a HTSSOP-20 (6.5 mm x 4.4 mm) package, as well as a WQFN-24 (4 mm × 4 mm)

package which features an exposed pad to aid in thermal dissipation.

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7.2 Functional Block Diagram

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7.3 Feature Description

7.3.1 High Voltage Start-up Regulator and VCC Disable

The LM5117 contains an internal high voltage bias regulator that provides the VCC bias supply for the PWM

controller and NMOS gate drivers. The VIN pin can be connected to an input voltage source as high as 65 V.

The output of the VCC regulator is set to 7.6V. When the input voltage is below the VCC set-point level, the VCC

output tracks the VIN with a small dropout voltage. The output of the VCC regulator is current limited at 30mA

minimum.

Upon power-up, the regulator sources current into the capacitor connected to the VCC pin. The recommended

capacitance range for the pin VCC is 0.47 µF to 10 µF. When the VCC pin voltage exceeds the VCC UV

threshold and the UVLO pin is greater than UVLO threshold, the HO and LO drivers are enabled and a soft-start

sequence begins. The HO and LO drivers remain enabled until either the VCC pin voltage falls below VCC UV

threshold, the UVLO pin voltage falls below UVLO threshold, hiccup mode is activated or the die temperature

exceeds the thermal shutdown threshold. Enabling/Disabling the IC by controlling UVLO is recommended in most

of cases.

An output voltage derived bias supply can be applied to the VCC pin to reduce the controller power dissipation at

higher input voltage. The VCCDIS input can be used to disable the internal VCC regulator when external biasing

is supplied. The externally supplied bias should be coupled to the VCC pin through a diode, preferably a

Schottky diode. If the VCCDIS pin voltage exceeds the VCCDIS threshold, the internal VCC regulator is disabled.

VCCDIS has a 500-kΩ internal pull-down resistor to ground for normal operation with no external bias.

The VCC regulator series pass transistor includes a diode between VCC (Anode) and VIN (Cathode) that should

not be forward biased in normal operation. If the voltage of the external bias supply is greater than the VIN pin

voltage, an external blocking diode is required from the input power supply to the VIN pin to prevent the external

bias supply from passing current to the input supply through VCC.

V

IN

VIN

LM5117

External

VCC Supply

VCC

Figure 15. VIN Configuration for V_VIN< V_VCC

For V_OUTbetween 6 V and 14.5 V, the output can be connected directly to VCC through a diode.

V

OUT

VCC

LM5117

VCCDIS resistor divider is

required when external VCC

supplying voltage is smaller

than 8.5V

VCCDIS

Figure 16. External VCC Supply for 6 V < V_OUT< 14.5 V

For V_OUT< 6 V, a bias winding on the output inductor can be added to generate the external VCC supply voltage.

VCC

LM5117

VCCDIS

V

OUT

SW

VCCDIS resistor divider is

required when external VCC

supplying voltage is smaller

than 8.5V

Figure 17. External VCC Supply for V_OUT< 6 V

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Feature Description (continued)

For 14.5 V <V_OUT, the external supply voltage can be regulated by using a series Zener diode from the output to

VCC.

V

OUT

R

1

VCC

Zener

R1 is required to limit maximum reverse

zener current 30 kW minimum resistive

loss at VCC guarantees minimum reverse

zener current

30 kW

LM5117

Figure 18. External VCC Supply for 14.5 V < V_OUT

In high input voltage applications, extra care should be taken to ensure the VIN pin does not exceed the absolute

maximum voltage rating of 75V. During line or load transients, voltage ringing on the VIN that exceeds the

Absolute Maximum Rating can damage the IC. Both careful PC board layout and the use of quality bypass

capacitors located close to the VIN and AGND pin are essential. Adding an R-C filter (R_VIN, C_VIN) on VIN is

optional and helps to prevent faulty operation caused by poor PC board layout and high frequency switching

noise injection. The recommended capacitance and resistance range are 0.1 µF to 10 µF and 1 Ω to 10 Ω.

7.3.2 UVLO

The LM5117 contains a dual level UVLO (under-voltage lockout) circuit. When the UVLO is less than 0.4 V, the

LM5117 is in shutdown mode. The shutdown comparator provides 100 mV of hysteresis to avoid chatter during

transitions. When the UVLO pin voltage is greater than 0.4 V but less than 1.25 V, the controller is in standby

mode. In the standby mode, the VCC bias regulator is active but the HO and LO drivers are disabled and the SS

pin is held low. This feature allows the UVLO pin to be used as a remote shutdown function by pulling the UVLO

pin down below 0.4 V with an external open collector or open drain device. When the VCC pin exceeds its under-

voltage lockout threshold and the UVLO pin voltage is greater than 1.25 V, the HO and LO drivers are enabled

and normal operation begins.

UVLO Hysteresis

V

IN

Current

LM5117

UVLO

Threshold

R

UV2

-

+

UVLO

STANDBY

UVLO

Shutdown

Threshold

C

FT

R

UV1

-

+

SHUTDOWN

Figure 19. UVLO Configuration

The UVLO pin should not be left floating. An external UVLO set-point voltage divider from the VIN to AGND is

used to set the minimum input operating voltage of the regulator. The divider must be designed such that the

voltage at the UVLO pin is greater than 1.25 V and never exceeds 15 V when the input voltage is in the desired

operating range. If necessary, the UVLO pin can be clamped with a Zener diode.

UVLO hysteresis is accomplished with an internal 20μA current source that is switched on or off into the

impedance of the UVLO set-point divider. When the UVLO pin voltage exceeds the 1.25 V threshold, the current

source is enabled to quickly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the 1.25

V threshold, the current source is disabled causing the voltage at the UVLO pin to quickly fall. The use of a C_FT

capacitor in parallel with R_UV1helps to minimize switching noise injection into UVLO pin, but it may slow down

the falling speed of the UVLO pin when the 20 μA current source is disabled. The recommended range for C_FTis

10 pF to 220 pF.

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Feature Description (continued)

The values of R_UV1and R_UV2can be determined from the following equations:

V_HYS

[5]

R_UV2

=

20 µA

(1)

1.25V x R_UV2

[5]

R_UV1

=

V_IN(STARTUP)- 1.25V

where

•

V_HYSis the desired UVLO hysteresis and V_IN(STARTUP)is the desired start-up voltage of the regulator during turn-

on (2)

7.3.3 Oscillator and Sync Capability

The LM5117 switching frequency is programmed by a single external resistor connected between the RT pin and

the AGND pin. The resistor should be located very close to the device and connected directly to the RT and

AGND pins. To set a desired switching frequency (ƒ_SW), the resistor value can be calculated from the following

equation:

5.2 x 10⁹

f_SW

- 948 [5]

R_T=

(3)

The RT pin can be used to synchronize the internal oscillator to an external clock. The internal oscillator can be

synchronized by AC coupling a positive edge into the RT pin. The voltage at the RT pin is nominally 1.25 V and

the voltage at the RT pin must exceed the RT Sync Positive Threshold to trip the internal synchronization pulse

detector. A 5 V amplitude pulse signal coupled through a 100-pF capacitor is a good starting point. The

frequency of the external synchronization pulse is recommended to be within ±10% of the frequency

programmed by the RT resistor but will operate to +100/-40% of the programmed frequency. Care should be

taken to guarantee that the RT pin voltage does not go below –0.3 V at the falling edge of the external pulse.

This may limit the duty cycle of external synchronization pulse.

The R_Tresistor is always required, whether the oscillator is free running or externally synchronized.

7.3.4 Ramp Generator and Emulated Current Sense

The ramp signal used in the pulse width modulator for traditional current mode control is typically derived directly

from the high-side switch current. This switch current corresponds to the positive slope portion of the inductor

current. Using this signal for the PWM ramp simplifies the control loop transfer function to a single pole response

and provides inherent input voltage feed-forward compensation.

The disadvantage of using the high-side switch current signal for PWM control is the large leading edge spike

due to circuit parasitics that must be filtered or blanked. Minimum achievable pulse width is limited by the

filtering, blanking time and propagation delay with a high-side current sensing scheme.

In the applications where the input voltage may be relatively large in comparison to the output voltage, controlling

small pulse widths and duty cycles are necessary for regulation. The LM5117 utilizes a unique ramp generator

which does not actually measure the high-side switch current but rather reconstructs the signal. Representing or

emulating the inductor current provides a ramp signal to the PWM comparator that is free of leading edge spikes

and measurement or filtering delays, while maintaining the advantages of traditional peak current mode control.

The current reconstruction is comprised of two elements: a sample-and-hold DC level and the emulated inductor

current ramp as shown in Figure 20. The sample-and-hold DC level is derived from a measurement of the

recirculating current flowing through the current sense resistor. The voltage across the sense resistor is sampled

and held just prior to the onset of the next conduction interval of the high-side switch. The current sense amplifier

with a gain of 10 and sample-and-hold circuit provide the DC level of the reconstructed current signal as shown

in Figure 21.

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Feature Description (continued)

Additional Slope

V

x t

IN

ON

x C

RAMP

=

PK

R

RAMP

I

x R x 10

S

LO

Sample and Hold

DC Level

t

ON

Figure 20. Composition of Emulated Current Sense Signal

CS

10 x V_CS(TH)

Current Sense

Amplifier

-

+

A_S=10

R

S

I

L

+

Current Limit

Comparator

CSG

HO_ENABLE

LM5117

RAMP

SW

R

RAMP

C

RAMP

Figure 21. RAMP Generator and Current Limit Circuit

The positive slope inductor current ramp is emulated by C_RAMPconnected between RAMP and AGND and R_RAMP

connected between SW and RAMP. R_RAMPshould not be connected to VIN directly because the RAMP pin

absolute maximum voltage rating could be exceeded under high input voltage conditions. C_RAMPis discharged by

an internal switch during the off-time and must be fully discharged during the minimum off-time. This limits the

ramp capacitor to be less than 2 nF. A good quality, thermally stable ceramic capacitor is recommended for

C_RAMP

.

The selection of R_RAMPand C_RAMPcan be simplified by adopting a K factor, which is defined as:

L_O

K =

R_RAMPx C_RAMPx R_Sx A_S

where

•

A_Sis the current sense amplifier gain which is normally 10

(4)

By choosing 1 as the K factor, the regulator removes any error after one switching cycle and the design

procedure is simplified. See Application and Implementation for detailed information.

7.3.5 Error Amplifier and PWM Comparator

The internal high-gain error amplifier generates an error signal proportional to the difference between the FB pin

voltage and the internal precision 0.8-V reference. The output of error amplifier is connected to the COMP pin

allowing the user to provide Type 2 loop compensation components, R_COMP, C_COMPand optional C_HF

.

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Feature Description (continued)

V

OUT

REF

LM5117

PWM

R

FB2

Comparator

+

-

+

-

+

FB

Error

Amplifier

R

COMP

C

COMP

RAMP Generator

Output

R

FB1

(optional)

C

HF

Type 2 Compensation

Components

Figure 22. Feedback Configuration and PWM Comparator

R_COMP, C_COMPand C_HFconfigure the error amplifier gain and phase characteristics to achieve a stable voltage

loop gain. This network creates a pole at DC (F_P1), a mid-band zero (F_Z) for phase boost, and a high frequency

pole (F_P2). The recommended range of R_COMPis 2 kΩ to 40 kΩ. See Application and Implementation for detailed

information.

F_P1= 0

[Hz]

(5)

1

F_Z=

[Hz]

2p x R_COMPx C_COMP

(6)

1

[Hz]

F_P2

=

C_COMPx C_HF

≈

x

’

2p x R_COMP

C_COMP+ C_HF

«

◊

(7)

The PWM comparator compares the emulated current sense signal from Ramp Generator to the voltage at the

COMP pin through a 1.2-V internal voltage drop and terminates the present cycle when the emulated current

sense signal is greater than V_COMP– 1.2 V.

7.3.6 Soft-Start

The soft-start feature allows the regulator to gradually reach the steady state operating point, thus reducing

startup stresses and surges. The LM5117 regulates the FB pin to the SS pin voltage or the internal 0.8-V

reference, whichever is lower. The internal 10-µA soft-start current source gradually increases the voltage on an

external soft-start capacitor connected to the SS pin. This results in a gradual rise of the output voltage. Soft-start

time (t_ss) can be calculated from the following equation:

C_SSx 0.8V

[sec]

t_SS

=

10 µA

(8)

The LM5117 can track the output of a master power supply during soft-start by connecting a voltage divider from

the output of master power supply to the SS pin. At the beginning of the soft-start sequence, V_SSshould be

allowed to go below 25 mV by the internal SS pull-down switch. During soft-start period, when SS pin voltage is

less than 0.8V, the LM5117 forces diode emulation for startup into a pre-biased load. If the tracking feature is

desired, connect the DEMB pin to GND or leave the pin floating.

7.3.7 Cycle-by-Cycle Current Limit

The LM5117 contains a current limit monitoring scheme to protect the regulator from possible over-current

conditions as shown in Figure 21. If the emulated ramp signal exceeds 1.2 V, the present cycle is terminated. For

the case where the switch current overshoots when the inductor is saturated or the output is shorted to ground,

the sample-and-hold circuit detects the excess recirculating current before the high-side NMOS driver is turned

on again. The high-side NMOS driver is disabled and will skip pulses until the current has decayed below the

current limit threshold. This approach prevents current runaway conditions since the inductor current is forced to

decay to a controlled level following any current overshoot.

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Feature Description (continued)

Maximum peak inductor current can be calculated as:

V_CS(TH)

V_OUT

[A]

I_{L(MAX)_PK}

=

+ I_PP-

R_S

f_SWx A_Sx R_Sx R_RAMPx C_RAMP

(9)

I_PP

2

I_{L(MAX)_AVE}= I_{L(MAX)_PK}

-

[A]

where

•

I_PPrepresents inductor peak to peak ripple current in Figure 23, and is defined as:

(10)

(11)

V_OUT

V_IN

V_OUT

L_Ox f_SW

≈

«

’

÷

◊

x 1 -

[A]

I_PP

=

∆

I_PP

I_OUT

1

f_SW

T=

0

Figure 23. Inductor Current

During an output short condition, the worst case peak inductor current is limited to:

V_CS(TH)V_IN(MAX)x t_ON(MIN)

+

[A]

I_{LIM_PK}

=

R_S

L_O

where

•

t_ON(MIN)is the minimum HO on-time

(12)

In most cases, especially if the output voltage is relatively high, it is recommended that a soft-saturating inductor

such as a powder core device is used. If a sharp-saturating inductor is used, the inductor saturation level must

be above I_{LIM_PK}. The temperatures of the NMOS devices, R_Sand inductor should be checked under this output

short condition.

7.3.8 Hiccup Mode Current Limiting

To further protect the regulator during prolonged current limit conditions, LM5117 provides a hiccup mode current

limit. An internal hiccup mode fault timer counts the PWM clock cycles during which cycle-by-cycle current

limiting occurs. When the hiccup mode fault timer detects 256 consecutive cycles of current limiting, an internal

restart timer forces the controller to enter a low power dissipation standby mode and starts sourcing 10 μA of

current into the RES pin capacitor C_RES. In this standby mode, HO and LO outputs are disabled and the soft-start

capacitor C_SSis discharged.

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Feature Description (continued)

C_RESis connected from RES pin to AGND and determines the time (t_RES) in which the LM5117 remains in the

standby before automatically restarting. When the RES pin voltage exceeds the 1.25-V RES threshold, RES

capacitor is discharged and a soft-start sequence begins. t_REScan be calculated from the following equation:

C_RESx 1.25V

[sec]

t_RES

=

10 mA

(13)

Current Limit

Detected

1.25V RES Threshold

I

= 10 µA

RES

0V

RES

SS

I

= 10 µA

SS

0.8V REF

HO

LO

Current Limit

t

SS

RES

persists during 256

consecutive cycles

Figure 24. Hiccup Mode Current Limit Timing Diagram

STANDBY

LM5117

RES

Current

HICCUP MODE

FAULT TIMER

256 CYCLES

HICCUP

RESTART

TIMER

RES

C

RES

Current Limit

Comparator

-

+

Figure 25. Hiccup Mode Current Limit Circuit

The RES pin can also be configured for latch-off mode current limiting or non-hiccup mode cycle-by-cycle current

limiting. If the RES pin is tied to VCC or a voltage greater than the RES threshold at initial power-on, the restart

timer is disabled and the regulator operates with non-hiccup mode cycle-by-cycle current limit. If the RES pin is

tied to GND, the regulator enters into the standby mode after 256 consecutive cycles of current limiting and then

never restarts until UVLO shutdown is cycled. The restart timer is configured during initial power-on when UVLO

is above the UVLO threshold and VCC is above the VCC UV threshold.

RES

C

RES

LM5117

VCC

(a) Hiccup Mode

Current Limit

(b) Latch-off Mode

Current Limit

(c) Cycle-by-cycle

Current Limit

Figure 26. RES Configurations

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Feature Description (continued)

7.3.9 HO and LO Drivers

The LM5117 contains high current NMOS drivers and an associated high-side level shifter to drive the external

high-side NMOS device. This high-side gate driver works in conjunction with an external diode D_HB, and

bootstrap capacitor C_HB. A 0.1-μF or larger ceramic capacitor, connected with short traces between the HB and

SW pin, is recommended. During the off-time of the high-side NMOS driver, the SW pin voltage is approximately

0V and the C_HBis charged from VCC through the D_HB. When operating with a high PWM duty cycle, the high-

side NMOS device is forced off each cycle for 320 ns to ensure that C_HBis recharged.

The LO and HO outputs are controlled with an adaptive dead-time methodology which insures that both outputs

are never enabled at the same time. When the controller commands HO to be enabled, the adaptive dead-time

logic first disables LO and waits for the LO voltage to drop. HO is then enabled after a small delay (LO Fall to HO

Rise Delay). Similarly, the LO turn-on is delayed until the HO voltage has discharged. LO is then enabled after a

small delay (HO Fall to LO Rise Delay). This technique insures adequate dead-time for any size NMOS device,

especially when VCC is supplied by a higher external voltage source. The adaptive dead-time circuitry monitors

the voltages of HO and LO outputs and insures the dead-time between the HO and LO outputs. Adding a gate

resister, R_GHor R_GL, may decrease the effective dead-time.

Care should be exercised in selecting an output NMOS device with the appropriate threshold voltage, especially

if VCC is supplied by an external bias supply voltage below the VCC regulation level. During startup at low input

voltages, the low-side NMOS device gate plateau voltage should be lower than the VCC under-voltage lockout

threshold. Otherwise, there may be insufficient VCC voltage to completely enhance the NMOS device as the

VCC under-voltage lockout is released during startup. If the high-side NMOS drive voltage is lower than the high-

side NMOS device gate plateau voltage during startup, the regulator may not start or it may hang up momentarily

in a high power dissipation state. This condition can be addressed by selecting an NMOS device with a lower

threshold voltage. This situation can be avoided if the minimum input voltage programmed by the UVLO resistor

is above the VCC regulation level.

7.3.10 Current Monitor

The LM5117 provides average output current information, enabling various applications requiring monitoring or

control of the output current.

Current Sense

Amplifier Output

LM5117

Current Monitor

Amplifier

R

CM

CONDITIONER

A

M

= 2

C

CM

40 kW

Figure 27. Current Monitor

The average of CM output can be calculated by:

= I +I ´R ´ A

V

[ ]

(

)

CM_ AVE

PEAK

VALLEY

S

(14)

The current monitor output is only valid in continuous conduction operation. The current monitor has a limited

bandwidth of approximately one tenth of f_SW. Adding an R-C filter, R_CMand C_CM, on the output of current monitor

with the cut off frequency below one tenth of f_SWis recommended to attenuate sampling noise.

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Feature Description (continued)

7.3.11 Maximum Duty Cycle

When operating with a high PWM duty cycle, the high-side NMOS device is forced off each cycle for 320ns to

ensure that C_HBis recharged and to allow time to sample and hold the current in the low-side NMOS FET. This

forced off-time limits the maximum duty cycle of the controller. When designing a regulator with high switching

frequency and high duty cycle requirements, a check should be made of the required maximum duty cycle

against the graph shown in Figure 28. The actual maximum duty cycle varies with the switching frequency as

follows:

Figure 28. Maximum Duty Cycle vs Switching Frequency

7.3.12 Thermal Protection

Internal thermal shutdown circuitry is provided to protect the controller in the event the maximum junction

temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low power shutdown

mode, disabling the output drivers and the VCC regulator. This feature is designed to prevent overheating and

destroying the device.

7.4 Device Functional Modes

7.4.1 Diode Emulation

A fully synchronous buck regulator implemented with a freewheeling NMOS rather than a diode has the

capability to sink current from the output in certain conditions such as light load, over-voltage or pre-bias startup.

The LM5117 provides a diode emulation feature that can be enabled to prevent reverse current flow in the low-

side NMOS device. When configured for diode emulation, the low-side NMOS driver is disabled when SW pin

voltage is greater than -5mV during the off-time of the high-side NMOS driver, preventing reverse current flow.

A benefit of the diode emulation is lower power loss at no load or light load conditions. The negative effect of

diode emulation is degraded light load transient response.

The diode emulation feature is configured with the DEMB pin. To enable diode emulation, connect the DEMB pin

to GND or leave the pin floating. If continuous conduction operation is desired, the DEMB pin should be tied to a

voltage greater than 3 V and may be connected to VCC. The LM5117 forces the regulator to operate in diode

emulation mode when SS pin voltage is less than the internal 0.8-V reference, allowing for startup into a pre-

biased load with the continuous conduction configuration.

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LM5117 is a step-down dc-dc controller. The device is typically used to convert a higher dc-dc voltage to a

lower dc voltage. Use the following design procedure to select component values. Alternately, use the

WEBENCH^®software to generate a complete design. The WEBENCH software uses an iterative design

procedure and assesses a comprehensive database of components when generating a design.

8.2 Typical Applications

Figure 29. 12 V, 9 A Typical Application Schematic

8.3 Detailed Design Procedure

8.3.1 Feedback Compensation

Open loop response of the regulator is defined as the product of modulator transfer function and feedback

transfer function. When plotted on a dB scale, the open loop gain is shown as the sum of modulator gain and

feedback gain.

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Detailed Design Procedure (continued)

The modulator transfer function includes a power stage transfer function with an embedded current loop and can

be simplified as one pole and one zero system as shown in Equation 15.

s

1 +

^

w

V_OUT

Z_ESR

= A_M

x

^

s

V_COMP

≈

’

◊

1+

w

«

P_LF

(15)

R_LOAD

R_Sx A_S

Where A_M(Modulator DC gain) =

,

1

,

w

_{Z_ESR}(ESR zero) =

R_ESRx C_OUT

1

w

_{P_LF}(Load pole) =

R_LOADx C_OUT

If the ESR of C_OUT(R_ESR) is very small, the modulator transfer function can be further simplified to a one pole

system and the voltage loop can be closed with only two loop compensation components, R_COMPand C_COMP

,

leaving a single pole response at the crossover frequency. A single pole response at the crossover frequency

yields a very stable loop with 90 degrees of phase margin.

The feedback transfer function includes the feedback resistor divider and loop compensation of the error

amplifier. R_COMP, C_COMPand optional C_HFconfigure the error amplifier gain and phase characteristics and create

a pole at origin, a low frequency zero and a high frequency pole. This is shown mathematically in Equation 16.

s

1 +

^

w

V_COMP

Z_EA

-

= A_FB

x

s

P_EA

^

V_OUT

s x (1+

)

w

(16)

1

,

Where A_FB(Feedback DC gain) =

w_{Z_EA}(Low frequency zero) =

R_FB2x (C_COMP+ C_HF

)

1

R_COMPx C_COMP

,

1

w_{P_EA}(High frequency pole) =

R_COMPx C_HF

The pole at the origin minimizes output steady state error. The low frequency zero should be placed to cancel the

load pole of the modulator. The high frequency pole can be used to cancel the zero created by the output

capacitor ESR or to decrease noise susceptibility of the error amplifier. By placing the low frequency zero an

order of magnitude less than the crossover frequency, the maximum amount of phase boost can be achieved at

the crossover frequency. The high frequency pole should be placed well beyond the crossover frequency since

the addition of C_HFadds a pole in the feedback transfer function.

The crossover frequency (loop bandwidth) is usually selected between one twentieth and one fifth of the f_SW. In a

simplified formula, the crossover frequency can be defined as:

R_COMP

[Hz]

f_CROSS

=

2 x ' x R_Sx R_FB2x A_Sx C_OUT

(17)

For higher crossover frequency, R_COMPcan be increased, while proportionally decreasing C_COMP. Conversely,

decreasing R_COMPwhile proportionally increasing C_COMP, results in lower bandwidth while keeping the same zero

frequency in the feedback transfer function.

The sampled gain inductor pole is inversely proportional to the K factor, which is defined as:

f_SW

w_{p_HF}

=

K - 0.5

(18)

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Detailed Design Procedure (continued)

The maximum achievable loop bandwidth, in fact, is limited by this sampled gain inductor pole. In traditional

current mode control, the maximum achievable loop bandwidth varies with input voltage. With the LM5117’s

unique slope compensation scheme, the sampled gain inductor pole is independent of changes to the input

voltage. This frees the user from additional concerns in wide varying input range applications and is an

advantage of the LM5117.

If the sampled gain inductor pole or the ESR zero is close to the crossover frequency, it is recommended that the

comprehensive formulas in Table 1 be used and the stability should be checked by a network analyzer. The

modulator transfer function can be measured and the feedback transfer function can be configured for the

desired open loop transfer function. If a network analyzer is not available, step load transient tests can be

performed to verify acceptable performance. The step load goal is minimum overshoot/undershoot with a

damped response.

8.3.2 Sub-Harmonic Oscillation

Peak current mode regulators can exhibit unstable behavior when operating above 50% duty cycle. This

behavior is known as sub-harmonic oscillation and is characterized by alternating wide and narrow pulses at the

SW pin. Sub-harmonic oscillation can be prevented by adding an additional voltage ramp (slope compensation)

on top of the sensed inductor current shown in Figure 20. By choosing K≥1, the regulator will not be subject to

sub-harmonic oscillation caused by a varying input voltage.

In time-domain analysis, the steady-state inductor current starts and ends at the same value during one clock

cycle. If the magnitude of the end-of-cycle current error, dI₁, caused by an initial perturbation, dI₀, is less than the

magnitude of dI₀or dI₁/dI₀> -1, the perturbation naturally disappears after a few cycles. When dI₁/dI₀< -1, the

initial perturbation does not disappear, resulting in sub-harmonic oscillation in steady-state operation.

Steady-State

Inductor

Current

dI

0

t

ON

dI

1

Inductor Current with

Initial Perturbation

Figure 30. Effect of Initial Perturbation when dl₁/dl₀< -1

dI₁/dI₀can be calculated by:

dl₁

dl₀

1

K

= 1 -

(19)

The relationship between dI₁/dI₀and K factor is illustrated graphically in Figure 31.

Figure 31. dl₁/dl₀vs K Factor

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Detailed Design Procedure (continued)

The minimum value of K is 0.5. When K<0.5, the amplitude of dI₁is greater than the amplitude of dI₀and any

initial perturbation results in sub-harmonic oscillation. If K=1, any initial perturbation will be removed in one

switching cycle. This is known as one-cycle damping. When -1<dl₁/dl₀<0, any initial perturbation will be under-

damped. Any perturbation will be over-damped when 0<dl₁/dl₀<1.

In the frequency-domain, Q, the quality factor of the sampling gain term in the modulator transfer function, is

used to predict the tendency for sub-harmonic oscillation, which is defined as:

1

Q =

p(K-0.5)

(20)

The relationship between Q and K factor is illustrated graphically in Figure 32.

Figure 32. Sampling gain Q vs K Factor

The minimum value of K is 0.5 again. This is the same as time domain analysis result. When K<0.5, the regulator

is unstable. High gain peaking at 0.5 results in sub-harmonic oscillation at F_SW/2. When K=1, one-cycle damping

is realized. Q is equal to 0.673 at this point. A higher K factor may introduce additional phase shift by moving the

sampled gain inductor pole closer to the crossover frequency, but will help reduce noise sensitivity in the current

loop. The maximum allowable value of K factor can be calculated by the Maximum Crossover Frequency

equation in Table 1.

8.3.3 Design Requirements

DESIGN PARAMETER

Output voltage

EXAMPLE VALUE

12 V

9 A

Full load current, I_OUT

Minimum input voltage, V_IN(MIN)

Maximum input voltage, V_IN(MAX)

Switching frequency, ƒ_SW

Diode emulation

15 V

55 V

230 kHz

yes

External VCC supply

yes

8.3.4 Timing Resistor R_T

Generally, higher frequency applications are smaller but have higher losses. Operation at 230 kHz was selected

for this example as a reasonable compromise between small size and high efficiency. The value of R_Tfor 230

kHz switching frequency can be calculated from Equation 3 as follows:

5.2 x 10⁹

230 x 10³

- 948 = 21.7 kW

R_T=

(21)

A standard value of 22.1 kΩ was chosen for R_T.

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8.3.5 Output Inductor L_O

The maximum inductor ripple current occurs at the maximum input voltage. Typically, 20% to 40% of the full load

current is a good compromise between core loss and copper loss of the inductor. Higher ripple current allows for

a smaller inductor size, but places more of a burden on the output capacitor to smooth the ripple voltage on the

output. For this example, a ripple current of 40% of 9 A was chosen. Knowing the switching frequency, maximum

ripple current, maximum input voltage and the nominal output voltage, the inductor value can be calculated as

follows:

æ

ö

÷

V

OUT

æ

ö

÷

ø

12V

55V

OUT

ç

L

=

´ 1-

=

´ 1-

= 11.3mH

ç

O

I

´ f

ç

è

V

÷

9A ´0.4´ 230kHz

è

PP(MAX)

SW

IN MAX

(

)

ø

(22)

The closest standard value of 10 μH was chosen for L_O. Using the value of 10 μH for L_O, calculate I_PPagain.

This step is necessary if the chosen value of L_Odiffers significantly from the calculated value.

From Equation 11,

12V

55V

≈

«

’

÷

◊

12V

x

1 -

I_PP(MAX)

=

= 4.1A

∆

10 mH x 230 kHz

(23)

At the minimum input voltage, this value is 1.04 A.

8.3.6 Diode Emulation Function

The DEMB pin is left floating since this example uses diode emulation to reduce the power loss under no load or

light load conditions.

8.3.7 Current Sense Resistor R_S

The performance of the converter will vary depending on the K value. For this example, K = 1 was chosen to

control sub-harmonic oscillation and achieve one-cycle damping. The maximum output current capability

(I_OUT(MAX)) should be 20~50% higher than the required output current, to account for tolerances and ripple

current. For this example, 130% of 9 A was chosen. The current sense resistor value can be calculated from

Equation 9 and Equation 10 as follows:

V_CS(TH)

[W]

R_S

=

V_OUTx K I_PP

_

I_OUT(MAX)

+

2

f_SWx L_O

(24)

(25)

0.12V

12 x 1

230 kHz x 10 µH

R_S

=

= 7.3 mW

1.04A

2

_

9A x 1.3 +

A value of 7.41 mΩ was realized for R_Sby placing an additional 0.1-Ω sense resistor in parallel with 8 mΩ. The

sense resistor must be rated to handle the power dissipation at maximum input voltage when current flows

through the low-side NMOS for the majority of the PWM cycle. The maximum power dissipation of R_Scan be

calculated as:

V_OUT

≈

«

’

÷

◊

I_OUT²x R_S

x

P_RS= 1 -

[W]

∆

V_IN(MAX)

(26)

12V

55V

2

≈

’

P_RS= 1 -

x 9A x 7.41 mW = 0.47W

«

◊

(27)

The worst case peak inductor current under the output short condition can be calculated from Equation 12 as

follows:

0.12V

7.41 mW

55V x 100 ns

+

= 16.7A

I_{LIM_PK}

=

10 mH

where

•

t_ON(MIN)is normally 100ns

(28)

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8.3.8 Current Sense Filter R_CSand C_CS

The LM5117 itself is not affected by the large leading edge spike because it samples valley current just prior to

the onset of the high-side switch. A current sense filter is used to minimize a noise injection from any external

noise sources. In general, a current sense filter is not necessary. In this example, a current sense filter is not

used

Adding R_CSresistor changes the current sense amplifier gain which is defined as A_S=10 k / (1 k+R_CS). A small

value of R_CSresistor below 100 Ω is recommended to minimize the gain change which is caused by the

temperature coefficient difference between internal and external resistors.

8.3.9 Ramp Resistor R_RAMPand Ramp Capacitor C_RAMP

The positive slope of the inductor current ramp signal is emulated by R_RAMPand C_RAMP. For this example, the

value of C_RAMPwas set at the standard capacitor value of 820 pF. With the inductor, sense resistor and the K

factor selected, the value of R_RAMPcan be calculated from Equation 4 as follows:

L_O

[W]

R_RAMP

=

K x C_RAMPx R_Sx A_S

(29)

10 mH

= 165 kW

R_RAMP

=

1 x 820 pF x 7.41 mW x 10

(30)

The standard value of 165 kΩ was selected for R_RAMP

.

8.3.10 UVLO Divider R_UV2, R_UV1and C_FT

The desired startup voltage and the hysteresis are set by the voltage divider R_UV1and R_UV2. Capacitor C_FT

provides filtering for the divider. For this design, the startup voltage was set to 14 V, 1 V below V_IN(MIN). V_HYSwas

set to 2 V. The value of R_UV1, R_UV2can be calculated from Equation 1 and Equation 2 as follows:

2V

20 µA

R_UV2

=

= 100 kW

(31)

1.25V x 100 kW

14V -1.25V

R_UV1

=

= 9.8 kW

(32)

The standard value of 100 kΩ was selected for R_UV2. R_UV1was selected to be 9.76 kΩ. A value of 47 pF was

chosen for C_FT.

8.3.11 VCC Disable and External VCC Supply

The 12-V output voltage allows the external VCC supply configuration as shown in Figure 16. In this example,

VCCDIS can be left floating since V_OUTis higher than VCC regulator set-point level.

8.3.12 Power Switches Q_Hand Q_L

Selection of the power NMOS devices is governed by the same trade-offs as switching frequency. Breaking

down the losses in the high-side and low-side NMOS devices is one way to compare the relative efficiencies of

different devices. Losses in the power NMOS devices can be broken down into conduction loss, gate charging

loss, and switching loss.

Conduction loss P_DCis approximately:

P_{DC (High-Side)}= D x (I_OUT²x R_DS(ON)x 1.3)

[W]

(33)

P_{DC (Low-Side)}= (1 œ D) x (I_OUT²x R_DS(ON)x 1.3)

[W]

where

•

D is the duty cycle

the factor of 1.3 accounts for the increase in the NMOS device on-resistance due to heating

(34)

Alternatively, the factor of 1.3 can be eliminated and the high temperature on-resistance of the NMOS device can

be estimated using the R_DS(ON)vs Temperature curves in the MOSFET datasheet.

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Gate charging loss (P_GC) results from the current driving the gate capacitance of the power NMOS devices and is

approximated as:

P_GC= n x V_VCCx Q_gx f_SW[W]

(35)

Qg refers to the total gate charge of an individual NMOS device, and ‘n’ is the number of NMOS devices. Gate

charge loss differs from conduction and switching losses in that the actual dissipation occurs in the controller IC.

Switching loss (P_SW) occurs during the brief transition period as the high-side NMOS device turns on and off.

During the transition period both current and voltage are present in the channel of the NMOS device. The

switching loss can be approximated as:

P_SW= 0.5 x V_INx I_OUTx (t_R+ t_F) x f_SW[W]

(36)

t_Rand t_Fare the rise and fall times of the high-side NMOS device. The rise and fall times are usually mentioned

in the MOSFET datasheet or can be empirically observed with an oscilloscope. Switching loss is calculated for

the high-side NMOS device only. Switching loss in the low-side NMOS device is negligible because the body

diode of the low-side NMOS device turns on before and after the low-side NMOS device switches. For this

example, the maximum drain-to-source voltage applied to either NMOS device is 55 V. The selected NMOS

devices must be able to withstand 55 V plus any ringing from drain to source and must be able to handle at least

the VCC voltage plus any ringing from gate to source.

8.3.13 Snubber Components R_SNBand C_SNB

A resistor-capacitor snubber network across the low-side NMOS device reduces ringing and spikes at the

switching node. Excessive ringing and spikes can cause erratic operation and can couple noise to the output

voltage. Selecting the values for the snubber is best accomplished through empirical methods. First, make sure

the lead lengths for the snubber connections are very short. Start with a resistor value between 5 and 50 Ω.

Increasing the value of the snubber capacitor results in more damping, but higher snubber losses. Select a

minimum value for the snubber capacitor that provides adequate damping of the spikes on the switch waveform

at heavy load. A snubber may not be necessary with an optimized layout.

8.3.14 Bootstrap Capacitor C_HBand Bootstrap Diode D_HB

The bootstrap capacitor between the HB and SW pin supplies the gate current to charge the high-side NMOS

device gate during each cycle’s turn-on and also supplies recovery charge for the bootstrap diode. These current

peaks can be several amperes. The recommended value of the bootstrap capacitor is at least 0.1 μF. C_HBshould

be a good quality, low ESR, ceramic capacitor located at the pins of the IC to minimize potentially damaging

voltage transients caused by trace inductance. The absolute minimum value for the bootstrap capacitor is

calculated as:

Q_g

C_HB

[F]

í

DV_HB

where

•

Qg is the high-side NMOS gate charge

ΔV_HBis the tolerable voltage droop on C_HB, which is typically less than 5% of VCC or 0.15 V conservatively

(37)

A value of 0.47 μF was selected for this design.

8.3.15 VCC Capacitor C_VCC

The primary purpose of the VCC capacitor (C_VCC) is to supply the peak transient currents of the LO driver and

bootstrap diode as well as provide stability for the VCC regulator. These peak currents can be several amperes.

The recommended value of C_VCCshould be no smaller than 0.47μF, and should be a good quality, low ESR,

ceramic capacitor. C_VCCshould be placed at the pins of the IC to minimize potentially damaging voltage

transients caused by trace inductance. A value of 1 μF was selected for this design.

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8.3.16 Output Capacitor C_O

The output capacitors smooth the output voltage ripple caused by inductor ripple current and provide a source of

charge during transient loading conditions. For this design example, a 470-μF electrolytic capacitor with

maximum 20mΩ ESR was selected as the main output capacitor. The fundamental component of the output

ripple voltage with maximum ESR is approximated as:

2

1

≈

R_ESR+

’

÷

◊

2

[V]

DV_OUT= I_PP

x

∆

8 x f_SWx C_OUT

«

(38)

2

1

≈

«

’

◊

DV_OUT= 4.1 x 0.02W²+

= 82 mV

∆

÷

8 x 230 kHz x 470 mF

(39)

Additional low ERS / ESL ceramic capacitors can be placed in parallel with the main output capacitor to further

reduce the output voltage ripple and spikes. In this example, two 22μF capacitors were added.

8.3.17 Input Capacitor C_IN

The regulator input supply voltage typically has high source impedance at the switching frequency. Good quality

input capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current

during the on-time. When the high-side NMOS device turns on, the current into the device steps to the valley of

the inductor current waveform, ramps up to the peak value, and then drops to the zero at turnoff. The input

capacitor should be selected for RMS current rating and minimum ripple voltage. A good approximation for the

required ripple current rating necessary is I_RMS> I_OUT/ 2.

In this example, seven 3.3μF ceramic capacitors were used. With ceramic capacitors, the input ripple voltage will

be triangular. The input ripple voltage can be approximated as:

I_OUT

[V]

DV_IN

=

4 x

x C_IN

f_SW

(40)

(41)

9 A

= 0.42 V

=

4 x 230 kHz x 3.3 mF x 7

Capacitors connected in parallel should be evaluated for RMS current rating. The current will split between the

input capacitors based on the relative impedance of the capacitors at the switching frequency.

8.3.18 VIN Filter R_VIN, C_VIN

An R-C filter (R_VIN, C_VIN) on VIN is optional. The filter helps to prevent faults caused by high frequency switching

noise injection into the VIN pin. A 0.47-μF ceramic capacitor is used for C_VINin the example. R_VINis selected to

be 3.9 Ω.

8.3.19 Soft-Start Capacitor C_SS

The capacitor at the SS pin (C_SS) determines the soft-start time (t_SS), which is the time for the output voltage to

reach the final regulated value. The t_SSfor a given C_SScan be calculated from Equation 8 as follows:

0.1 µF x 0.8V

= 8 ms

t_SS

=

10 µA

(42)

For this example, a value of 0.1 μF was chosen for a soft-start time of 8 ms.

8.3.20 Restart Capacitor C_RES

The capacitor at the RES pin (C_RES) determines t_RES, which is the time the LM5117 remains off before a restart

attempt is made in hiccup mode current limiting. t_RESfor a given C_REScan be calculated from Equation 13 as

follows:

0.47 µF x 1.25V

t_RES

=

= 59 ms

10 µA

(43)

29

For this example, a value of 0.47 μF was chosen for a restart time of 59 ms.

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8.3.21 Output Voltage Divider R_FB2and R_FB1

R_FB1and R_FB2set the output voltage level. The ratio of these resistors is calculated as:

R_FB2V_OUT

=

- 1

0.8V

R_FB1

(44)

The ratio between R_COMPand R_FB2determines the mid-band gain, A_{FB_MID}. A larger value for R_FB2may require a

corresponding larger value for R_COMP. R_FB2should be large enough to keep the total divider power dissipation

small. 4.99 kΩ was chosen for R_FB2in this example, which results in a R_FB1value of 357 Ω for 12-V output.

8.3.22 Loop Compensation Components C_COMP, R_COMPand C_HF

R_COMP, C_COMPand C_HFconfigure the error amplifier gain and phase characteristics to produce a stable voltage

loop. For a quick start, follow the 4 steps listed below.

STEP1: Select f_CROSS

By selecting one tenth of the switching frequency, f_CROSSis calculated as follows:

f_SW

10

f_CROSS

=

= 23 kHz

(45)

STEP2: Determine required R_COMP

Knowing f_CROSS, R_COMPis calculated as follows:

R_COMP= 2p x R_Sx A_Sx C_OUTx R_FB2x f_CROSS

[W]

(46)

(47)

R_COMP= 2p x 7.41 mW x 10 x 514 µF x 4.99 kW x 23 kHz = 27.5 kW

The standard value of 27.4kΩ was selected for R_COMP

STEP3: Determine C_COMPto cancel load pole

Knowing R_COMP, C_COMPis calculated as follows:

æ

ç

è

ö

12V

9A

´ 514mF

÷

R

´ C

OUT

ø

LOAD

C

=

= 25nF

COMP

R

27.4kW

COMP

(48)

The standard value of 22nF was selected for C_COMP

STEP4: Determine C_HFto cancel ESR zero

Knowing R_COMPand C_COMP, C_HFis calculated as follows:

R_ESRx C_OUTx C_COMP

R_COMPx C_COMP- R_ESRx C_OUT

C_HF

[F]

=

(49)

(50)

10mW x514µFx22nF

27.4kW x22nF-10mW x514µF

C_HF

= 189pF

=

Half of the maximum ESR is assumed as a typical ESR. The standard value of 180pF was selected for C_HF

.

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Table 1. LM5117 Frequency Analysis Formulas

SIMPLE FORMULA

COMPREHENSIVE FORMULA⁽¹⁾

MODULATOR

TRANSFER

FUNCTION

s

1 +

^

w_{Z_ESR}

V_OUT

A

M

^x(1 +

) (1 +

+

)

=

^x(1 +

)

A

M

=

s²

^

s

x

s

V_COMP

x

) (1 +

V_COMP

2

w_{P_LF}

w

w_{P_HF}

w

P_ESR

P_LF

w_n

Modulator DC

Gain

R_LOAD

1

R_LOAD

x

A_M

=

A_M

=

R_LOAD

w_{P_HF}

R_Sx A_S

1 +

x L_O

ESR Zero

ESR Pole

1

w_{Z_ESR}

=

w_{Z_ESR}

=

R_ESRx C_OUT

R

_ESR1x C_OUT1

Not considered

1

w_{P_ESR}

=

R_ESR1x (C_OUT1// C_OUT2

)

Dominant Load

Pole

1

+

w_{P_LF}

=

w_{P_LF}

=

(R_LOAD+ R_ESR1) x (C_OUT1+ C_OUT2

)

L_Ox (C_OUT1+ C_OUT2) x w_{P_HF}

R_LOADx C_OUT

Sampled Gain

Inductor Pole

Not considered

f_SW

K ꢀ 0.5

w_{P_HF =}

^orw_{P_HF}Q x w

=

n

Quality Factor

Not considered

1

Q =

p(K - 0.5)

Sub-harmonic

Double Pole

w_SW

f_SW

w_n=

= p x f_SWor f_n=

2

K Factor

L_O

K = 1

K =

R_RAMPx C_RAMPx R_Sx A_S

FEEDBACK

TRANSFER

FUNCTION

s

Z_EA

s

1 +

^

w

V_COMP

w

V_COMP

Z_EA

-

= A_FB

x

-

= A_FB

x

s

^

s

^

V_OUT

s x (1+

)

V_OUT

s x (1+

)

w

P_EA

w

P_EA

Feedback DC

Gain

1

A_FB

=

A_FB

=

R_FB2x (C_COMP+ C_HF

)

R_FB2x (C_COMP+ C_HF)

Mid-band Gain

R_COMP

R_FB2

R_COMP

R_FB2

A_{FB_MID}

=

A_{FB_MID}

=

Low

Frequency

Zero

1

=

w_{Z_EA}

R_COMPx C_COMP

High

Frequency

Pole

1

w_{P_EA}

=

w_{P_EA}

=

R_COMPx C_HF

R

_COMPx (C_HF// C_COMP

)

(1) Comprehensive Equation includes an inductor pole and a gain peaking at f_SW/2, which caused by sampling effect of the current mode

control. Also it assumes that a ceramic capacitor C_OUT2(No ESR) is connected in parallel with C_OUT1. R_ESR1represents ESR of C_OUT1

.

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Table 1. LM5117 Frequency Analysis Formulas (continued)

SIMPLE FORMULA

COMPREHENSIVE FORMULA⁽¹⁾

OPEN-LOOP

RESPONSE

s

Z_EA

s

Z_EA

1 +

w

w_{Z_ESR}

w

Z_ESR

^x(1 +

)

(1 +

)

T(s) = A_Mx A_FB

x

T(s) = A_Mx A_FB

^x(1 +

) (1 +

+

)

s

s x

s²

x

) (1 +

x

s x

(1 +

)

w

P_EA

P_LF

2

w

w_{P_LF}

w

w_{P_HF}

P_EA

P_ESR

w_n

s

A_Mx A_FB

s

1 +

T(s) =

w_{Z_ESR}

A_Mx A_FB

s

^x(1 +

) (1 +

+

)

T(s) =

s²

s

x

s

x

) (1 +

when

w_{Z_EA}= w_{P_LF}

w_{P_EA}= w_{Z_ESR}

&

2

w_{P_EA}

w

w_{P_HF}

P_ESR

w_n

^whenw_{Z_EA}= w_{P_LF}

Cross Over

Frequency

(Open Loop

Bandwidth)

R_COMP

2 x ' x R_Sx R_FB2x A_Sx C_OUT

R_COMP

2 x ' x R_Sx R_FB2x A_Sx (C_OUT1+ C_OUT2

f_CROSS

=

f_CROSS

=

)

when

w_{Z_EA}= w_{P_LF}

w_{P_EA}= w_{Z_ESR}

&

w_{P_EA}= w_{Z_ESR}

^whenw_{Z_EA}= w_{P_LF}

&

w_{P_HF}

w_{P_ESR}

f_CROSS<

f_CROSS

<

&

2 x p x 10

Maximum

Cross Over

Frequency

f_SW

5

f_SW

4 x Q

²-1

f_{CROSS_MAX}

=

x

(

1 + 4 x Q

)

f_{CROSS_MAX}

=

The frequency at which 45° phase shift occurs in modulator phase

characteristics.

8.4 Application Curves

Figure 34. Typical Efficiency vs Load Current

Figure 33. Start-Up with Resistive Load

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Application Curves (continued)

8.4.1 Constant Current Regulator

The LM5117 can be configured as a constant current regulator by using the current monitor feature (CM) as the

feedback input. A voltage divider at the VCCDIS pin from VOUT to AGND can be used to protect against output

over-voltage. When the VCCDIS pin voltage is greater than the VCCDIS threshold, the controller disables the

VCC regulator and the VCC pin voltage decays. When the VCC pin voltage is less than the VCC UV threshold,

both HO and LO outputs stop switching. Due to the time delay required for VCC to decay below the VCC UV

threshold, the over-voltage protection operates in hiccup mode. See Figure 35.

V

IN

100kW

15 kW

C

IN

UVLO VIN RES DEMB VCC

SW

C

VCC

D

HB

Hiccup Mode OVP

Triggered at 13.4V

LM5117

100 kW

HB

RAMP

V

OUT

C

HB

1500 pF

Q

H

V

68 µH

OUT

HO

SW

3.24 kW

CC Mode: 2A

80 µF

VCCDIS

Q

L

LO

332W

CS

47 mW

CSG

CM

0.022 µF

3.24 kW

2.37 kW

COMP

FB

RT

SS

AGND PGND

22.1 kW

0.47 µF

Current Control (CC)

Figure 35. Constant Current Regulator With Hiccup Mode Output OVP

8.4.2 Constant Voltage and Constant Current Regulator

The LM5117 also can be configured as a constant voltage and constant current regulator, known as CV+CC

regulator. In this configuration, there is much less variation in the current limiting as compared to peak cycle-by-

cycle current limiting of the inductor current. The LMV431 and the PNP transistor create a voltage-to-current

amplifier in the current loop. This amplifier circuitry does not affect the normal operation when the output current

is less than the current limit set-point. When the output current is greater than the set-point, the PNP transistor

sources a current into C_RAMPand increases the positive slope of emulated inductor current ramp until the output

current is less than or equal to the current limit set-point. See Figure 36 and Figure 37.

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Product Folder Links: LM5117 LM5117-Q1

LM5117, LM5117-Q1

SNVS698F –APRIL 2011–REVISED AUGUST 2015

www.ti.com

Application Curves (continued)

V

IN

Current Control (CC)

100 kW

C

IN

V

CC

UVLO VIN RES DEMB VCC

C

VCC

SW

10 kW

100W

15 kW

D

HB

100 kW

LM5117

PNP

HB

RAMP

C

HB

1 nF

Q

V

OUT

H

68 mH

1500 pF

HO

100 kW

200 kW

CV Mode : 5V

CC Mode: 2A

CM

SW

LMV431

Q

L

80 mF

LO

VCCDIS

CS

47 mW

V

OUT

CSG

0.1 mF

34.8 kW

3.24 kW

COMP

FB

RT

SS

AGND PGND

619W

22.1 kW

0.33 mF x2

Voltage Control (CV)

Figure 36. Constant Voltage Regulator with Accurate Current Limit

Figure 37. Current Limit Comparison

34

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Product Folder Links: LM5117 LM5117-Q1

LM5117, LM5117-Q1

www.ti.com

SNVS698F –APRIL 2011–REVISED AUGUST 2015

9 Power Supply Recommendations

The LM5117 is a power management device. The power supply for the device is any DC voltage source within

the specified input range.

10 Layout

10.1 Layout Guideline

Controller

Q_L

Place controller as

close to the switches

Inductor

Q_H

R_SENSE

C_OUT

C_IN

VIN GND GND

Figure 38. Layout Example

10.1.1 PC Board Layout Recommendation

VOUT

In a buck regulator the primary switching loop consists of the input capacitor, NMOS power switches and current

sense resistor. Minimizing the area of this loop reduces the stray inductance and minimizes noise and possible

erratic operation. High quality input capacitors should be placed as close as possible to the NMOS power

switches, with the V_INside of the capacitor connected directly to the high-side NMOS drain and the ground side

of the capacitor connected as close as possible to the current sense resistor ground connection.

Connect all of the low power ground connections (R_UV1, R_T, R_FB1, C_SS, C_RES, C_CM, C_VIN, C_RAMP) directly to the

regulator AGND pin. Connect C_VCCdirectly to the regulator PGND pin. Note that C_VINand C_VCCmust be as

physically close as possible to the IC. AGND and PGND must be directly connected together through a top-side

copper pattern connected to the exposed pad. Ensure no high current flows beneath the underside exposed pad.

The LM5117 has an exposed thermal pad to aid power dissipation. Adding several vias under the exposed pad

helps conduct heat away from the IC. The junction to ambient thermal resistance varies with application. The

most significant variables are the area of copper in the PC board, the number of vias under the exposed pad and

the amount of forced air cooling. The integrity of the solder connection from the IC exposed pad to the PC board

is critical. Excessive voids greatly decrease the thermal dissipation capacity.

The highest power dissipating components are the two power switches. Selecting NMOS switches with exposed

pads aids the power dissipation of these devices.

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Product Folder Links: LM5117 LM5117-Q1

LM5117, LM5117-Q1

SNVS698F –APRIL 2011–REVISED AUGUST 2015

www.ti.com

11 Device and Documentation Support

11.1 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 2. Related Links

TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

SAMPLE & BUY

LM5117

Click here

LM5117-Q1

11.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.3 Trademarks

E2E is a trademark of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

36

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Product Folder Links: LM5117 LM5117-Q1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jun-2015

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LM5117PMHE/NOPB HTSSOP PWP

LM5117PMHX/NOPB HTSSOP PWP

20

24

20

24

250

2500

1000

250

178.0

330.0

178.0

330.0

178.0

330.0

178.0

330.0

16.4

12.4

16.4

12.4

6.95

4.3

7.1

4.3

7.1

4.3

1.6

1.3

1.6

1.3

8.0

16.0

12.0

16.0

12.0

Q1

LM5117PSQ/NOPB

LM5117PSQE/NOPB

LM5117PSQX/NOPB

WQFN

RTW

4.3

4500

250

4.3

LM5117QPMHE/NOPB HTSSOP PWP

LM5117QPMHX/NOPB HTSSOP PWP

6.95

4.3

2500

1000

250

LM5117QPSQ/NOPB

LM5117QPSQE/NOPB

LM5117QPSQX/NOPB

WQFN

RTW

4.3

4500

4.3

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jun-2015

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LM5117PMHE/NOPB

LM5117PMHX/NOPB

LM5117PSQ/NOPB

HTSSOP

WQFN

PWP

RTW

PWP

RTW

20

24

20

24

250

2500

1000

250

213.0

367.0

210.0

367.0

213.0

367.0

210.0

367.0

191.0

367.0

185.0

367.0

191.0

367.0

185.0

367.0

55.0

38.0

35.0

55.0

38.0

35.0

LM5117PSQE/NOPB

LM5117PSQX/NOPB

LM5117QPMHE/NOPB

LM5117QPMHX/NOPB

LM5117QPSQ/NOPB

LM5117QPSQE/NOPB

LM5117QPSQX/NOPB

WQFN

4500

250

HTSSOP

WQFN

2500

1000

250

WQFN

4500

Pack Materials-Page 2

MECHANICAL DATA

PWP0020A

MXA20A (Rev C)

www.ti.com

MECHANICAL DATA

RTW0024A

SQA24A (Rev B)

www.ti.com

IMPORTANT NOTICE

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

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to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

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型号：	LM5117PSQX/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	Wide Input Range Synchronous Buck Controller with Analog Current Monitor
文件：	总43页 (文件大小：1797K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LM5117PSQX/NOPB [TI]

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