LM5109BSDX/NOPB [TI]
具有 8V UVLO 和高噪声抗扰度的 1A、100V 半桥栅极驱动器 | NGT | 8 | -40 to 125;
| 型号： | LM5109BSDX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 8V UVLO 和高噪声抗扰度的 1A、100V 半桥栅极驱动器 | NGT | 8 | -40 to 125 栅极驱动 驱动器 MOSFET驱动器 驱动程序和接口 |
| 文件： | 总16页 (文件大小：796K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM5109A
www.ti.com
SNVS412A –APRIL 2006–REVISED MARCH 2013
LM5109A High Voltage 1A Peak Half Bridge Gate Driver
Check for Samples: LM5109A
1
FEATURES
DESCRIPTION
The LM5109A is a cost effective, high voltage gate
driver designed to drive both the high-side and the
low-side N-Channel MOSFETs in a synchronous
buck or a half bridge configuration. The floating high-
side driver is capable of working with rail voltages up
to 90V. The outputs are independently controlled with
TTL compatible input thresholds. The robust level
shift technology operates at high speed while
consuming low power and providing clean level
transitions from the control input logic to the high-side
gate driver. Under-voltage lockout is provided on both
the low-side and the high-side power rails. The
device is available in the SOIC and the thermally
enhanced WSON packages.
2
•
Drives Both a High-Side and Low-Side N-
Channel MOSFET
•
1A peak Output Current (1.0A Sink / 1.0A
Source)
•
•
•
•
Independent TTL Compatible Inputs
Bootstrap Supply Voltage to 108V DC
Fast Propagation Times (30 ns Typical)
Drives 1000 pF Load with 15ns Rise and Fall
Times
•
Excellent Propagation Delay Matching (2 ns
Typical)
•
•
•
Supply Rail Under-Voltage Lockout
Low Power Consumption
Package
Pin Compatible with ISL6700
•
•
SOIC
WSON-8 (4 mm x 4 mm)
TYPICAL APPLICATIONS
•
•
•
•
Current Fed Push-Pull Converters
Half and Full Bridge Power Converters
Solid State Motor Drives
Two Switch Forward Power Converters
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
LM5109A
SNVS412A –APRIL 2006–REVISED MARCH 2013
www.ti.com
Simplified Block Diagram
V
DD
HV
HB
HO
HS
DRIVER
LEVEL
SHIFT
UVLO
HI
V
DD
UVLO
LO
DRIVER
LI
V
SS
Connection Diagrams
VDD
HI
VDD
HI
1
2
3
4
8
7
6
5
HB
HO
HS
LO
1
2
3
4
8
7
6
5
HB
HO
HS
LO
LI
LI
VSS
VSS
Figure 1. 8-Lead SOIC
See D Package
Figure 2. 8-Lead WSON
See NGT0008A Package
PIN DESCRIPTIONS
Pin #
WSON(1)
NAME
VDD
DESCRIPTION
APPLICATION INFORMATION
SOIC
Locally decouple to VSS using low ESR/ESL capacitor located as
close to IC as possible.
1
1
2
3
Positive gate drive supply
High side control input
Low side control input
The HI input is compatible with TTL input thresholds. Unused HI input
should be tied to ground and not left open
2
3
HI
LI
The LI input is compatible with TTL input thresholds. Unused LI input
should be tied to ground and not left open.
4
5
4
5
VSS
LO
Ground reference
All signals are referenced to this ground.
Low side gate driver output
Connect to the gate of the low-side N- MOS device.
Connect to the negative terminal of the bootstrap capacitor and to the
source of the high-side N-MOS device.
6
7
6
7
HS
HO
High side source connection
High side gate driver output
Connect to the gate of the high-side N-MOS device.
(1) For WSON package it is recommended that the exposed pad on the bottom of the package be soldered to ground plane on the PCB
and the ground plane should extend out from underneath the package to improve heat dissipation.
2
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LM5109A
LM5109A
www.ti.com
SNVS412A –APRIL 2006–REVISED MARCH 2013
PIN DESCRIPTIONS (continued)
Pin #
NAME
DESCRIPTION
APPLICATION INFORMATION
SOIC
WSON(1)
Connect the positive terminal of the bootstrap capacitor to HB and
the negative terminal of the bootstrap capacitor to HS. The bootstrap
capacitor should be placed as close to IC as possible.
High side gate driver positive
supply rail
8
8
HB
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
VDD to VSS
–0.3V to 18V
−0.3V to 18V
HB to HS
LI or HI to VSS
LO to VSS
−0.3V to VDD + 0.3V
−0.3V to VDD + 0.3V
HS − 0.3V to VHB + 0.3V
−5V to 90V
HO to VSS
V
(3)
HS to VSS
HB to VSS
108V
Junction Temperature
Storage Temperature Range
ESD Rating HBM(4)
–40°C to 150°C
−55°C to 150°C
1.5 kV
(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test
conditions, see the Electrical Characteristics .
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally
not exceed –1V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated
voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD – 15V. For example, if
VDD = 10V, the negative transients at HS must not exceed –5V.
(4) The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin.
Recommended Operating Conditions
VDD
HS(1)
8V to 14V
−1V to 90V
HB
VHS + 8V to VHS + 14V
< 50 V/ns
HS Slew Rate
Junction Temperature
−40°C to 125°C
(1) In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally
not exceed –1V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated
voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD – 15V. For example, if
VDD = 10V, the negative transients at HS must not exceed –5V.
Electrical Characteristics
Specifications in standard typeface are for TJ = 25°C, and those in boldface type apply over the full operating junction
temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO(1)
.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Supply Currents
IDD
VDD quiescent current
VDD operating current
LI = HI = 0V
f = 500 kHz
LI = HI = 0V
f = 500 kHz
0.3
1.8
0.6
2.9
0.2
2.8
mA
mA
mA
mA
IDDO
IHB
Total HB quiescent current
Total HB operating current
0.06
1.4
IHBO
(1) Minimum and maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through
correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
Copyright © 2006–2013, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: LM5109A
LM5109A
SNVS412A –APRIL 2006–REVISED MARCH 2013
www.ti.com
Electrical Characteristics (continued)
Specifications in standard typeface are for TJ = 25°C, and those in boldface type apply over the full operating junction
temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO(1)
.
SYMBOL
IHBS
PARAMETER
HB to VSS current, quiescent
HB to VSS current, operating
CONDITIONS
VHS = VHB = 90V
MIN
TYP
0.1
MAX
10
UNIT
µA
IHBSO
f = 500 kHz
0.5
mA
Input Pins LI and HI
VIL
VIH
RI
Low-level input voltage threshold
0.8
100
6.0
5.7
1.8
1.8
200
V
V
High-level input voltage threshold
Input pulldown resistance
2.2
500
kΩ
Under-Voltage Protection
VDDR
VDDH
VHBR
VHBH
VDD rising threshold
VDDR = VDD – VSS
6.7
0.5
6.6
0.4
7.4
7.1
V
V
V
V
VDD threshold hysteresis
HB rising threshold
VHBR = VHB – VHS
HB threshold hysteresis
LO Gate Driver
VOLL
VOHL
IOHL
IOLL
Low-level output voltage
ILO = 100 mA, VOHL = VLO – VSS
ILO = −100 mA, VOHL = VDD – VLO
VLO = 0V
0.38
0.72
1.0
0.65
1.20
V
V
A
A
High-level output voltage
Peak pullup current
Peak pulldown current
VLO = 12V
1.0
HO Gate Driver
VOLH
VOHH
IOHH
IOLH
Low-level output voltage
IHO = 100 mA, VOLH = VHO – VHS
IHO = −100 mA, VOHH = VHB – VHO
VHO = 0V
0.38
0.72
1.0
0.65
1.20
V
V
A
A
High-level output voltage
Peak pullup current
Peak pulldown current
VHO = 12V
1.0
Thermal Resistance
θJA
SOIC(2)(3)
WSON(2)(3)
160
40
Junction to ambient
°C/W
(2) 4-layer board with Cu finished thicknesses 1.5/1/1/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm
ground and power planes embedded in PCB. See Application Note AN-1187.
(3) The θJA is not a constant for the package and depends on the printed circuit board design and the operating conditions.
Switching Characteristics
Specifications in standard typeface are for TJ = 25°C, and those in boldface type apply over the full operating junction
temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO.
SYMBOL
LM5109A
tLPHL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Lower turn-off propagation delay
(LI falling to LO falling)
30
30
32
32
2
56
56
56
56
15
ns
ns
ns
ns
ns
tHPHL
tLPLH
tHPLH
tMON
tMOFF
Upper turn-off propagation delay
(HI falling to HO falling)
Lower turn-on propagation delay
(LI rising to LO rising)
Upper turn-on propagation delay
(HI rising to HO rising)
Delay matching: lower turn-on and upper
turn-off
Delay matching: lower turn-off and upper
turn-on
2
15
ns
ns
ns
tRC, tFC
tPW
Either output rise or fall time
CL = 1000 pF
15
50
-
Minimum input pulse width that changes
the output
4
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LM5109A
LM5109A
www.ti.com
SNVS412A –APRIL 2006–REVISED MARCH 2013
Typical Performance Characteristics
VDD Operating Current vs Frequency
HB Operating Current vs Frequency
100
10
1
100
V
= V = 12V
HB
V
= V = 12V
HB
DD
DD
C
L
= 1000 pF
V
= V = 0V
HS
SS
V
= V = 0V
HS
SS
C
= 1000 pF
L
10
C
= 2200 pF
L
C
L
= 2200 pF
C
= 4400 pF
L
C
L
= 4400 pF
1
C
L
= 0 pF
0.1
0.01
C
= 0 pF
L
C
L
= 470 pF
C
L
= 470 pF
0.1
1
10
100
1000
1
10
100
1000
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 3.
Figure 4.
Operating Current vs Temperature
Quiescent Current vs Temperature
0.45
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
I
DDO
I
DDO
C
= 0 pF
L
f = 500 kHz
LI = HI = 0V
V
= V = 12V
HB
DD
SS
V
V
= V = 12V
HB
DD
SS
V
= V = 0V
HS
= V = 0V
HS
I
HBO
50
I
HBO
50
20 35
65
80 95 110 125
-40 -25 -10
5
5
20 35
65
80 95 110 125
-40 -25 -10
TEMPERATURE (oC)
TEMPERATURE (°C)
Figure 5.
Figure 6.
Quiescent Current vs Voltage
Propagation Delay vs Temperature
600
500
44
40
36
32
28
24
20
C
= 0 pF
L
t
LI = HI = 0V
LPHL
t
HPHL
V
V
= V = 12V
HB
DD
SS
V
V
= V
HB
DD
= V
HS
= 0V
= V = 0V
SS HS
I
DD
400
300
200
turn off
t
HPLH
t
LPLH
I
HB
turn on
100
0
8
10
12
14
, V (V)
16
18
50
20 35
65
-40 -25 -10 5
80 95 110 125
TEMPERATURE (oC)
V
DD HB
Figure 7.
Figure 8.
Copyright © 2006–2013, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: LM5109A
LM5109A
SNVS412A –APRIL 2006–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics (continued)
LO and HO High Level Output Voltage
LO and HO Low Level Output Voltage
vs Temperature
vs Temperature
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.6
0.5
0.4
0.3
0.2
Output Current : -100 mA
Output Current : -100 mA
V
= V = 0V
HS
SS
V
= V = 0V
HS
SS
V
= V = 8V
HB
DD
V
= V = 8V
HB
DD
V
DD
= V = 12V
HB
V
= V = 12V
HB
DD
V
DD
= V = 16V
V
= V = 16V
HB
HB
DD
50
-40 -25 -10
5
20 35
65
80 95 110 125
50
20 35
65 80 95 110 125
-40 -25 -10
5
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9.
Figure 10.
Undervoltage Rising Thresholds vs Temperature
Undervoltage Hysteresis vs Temperature
0.50
7.0
V
V
= V - V
DD
DDR
SS
0.48
0.46
0.44
0.42
0.40
0.38
0.36
0.34
0.32
0.30
6.9
6.8
6.7
6.6
6.5
6.4
6.3
= V - V
HB
HBR
HS
V
DDH
V
DDR
V
HBR
V
HBH
50
-40 -25 -10
5
20 35
65
80 95 110 125
50
-40 -25 -10
5
20 35
65
80 95 110 125
TEMPERATURE (oC)
TEMPERATURE (oC)
Figure 11.
Figure 12.
Input Thresholds vs Temperature
Input Thresholds vs Supply Voltage
1.92
1.91
1.90
1.89
1.88
1.87
1.86
1.85
1.84
1.83
1.82
1.81
1.80
2.00
1.95
1.90
1.85
1.80
1.75
1.70
V
= 12V
= 0V
DD
Rising
V
SS
Rising
Falling
Falling
12
(V)
8
9
10
11
13
14 15 16
50
-40 -25 -10
5
20 35
65
80 95 110 125
V
DD
TEMPERATURE (oC)
Figure 13.
Figure 14.
6
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LM5109A
LM5109A
www.ti.com
SNVS412A –APRIL 2006–REVISED MARCH 2013
Timing Diagram
LI
LI
HI
HI
t
HPLH
t
LPLH
t
HPHL
t
LPHL
LO
LO
HO
HO
t
t
MOFF
MON
Figure 15.
Layout Considerations
Optimum performance of high and low-side gate drivers cannot be achieved without taking due considerations
during circuit board layout. The following points are emphasized:
1. Low ESR / ESL capacitors must be connected close to the IC between VDD and VSS pins and between HB
and HS pins to support high peak currents being drawn from VDD and HB during the turn-on of the external
MOSFETs.
2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor and a
good quality ceramic capacitor must be connected between the MOSFET drain and ground (VSS).
3. In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances between
the top MOSFET source and the of the bottom MOSFET drain (synchronous rectifier) must be minimized.
4. Grounding considerations:
–
The first priority in designing grounding connections is to confine the high peak currents that charge and
discharge the MOSFET gates to a minimal physical area. This will decrease the loop inductance and
minimize noise issues on the gate terminals of the MOSFETs. The gate driver should be placed as close
as possible to the MOSFETs.
–
The second consideration is the high current path that includes the bootstrap capacitor, the bootstrap
diode, the local ground referenced bypass capacitor, and the low-side MOSFET body diode. The
bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode from the ground
referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak
current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation.
HS Transient Voltages Below Ground
The HS node will always be clamped by the body diode of the lower external FET. In some situations, board
resistances and inductances can cause the HS node to transiently swing several volts below ground. The HS
node can swing below ground provided:
1. HS must always be at a lower potential than HO. Pulling HO more than –0.3V below HS can activate
parasitic transistors resulting in excessive current flow from the HB supply, possibly resulting in damage to
the IC. The same relationship is true with LO and VSS. If necessary, a Schottky diode can be placed
externally between HO and HS or LO and GND to protect the IC from this type of transient. The diode must
be placed as close to the IC pins as possible in order to be effective.
2. HB to HS operating voltage should be 15V or less. Hence, if the HS pin transient voltage is –5V, VDD should
be ideally limited to 10V to keep HB to HS below 15V.
3. Low ESR bypass capacitors from HB to HS and from VDD to VSS are essential for proper operation. The
Copyright © 2006–2013, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: LM5109A
LM5109A
SNVS412A –APRIL 2006–REVISED MARCH 2013
www.ti.com
capacitor should be located at the leads of the IC to minimize series inductance. The peak currents from LO
and HO can be quite large. Any series inductances with the bypass capacitor will cause voltage ringing at the
leads of the IC which must be avoided for reliable operation.
8
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LM5109A
LM5109A
www.ti.com
SNVS412A –APRIL 2006–REVISED MARCH 2013
REVISION HISTORY
Changes from Original (March 2013) to Revision A
Page
•
Changed layout of National Data Sheet to TI format ............................................................................................................ 7
Copyright © 2006–2013, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: LM5109A
PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
PACKAGING INFORMATION
Orderable Device
LM5109AMA/NOPB
LM5109AMAX/NOPB
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOIC
SOIC
D
8
8
95
Green (RoHS
& no Sb/Br)
SN | CU SN
Level-1-260C-UNLIM
L5109
AMA
ACTIVE
D
2500
Green (RoHS
& no Sb/Br)
SN | CU SN
Level-1-260C-UNLIM
-40 to 125
L5109
AMA
LM5109ASD
NRND
WSON
WSON
NGT
NGT
8
8
1000
1000
TBD
Call TI
SN
Call TI
-40 to 125
-40 to 125
5109ASD
5109ASD
LM5109ASD/NOPB
ACTIVE
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
LM5109ASDX/NOPB
ACTIVE
WSON
NGT
8
4500
Green (RoHS
& no Sb/Br)
SN
Level-1-260C-UNLIM
-40 to 125
5109ASD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5109AMAX/NOPB
LM5109ASD
SOIC
WSON
WSON
WSON
D
8
8
8
8
2500
1000
1000
4500
330.0
178.0
178.0
330.0
12.4
12.4
12.4
12.4
6.5
4.3
4.3
4.3
5.4
4.3
4.3
4.3
2.0
1.3
1.3
1.3
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
NGT
NGT
NGT
LM5109ASD/NOPB
LM5109ASDX/NOPB
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM5109AMAX/NOPB
LM5109ASD
SOIC
WSON
WSON
WSON
D
8
8
8
8
2500
1000
1000
4500
367.0
210.0
210.0
367.0
367.0
185.0
185.0
367.0
35.0
35.0
35.0
35.0
NGT
NGT
NGT
LM5109ASD/NOPB
LM5109ASDX/NOPB
Pack Materials-Page 2
MECHANICAL DATA
NGT0008A
SDC08A (Rev A)
www.ti.com
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Automotive and Transportation www.ti.com/automotive
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/industrial
www.ti.com/medical
Medical
Logic
Security
www.ti.com/security
Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense
Video and Imaging
www.ti.com/space-avionics-defense
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/omap
OMAP Applications Processors
Wireless Connectivity
TI E2E Community
e2e.ti.com
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明