LM5109MAX [NSC]
100V / 1A Peak Half Bridge Gate Driver; 100V / 1A峰值半桥栅极驱动器
| 型号： | LM5109MAX |
| 厂家： | 
National Semiconductor |
| 描述： | 100V / 1A Peak Half Bridge Gate Driver |
| 文件： | 总9页 (文件大小：656K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 2005
LM5109
100V / 1A Peak Half Bridge Gate Driver
n Bootstrap supply voltage to 118V DC
n Fast propagation times (27 ns typical)
General Description
The LM5109 is a low cost high voltage gate driver, designed
to drive both the high side and the low side N-Channel
MOSFETs in a synchronous buck or a half bridge configura-
tion. The floating high-side driver is capable of working with
rail voltages up to 100V. The outputs are independently
controlled with TTL compatible input thresholds. A robust
level shifter technology operates at high speed while con-
suming low power and providing clean level transitions from
the control input logic to the high side gate driver. Under-
voltage lockout is provided on both the low side and the high
side power rails. The device is available in the SOIC-8 and
the thermally enhanced LLP-8 packages.
n Drives 1000 pF load with 15ns rise and fall times
n Excellent propagation delay matching (2 ns typical)
n Supply rail under-voltage lockout
n Low power consumption
n Pin compatible with ISL6700
Typical Applications
n Current Fed push-pull converters
n Half and Full Bridge power converters
n Solid state motor drives
n Two switch forward power converters
Features
Package
n Drives both a high side and low side N-Channel
n SOIC-8
MOSFET
n LLP-8 (4 mm x 4 mm)
n
n
1A peak output current (1.0A sink / 1.0A source)
Independent TTL compatible inputs
Simplified Block Diagram
20150501
FIGURE 1.
© 2005 National Semiconductor Corporation
DS201505
www.national.com
Connection Diagrams
20150502
20150503
FIGURE 2.
Ordering Information
Ordering Number
Package Type
NSC Package Drawing
M08A
Supplied As
LM5109MA
SOIC-8
Shipped in anti static rails
2500 shipped as Tape & Reel
1000 shipped as Tape & Reel
4500 shipped as Tape & Reel
LM5109MAX
LM5109SD
SOIC-8
M08A
LLP-8
SDC08A
LM5109SDX
LLP-8
SDC08A
Pin Description
Pin #
Name
VDD
Description
Application Information
SO-8
LLP-8
1
1
Positive gate drive supply
High side control input
Low side control input
Locally decouple to VSS using low ESR/ESL capacitor located
as close to IC as possible.
2
3
2
3
HI
LI
The LM5109 HI input is compatible with TTL input thresholds.
Unused HI input should be tied to ground and not left open
The LM5109 LI input is compatible with TTL input thresholds.
Unused LI input should be tied to ground and not left open.
All signals are referenced to this ground.
4
5
6
4
5
6
VSS
LO
Ground reference
Low side gate driver output
High side source connection
Connect to the gate of the low side N-MOS device.
Connect to the negative terminal of the bootstrap capacitor
and to the source of the high side N-MOS device.
Connect to the gate of the low side N-MOS device.
HS
7
8
7
8
HO
HB
High side gate driver output
High side gate driver positive Connect the positive terminal of the bootstrap capacitor to HB
supply rail
and the negative terminal of the bootstrap capacitor to HS.
The bootstrap capacitor should be placed as close to IC as
possible.
Note: For LLP-8 package it is recommended that the exposed pad on the bottom of the LM5109 be soldered to ground plane on the PCB board and the
ground plane should extend out from underneath the package to improve heat dissipation.
www.national.com
2
Absolute Maximum Ratings (Note 1)
Storage Temperature Range
ESD Rating HBM (Note 2)
−55˚C to +150˚C
2 kV
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Recommended Operating
Conditions
VDD to VSS
-0.3V to 18V
−0.3V to 18V
HB to HS
VDD
8V to 14V
LI or HI to VSS
LO to VSS
−0.3V to VDD +0.3V
−0.3V to VDD +0.3V
VHS −0.3V to VHB +0.3V
−5V to 100V
HS (Note 6)
−1V to 100V
HB
VHS +8V to VHS +14V
HO to VSS
<
HS Slew Rate
Junction Temperature
50 V/ns
HS to VSS (Note 6)
HB to VSS
−40˚C to +125˚C
118V
Junction Temperature
-40˚C to +150˚C
Electrical Characteristics
Specifications in standard typeface are for TJ = +25˚C, and those in boldface type apply over the full operating junction tem-
perature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO .
Symbol
Parameter
Conditions
Min
Typ
Max
Units
SUPPLY CURRENTS
IDD
VDD Quiescent Current
LI = HI = 0V
0.3
2.1
0.6
3.4
0.2
3.0
10
mA
mA
mA
mA
µA
IDDO
IHB
VDD Operating Current
f = 500 kHz
Total HB Quiescent Current
Total HB Operating Current
HB to VSS Current, Quiescent
HB to VSS Current, Operating
LI = HI = 0V
f = 500 kHz
0.06
1.6
IHBO
IHBS
IHBSO
VHS = VHB = 100V
f = 500 kHz
0.1
0.5
mA
INPUT PINS LI and HI
VIL
VIH
RI
Low Level Input Voltage Threshold
0.8
100
6.0
5.7
1.8
1.8
180
V
V
High Level Input Voltage Threshold
Input Pulldown Resistance
2.2
500
kΩ
UNDER VOLTAGE PROTECTION
VDDR
VDDH
VHBR
VHBH
VDD Rising Threshold
VDD Threshold Hysteresis
HB Rising Threshold
VDDR = VDD - VSS
VHBR = VHB - VHS
6.9
0.5
6.6
0.4
7.4
7.1
V
V
V
V
HB Threshold Hysteresis
LO GATE DRIVER
VOLL Low-Level Output Voltage
ILO = 100 mA
VOHL = VLO – VSS
ILO = −100 mA,
VOHL = VDD– VLO
VLO = 0V
0.28
0.45
0.45
0.75
V
V
VOHL
High-Level Output Voltage
IOHL
IOLL
Peak Pullup Current
1.0
1.0
A
A
Peak Pulldown Current
VLO = 12V
HO GATE DRIVER
VOLH Low-Level Output Voltage
IHO = 100 mA
VOLH = VHO– VHS
IHO = −100 mA
VOHH = VHB– VHO
VHO = 0V
0.28
0.45
0.45
0.75
V
V
VOHH
High-Level Output Voltage
IOHH
IOLH
Peak Pullup Current
1.0
1.0
A
A
Peak Pulldown Current
VHO = 12V
THERMAL RESISTANCE
θJA Junction to Ambient
SOIC-8
160
40
˚C/W
LLP-8 (Note 3)
3
www.national.com
Switching Characteristics
Specifications in standard typeface are for TJ = +25˚C, and those in boldface type apply over the full operating junction tem-
perature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO.
Symbol
LM5109
tLPHL
Parameter
Conditions
Min
Typ
Max
Units
Lower Turn-Off Propagation Delay (LI
Falling to LO Falling)
27
27
29
29
2
56
56
56
56
15
ns
ns
ns
ns
ns
tHPHL
tLPLH
tHPLH
tMON
tMOFF
Upper Turn-Off Propagation Delay (HI
Falling to HO Falling)
Lower Turn-On Propagation Delay (LI
Rising to LO Rising)
Upper Turn-On Propagation Delay (HI
Rising to HO Rising)
Delay Matching: Lower Turn-On and
Upper Turn-Off
Delay Matching: Lower Turn-Off and
Upper Turn-On
2
15
ns
ns
ns
tRC, tFC
tPW
Either Output Rise/Fall Time
Minimum Input Pulse Width that
Changes the Output
CL = 1000 pF
15
50
-
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of
the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the
Electrical Characteristics tables.
Note 2: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. Pin 6 , Pin 7 and Pin 8 are rated at 500V.
Note 3: 4 layer board with Cu finished thickness 1.5/1/1/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm ground and power
planes embedded in PCB. See Application Note AN-1187.
Note 4: Min and Max limits are 100% production tested at 25˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical
Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
Note 5: The θ is not a constant for the package and depends on the printed circuit board design and the operating conditions.
JA
Note 6: In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally not exceed -1V.
However in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently.
If negative transients occur on HS, the HS voltage must never be more negative than V - 15V. For example, if V = 10V, the negative transients at HS must not
DD
DD
exceed -5V.
www.national.com
4
Typical performance Characteristics
VDD Operating Current vs Frequency
HB Operating Current vs Frequency
20150504
20150505
Operating Current vs Temperature
Quiescent Current vs Temperature
20150506
20150507
Quiescent Current vs Voltage
Propagation Delay vs Temperature
20150509
20150508
5
www.national.com
Typical performance Characteristics (Continued)
LO and HO High Level Output Voltage vs Temperature
LO and HO Low Level Output Voltage vs Temperature
20150510
20150511
Undervoltage Rising Thresholds vs Temperature
Undervoltage Hysteresis vs Temperature
20150514
20150515
Input Thresholds vs Temperature
Input Thresholds vs Supply Voltage
20150517
20150516
www.national.com
6
Timing Diagram
20150518
FIGURE 3.
peak current. Minimizing this loop length and area on the
circuit board is important to ensure reliable operation.
Layout Considerations
The optimum performance of high and low side gate drivers
cannot be achieved without taking due considerations during
circuit board layout. Following points are emphasized.
HS Transient Voltages Below
Ground
The HS node will always be clamped by the body diode of
the lower external FET. In some situations, board resis-
tances and inductances can cause the HS node to tran-
siently swing several volts below ground. The HS node can
swing below ground provided:
1. A low ESR / ESL capacitor must be connected close to
the IC, and between VDD and VSS pins and between HB
and HS pins to support high peak currents being drawn
from VDD during turn-on of the external MOSFET.
2. To prevent large voltage transients at the drain of the top
MOSFET, a low ESR electrolytic capacitor must be con-
nected between MOSFET drain and ground (VSS).
1. HS must always be at a lower potential than HO. Pulling
HO more than -0.3V below HS can activate parasitic
transistors resulting in excessive current to flow from the
HB supply possibly resulting in damage to the IC. The
same relationship is true with LO and VSS. If necessary,
a Schottky diode can be placed externally between HO
and HS or LO and GND to protect the IC from this type
of transient. The diode must be placed as close to the IC
pins as possible in order to be effective.
3. In order to avoid large negative transients on the switch
node (HS) pin, the parasitic inductances in the source of
top MOSFET and in the drain of the bottom MOSFET
(synchronous rectifier) must be minimized.
4. Grounding Considerations:
a) The first priority in designing grounding connections
is to confine the high peak currents from charging and
discharging the MOSFET gate in a minimal physical
area. This will decrease the loop inductance and mini-
mize noise issues on the gate terminal of the MOSFET.
The MOSFETs should be placed as close as possible to
the gate driver.
2. HB to HS operating voltage should be 15V or less .
Hence, if the HS pin transient voltage is -5V, VDD should
be ideally limited to 10V to keep HB to HS below 15V.
3. A low ESR bypass capacitor between HB to HS as well
as VDD to VSS is essential for proper operation. The
capacitor should be located at the leads of the IC to
minimize series inductance. The peak currents from LO
and HO can be quite large. Any series inductances with
the bypass capacitor will cause voltage ringing at the
leads of the IC which must be avoided for reliable
operation.
b) The second high current path includes the boot-
strap capacitor, the bootstrap diode, the local ground
referenced bypass capacitor and low side MOSFET
body diode. The bootstrap capacitor is recharged on the
cycle-by-cycle basis through the bootstrap diode from
the ground referenced VDD bypass capacitor. The re-
charging occurs in a short time interval and involves high
7
www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted
Controlling dimension is inch. Values in [ ] are millimeters.
Notes: Unless otherwise specified.
1. Standard lead finish to be 200 microinches/5.08 micrometers minimum lead/tin (solder) on copper.
2. Dimension does not include mold flash.
3. Reference JEDEC registration MS-012, Variation AA, dated May 1990.
SOIC-8 Outline Drawing
NS Package Number M08A
www.national.com
8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Notes: Unless otherwise specified.
1. For solder thickness and composition, see “Solder Information” in the packaging section of the National Semiconductor web
page (www.national.com).
2. Maximum allowable metal burr on lead tips at the package edges is 76 microns.
3. No JEDEC registration as of May 2003.
LLP-8 Outline Drawing
NS Package Number SDC08A
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
BANNED SUBSTANCE COMPLIANCE
National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products
Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain
no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
National Semiconductor
Americas Customer
Support Center
National Semiconductor
Europe Customer Support Center
Fax: +49 (0) 180-530 85 86
National Semiconductor
Asia Pacific Customer
Support Center
National Semiconductor
Japan Customer Support Center
Fax: 81-3-5639-7507
Email: new.feedback@nsc.com
Tel: 1-800-272-9959
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 69 9508 6208
English Tel: +44 (0) 870 24 0 2171
Français Tel: +33 (0) 1 41 91 8790
Email: ap.support@nsc.com
Email: jpn.feedback@nsc.com
Tel: 81-3-5639-7560
www.national.com
相关型号：
©2020 ICPDF网 联系我们和版权申明