LM3485MWC [TI]
IC,SMPS CONTROLLER,VOLTAGE-MODE,DIE;
| 型号： | LM3485MWC |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC,SMPS CONTROLLER,VOLTAGE-MODE,DIE |
| 文件： | 总16页 (文件大小：445K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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September 2003
LM3485
Hysteretic PFET Buck Controller
n 4.5V to 35V wide input range
n 1.242V to VIN adjustable output range
n High Efficiency 93%
General Description
The LM3485 is a high efficiency PFET switching regulator
controller that can be used to quickly and easily develop a
small, low cost, switching buck regulator for a wide range of
applications. The hysteretic control architecture provides for
simple design without any control loop stability concerns
using a wide variety of external components. The PFET
architecture also allows for low component count as well as
ultra-low dropout, 100% duty cycle operation. Another ben-
efit is high efficiency operation at light loads without an
increase in output ripple.
n
1.3% ( 2% over temp) internal reference
n 100% duty cycle
>
n Maximum operating frequency 1MHz
n Current limit protection
n MSOP-8
Applications
n Set-Top Box
n DSL/Cable Modem
n PC/IA
n Auto PC
n TFT Monitor
Current limit protection is provided by measuring the voltage
across the PFET’s RDS(ON), thus eliminating the need for a
sense resistor. The cycle-by-cycle current limit can be ad-
justed with a single resistor, ensuring safe operation over a
range of output currents.
n Battery Powered Portable Applications
n Distributed Power Systems
n Always On Power
Features
n Easy to use control methodology
n No control loop compensation required
Typical Application Circuit
20034608
© 2003 National Semiconductor Corporation
DS200346
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Connection Diagram
Top View
20034609
8 Lead Plastic MSOP-8
NS package Number MUA08A
Package Marking and Ordering Information
Order Number
Package Type
Package Marking
Supplied As:
LM3485MM
MSOP-8
S29B
1000 units on Tape and Reel
3500 units on Tape and Reel
LM3485MMX
MSOP-8
S29B
Pin Description
Pin Name
Pin Number
Description
ISENSE
1
The current sense input pin. This pin should be connected to Drain
node of the external PFET.
GND
NC
2
3
4
Signal ground.
No connection.
FB
The feedback input. Connect the FB to a resistor voltage divider
between the output and GND for an adjustable output voltage.
Current limit threshold adjustment. It connects to an internal 5.5µA
current source. A resistor is connected between this pin and the
input Power Supply. The voltage across this resistor is compared
with the VDS of the external PFET to determine if an over-current
condition has occurred.
ADJ
5
PWR GND
PGATE
6
7
Power ground.
Gate Drive output for the external PFET. PGATE swings between
VIN and VIN-5V.
VIN
8
Power supply input pin.
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2
Absolute Maximum Ratings (Note 1)
ESD Susceptibilty
Human Body Model (Note 3)
Lead Temperature
2kV
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Vapor Phase (60 sec.)
Infared (15 sec.)
215˚C
220˚C
VIN Voltage
−0.3V to 36V
−0.3V to 36V
−0.3V to 5V
−1.0V to 36V
−0.3V to 36V
150˚C
Storage Temperature
−65˚C to 150˚C
PGATE Voltage
FB Voltage
ISENSE Voltage
ADJ Voltage
Operating Ratings (Note 1)
Supply Voltage
Operating Junction
Temperature
4.5V to 35V
Maximum Junction Temp.
Power Dissipation
@
417mW TA
=
−40˚C to +125˚C
25˚C
Electrical Characteristics
Specifications in Standard type face are for TJ = 25˚C, and in bold type face apply over the full Operating Temperature
Range (TJ = −40˚C to +125˚C). Unless otherwise specified, VIN = 12V, VISNS = VIN − 1V, and VADJ = VIN − 1.1V. Datasheet
min/max specification limits are guaranteed by design, test, or statistical analysis.
Symbol
Parameter
Conditions
Min
(Note 4)
Typ
(Note 5)
250
Max
(Note 4)
400
Unit
IQ
Quiescent Current at
ground pin
FB = 1.5V
µA
(Not Switching)
VFB
Feedback Voltage
(Note 6)
1.226
1.242
1.258
1.267
15
V
1.217
VHYST
Comparator
10
14
mV
mV
Hysteresis
20
VCL(Note 7)
Current limit
RADJ = 20kΩ
RADJ = 160kΩ
VFB = 1.5V
110
comparator trip
voltage
880
0
VCL_OFFSET
ICL_ADJ
TCL
Current limit
−20
3.0
6
+20
7.0
14
mV
µA
µs
comparator offset
Current limit ADJ
current source
Current limit one shot
off time
VFB = 1.5V
5.5
9
VADJ = 11.5V
VISNS = 11.0V
VFB = 1.0V
Source
RPGATE
Driver resistance
5.5
8.5
Ω
ISOURCE = 100mA
Sink
ISink = 100mA
Source
IPGATE
Driver Output current
0.44
A
VIN = 7V,
PGATE = 3.5V
Sink
0.32
1.2
VIN = 7V,
PGATE = 3.5V
VIN = 4.5V
VFB = 1.0V
IGATE = 100µA sink
VFB = 1.0V
VPGATEMIN
Minimum driver
voltage
V
IFB
FB pin Bias Current
(Note 8)
300
100
750
nA
ns
TONMIN_NOR
Minimum on time in
normal operation
VISNS = VADJ+0.1V
Cload on OUT =
1000pF
(Note 9)
3
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Electrical Characteristics (Continued)
Specifications in Standard type face are for TJ = 25˚C, and in bold type face apply over the full Operating Temperature
Range (TJ = −40˚C to +125˚C). Unless otherwise specified, VIN = 12V, VISNS = VIN − 1V, and VADJ = VIN − 1.1V. Datasheet
min/max specification limits are guaranteed by design, test, or statistical analysis.
Symbol
Parameter
Conditions
Min
(Note 4)
Typ
(Note 5)
175
Max
(Note 4)
Unit
TONMIN_CL
Minimum on time in
current limit
VISNS = VADJ+0.1V
VFB = 1.0V Cload on
OUT = 1000pF
(Note 9)
ns
%VFB/∆VIN
Feedback Voltage
Line Regulation
4.5 ≤ VIN ≤ 35V
0.010
%/V
Note 1: Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is intended to
be functional, but device parameter specifications may not be guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: The maximum allowable power dissipation is a function of the maximum junction temperature, T
, the junction-to-ambient thermal resistance, θ
=
JA
J_MAX
240˚C/W, and the ambient temperature, T . The maximum allowable power dissipation at any ambient temperature is calculated using:
A
P
= (T
- T )/θ . Exceeding the maximum allowable power dissipation will cause excessive die temperature.
D_MAX
J_MAX A JA
Note 3: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin.
Note 4: All limits are guaranteed at room temperature (standard type face) and at temperature extremes (bold type face). All room temperature limits are 100%
tested. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate
Average Outgoing Quality Level (AOQL).
Note 5: Typical numbers are at 25˚C and represent the most likely norm.
Note 6: The V is the trip voltage at the FB pin when PGATE switches from high to low.
FB
*
Note 7: V = I
R
ADJ
CL
CL_ADJ
Note 8: Bias current flows out from the FB pin.
Note 9: A 1000pF capacitor is connected between V and PGATE.
IN
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4
Typical Performance Characteristics Unless otherwise specified, TJ = 25˚C
Quiescent Current vs Input Voltage
(FB = 1.5V)
Feedback Voltage vs Temperature
20034607
20034601
Hysteresis Voltage vs Input Voltage
Hysteresis Voltage vs Temperature
20034606
20034605
Current Limit ADJ Current vs Temperature
Current Limit One Shot OFF Time vs. Temperature
20034602
20034604
5
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Typical Performance Characteristics Unless otherwise specified, TJ = 25˚C (Continued)
PGATE Voltage vs Input Voltage
Minimum ON Time vs. Temperature
20034612
20034603
Operating ON Time vs
Output Load Current
(VIN = 4.5V)
Operating ON Time vs
Output Load Current
(VIN = 12V)
20034622
20034640
Efficiency vs Load Current
(VOUT = 3.3V, L = 6.8µH)
Efficiency vs Load Current
(VOUT = 3.3V, L = 22µH)
20034618
20034617
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Typical Performance Characteristics Unless otherwise specified, TJ = 25˚C (Continued)
Efficiency vs Load Current
(VOUT = 5.0V, L = 22µH)
Start Up
20034620
20034631
Continuous Mode Operation
Discontinuous Mode Operation
(VIN = 12V, VOUT = 3.3 V, IOUT = 500mA, L = 22µH)
(VIN = 12V, VOUT =3.3 V, IOUT = 50mA, L = 22µH)
20034616
20034615
Operating Frequency vs Input Voltage
Output Ripple Voltage vs Input Voltage
(VOUT = 3.3V, IOUT = 1A, COUT(ESR) = 80mΩ, Cff = 100pF)
(VOUT = 3.3V, IOUT = 1A, COUT(ESR) = 80mΩ, Cff = 100pF)
20034613
20034643
7
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Typical Performance Characteristics Unless otherwise specified, TJ = 25˚C (Continued)
Operating Frequency vs
Output Load Current
(L = 22µH, COUT(ESR) = 45mΩ, Cff = 100pF)
Feed-Forward Capacitor (Cff) Effect
(VOUT = 3.3V, L = 22µH, IOUT = 500mA)
20034621
20034630
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Block Diagram
20034610
diode turns on, and the current through the inductor ramps
down. Then, as the output voltage reaches the internal ref-
erence voltage again, the next cycle starts.
Functional Description
Overview
The LM3485 operates in discontinuous conduction mode at
light load current or continuous conduction mode at heavy
load current. In discontinuous conduction mode, current
through the inductor starts at zero and ramps up to the peak,
then ramps down to zero. Next cycle starts when the FB
voltage reaches the internal voltage. Until then, the inductor
current remains zero. Operating frequency is lower and
switching losses reduce. In continuous conduction mode,
current always flows through the inductor and never ramps
down to zero.
The LM3485 is buck (step-down) DC-DC controller that uses
a hysteretic control scheme. The comparator is designed
with approximately 10mV of hysteresis. In response to the
voltage at the FB pin, the gate drive (PGATE pin) turns the
external PFET on or off. When the inductor current is too
high, the current limit protection circuit engages and turns
the PFET off for approximately 9µs.
Hysteretic control does not require an internal oscillator.
Switching frequency depends on the external components
and operating conditions. Operating frequency reduces at
light loads resulting in excellent efficiency compared to other
architectures.
The output voltage (VOUT) can be programmed by 2 external
resistors. It can be calculated as follows:
*
VOUT = 1.242 ( R1 + R2 ) / R2
2 external resistors can easily program the output voltage.
The output can be set in a wide range from 1.242V (typical)
to VIN
.
Hysteretic Control Circuit
The LM3485 uses a comparator based voltage control loop.
The feedback is compared to a 1.242V reference and a
10mV hysteresis is designed into the comparator to ensure
noise free operation.
When the FB input to the comparator falls below the refer-
ence voltage, the output of the comparator moves to a low
state. This results in the driver output, PGATE, pulling the
gate of the PFET low and turning on the PFET. With the
PFET on, the input supply charges Cout and supplies cur-
rent to the load via the series path through the PFET and the
inductor. Current through the Inductor ramps up linearly and
the output voltage increases. As the FB voltage reaches the
upper threshold, which is the internal reference voltage plus
10mV, the output of the comparator changes from low to
high, and the PGATE responds by turning the PFET off. As
the PFET turns off, the inductor voltage reverses, the catch
20034623
FIGURE 1. Hysteretic Window
9
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Current Limit Operation
Functional Description (Continued)
The LM3485 has a cycle-by-cycle current limit. Current limit
is sensed across the VDS of the PFET or across an addi-
tional sense resistor. When current limit is activated, the
LM3485 turns off the external PFET for a period of 9µs(typi-
cal). The current limit is adjusted by an external resistor,
The minimum output voltage ripple (VOUT_PP) can be calcu-
lated in the same way.
VOUT_PP = VHYST ( R1 + R2 ) / R2
For example, with VOUT set to 3.3V, VOUT_PP is 26.6mV
RADJ
.
*
VOUT_PP = 0.01 ( 33K + 20K ) / 20K = 0.0266V
The current limit circuit is composed of the ISENSE com-
parator and the one-shot pulse generator. The positive input
of the ISENSE comparator is the ADJ pin. An internal 5.5µA
current sink creates a voltage across the external RADJ
resistor. This voltage is compared to the voltage across the
PFET or sense resistor. The ADJ voltage can be calculated
as follows:
Operating frequency (F) is determined by knowing the input
voltage, output voltage, inductor, VHYST, ESR (Equivalent
Series Resistance) of output capacitor, and the delay. It can
be approximately calculated using the formula:
*
VADJ = VIN − (RADJ 3.0µA)
Where 3.0µA is the minimum ICL-ADJ value.
The negative input of the ISENSE comparator is the ISENSE
pin that should be connected to the drain of the external
PFET. The inductor current is determined by sensing the
VDS. It can be calculated as follows.
where:
α: ( R1 + R2 ) / R2
delay: It includes the LM3485 propagation delay time
and the PFET delay time. The propagation delay is 90ns
typically. (See the Propagation Delay curve below.)
*
VISENSE = VIN − (RDSON IIND_PEAK) = VIN − VDS
20034625
FIGURE 3. Current Sensing by VDS
20034614
The current limit is activated when the voltage at the ADJ pin
exceeds the voltage at the ISENSE pin. The ISENSE com-
parator triggers the 9µs one shot pulse generator forcing the
driver to turn the PFET off. The driver turns the PFET back
on after 9µs. If the current has not reduced below the set
threshold, the cycle will repeat continuously.
FIGURE 2. Propagation Delay
The operating frequency and output ripple voltage can also
be significantly influenced by the speed up capacitor (Cff).
Cff is connected in parallel with the high side feedback
resistor, R1. The location of this capacitor is similar to where
a feed forward capacitor would be located in a PWM control
scheme. However it’s effect on hysteretic operation is much
different. The output ripple causes a current to be sourced or
sunk through this capacitor. This current is essentially a
square wave. Since the input to the feedback pin, FB, is a
high impedance node, the current flows through R2. The end
result is a reduction in output ripple and an increase in
operating frequency. When adding Cff, calculate the formula
above with α = 1. The value of Cff depend on the desired
operating frequency and the value of R2. A good starting
point is 470pF ceramic at 100kHz decreasing linearly with
increased operating frequency. Also note that as the output
voltage is programmed below 2.5V, the effect of Cff will
decrease significantly.
A filter capacitor, CADJ, should be placed as shown in Figure
3. CADJ filters unwanted noise so that the ISENSE compara-
tor will not be accidentally triggered. A value of 100pF to 1nF
is recommended in most applications. Higher values can be
used to create a soft-start function (See Start Up section).
The current limit comparator has approximately 100ns of
blanking time. This ensures that the PFET is fully on when
the current is sensed. However, under extreme conditions
such as cold temperature, some PFETs may not fully turn on
within the blanking time. In this case, the current limit thresh-
old must be increased. If the current limit function is used,
the on time must be greater than 100ns. Under low duty
cycle operation, the maximum operating frequency will be
limited by this minimum on time.
During current limit operation, the output voltage will drop
significantly as will operating frequency. As the load current
is reduced, the output will return to the programmed voltage.
However, there is a current limit fold back phenomenon
inherent in this current limit architecture. See Figure 4.
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parallel with RADJ results in soft-start. CADJ and RADJ create
an RC time constant forcing current limit to activate at a
lower current. The output voltage will ramp more slowly
when using the soft-start functionality. There are example
start-up plots for CADJ equal to 1nF and 10nF in the Typical
Performance Characteristics. Lower values for CADJ will
have little to no effect on soft-start.
Functional Description (Continued)
External Sense Resistor
The VDS of a PFET will tend to vary significantly over tem-
perature. This will result an equivalent variation in current
limit. To improve current limit accuracy an external sense
resistor can be connected from VIN to the source of the
PFET, as shown in Figure 5.
20034626
FIGURE 4. Current Limit Fold Back Phenomenon
>
At high input voltages ( 28V) increased undershoot at the
switch node can cause an increase in the current limit
threshold. To avoid this problem, a low Vf Schottky catch
diode must be used (See Catch Diode Selection). Addition-
ally, a resistor can be placed between the ISENSE pin and
the switch node. Any value up to approximately 600Ω is
recommended.
Start Up
The current limit circuit is active during start-up. During
start-up the PFET will stay on until either the current limit or
the feedback comparator is tripped
20034627
If the current limit comparator is tripped first then the fold
back characteristic should be taken into account. Start-up
into full load may require a higher current limit set point or the
load must be applied after start-up.
FIGURE 5. Current Sensing by External Resistor
One problem with selecting a higher current limit is inrush
current during start-up. Increasing the capacitance (CADJ) in
11
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Design Information
Hysteretic control is a simple control scheme. However the
operating frequency and other performance characteristics
highly depend on external conditions and components. If
either the inductance, output capacitance, ESR, VIN, or Cff is
changed, there will be a change in the operating frequency
and output ripple. The best approach is to determine what
operating frequency is desirable in the application and then
begin with the selection of the inductor and COUT ESR.
CON, Panasonic SP CAP, Nichicon "NA" series, are also
recommended and may be used without additional series
resistance.
For all practical purposes, any type of output capacitor may
be used with proper circuit verification.
Input Capacitor Selection (CIN
)
A bypass capacitor is required between the input source and
ground. It must be located near the source pin of the external
PFET. The input capacitor prevents large voltage transients
at the input and provides the instantaneous current when the
PFET turns on.
Inductor Selection (L1)
The important parameters for the inductor are the induc-
tance and the current rating. The LM3485 operates over a
wide frequency range and can use a wide range of induc-
tance values. A good rule of thumb is to use the equations
used for National’s Simple Switchers®. The equation for
inductor ripple (∆i) as a function of output current (IOUT) is:
The important parameters for the input capacitor are the
voltage rating and the RMS current rating. Follow the manu-
facturer’s recommended voltage derating. For high input
voltage application, low ESR electrolytic capacitor, the Nichi-
con "UD" series or the Panasonic "FK" series, is available.
The RMS current in the input capacitor can be calculated.
<
for Iout 2.0Amps
−0.366726
*
*
∆i ≤ Iout 0.386827 Iout
>
for Iout 2.0Amps
*
∆i ≤ Iout 0.3
The inductance can be calculated based upon the desired
operating frequency where:
The input capacitor power dissipation can be calculated as
follows.
2
*
PD(CIN) = IRMS_CIN
ESRCIN
The input capacitor must be able to handle the RMS current
and the PD. Several input capacitors may be connected in
parallel to handle large RMS currents. In some cases it may
be much cheaper to use multiple electrolytic capacitors than
a single low ESR, high performance capacitor such as OS-
CON or Tantalum. The capacitance value should be selected
such that the ripple voltage created by the charge and
discharge of the capacitance is less than 10% of the total
ripple across the capacitor.
And
where D is the duty cycle, VD is the diode forward voltage,
and VDS is the voltgae drop across the PFET.
The inductor should be rated to the following:
Programming the Current Limit (RADJ
)
*
Ipk = (Iout+∆i/2) 1.1
The current limit is determined by connecting a resistor
(RADJ) between input voltage and the ADJ pin.
*
RADJ = IIND_PEAK RDSON/ICL_ADJ
where:
The inductance value and the resulting ripple is one of the
key parameters controlling operating frequency. The second
is the ESR.
RDSON : Drain-Source ON resistance of the external PFET
ICL_ADJ : 3.0µA minimum
IIND_PEAK = ILOAD + IRIPPLE/2
Using the minimum value for ICL_ADJ (3.0µA) ensures that
the current limit threshold will be set higher than the peak
inductor current.
Output Capacitor Selection (COUT
)
The ESR of the output capacitor times the inductor ripple
current is equal to the output ripple of the regulator. How-
ever, the VHYST sets the first order value of this ripple. As
ESR is increased with a given inductance, then operating
frequency increases as well. If ESR is reduced then the
operating frequency reduces.
The RADJ value must be selected to ensure that the voltage
at the ADJ pin does not fall below 3.5V. With this in mind,
RADJ_MAX = (VIN-3.5)/7µA. If a larger RADJ value is needed
to set the desired current limit, either use a PFET with a
lower RDSON, or use a current sense resistor as shown in
Figure 5.
The use of ceramic capacitors has become a common de-
sire of many power supply designers. However, ceramic
capacitors have a very low ESR resulting in a 90˚ phase shift
of the output voltage ripple. This results in low operating
frequency and increased output ripple. To fix this problem a
low value resistor should be added in series with the ceramic
output capacitor. Although counter intuitive, this combination
of a ceramic capacitor and external series resistance provide
highly accurate control over the output voltage ripple. The
other types capacitor, such as Sanyo POS CAP and OS-
The current limit function can be disabled by connecting the
ADJ pin to ground and ISENSE to VIN.
Catch Diode Selection (D1)
The important parameters for the catch diode are the peak
current, the peak reverse voltage, and the average power
dissipation. The average current through the diode can be
calculated as following.
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higher than the 25˚C value. This increase in RDSON must be
considered it when determining RADJ in wide temperature
range applications. If the current limit is set based upon 25˚C
ratings, then false current limiting can occur at high tempera-
ture.
Design Information (Continued)
*
ID_AVE = IOUT (1 − D)
The off state voltage across the catch diode is approximately
equal to the input voltage. The peak reverse voltage rating
must be greater than input voltage. In nearly all cases a
Schottky diode is recommended. In low output voltage ap-
plications a low forward voltage provides improved effi-
ciency. For high temperature applications, diode leakage
current may become significant and require a higher reverse
voltage rating to achieve acceptable performance.
Keeping the gate capacitance below 2000pF is recom-
mended to keep switching losses and transition times low.
As gate capacitance increases, operating frequency should
be reduced and as gate capacitance decreases operating
frequency can be increased.
PCB Layout
P-Channel MOSFET Selection (Q1)
The PC board layout is very important in all switching regu-
lator designs. Poor layout can cause switching noise into the
feedback signal and general EMI problems. For minimal
inductance, the wires indicated by heavy lines should be as
wide and short as possible. Keep the ground pin of the input
capacitor as close as possible to the anode of the diode. This
path carries a large AC current. The switching node, the
node with the diode cathode, inductor, and FET drain, should
be kept short. This node is one of the main sources for
radiated EMI since it is an AC voltage at the switching
frequency. It is always good practice to use a ground plane in
the design, particularly at high currents.
The important parameters for the PFET are the maximum
Drain-Source voltage (VDS), the on resistance (RDSON), Cur-
rent rating, and the input capacitance.
The voltage across the PFET when it is turned off is equal to
the sum of the input voltage and the diode forward voltage.
The VDS must be selected to provide some margin beyond
the input voltage.
PFET drain current, Id, must be rated higher than the peak
inductor current, IIND-PEAK
.
PGATE swings the PFET’s gate from VIN to VIN − 5V when
the input voltage is greater than 7V. At less than 7V input, the
PGATE voltage swing is smaller. At 4.5V input the PGATE
swings from VIN to VIN − 3.3V. To insure that the PFET turns
on completely, a low threshold PFET should be used when
the input voltage is less than 7V.
The two ground pins, PWR GND and GND, should be con-
nected by as short a trace as possible; they can be con-
nected underneath the device. These pins are resistively
connected internally by approximately 50Ω. The ground pins
should be tied to the ground plane, or to a large ground trace
in close proximity to both the FB divider and COUT grounds.
However, PFET switching losses will increase as the VGS
threshold decreases. Therefore, whenever possible, a high
threshold PFET should be selected. Total power loss in the
FET can be approximated using the following equation:
2
The gate pin of the external PFET should be located close to
the PGATE pin. However, if a very small FET is used, a
resistor may be required between PGATE and the gate of
the FET to reduce high frequency ringing. Since this resistor
will slow the PFET’s rise time, the current limit blanking time
should be taken into consideration (see Current Limit Opera-
tion).
*
*
*
*
*
PDswitch = RDSON IOUT D + F IOUT VIN (ton + toff)/2
where:
ton = FET turn on time
toff = FET turn off time
A value of 10ns to 20ns is typical for ton and toff.
The feedback voltage signal line can be sensitive to noise.
Avoid inductive coupling to the inductor or the switching
node, by keeping the FB trace away from these areas.
The RDSON is used in determining the current limit resistor
value, RADJ. Note that the RDSON has a positive temperature
coefficient. At 100˚C, the RDSON may be as much as 150%
20034628
FIGURE 6. Typical PCB Layout Schematic (3.3V output)
13
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PCB Layout (Continued)
20034644
Bottom Layer
20034642
Top Layer
20034641
Silk Screen
C1: CIN 22µF/35V EEJL1VD226R (Panasonic)
C2: COUT 100µF/6.3V 6TPC100M (Sanyo)
C3: CADJ 1nF Ceramic Chip Capacitor
C4: CFF 100pF Ceramic Chip Capacitor
D1: 1A/40V MBRS140T3 (On Semiconductor)
L1: 22µH :QH66SN220M01L (Murata)
Q1: FDC5614P (Fairchild)
R1: 33KΩ Chip Resistor
R2: 20KΩ Chip Resistor
R3: RADJ 24KΩ Chip Resistor
FIGURE 7. Typical PCB Layout (3.3V Output)
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14
Physical Dimensions inches (millimeters)
unless otherwise noted
8 Lead Plastic MSOP-8
NS package Number MUA08A
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1. Life support devices or systems are devices or
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whose failure to perform when properly used in
accordance with instructions for use provided in the
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significant injury to the user.
2. A critical component is any component of a life
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can be reasonably expected to cause the failure of
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