LM3485Q1MM [NSC]
IC SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO8, PLASTIC, MSOP-8, Switching Regulator or Controller;
| 型号： | LM3485Q1MM |
| 厂家： | 
National Semiconductor |
| 描述： | IC SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO8, PLASTIC, MSOP-8, Switching Regulator or Controller 开关 光电二极管 |
| 文件： | 总16页 (文件大小：375K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 29, 2009
LM3485
Hysteretic PFET Buck Controller
General Description
Features
The LM3485 is a high efficiency PFET switching regulator
controller that can be used to quickly and easily develop a
small, low cost, switching buck regulator for a wide range of
applications. The hysteretic control architecture provides for
simple design without any control loop stability concerns us-
ing a wide variety of external components. The PFET archi-
tecture also allows for low component count as well as ultra-
low dropout, 100% duty cycle operation. Another benefit is
high efficiency operation at light loads without an increase in
output ripple.
Easy to use control methodology
■
No control loop compensation required
4.5V to 35V wide input range
1.242V to VIN adjustable output range
High Efficiency 93%
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■
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±1.3% (±2% over temp) internal reference
100% duty cycle
Maximum operating frequency > 1MHz
Current limit protection
Current limit protection is provided by measuring the voltage
across the PFET’s RDS(ON), thus eliminating the need for a
sense resistor. The cycle-by-cycle current limit can be adjust-
ed with a single resistor, ensuring safe operation over a range
of output currents.
MSOP-8
Applications
Set-Top Box
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DSL/Cable Modem
PC/IA
Auto PC
TFT Monitor
Battery Powered Portable Applications
Distributed Power Systems
Always On Power
Typical Application Circuit
20034608
Connection Diagram
Top View
20034609
8 Lead Plastic MSOP-8
NS package Number MUA08A
© 2009 National Semiconductor Corporation
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Package Marking and Ordering Information
Order Number
LM3485MM
Package Type
Package Marking
S29B
Supplied As
MSOP-8
1000 units on Tape and Reel
3500 units on Tape and Reel
LM3485MMX
S29B
Pin Descriptions
Pin Name
Pin Number
Description
ISENSE
1
The current sense input pin. This pin should be connected to Drain
node of the external PFET.
GND
NC
2
3
4
Signal ground.
No connection.
FB
The feedback input. Connect the FB to a resistor voltage divider
between the output and GND for an adjustable output voltage.
ADJ
5
Current limit threshold adjustment. It connects to an internal 5.5µA
current source. A resistor is connected between this pin and the input
Power Supply. The voltage across this resistor is compared with the
VDS of the external PFET to determine if an over-current condition has
occurred.
PWR GND
PGATE
6
7
Power ground.
Gate Drive output for the external PFET. PGATE swings between
VIN and VIN-5V.
VIN
8
Power supply input pin.
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2
ESD Susceptibilty
Human Body Model (Note 3)
Lead Temperature
Vapor Phase (60 sec.)
Infared (15 sec.)
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
2kV
215°C
220°C
VIN Voltage
PGATE Voltage
FB Voltage
ISENSE Voltage
ADJ Voltage
Maximum Junction Temp.
Power Dissipation
−0.3V to 36V
−0.3V to 36V
−0.3V to 5V
−1.0V to 36V
−0.3V to 36V
150°C
Storage Temperature
−65°C to 150°C
Operating Ratings (Note 1)
Supply Voltage
Operating Junction
Temperature
4.5V to 35V
−40°C to +125°C
417mW @ TA = 25°C
Electrical Characteristics
Specifications in Standard type face are for TJ = 25°C, and in bold type face apply over the full Operating Temperature
Range (TJ = −40°C to +125°C). Unless otherwise specified, VIN = 12V, VISNS = VIN − 1V, and VADJ = VIN − 1.1V. Datasheet min/
max specification limits are guaranteed by design, test, or statistical analysis.
Min
(Note 4)
Typ
(Note 5)
Max
(Note 4)
Symbol
Parameter
Conditions
FB = 1.5V
Unit
IQ
Quiescent Current at
ground pin
250
400
µA
(Not Switching)
VFB
Feedback Voltage
1.226
1.242
1.258
V
(Note 6)
1.217
1.267
VHYST
Comparator Hysteresis
10
14
15
20
mV
mV
VCL(Note 7)
Current limit comparator trip
voltage
110
880
0
RADJ = 20kΩ
RADJ = 160kΩ
VFB = 1.5V
VCL_OFFSET
ICL_ADJ
TCL
Current limit comparator
offset
−20
3.0
6
+20
7.0
14
mV
µA
µs
Current limit ADJ current
source
VFB = 1.5V
5.5
9
Current limit one shot off
time
VADJ = 11.5V
VISNS = 11.0V
VFB = 1.0V
RPGATE
Driver resistance
Source
ISOURCE = 100mA
5.5
8.5
Ω
Sink
ISink = 100mA
IPGATE
Driver Output current
Source
0.44
A
VIN = 7V,
PGATE = 3.5V
Sink
0.32
VIN = 7V,
PGATE = 3.5V
IFB
FB pin Bias Current
(Note 8)
VFB = 1.0V
300
100
750
nA
ns
TONMIN_NOR
Minimum on time in normal VISNS = VADJ+0.1V Cload on
operation
OUT = 1000pF
(Note 9)
TONMIN_CL
Minimum on time in current VISNS = VADJ+0.1V
175
ns
limit
VFB = 1.0V Cload on OUT =
1000pF
(Note 9)
Feedback Voltage Line
Regulation
0.010
%/V
%VFB/ΔVIN
4.5 ≤ VIN ≤ 35V
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Note 1: Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is intended
to be functional, but device parameter specifications may not be guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: The maximum allowable power dissipation is a function of the maximum junction temperature, TJ_MAX, the junction-to-ambient thermal resistance, θJA
240°C/W, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using:
=
PD_MAX = (TJ_MAX - TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature.
Note 3: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin.
Note 4: All limits are guaranteed at room temperature (standard type face) and at temperature extremes (bold type face). All room temperature limits are 100%
tested. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate
Average Outgoing Quality Level (AOQL).
Note 5: Typical numbers are at 25°C and represent the most likely norm.
Note 6: The VFB is the trip voltage at the FB pin when PGATE switches from high to low.
Note 7: VCL = ICL_ADJ * RADJ
Note 8: Bias current flows out from the FB pin.
Note 9: A 1000pF capacitor is connected between VIN and PGATE.
Typical Performance Characteristics Unless otherwise specified, TJ = 25°C
Quiescent Current vs Input Voltage
(FB = 1.5V)
Feedback Voltage vs Temperature
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Hysteresis Voltage vs Input Voltage
Hysteresis Voltage vs Temperature
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Current Limit ADJ Current vs Temperature
Current Limit One Shot OFF Time vs. Temperature
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PGATE Voltage vs Input Voltage
Typical VPGATE vs Time
VIN = 9V
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Minimum ON Time vs. Temperature
Operating ON Time vs
Output Load Current
(VIN = 4.5V)
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Operating ON Time vs
Output Load Current
(VIN = 12V)
Efficiency vs Load Current
(VOUT = 3.3V, L = 6.8µH)
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Efficiency vs Load Current
(VOUT = 3.3V, L = 22µH)
Efficiency vs Load Current
(VOUT = 5.0V, L = 22µH)
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Start Up
Continuous Mode Operation
(VIN = 12V, VOUT = 3.3 V, IOUT = 500mA, L = 22µH)
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Discontinuous Mode Operation
(VIN = 12V, VOUT =3.3 V, IOUT = 50mA, L = 22µH)
Operating Frequency vs Input Voltage
(VOUT = 3.3V, IOUT = 1A, COUT(ESR) = 80mΩ, Cff = 100pF)
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Output Ripple Voltage vs Input Voltage
(VOUT = 3.3V, IOUT = 1A, COUT(ESR) = 80mΩ, Cff = 100pF)
Operating Frequency vs
Output Load Current
(L = 22µH, COUT(ESR) = 45mΩ, Cff = 100pF)
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Feed-Forward Capacitor (Cff) Effect
(VOUT = 3.3V, L = 22µH, IOUT = 500mA)
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Block Diagram
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inductor voltage reverses, the catch diode turns on, and the
Functional Description
current through the inductor ramps down. Then, as the output
voltage reaches the internal reference voltage again, the next
cycle starts.
OVERVIEW
The LM3485 is buck (step-down) DC-DC controller that uses
a hysteretic control scheme. The comparator is designed with
approximately 10mV of hysteresis. In response to the voltage
at the FB pin, the gate drive (PGATE pin) turns the external
PFET on or off. When the inductor current is too high, the
current limit protection circuit engages and turns the PFET off
for approximately 9µs.
The LM3485 operates in discontinuous conduction mode at
light load current or continuous conduction mode at heavy
load current. In discontinuous conduction mode, current
through the inductor starts at zero and ramps up to the peak,
then ramps down to zero. Next cycle starts when the FB volt-
age reaches the internal voltage. Until then, the inductor
current remains zero. Operating frequency is lower and
switching losses reduce. In continuous conduction mode, cur-
rent always flows through the inductor and never ramps down
to zero.
Hysteretic control does not require an internal oscillator.
Switching frequency depends on the external components
and operating conditions. Operating frequency reduces at
light loads resulting in excellent efficiency compared to other
architectures.
The output voltage (VOUT) can be programmed by 2 external
resistors. It can be calculated as follows:
2 external resistors can easily program the output voltage.
The output can be set in a wide range from 1.242V (typical)
to VIN.
VOUT = 1.242* ( R1 + R2 ) / R2
HYSTERETIC CONTROL CIRCUIT
The LM3485 uses a comparator based voltage control loop.
The feedback is compared to a 1.242V reference and a 10mV
hysteresis is designed into the comparator to ensure noise
free operation.
When the FB input to the comparator falls below the reference
voltage, the output of the comparator moves to a low state.
This results in the driver output, PGATE, pulling the gate of
the PFET low and turning on the PFET. With the PFET on,
the input supply charges Cout and supplies current to the load
via the series path through the PFET and the inductor. Current
through the Inductor ramps up linearly and the output voltage
increases. As the FB voltage reaches the upper threshold,
which is the internal reference voltage plus 10mV, the output
of the comparator changes from low to high, and the PGATE
responds by turning the PFET off. As the PFET turns off, the
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The operating frequency and output ripple voltage can also
be significantly influenced by the speed up capacitor (Cff). Cff
is connected in parallel with the high side feedback resistor,
R1. The location of this capacitor is similar to where a feed
forward capacitor would be located in a PWM control scheme.
However it's effect on hysteretic operation is much different.
The output ripple causes a current to be sourced or sunk
through this capacitor. This current is essentially a square
wave. Since the input to the feedback pin, FB, is a high
impedance node, the current flows through R2. The end result
is a reduction in output ripple and an increase in operating
frequency. When adding Cff, calculate the formula above with
α = 1. The value of Cff depend on the desired operating fre-
quency and the value of R2. A good starting point is 470pF
ceramic at 100kHz decreasing linearly with increased oper-
ating frequency. Also note that as the output voltage is pro-
grammed below 2.5V, the effect of Cff will decrease
significantly.
CURRENT LIMIT OPERATION
The LM3485 has a cycle-by-cycle current limit. Current limit
is sensed across the VDS of the PFET or across an additional
sense resistor. When current limit is activated, the LM3485
turns off the external PFET for a period of 9µs(typical). The
20034623
FIGURE 1. Hysteretic Window
current limit is adjusted by an external resistor, RADJ
.
The minimum output voltage ripple (VOUT_PP) can be calcu-
lated in the same way.
The current limit circuit is composed of the ISENSE compara-
tor and the one-shot pulse generator. The positive input of the
ISENSE comparator is the ADJ pin. An internal 5.5µA current
sink creates a voltage across the external RADJ resistor. This
voltage is compared to the voltage across the PFET or sense
resistor. The ADJ voltage can be calculated as follows:
VOUT_PP = VHYST ( R1 + R2 ) / R2
For example, with VOUT set to 3.3V, VOUT_PP is 26.6mV
VOUT_PP = 0.01* ( 33K + 20K ) / 20K = 0.0266V
Operating frequency (F) is determined by knowing the input
voltage, output voltage, inductor, VHYST, ESR (Equivalent Se-
ries Resistance) of output capacitor, and the delay. It can be
approximately calculated using the formula:
VADJ = VIN − (RADJ * 3.0µA)
Where 3.0µA is the minimum ICL-ADJ value.
The negative input of the ISENSE comparator is the ISENSE
pin that should be connected to the drain of the external
PFET. The inductor current is determined by sensing the
VDS. It can be calculated as follows.
VISENSE = VIN − (RDSON * IIND_PEAK) = VIN − VDS
where:
ꢀα: ( R1 + R2 ) / R2
delay: It includes the LM3485 propagation delay time and
the PFET delay time. The propagation delay is 90ns typi-
cally. (See the Propagation Delay curve below.)
20034625
FIGURE 3. Current Sensing by VDS
The current limit is activated when the voltage at the ADJ pin
exceeds the voltage at the ISENSE pin. The ISENSE compara-
tor triggers the 9µs one shot pulse generator forcing the driver
to turn the PFET off. The driver turns the PFET back on after
9µs. If the current has not reduced below the set threshold,
the cycle will repeat continuously.
20034614
A filter capacitor, CADJ, should be placed as shown in Figure
3. CADJ filters unwanted noise so that the ISENSE comparator
FIGURE 2. Propagation Delay
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will not be accidentally triggered. A value of 100pF to 1nF is
recommended in most applications. Higher values can be
used to create a soft-start function (See Start Up section).
an RC time constant forcing current limit to activate at a lower
current. The output voltage will ramp more slowly when using
the soft-start functionality. There are example start-up plots
for CADJ equal to 1nF and 10nF in the Typical Performance
Characteristics. Lower values for CADJ will have little to no
effect on soft-start.
The current limit comparator has approximately 100ns of
blanking time. This ensures that the PFET is fully on when the
current is sensed. However, under extreme conditions such
as cold temperature, some PFETs may not fully turn on within
the blanking time. In this case, the current limit threshold must
be increased. If the current limit function is used, the on time
must be greater than 100ns. Under low duty cycle operation,
the maximum operating frequency will be limited by this min-
imum on time.
EXTERNAL SENSE RESISTOR
The VDS of a PFET will tend to vary significantly over temper-
ature. This will result an equivalent variation in current limit.
To improve current limit accuracy an external sense resistor
can be connected from VIN to the source of the PFET, as
shown in Figure 5.
During current limit operation, the output voltage will drop sig-
nificantly as will operating frequency. As the load current is
reduced, the output will return to the programmed voltage.
However, there is a current limit fold back phenomenon in-
herent in this current limit architecture. See Figure 4.
20034627
FIGURE 5. Current Sensing by External Resistor
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PGATE
FIGURE 4. Current Limit Fold Back Phenomenon
When switching, the PGATE pin swings from VIN (off) to
some voltage below VIN (on). How far the PGATE will swing
depends on several factors including the capacitance, on
time, and input voltage.
At high input voltages (>28V) increased undershoot at the
switch node can cause an increase in the current limit thresh-
old. To avoid this problem, a low Vf Schottky catch diode must
be used (See Catch Diode Selection). Additionally, a resistor
can be placed between the ISENSE pin and the switch node.
Any value up to approximately 600Ω is recommended.
As shown in the Typical Performance Characteristics,
PGATE voltage swing will increase with decreasing gate ca-
pacitance. Although PGATE voltage will typically be around
VIN-5V, with every small gate capacitances, this value can
increase to a typical maximum of VIN-8.3V.
START UP
The current limit circuit is active during start-up. During start-
up the PFET will stay on until either the current limit or the
feedback comparator is tripped
Additionally, PGATE swing voltage will increase as on time
increases. During long on times, such as when operating at
100% duty cycle, the PGATE voltage will eventually fall to its
maximum voltage of VIN-8.3V (typical) regardless of the
PFET gate capacitance.
If the current limit comparator is tripped first then the fold back
characteristic should be taken into account. Start-up into full
load may require a higher current limit set point or the load
must be applied after start-up.
The PGATE voltage will not fall below 0.4V (typical). There-
fore, when the input voltage falls below approximately 9V, the
PGATE swing voltage range will be reduced. At an input volt-
age of 7V, for instance, PGATE will swing from 7V to a
minimum of 0.4V.
One problem with selecting a higher current limit is inrush
current during start-up. Increasing the capacitance (CADJ) in
parallel with RADJ results in soft-start. CADJ and RADJ create
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CON, Panasonic SP CAP, Nichicon "NA" series, are also
recommended and may be used without additional series re-
sistance.
Design Information
Hysteretic control is a simple control scheme. However the
operating frequency and other performance characteristics
highly depend on external conditions and components. If ei-
ther the inductance, output capacitance, ESR, VIN, or Cff is
changed, there will be a change in the operating frequency
and output ripple. The best approach is to determine what
operating frequency is desirable in the application and then
begin with the selection of the inductor and COUT ESR.
For all practical purposes, any type of output capacitor may
be used with proper circuit verification.
INPUT CAPACITOR SELECTION (CIN)
A bypass capacitor is required between the input source and
ground. It must be located near the source pin of the external
PFET. The input capacitor prevents large voltage transients
at the input and provides the instantaneous current when the
PFET turns on.
INDUCTOR SELECTION (L1)
The important parameters for the inductor are the inductance
and the current rating. The LM3485 operates over a wide fre-
quency range and can use a wide range of inductance values.
A good rule of thumb is to use the equations used for
National's Simple Switchers®. The equation for inductor rip-
ple (Δi) as a function of output current (IOUT) is:
The important parameters for the input capacitor are the volt-
age rating and the RMS current rating. Follow the
manufacturer's recommended voltage derating. For high in-
put voltage application, low ESR electrolytic capacitor, the
Nichicon "UD" series or the Panasonic "FK" series, is avail-
able. The RMS current in the input capacitor can be calculat-
ed.
for Iout < 2.0Amps
−0.366726
ꢀΔi ≤ Iout * 0.386827 * Iout
for Iout > 2.0Amps
ꢀΔi ≤ Iout * 0.3
The inductance can be calculated based upon the desired
operating frequency where:
The input capacitor power dissipation can be calculated as
follows.
PD(CIN) = IRMS_CIN2 * ESRCIN
The input capacitor must be able to handle the RMS current
and the PD. Several input capacitors may be connected in
parallel to handle large RMS currents. In some cases it may
be much cheaper to use multiple electrolytic capacitors than
a single low ESR, high performance capacitor such as OS-
CON or Tantalum. The capacitance value should be selected
such that the ripple voltage created by the charge and dis-
charge of the capacitance is less than 10% of the total ripple
across the capacitor.
And
where D is the duty cycle, VD is the diode forward voltage, and
VDS is the voltgae drop across the PFET.
PROGRAMMING THE CURRENT LIMIT (RADJ
)
The inductor should be rated to the following:
The current limit is determined by connecting a resistor
(RADJ) between input voltage and the ADJ pin.
Ipk = (Iout+Δi/2)*1.1
RADJ = IIND_PEAK * RDSON/ICL_ADJ
where:
RDSON : Drain-Source ON resistance of the external PFET
ICL_ADJ : 3.0µA minimum
The inductance value and the resulting ripple is one of the key
parameters controlling operating frequency. The second is
the ESR.
IIND_PEAK = ILOAD + IRIPPLE/2
Using the minimum value for ICL_ADJ (3.0µA) ensures that the
current limit threshold will be set higher than the peak inductor
current.
OUTPUT CAPACITOR SELECTION (COUT
)
The ESR of the output capacitor times the inductor ripple cur-
rent is equal to the output ripple of the regulator. However, the
VHYST sets the first order value of this ripple. As ESR is in-
creased with a given inductance, then operating frequency
increases as well. If ESR is reduced then the operating fre-
quency reduces.
The RADJ value must be selected to ensure that the voltage
at the ADJ pin does not fall below 3.5V. With this in mind,
RADJ_MAX = (VIN-3.5)/7µA. If a larger RADJ value is needed to
set the desired current limit, either use a PFET with a lower
RDSON, or use a current sense resistor as shown in Figure 5.
The current limit function can be disabled by connecting the
ADJ pin to ground and ISENSE to VIN.
The use of ceramic capacitors has become a common desire
of many power supply designers. However, ceramic capaci-
tors have a very low ESR resulting in a 90° phase shift of the
output voltage ripple. This results in low operating frequency
and increased output ripple. To fix this problem a low value
resistor should be added in series with the ceramic output
capacitor. Although counter intuitive, this combination of a
ceramic capacitor and external series resistance provide
highly accurate control over the output voltage ripple. The
other types capacitor, such as Sanyo POS CAP and OS-
CATCH DIODE SELECTION (D1)
The important parameters for the catch diode are the peak
current, the peak reverse voltage, and the average power
dissipation. The average current through the diode can be
calculated as following.
ID_AVE = IOUT* (1 − D)
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The off state voltage across the catch diode is approximately
equal to the input voltage. The peak reverse voltage rating
must be greater than input voltage. In nearly all cases a
Schottky diode is recommended. In low output voltage appli-
cations a low forward voltage provides improved efficiency.
For high temperature applications, diode leakage current may
become significant and require a higher reverse voltage rating
to achieve acceptable performance.
higher than the 25°C value. This increase in RDSON must be
considered it when determining RADJ in wide temperature
range applications. If the current limit is set based upon 25°C
ratings, then false current limiting can occur at high temper-
ature.
Keeping the gate capacitance below 2000pF is recommend-
ed to keep switching losses and transition times low. This will
also help keep the PFET drive current low, which will improve
efficiency and lower the power dissipation within the con-
troller.
P-CHANNEL MOSFET SELECTION (Q1)
The important parameters for the PFET are the maximum
Drain-Source voltage (VDS), the on resistance (RDSON), Cur-
rent rating, and the input capacitance.
As gate capacitance increases, operating frequency should
be reduced and as gate capacitance decreases operating
frequency can be increased.
The voltage across the PFET when it is turned off is equal to
the sum of the input voltage and the diode forward voltage.
The VDS must be selected to provide some margin beyond the
input voltage.
PCB Layout
The PC board layout is very important in all switching regu-
lator designs. Poor layout can cause switching noise into the
feedback signal and general EMI problems. For minimal in-
ductance, the wires indicated by heavy lines should be as
wide and short as possible. Keep the ground pin of the input
capacitor as close as possible to the anode of the diode. This
path carries a large AC current. The switching node, the node
with the diode cathode, inductor, and FET drain, should be
kept short. This node is one of the main sources for radiated
EMI since it is an AC voltage at the switching frequency. It is
always good practice to use a ground plane in the design,
particularly at high currents.
PFET drain current, Id, must be rated higher than the peak
inductor current, IIND-PEAK
.
Depending on operating conditions, the PGATE voltage may
fall as low as VIN - 8.3V. Therefore, a PFET must be selected
with a VGS greater than the maximum PGATE swing voltage.
As input voltage desreases below 9V, PGATE swing voltage
may also decrease. At 5.0V input the PGATE will swing from
VIN to VIN - 4.6V. To ensure that the PFET turns on quickly
and completely, a low threshold PFET should be used when
the input voltage is less than 7V.
However, PFET switching losses will increase as the VGS
threshold decreases. Therefore, whenever possible, a high
threshold PFET should be selected. Total power loss in the
FET can be approximated using the following equation:
The two ground pins, PWR GND and GND, should be con-
nected by as short a trace as possible; they can be connected
underneath the device. These pins are resistively connected
internally by approximately 50Ω. The ground pins should be
tied to the ground plane, or to a large ground trace in close
proximity to both the FB divider and COUT grounds.
PDswitch = RDSON*IOUT2*D + F*IOUT*VIN*(ton + toff)/2
where:
The gate pin of the external PFET should be located close to
the PGATE pin. However, if a very small FET is used, a re-
sistor may be required between PGATE and the gate of the
FET to reduce high frequency ringing. Since this resistor will
slow the PFET's rise time, the current limit blanking time
should be taken into consideration (see Current Limit Opera-
tion).
ton = FET turn on time
toff = FET turn off time
A value of 10ns to 20ns is typical for ton and toff.
A PFET should be selected with a turn on rise time of less
than 100ns. Slower rise times will degrade efficiency, can
cause false current limiting, and in extreme cases may cause
abnormal spiking at the PGATE pin.
The feedback voltage signal line can be sensitive to noise.
Avoid inductive coupling to the inductor or the switching node,
by keeping the FB trace away from these areas.
The RDSON is used in determining the current limit resistor
value, RADJ. Note that the RDSON has a positive temperature
coefficient. At 100°C, the RDSON may be as much as 150%
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12
20034628
FIGURE 6. Typical PCB Layout Schematic (3.3V output)
20034642
20034644
Top Layer
Bottom Layer
13
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20034641
Silk Screen
C1: CIN 22µF/35V EEJL1VD226R (Panasonic)
C2: COUT 100µF/6.3V 6TPC100M (Sanyo)
C3: CADJ 1nF Ceramic Chip Capacitor
C4: CFF 100pF Ceramic Chip Capacitor
D1: 1A/40V MBRS140T3 (On Semiconductor)
L1: 22µH :QH66SN220M01L (Murata)
Q1: FDC5614P (Fairchild)
R1: 33KΩ Chip Resistor
R2: 20KΩ Chip Resistor
R3: RADJ 24KΩ Chip Resistor
FIGURE 7. Typical PCB Layout (3.3V Output)
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14
Physical Dimensions inches (millimeters) unless otherwise noted
8 Lead Plastic MSOP-8
NS package Number MUA08A
15
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