LF411MWGRLQMLV [TI]

航天级、单路、30V、3MHz、低失调电压运算放大器 | NAC | 10 | -55 to 125;


型号：	LF411MWGRLQMLV
厂家：	TEXAS INSTRUMENTS
描述：	航天级、单路、30V、3MHz、低失调电压运算放大器 \| NAC \| 10 \| -55 to 125 放大器 CD 运算放大器
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LF411QML

LF411QML Low Offset, Low Drift JFET Input Operational Amplifier

Literature Number: SNOSAO6B

June 30, 2011

LF411QML

Low Offset, Low Drift JFET Input Operational Amplifier

General Description

Features

This device is a low cost, high speed, JFET input operational

amplifier with very low input offset voltage and guaranteed

input offset voltage drift. It requires low supply current yet

maintains a large gain bandwidth product and fast slew rate.

In addition, well matched high voltage JFET input devices

provide very low input bias and offset currents. The

LF411QML is pin compatible with the standard LM741 allow-

ing designers to immediately upgrade the overall perfor-

mance of existing designs.

Available with radiation guarantee

■

ELDRS FREE

100 krad(Si)

0.5 mV(Typ)

—

Internally trimmed offset voltage:

Input offset voltage drift:

Low input bias current:

Low input noise current:

Wide gain bandwidth:

High slew rate:

Low supply current:

High input impedance:

Low total harmonic distortion:

■

10 μV/°C

50 pA

0.01 pA/√Hz

3 MHz

10V/μs

1.8 mA

10¹²Ω

This amplifier may be used in applications such as high speed

integrators, fast D/A converters, sample and hold circuits and

many other circuits requiring low input offset voltage and drift,

low input bias current, high input impedance, high slew rate

and wide bandwidth.

<0.0

A_V= 10, R_L= 10KΩ,

V_O= 20V_P-P, BW = 20Hz - 20KHz

Low 1/f noise corner:

50 Hz

■

Fast settling time to 0.01%:

2 μs

Ordering Information

NS Part Number

LF411MH/883

SMD Part Number

NS Package Number

H08C

Package Description

8LD T0–99 Can

LF411MWG/883

WG10A

10LD Ceramic SOIC

LF411MWG-MLS

50 krad(Si)

WG10A

(Note 9)

LF411MWGRLQMLV

100 krad(Si)

5962R1122201VZA

ELDRS Free

WG10A

10LD Ceramic SOIC

(Note 10)

Connection Diagrams

Metal Can Package

10LD Ceramic SOIC Package

20149244

Top View

See NS Package Number WG10A

20149205

Note: Pin 4 connected to case.

Top View

See NS Package Number H08A

BI-FET II™ is a trademark of National Semiconductor Corporation.

201492

www.national.com

Simplified Schematic

20149206

Detailed Schematic

20149234

www.national.com

Absolute Maximum Ratings (Note 1)

Supply Voltage

±18V

±30V

±15V

Differential Input Voltage

Input Voltage Range (Note 4)

Output Short Circuit Duration

Power Dissipation (Note 2), (Note 3)

H Package

Continuous

670mW

WG Package

T_Jmax

H Package

WG Package

150°C

Thermal Resistance

ꢀθ_JA

H Package Still Air

H Package 500LF/Min Air Flow

WG Package Still Air

WG Package 500LF/Min Air Flow

ꢀθ_JC

162°C/W

65°C/W

170°C/W

120°C/W

H Package

WG Package

20°C/W

26°C/W

Operating Temperature Range

−55°C ≤ T_A≤ 125°C

Storage Temperature Range

−65°C ≤ T_A≤ 150°C

Lead Temperature (Soldering, 10 seconds)

Package Weight (Typical)

H Package

WG Package

ESD Tolerance (Note 5)

260°C

TBD

220mg

750V

Quality Conformance Inspection

Mil-Std-883, Method 5005 - Group A

Subgroup

Description

Static tests at

Temp °C

+25

Static tests at

+125

-55

Static tests at

Dynamic tests at

Functional tests at

Switching tests at

Settling time at

+25

+125

-55

+25

+125

-55

+25

+125

-55

+25

+125

-55

www.national.com

LF411 883 Electrical Characteristics

DC Parameters

The following conditions apply, unless otherwise specified.

DC: V_CC= ±15V, V_CM= 0V, R_S= 0Ω

Sub-

groups

Symbol

V_IO

Parameter

Conditions

R_S= 10KΩ

Notes

Min Max

Unit

Input Offset Voltage

-2.0

-3.7

-3.3

-0.1

-25

2.0

3.7

3.3

0.1

I_IO

Input Offset Current

Input Bias Current

(Note 8)

±I_IB

-0.2

-50

0.2

(Note 8)

(Note 6)

V_CM

Input Common Mode Voltage

Range

±9.0

1, 2, 3

CMRR

Common Mode Rejection Ratio

1, 2, 3

R_S≤ 10KΩ, V_CM= ±9V

+PSRR

-PSRR

I_S

Supply Voltage Rejection Ratio +V_CC= 6V, -V_CC= -15V

Supply Voltage Rejection Ratio +V_CC= 15V, -V_CC= -6V

Supply Current

1, 2, 3

3.4

V/mV

1, 2, 3

-I_OS

Output Short Circuit Current

+V_I= -11V, -V_I= 11V,

R_S= 10KΩ

6.0

-50

-60

8.0

2, 3

+I_OS

Output Short Circuit Current

+V_I= 11V, -V_I= -11V,

R_S= 10KΩ

-13

-6.0

2, 3

+V_{IO Adj}

-V_{IO Adj}

+A_VS

Input Offset Voltage Adjustment

Large Signal Voltage Gain

-8.0

(Note 7)

V_O= 0 to 10V, R_L= 2KΩ

V_O= 0 to -10V, R_L= 2KΩ

V/mV

5, 6

-A_VS

Large Signal Voltage Gain

5, 6

4, 5, 6

V_O+

V_O-

Output Voltage Swing

R_L= 10KΩ, +V_I= 11V,

-V_I= -11V, R_S= 10KΩ

-12

4, 5, 6

R_L= 10KΩ, +V_I= -11V,

-V_I= 11V, R_S= 10KΩ

AC Parameters

The following conditions apply, unless otherwise specified.

AC: V_CC= ±15V, V_CM= 0V, R_S= 0Ω

Sub-

groups

Symbol

SR+

Parameter

Conditions

Notes

Min Max

Unit

Slew Rate

V_O= -5V to 5V

V_O= 5V to -5V

8.0

2.7

V/µS

MHz

SR-

GBW

Gain Bandwidth Product

www.national.com

Space Level Electrical Characteristics

DC Parameters

The following conditions apply, unless otherwise specified.

DC: V_CC= ±15V, V_CM= 0V, R_S= 0Ω

Sub-

groups

Symbol

V_IO

Parameter

Conditions

R_S= 10KΩ

Notes

Min Max

Unit

Input Offset Voltage

-2.0

-3.7

-3.3

-0.1

-25

2.0

3.7

3.3

0.1

I_IO

Input Offset Current

Input Bias Current

(Note 8)

±I_IB

-0.2

-50

0.2

(Note 8)

(Note 6)

V_CM

Input Common Mode Voltage

Range

±9.0

1, 2, 3

CMRR

Common Mode Rejection Ratio

1, 2, 3

R_S≤ 10KΩ, V_CM= ±9V

+PSRR

-PSRR

I_S

Supply Voltage Rejection Ratio +V_CC= 6V, -V_CC= -15V

Supply Voltage Rejection Ratio +V_CC= 15V, -V_CC= -6V

Supply Current

1, 2, 3

3.4

V/mV

1, 2, 3

-I_OS

Output Short Circuit Current

+V_I= -11V, -V_I= 11V,

R_S= 10KΩ

6.0

-50

-60

8.0

2, 3

+I_OS

Output Short Circuit Current

+V_I= 11V, -V_I= -11V,

R_S= 10KΩ

-13

-6.0

2, 3

+V_{IO Adj}

-V_{IO Adj}

+A_VS

Input Offset Voltage Adjustment

Large Signal Voltage Gain

-8.0

(Note 7)

V_O= 0 to 10V, R_L= 2KΩ

V_O= 0 to -10V, R_L= 2KΩ

V/mV

5, 6

-A_VS

Large Signal Voltage Gain

5, 6

4, 5, 6

V_O+

V_O-

Output Voltage Swing

R_L= 10KΩ, +V_I= 11V,

-V_I= -11V, R_S= 10KΩ

-12

4, 5, 6

R_L= 10KΩ, +V_I= -11V,

-V_I= 11V, R_S= 10KΩ

AC Parameters

The following conditions apply, unless otherwise specified.

AC: V_CC= ±15V, V_CM= 0V, R_S= 0Ω

Sub-

groups

Symbol

SR+

Parameter

Conditions

Notes

Min Max

Unit

Slew Rate

V_O= -5V to 5V

V_O= 5V to -5V

8.0

2.7

V/µS

MHz

SR-

GBW

Gain Bandwidth Product

www.national.com

Space Level Electrical Characteristics (Continued)

DC Parameters - Drift Values

The following conditions apply, unless otherwise specified.

DC: V_CC= ±15V, V_CM= 0V, R_S= 0Ω “Delta calculations performed on Space Level devices at Group B Subgroup 5 ONLY”

Sub-

groups

Symbol

V_IO

Parameter

Conditions

Notes

Min Max

Unit

Input Offset Voltage

Input Bias Current

−1

+I_IB

−I_IB

−0.1

0.1

LF411–MLS 50k Radiation Electrical Characteristics

DC Parameters - Post Radiation Limits (Note 9)

The following conditions apply, unless otherwise specified.

DC: V_CC= ±15V, V_CM= 0V, R_S= 0Ω Post Radiation Limits +25°C

Sub-

groups

Symbol

Parameter

Conditions

Notes

Min Max

Unit

I_IO

I_IB+

I_IB-

Input Offset Current

Input Bias Current

−0.25 0.25

−1.0

1.0

LF411MWGRLQMLV 100k Radiation Electrical Characteristics —

ELDRS Free Only SMD# 5962R1122201

DC Parameters - Post Radiation Limits (Note 10)

The following conditions apply, unless otherwise specified.

DC: V_CC= ±15V, V_CM= 0V, R_S= 0Ω Post Radiation Limits +25°C

Sub-

groups

Symbol

Parameter

Conditions

Notes

Min Max

−1.0 1.0

Unit

I_IO

I_IB+

I_IB-

Input Offset Current

Input Bias Current

−0.20 6.0

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed

specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test

conditions.

Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by T_Jmax(maximum junction temperature), θ_JA(package

junction to ambient thermal resistance), and T_A(ambient temperature). The maximum allowable power dissipation at any temperature is P_Dmax= (T_Jmax- T_A)/

_JAor the number given in the Absolute Maximum Ratings, whichever is lower.

Note 3: Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the part to operate

outside guaranteed limits.

Note 4: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.

Note 5: Human body model, 100pF discharged through 1.5KΩ.

Note 6: Parameters guaranteed by CMRR test.

Note 7: Datalog in K = V/mV.

Note 8: R_S= 10KΩ @ +125°C.

Note 9: Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post Radiation Limits Table.

These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate effect. Radiation end point limits for the noted parameters

are guaranteed only for the conditions as specified in MIL-STD-883, Method 1019

Note 10: Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post Radiation Limits Table.

These parts may be sensitive in a high dose rate environment. Low dose rate testing has been performed on a wafer-by-wafer basis, per Test Method 1019,

Condition D of MIL-STD-883, with no enhanced low dose rate sensitivity (ELDRS).

www.national.com

Typical Connection

20149201

Typical Performance Characteristics

Input Bias Current

20149211

20149212

Supply Current

Positive Common-Mode

Input Voltage Limit

20149213

20149214

www.national.com

Negative Common-Mode

Input Voltage Limit

Positive Current Limit

20149216

20149215

Negative Current Limit

Output Voltage Swing

20149217

20149218

Output Voltage Swing

Gain Bandwidth

20149219

20149220

www.national.com

Bode Plot

Slew Rate

20149222

20149221

Distortion vs Frequency

Undistorted Output

Voltage Swing

20149223

20149224

Open Loop Frequency

Response

Common-Mode Rejection

Ratio

20149225

20149226

www.national.com

Power Supply

Rejection Ratio

Equivalent Input Noise

Voltage

20149227

20149228

Open Loop Voltage Gain

Output Impedance

20149229

20149230

Inverter Settling Time

20149231

www.national.com

Pulse Response

R_L=2 kΩ, C_L10 pF

Small Signal Inverting

Small Signal Non-Inverting

20149240

20149239

Large Signal Inverting

Large Signal Non-Inverting

20149241

20149242

Current Limit (R_L=100Ω)

20149243

www.national.com

The LF411QML will drive a 2 kΩ load resistance to ±10V over

the full temperature range. If the amplifier is forced to drive

heavier load currents, however, an increase in input offset

voltage may occur on the negative voltage swing and finally

reach an active current limit on both positive and negative

swings.

Application Hints

The LF411QML series of internally trimmed JFET input op

amps ( BI-FET II™ ) provide very low input offset voltage and

guaranteed input offset voltage drift. These JFETs have large

reverse breakdown voltages from gate to source and drain

eliminating the need for clamps across the inputs. Therefore,

large differential input voltages can easily be accommodated

without a large increase in input current. The maximum dif-

ferential input voltage is independent of the supply voltages.

However, neither of the input voltages should be allowed to

exceed the negative supply as this will cause large currents

to flow which can result in a destroyed unit.

Precautions should be taken to ensure that the power supply

for the integrated circuit never becomes reversed in polarity

or that the unit is not inadvertently installed backwards in a

socket as an unlimited current surge through the resulting

forward diode within the IC could cause fusing of the internal

conductors and result in a destroyed unit.

As with most amplifiers, care should be taken with lead dress,

component placement and supply decoupling in order to en-

sure stability. For example, resistors from the output to an

input should be placed with the body close to the input to

minimize “pick-up” and maximize the frequency of the feed-

back pole by minimizing the capacitance from the input to

ground.

Exceeding the negative common-mode limit on either input

will force the output to a high state, potentially causing a re-

versal of phase to the output. Exceeding the negative com-

mon-mode limit on both inputs will force the amplifier output

to a high state. In neither case does a latch occur since raising

the input back within the common-mode range again puts the

input stage and thus the amplifier in a normal operating mode.

A feedback pole is created when the feedback around any

amplifier is resistive. The parallel resistance and capacitance

from the input of the device (usually the inverting input) to AC

ground set the frequency of the pole. In many instances the

frequency of this pole is much greater than the expected

3 dB frequency of the closed loop gain and consequently

there is negligible effect on stability margin. However, if the

feedback pole is less than approximately 6 times the expected

3 dB frequency, a lead capacitor should be placed from the

output to the input of the op amp. The value of the added

capacitor should be such that the RC time constant of this

capacitor and the resistance it parallels is greater than or

equal to the original feedback pole time constant.

Exceeding the positive common-mode limit on a single input

will not change the phase of the output; however, if both inputs

exceed the limit, the output of the amplifier may be forced to

a high state.

The amplifier will operate with a common-mode input voltage

equal to the positive supply; however, the gain bandwidth and

slew rate may be decreased in this condition. When the neg-

ative common-mode voltage swings to within 3V of the neg-

ative supply, an increase in input offset voltage may occur.

The LF411QML is biased by a zener reference which allows

normal circuit operation on ±4.5V power supplies. Supply

voltages less than these may result in lower gain bandwidth

and slew rate.

www.national.com

Typical Applications

High Speed Current Booster

20149209

PNP=2N2905

NPN=2N2219 unless noted

TO-5 heat sinks for Q6-Q7

www.national.com

10-Bit Linear DAC with No V_OSAdjust

20149232

where A_N=1 if the A_Ndigital input is high

A_N=0 if the A_Ndigital input is low

Single Supply Analog Switch with Buffered Output

20149233

www.national.com

Revision History

Date Released Revision

Section

Originator

Changes

10/11/05

New Release to corporate format

L. Lytle

1 MDS data sheet was converted into the

corporate data sheet format. MDS

MNLF411M-X Rev 2A2 will be archived.

05/07/07

Features, Ordering Information Table, L. McGee

LF411-MLS Electricals

Added reference to Radiation and Radiation

Electricals for LF411-MLS device. Revision A

will be archived.

06/30/11

Features, Ordering Information Table, L. McGee &

Added LF411MWGRLQMLV to Ordering Info

LF411-MLS 50k Post Radiation

Electricals, LF411MWGRLQMLV Post

Radiation Electricals

K.Kruckmeyer and modified Radiation Electricals to

“Radiation” devices. Added 50k and 100k Post

Radiation DC parameter tables. Revision B will

be archived.

www.national.com

Physical Dimensions inches (millimeters) unless otherwise noted

Metal Can Package (H)

NS Package Number H08C

10 Lead Ceramic SOIC (WG))

NS Package Number WG10A

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Notes

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Notes

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Space, Avionics and Defense www.ti.com/space-avionics-defense

Transportation and Automotive www.ti.com/automotive

Power Mgmt

Microcontrollers

RFID

power.ti.com

microcontroller.ti.com

www.ti-rfid.com

Video and Imaging

www.ti.com/video

OMAP Mobile Processors www.ti.com/omap

Wireless Connectivity www.ti.com/wirelessconnectivity

TI E2E Community Home Page

e2e.ti.com

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

LF411MWGRLQMLV [TI]

相关型号：

LF411P

LF411QML

LF411QML-SP

LF411XYZ

LF411_11

LF412

LF412

LF412 MD8

LF412-MIL

LF412-N

LF412883

LF412A