ISOW1044DFMR [TI]
ISOW1044 Isolated CAN FD Transceiver with Integrated Low-Emissions, Low-Noise, High-Efficiency DC-DC Converter;
| 型号： | ISOW1044DFMR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ISOW1044 Isolated CAN FD Transceiver with Integrated Low-Emissions, Low-Noise, High-Efficiency DC-DC Converter |
| 文件： | 总45页 (文件大小：3180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISOW1044
SLLSFF7A – MAY 2021 – REVISED DECEMBER 2021
ISOW1044 Isolated CAN FD Transceiver with Integrated Low-Emissions, Low-Noise,
High-Efficiency DC-DC Converter
– UL 1577 component recognition program
– IEC 62368-1, IEC 61010-1, IEC 60601-1 and
1 Features
•
Meets the requirements of ISO 11898-2:2016
physical layer standards
– Support of Classical CAN: 1 Mbps
– Optimized for CAN FD: 2 and 5 Mbps
Integrated DC-DC converter with low-emissions,
low-noise
– Meets CISPR 32 and EN 55032 Class B with
greater than 6 dB margin on a two-layer PCB
– Low frequency power converter at 25 MHz
enabling low noise performance
GB 4943.1-2011 certifications
2 Applications
•
•
•
•
•
Factory Automation
Building Automation
Industrial Transport
Solar Inverters, Protection Relay
Motor Drives
•
3 Description
The ISOW1044 device is a galvanically-isolated
controller area network (CAN) transceiver with a
built-in isolated DC-DC converter that eliminates the
need for a separate isolated power supply in space-
constrained isolated designs. The low-emissions,
isolated DC-DC meets CISPR 32 radiated emissions
Class B standard with just two ferrite beads on
a simple two-layer PCB. Additional 20 mA output
current can be used to power other circuits on the
board. An integrated 10 Mbps GPIO channel is
available and can help remove an additional digital
isolator or optocoupler for diagnotstics, LED indication
or supply monitoring.
•
•
Additional 10 Mbps GPIO channel
High efficiency output power
– Typical efficiency: 47%
– Isolated output voltage accuracy: ± 5%
– Additional output current: 20 mA
Independent power supply for CAN & DC-DC
– Logic supply (VIO): 1.71 V to 5.5 V
– Power converter supply ( VDD): 4.5 V to 5.5 V
Fault-Protected CAN FD Transceiver
– DC Bus fault protection voltage: ± 58V
– Receiver common mode input voltage: ±12 V
– Remote wakeup via BUS wake-up pattern
Typical loop delay: 167 ns
•
•
•
•
•
•
Device Information
Reinforced and Basic isolation options
High CMTI: 100-kV/µs (typical)
High ESD bus protection w.r.t GND2
FEATURE
ISOW1044
Reinforced
10 kVPK
ISOW1044B
Basic
Protection Level
Surge Test Voltage
Isolation Rating
Working Voltage
– HBM ESD: ±12 kV
7.8 kVPK
5000 VRMS
– IEC 61000-4-2 contact discharge: ±8 kV
Operating temperature range: -40°C to 125°C
Current limit and thermal shutdown
20-pin wide SOIC package
5000 VRMS
•
•
•
1000 VRMS/1500 1000 VRMS/1500 VPK
VPK
Package
DFM (20)
DFM (20)
•
Safety-Related Certifications planned:
Body Size (Nom)
12.83mm × 7.5 mm 12.83mm × 7.5 mm
– VDE Reinforced and Basic insulation per DIN
VDE V 0884-11:2017-01
VCC
Must be connected on PCB,
not connected internally
VIO
VISOIN
TXD
CANH
CAN
BUS
STB
Signal
RXD
CANL
OUT
Signal
Isolation
CAN
MCU
Isolation
IN
GNDIO
GISOIN
VDD
VISOOUT
GND2
DC-DC
Primary
DC-DC
Secondary
GND1
Galvanic Isolation
Barrier
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISOW1044
SLLSFF7A – MAY 2021 – REVISED DECEMBER 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description Continued....................................................2
6 Device Comparison Table ..............................................2
7 Pin Configuration and Functions...................................3
8 Specifications.................................................................. 5
8.1 Absolute Maximum Ratings........................................ 5
8.2 ESD Ratings............................................................... 5
8.3 Recommended Operating Conditions.........................5
8.4 ThermalInformation.....................................................6
8.5 Power Ratings.............................................................6
8.6 Insulation Specifications............................................. 7
8.7 Safety-Related Certifications...................................... 8
8.8 Safety Limiting Values.................................................8
8.9 Electrical Characteristics.............................................9
8.10 Supply Current Characteristics............................... 12
8.11 Switching Characteristics........................................13
8.12 Insulation Characteristics Curves........................... 14
8.13 Typical Characteristics............................................15
9 Parameter Measurement Information..........................18
10 Detailed Description....................................................22
10.1 Overview.................................................................22
10.2 Power Isolation....................................................... 22
10.3 Signal Isolation........................................................22
10.4 CAN Transceiver.....................................................22
10.5 Functional Block Diagram.......................................24
10.6 Feature Description.................................................24
10.7 Device Functional Modes........................................28
10.8 Device I/O Schematics............................................30
11 Application and Implementation................................ 31
11.1 Application Information............................................31
11.2 Typical Application.................................................. 31
12 Power Supply Recommendations..............................35
13 Layout...........................................................................36
13.1 Layout Guidelines................................................... 36
13.2 Layout Example...................................................... 36
14 Device and Documentation Support..........................37
14.1 Documentation Support.......................................... 37
14.2 Receiving Notification of Documentation Updates..37
14.3 Support Resources................................................. 37
14.4 Trademarks.............................................................37
14.5 Electrostatic Discharge Caution..............................37
14.6 Glossary..................................................................37
15 Mechanical, Packaging, and Orderable
Information.................................................................... 37
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (March 2021) to Revision A (December 2021)
Page
•
Updated device status to Production status....................................................................................................... 1
5 Description Continued
The device supports both classical CAN and CAN FD networks up to 5 Megabits per second (Mbps) data rate. It
offers ±58-V DC bus fault protection and ±12-V common-mode voltage range. Both signal and power paths are
5-kVRMS isolated per UL1577 and are qualified for reinforced and basic isolation per VDE, CSA, TUV and CQC.
The bus pins of these devices can endure up to 8 kV of IEC 61000-4-2 electrostatic discharge (ESD),.
The ISOW1044 device can operate from a single supply voltage of 4.5 V to 5.5 V by connecting VIO and VDD
together on PCB. If lower logic levels are required, these devices support 1.71 V to 5.5 V logic supply (VIO)
that can be independent from the power converter supply (VDD) of 4.5 V to 5.5 V. This device supports a wide
operating ambient temperature range from –40°C to +125°C and are available in 20-pin DFM (SOIC-20 footprint
compatible package) offering a minimum of 8-mm creepage and clearance.
The ISOW1044 supports a standby mode and wake over CAN compliant to the ISO 11898-2:2016 defined wake-
up pattern (WUP). The device also includes protection and diagnostic features supporting thermal-shutdown
(TSD), TXD dominant time-out (DTO) and supply undervoltage detection.
6 Device Comparison Table
PART NUMBER
ISOW1044
ISOLATION
Reinforced
Basic
PACKAGE
BODY SIZE (NOM)
12.83 mm x 7.5 mm
12.83 mm x 7.5 mm
20-DFM (SOIC)
20-DFM (SOIC)
ISOW1044B
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7 Pin Configuration and Functions
VIO
VISOIN
1
2
3
20
19
18
IN
CANH
CANL
TXD
STB
RXD
GISOIN
GISOIN
GISOIN
4
5
6
17
16
15
GNDIO
NC
OUT
7
14
EN/FLT
VDD
VSIN
VISOOUT
GND2
8
13
12
11
9
GND1
10
Figure 7-1. ISOW1044 20-pin DFM Top View
Table 7-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
VIO
NO.
1
--
I
Side 1 Logic supply
IN
2
General purpose logic (GPIO) input (internal pull-down)
Driver enable. If this pin is floating, the driver is disabled (internal pull-down)
TXD
3
I
Standby enable. Connect this pin to GNDIO in normal mode. If this pin is floating or logic high,
driver is in standby mode.
STB
4
5
6
7
I
RXD
GNDIO
NC
O
--
--
Receiver data output
Ground connection on side 1 for VIO. GNDIO and GND1 are not internally connected and need
be shorted on PCB.
Not connected internally
Multi-function power converter enable input pin or fault output pin. Can only be used as either an
input pin or an output pin.
•
•
If it's used as Power converter enable input pin, it enables and disables the integrated
DC-DC power converter. Connect directly to microcontroller or through a series current
limiting resistor to use as an enable input pin. DC-DC power converted is enabled when EN
is high (connected to VIO) and disabled when low (connected to GND1). If EN is floating,
DC-DC converter is enabled (internal pull-up resistor)
EN/FLT
8
I/O
If it's used as Fault output pin, it gives an alert signal if power converter is not operating
properly. This pin is active low. Connect to microcontroller through a 5 kΩ or greater pull-up
resistor in order to use as a fault outpin pin.
VDD
9
--
--
Side 1 DC-DC converter power supply
Ground connections on side for VDD . GNDIO and GND1 are not internally connected and need
be shorted on PCB.
GND1
10
Ground connections on side for VISOOUT . GND2 and GISOIN are not internally connected and
need be shorted direclty on PCB, or connected through a ferrite bead.
GND2
11
--
Isolated power converter output voltage. VISOOUT and VISOIN need be shorted directly on PCB, or
connected through a ferrite bead.
VISOOUT
VSIN
12
13
--
I
Power converter input . Pin 12 and pin 13 need be shorted directly on PCB.
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Table 7-1. Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
OUT
14
O
--
General purpose logic (GPIO) output (default output is low)
Ground connections for VISOIN. GND2 and GISOIN need be shorted direclty on PCB, or
connected through a ferrite bead.
GISOIN
15, 16, 17
CANL
CANH
18
19
I/O
I/O
Low-level CAN bus line
High-level CAN bus line
Power supply input for CAN tranceiver. VISOIN and VISOOUT need be shorted direclty on PCB, or
connected through a ferrite bead.
VISOIN
20
--
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
–0.5
–0.5
–0.5
–0.5
-58
MAX
UNIT
V
VDD
Power converter supply voltage
6
VISOIN
VISOOUT
VIO
Isolated supply voltage, input supply for CAN transceiver
Isolated supply voltage, Power converter output
Logic supply voltage
6
V
6
V
6
V
VBUS
Voltage on bus pins (CANH, CANL with respect to GND2)
58
45
V
VBUS_DIFF Max Differential voltage on bus pins (CANH-CANL)
-45
V
Logic I/O voltage level ( RXD, TXD, STB, EN, IN)
–0.5
-0.5
–15
–40
–65
VIO + 0.5(3)
VISOIN + 0.5
15
V
Vlogic_IO
OUT
V
IO
Output current on RXD, OUT pins
Junction temperature
mA
°C
°C
TJ
150
Tstg
Storage temperature
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the deviceat these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground pin (GND1 or GND2). All voltage values
except differential I/O bus voltages are peak voltage values.
(3) The maximum voltage must not be greater than 6 V.
8.2 ESD Ratings
VALUE
UNIT
All pins except bus pins
±2000
Electrostatic
discharge
Human body model (HBM), per ANSI/
ESDA/JEDEC JS-001(1)
V(ESD)
V
CANH, CANL Bus pins w.r.t
GND2(pin15/16/17)
±12000
±1500
±8000
Electrostatic
discharge
V(ESD)
V(ESD)
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
V
V
Electrostatic
discharge
per IEC61000-4-2 contact discharge,
CANH and CANL w.r.t. GND2
per IEC61000-4-2 contact discharge,
CANH and CANL w.r.t. GND1 (across
Isolation barrier)
Electrostatic
discharge
V(ESD)
±8000
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD controlprocess.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD controlprocess.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.71
2.25
4.5
NOM
MAX
1.89
5.5
UNIT
1.8-V operation
VIO
Logic supply voltage
V
2.5-V, 3.3-V, and 5.5-V operation
VDD
Power converter supply voltage
5.5
V
V
VDD(UVLO+) Supply threshold when Power converter supply is rising
VDD(UVLO-) Supply threshold when Power converter supply is falling
VHYS1(UVLO) Power converter supply voltage hysteresis
2.7
2.55
0.24
2.95
2.40
0.15
V
V
VIO(UVLO+)
VIO(UVLO-)
Rising threshold of Logic supply voltage
Falling threshold of Logic supply voltage
1.7
V
1
V
VHYS2(UVLO) Logic supply voltage hysteresis
75
125
mV
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over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
VIO
UNIT
V
VIH
VIL
High-level input voltage (TXD, STB, EN, and IN inputs)
Low-level input voltage (TXD, STB, EN, and IN inputs)
VIO = 5V
0.7 × VIO
0
-4
-2
-1
0.3 × VIO
V
mA
mA
mA
mA
mA
mA
mA
mA
Mbps
Mbps
IOH
High-level output current RXD
VIO = 3.3V
VIO = 1.8 or 2.5V
VIO = 5V
4
2
1
IOL
Low-level output current RXD
VIO = 3.3V
VIO = 1.8 or 2.5V
VDD=4.5 to 5.5V
VDD=4.5 to 5.5V
CAN
IOH
IOL
High-level output current OUT
Low-level output current OUT
Signaling rate
-4
4
5
1/tUI
DR
Data rate for extra GPIO channel
GPIO
10
Power up time after applying input supply(Isolated output supply reaches 90%
of setpoint and data transmission can start after this)
Tpwrup
TA
5
ms
≤ 50% of bits are dominant
–40
–40
125
105
°C
°C
Ambient operating temperature
8.4 ThermalInformation
ISOW1044
THERMAL METRIC(1)
DFM
20 PINS
68.5
20.9
44.8
13
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ΨJB
44
RθJC(bot)
--
(1) For more informationabout traditional and new thermal metrics, see theSemiconductor andIC Package Thermal Metrics application
report.
8.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1060
490
UNIT
mW
mW
mW
PD
Maximum power dissipation (both sides)
Maximum power dissipation (side-1)
Maximum power dissipation by (side-2)
VIO = VDD = 5.5 V, STB= GND1, CAN Bus load
RL= 60 Ω, TXD=repetitive pattern of 1 ms time
period with 990 µs LOW time, 10 µs HIGH time,
Extra load on VISOOUT= 20 mA
PD1
PD2
570
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8.6 Insulation Specifications
PARAMETER
TEST CONDITIONS
VALUE
UNIT
GENERAL
CLR
CPG
External clearance(1)
External creepage(1)
Shortest terminal-to-terminal distance through air
>8
>8
mm
mm
Shortest terminal-to-terminal distance across the package
surface
Minimum internal gap (internal clearance – capacitive
signal isolation)
DTI
Distance through the insulation
Distance through the insulation
>17
um
Minimum internal gap (internal clearance- transformer
power isolation)
DTI
CTI
>120
um
V
Comparative tracking index
Material group
IEC 60112; UL 746A
>600
I
According to IEC 60664-1
Rated mains voltage ≤ 600 VRMS
Rated mains voltage ≤ 1000 VRMS
I-IV
I-III
Overvoltage Category
DIN VDE V 0884-11:2017-01(2)
VIORM Maximum repetitive peak isolation voltage
AC voltage (bipolar)
1500
1000
1500
7071
VPK
AC voltage (sine wave) Time dependent dielectric
breakdown (TDDB) test
VIOWM
Maximum working isolation voltage
VRMS
DC voltage
VTEST = VIOTM, t = 60s (qualification);
VTEST = 1.2 × VIOTM, t = 1s (100% production)
VIOTM
VIOSM
VIOSM
Maximum transient isolation voltage
VPK
VPK
VPK
Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 10000 VPK (qualification)
Maximum surge isolation voltage ISOW1044(3)
Maximum surge isolation voltage ISOW1044B(3)
6250
6000
Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.3 × VIOSM = 7800 VPK (qualification)
Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM , tm = 10 s
≤5
≤5
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
ISOW1044: Vpd(m) = 1.6 × VIORM, tm = 10 s. ISOW1044B:
Vpd(m) = 1.2 × VIORM, tm = 10 s
qpd
Apparent charge(4)
pC
Method b1: At routine test (100% production) and
preconditioning (type test)
Vini = 1.2 × VIOTM, tini = 1 s;
ISOW1044: Vpd(m) = 1.875 × VIORM, tm = 1
≤5
s.
s
ISOW1044B: Vpd(m) = 1.5 × VIORM, tm = 1
CIO
RIO
Barrier capacitance, input to output(5)
Isolation resistance, input to output(5)
VIO = 0.4 sin (2πft), f = 1 MHz
VIO = 500 V, TA = 25°C
~3.5
> 1012
> 1011
> 109
pF
Ω
VIO = 500 V, 100°C ≤ TA ≤ 125°C
VIO = 500 V at TS = 150°C
Ω
Ω
Pollution degree
Climatic category
2
40/125/21
UL 1577
VTEST = VISO, t = 60 s (qualification); VTEST = 1.2 × VISO , t
= 1 s (100% production)
VISO
Withstand isolation voltage
5000
VRMS
(1) Creepage and clearance requirements should be applied accordingto the specific equipment isolation standards of an application.
Care should be taken to maintainthe creepage and clearance distance of a board design to ensure that the mounting pads of
theisolator on the printed-circuit board do not reduce this distance. Creepage and clearance on aprinted-circuit board become
equal in certain cases. Techniques such as inserting grooves and/orribs on a printed circuit board are used to help increase these
specifications.
(2) This coupler is suitable for safe electrical insulation (ISOW1044) and basic electrical insulation (ISOW1044B) only within the maximum
operating ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsicsurge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partialdischarge (pd).
(5) All pins on each side of the barrier tied together creating atwo-terminal device
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8.7 Safety-Related Certifications
VDE
CSA
UL
TUV
CQC
Plan to certifiy according
to DIN VDE V
0884-11 :2017-01
Plan to certifiy according to Plan to certifiy under
IEC 62368-1, IEC 61010-1 UL 1577 Component
Plan to certifiy ccording to EN
61010-1:2010/ A1:2019 and EN
62368-1:2014
Plan to certifiy according to
GB4943.1-2011
and IEC 60601-1
Recognition Program
Per CSA62368-1:19,
IEC 62368-1:2018 Ed.
3, CSA 61010-1-12+A1
and IEC 61010-1 3rd Ed.,
Maximum transient isolation ISOW1044 (Reinforced):
voltage 7071 VPK; Maximum 600 VRMS, ISOW1044B
ISOW1044 (Reinforced): 5000
Reinforced insulation, Altitude VRMS reinforced insulation per
repetitive peak isolation
voltage, 1500 VPK
Maximum surge isolation
voltage, ISOW1044:
6250 VPK (Reinforced),
ISOW1044B:
(Basic): 1000 VRMS
maximum working voltage
(pollution degree 2,
;
Single protection, 5000
VRMS
≤ 5000 m, Tropical Climate,
700 VRMS maximum working
voltage.
EN 61010-1:2010/A1:2019 and EN
62368-1:2014 up to working voltage
of 600 VRMS . ISOW1044B (Basic):
1000 VRMS
material group I, ambient
temperature 90 ℃),
1 MOPP (Means of
6000 VPK (Basic)
Patient Protection) per CSA
60601- 1:14 . IEC 60601-1
(ISOW1044 only) Ed.3+A1,
250 VRMS maximum
working voltage
Certification planned
Certification planned
Certification planned
Certification planned
Certification planned
8.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier uponfailure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RθJA = 68.5 °C/W, VI = 5.5 V, TJ = 150 °C, TA = 25 °C,
See Figure 8-1
332
IS
Safety input, output, or supply current(1)
mA
RθJA = 68.5 °C/W, VI = 3.6 V, TJ = 150 °C, TA = 25 °C,
See Figure 8-1
507
PS
TS
Safety input, output, or total power(1)
Safety temperature(1)
RθJA = 68.5 °C/W, TJ = 150 °C, TA = 25 °C, See Figure 8-2
1826
150
mA
℃
(1) The maximum safety temperature,TS, has the same value as the maximum junction temperature,TJ, specified for the device. The
S andPS parameters represent the safety current and safety power respectively.The maximum limits of IS and PS should not
I
beexceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the table is that of a device installed on a high-K test board forleaded surface-mount
packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P,where P is the power dissipated in the device.
TJ(max) = TS = TA +RθJA × PS, where TJ(max) isthe maximum allowed junction temperature.
PS = IS × VI, whereVI is the maximum input voltage.
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8.9 Electrical Characteristics
over recommended operating conditions, typical values are at VDD = 5V, GND1 = GNDIO, GND2 = GISOIN, VIO = 3.3 V and
TA =25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Device
VISOOUT
Isolated Output supply voltage EN=VDD, STB, TXD, IN floating
4.75
5
5.25
V
Extra current available on
Visoout
VDD = 4.5 to 5.5 V, CAN full loaded 60 Ω,
TXD toggling 5 Mbps, IN toggling 10 Mbps
Iout
VOH
VOL
20
mA
Output high voltage on OUT
pin
VDD = 5 V ± 10%, IOH = –4 mA, IN = VIO
VDD = 5 V ± 10%, IOL = 4 mA, IN = GND2
VISOIN – 0.4
V
V
Output low voltage on OUT
pin
0.4
II
II
Input current, IN
Input current, EN
IN at GND1 or VIO
EN at GND1 or VIO
–25
–25
25
25
µA
µA
TXD TERMINAL
II
Input leakage current
Input capacitance
TXD = VIO or GND1
–25
25
uA
pF
VIN = 0.4 x sin(2 x π x 1E+6 x t) + 1.65 V,
VIO = 3.3 V
CI
2
RXD TERMINAL
IO = -4 mA for 4.5 V ≤ VIO ≤ 5.5 V,
See Figure 9-4
VIO – 0.4
VIO – 0.2
V
V
V
V
V
V
V
V
IO = -2 mA for 3.0 V ≤ VIO ≤ 3.6 V,
See Figure 9-4
VIO – 0.2 VIO – 0.06
VOH
High level output voltage
IO = -1 mA for 2.25 V ≤ VIO ≤ 2.75 V,
See Figure 9-4
VIO – 0.1 VIO – 0.04
IO = -1 mA for 1.71 V ≤ VIO ≤ 1.89 V,
See Figure 9-4
VIO – 0.1 VIO – 0.04
IO = 4 mA for 4.5 V ≤ VIO ≤ 5.5 V, See Figure
9-4
0.2
0.07
0.4
0.2
0.1
0.1
IO = 2 mA for 3.0 V ≤ VIO ≤ 3.6 V, See Figure
9-4
VOL
Low level output voltage
IO = 1 mA for 2.25 V ≤ VIO ≤ 2.75 V,
See Figure 9-4
0.035
0.04
IO = 1 mA for 1.71 V ≤ VIO ≤ 1.89 V,
See Figure 9-4
STB Terminal
II
Input leakage current
Input capacitance
STB = VIO or GND1
-25
25
uA
pF
VIN = 0.4 x sin(2 x π x 1E+6 x t) + 1.65 V,
VIO = 3.3 V
CI
2
DRIVER ELECTRICAL CHARACTERISTICS
STB=GND1, TXD = 0 V, 50 Ω ≤ RL ≤ 65 Ω,
and CL = open, See Figure 9-1 and Figure
9-2
Bus output voltage(Dominant),
CANH
2.75
4.5
V
VO(DOM)
STB=GND1, TXD = 0 V, 50 Ω ≤ RL ≤ 65 Ω,
and CL = open, See Figure 9-1 and Figure
9-2
Bus output voltage(Dominant),
CANL
0.5
2.25
3.0
V
V
Bus output voltage(recessive), STB=GND1, TXD = VIO and RL =
VO(REC)
2.0 0.5 x VISOIN
CANH and CANL
open, See Figure 9-1 and Figure 9-2
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over recommended operating conditions, typical values are at VDD = 5V, GND1 = GNDIO, GND2 = GISOIN, VIO = 3.3 V and
TA =25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
STB=GND1, TXD = 0 V, 45 Ω ≤ RL ≤ 70 Ω,
and CL = open, See Figure 9-1 and Figure
9-2
Differential output
voltage(dominant)
1.4
3.3
3.0
V
V
STB=GND1, TXD = 0 V, 50 Ω ≤ RL ≤ 65 Ω,
and CL = open, See Figure 9-1 and Figure
9-2
VOD(DOM)
Differential output
voltage(dominant)
1.5
Differential output
voltage(dominant)
STB=GND1, TXD = 0 V, RL = 2240 Ω, and
CL = open, See Figure 9-1 and Figure 9-2
1.5
–120.0
–50.0
–100
5.0
12.0
50.0
100
V
Differential output
voltage(recessive)
TXD = VIO, RL = 60 Ω, and CL =
open, See Figure 9-1 and Figure 9-2
mV
mV
mV
mV
mV
mV
mA
mA
mA
VOD(REC)
Differential output
voltage(recessive)
TXD = VIO, RL = open, and CL =
open, See Figure 9-1 and Figure 9-2
Bus Output Voltage, CANH,
Standby mode
STB = VIO, RL = open, See Figure
9-1 and Figure 9-2
VO(STB)
VO(STB)
VOD(STB)
VSYM_DC
Bus Output Voltage, CANL,
Standby mode
STB = VIO, RL = open, See Figure
9-1 and Figure 9-2
–100
100
Bus Output Voltage, CANH-
CANL, Standby mode
STB=VIO, RL = open, See Figure
9-1 and Figure 9-2
-200
200
Output symmetry (VISOIN
VO(CANH) - VO(CANL)
-
RL = 60 Ω and CL = open, TXD = VIO or
GND1, See Figure 9-1 and Figure 9-2
–400.0
–115.0
400.0
)
-15 V < CANH < 40 V, CANL = open, and
TXD = 0 V, See Figure 9-8
Short circuit current steady
state output current, dominant
IOS(SS_DOM)
-15 V < CANL < 40 V, CANH = open, and
TXD = 0 V, See Figure 9-8
115.0
5.0
Short circuit current steady
state output current, recessive CANL, and TXD = VIO , See Figure 9-8
-27 V < VBUS < 32 V, VBUS = CANH =
IOS(SS_REC)
–5.0
RECEIVER ELECTRICAL CHARACTERISTICS
VCM
VIT
Input common mode range
See Figure 9-4 and Table 9-1
–12
12
V
Differential input threshold
voltage, normal mode
-12 V ≤ VCM ≤ 12 V, STB =
GND1, See Figure 9-4 and Table 9-1
500.0
900.0
mV
Differential input threshold
voltage, standby mode
VIT(STB)
-12 V ≤ VCM ≤ 12 V, STB = VIO
-12 V ≤ VCM ≤ 12 V, STB = GND1
400
1150
mV
mV
Hysteresis voltage for
differential input threshold,
normal mode
VHYS
100
Dominant state differential
VDIFF(DOM) input voltage range, normal
mode
-12 V ≤ VCM ≤ 12 V, STB =
GND1, See Figure 9-4 and Table 9-1
0.9
1.15
–4
9
9
V
V
V
V
Dominant state differential
VDIFF(DOM) input voltage range, standby
mode
-12 V ≤ VCM ≤ 12 V, STB = VIO, See Figure
9-4 and Table 9-1
Recessive state differential
VDIFF(REC) input voltage range, normal
mode
-12 V ≤ VCM ≤ 12 V, STB =
GND1, See Figure 9-4 and Table 9-1
0.5
0.4
Recessive state differential
VDIFF(REC) input voltage range, standby
mode
-12 V ≤ VCM ≤ 12 V, STB = VIO, See Figure
9-4 and Table 9-1
–4
power-off bus input leakage
IOFF(LKG)
current
CANH = CANL = 5 V, VDD = VIO = GND1
TXD = VIO
5
uA
pF
Input capacitance to ground
(CANH or CANL)
CI
20
CID
RID
Differential input capacitance TXD = VIO
10
90
pF
kΩ
Differential input resistance
TXD = VIO ; -12 V ≤ VCM ≤ +12 V
40
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over recommended operating conditions, typical values are at VDD = 5V, GND1 = GNDIO, GND2 = GISOIN, VIO = 3.3 V and
TA =25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Input resistance (CANH or
CANL)
RIN
TXD = VIO ; -12 V ≤ VCM ≤ +12 V
20
45
1
kΩ
%
Input resistance matching: (1 -
RIN(CANH)/RIN(CANL)) x 100%
RIN(M)
VCANH = VCANL = 5 V
–1
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8.10 Supply Current Characteristics
Typical values are at VDD=5V, VIO=3.3V, Min/Max over recommended operating conditions, GND1 = GNDIO, GND2 =
GISOIN, VDD = 4.5 V to 5.5 V(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power converter disabled
Power converter supply
current
IDD
IIO
EN = GND1, STB, TXD, IN floating
EN = GND1, STB, TXD, IN floating
0.23
0.34
0.27
0.70
mA
mA
Logic supply current
Supply current: Normal Mode
Power converter supply
current
IDD
TXD = GND1, Bus dominant, RL= 60 Ω
124
26
211
46
mA
mA
mA
mA
Power converter supply
current
IDD
TXD = VIO, Bus recessive, RL = 60 Ω
Power converter supply
current
IDD
TXD = 1Mbps 50% duty square wave, RL = 60 Ω
TXD = 5 Mbps 50% duty square wave, RL= 60 Ω
76
123
136
Power converter supply
current
IDD
78
IIO
IIO
IIO
IIO
IIO
IIO
Logic supply current
Logic supply current
Logic supply current
Logic supply current
Logic supply current
Logic supply current
TXD = GND1, Bus dominant, VIO = 1.71 to 1.89 V
TXD = GND1, Bus dominant, VIO = 2.25 to 5.5 V
TXD = VIO, Bus recessive, VIO = 1.71 to 1.89 V
TXD = VIO, Bus recessive, VIO = 2.25 to 5.5 V
TXD = 1 Mbps square wave 50% duty, VIO = 3 to 3.6V
TXD = 5 Mbps square wave 50% duty, VIO = 3 to 3.6V
4.3
4.9
3.3
3.8
4.4
4.5
5.5
6.0
5.4
5.5
5.3
6.2
mA
mA
mA
mA
mA
mA
Supply current: Standby mode
Power converter supply
current
IDD
STB = VIO , RL = 60 Ω
16
23
mA
mA
IIO
Logic supply current
STB = VIO , VIO = 3 to 3.6 V
2.7
3.5
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8.11 Switching Characteristics
Typical specifications are at VIO = 3.3V, VDD = 5V, GND1 = GNDIO, GND2 = GISOIN, Min/Max are over recommended
operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
140
167
MAX
205
UNIT
ns
DEVICE SWITCHING CHARACTERISTICS
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF;
input rise/fall time (10% to 90%) on TXD
= 1 ns; 1.71 V < VIO < 5.5 V, See Figure
9-3
tPROP(LOO Total loop delay, driver input TXD to
receiver RXD, recessive to dominant
P1)
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF;
input rise/fall time (10% to 90%) on TXD
=1 ns; 1.71 V < VIO <5.5 V, See Figure
9-3
tPROP(LOO Total loop delay, driver input TXD to
222
ns
receiver RXD, dominant to recessive
P2)
Mode change time, from Normal to
tMODE
20
1.8
5
us
us
Standby or from Standby to Normal
tWK_FILTE
Filter time for a valid wake-up pattern
0.5
0.8
85
R
tWK_TIME
Bus wake-up timeout value
ms
OUT
TXD = VIO or GND1, VCM = 1200 VPK
See Figure 9-9
,
CMTI
Common mode transient immunity
100
kV/µs
DRIVER SWITCHING CHARACTERISTICS
Propagation delay time, LOW to HIGH
tpHR
TXD edge to driver recessive (dominant
to recessive)
87
78
110
105
Propagation delay time, HIGH TO LOW
TXD edge to driver dominant (recessive
to dominant)
RL = 60 Ω and CL = 100 pF; input rise/
fall time (10% to 90%) on TXD =1 ns,
See Figure 9-3
tpLD
ns
tsk(p)
tR
pulse skew (|tpHR - tpLD|)
15
27
48
Differential output signal rise time
Differential output signal fall time
tF
RTERM = 60 Ω, CL = open, CSPLIT = 4.7nF,
TXD = Dominant or receissive or toggling
at 250khz, 1Mhz See Figure 9-3
Driver symmetry (VO(CANH)
VO(CANL))/VCC
+
VSYM
0.9
1.2
1.1
3.8
V/V
ms
RL = 60 Ω and CL = open,
See GUID-20200710-SS0I-JPX8-LTFT-
RNRQCRR6XDXR
tTXD_DTO Dominant time out
RECEIVER SWITCHING CHARACTERISTICS
Propagation delay time, bus dominant to
tpRH
recessive transition to RXD high output
(dominant to recessive)
90
80
115
105
ns
ns
Propogation delay time, bus recessive to
dominant transition to RXD low output
(recessive to dominant)
CL(RXD) = 15 pF, See Figure 9-5
tpDL
tR
tF
Output signal rise time(RXD)
Output signal fall time(RXD)
1
1
ns
ns
FD TIMING PARAMETERS
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF;
input rise/fall time (10% to 90%) on TXD
=1 ns, See Figure 9-6
Bit time on CAN bus output pins with
tBIT(TXD) = 500 ns
435
155
530
210
ns
ns
tBIT(BUS)
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF;
input rise/fall time (10% to 90%) on TXD
=1 ns, See Figure 9-6
Bit time on CAN bus output pins with
tBIT(TXD) = 200 ns
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Typical specifications are at VIO = 3.3V, VDD = 5V, GND1 = GNDIO, GND2 = GISOIN, Min/Max are over recommended
operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF;
input rise/fall time (10% to 90%) on TXD
=1 ns, See Figure 9-6
Bit time on RXD bus output pins with
tBIT(TXD) = 500 ns
400
550
ns
tBIT(RXD)
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF;
input rise/fall time (10% to 90%) on TXD
=1 ns, See Figure 9-6
Bit time on RXD bus output pins with
tBIT(TXD) = 200 ns
120
-65
220
40
ns
ns
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15
pF; input rise/fall time (10% to 90%) on
Receiver timing symmetry with tBIT(TXD)
500 ns
=
=
TXD =1 ns; ΔtREC = tBIT(RXD) - tBIT(BUS)
See Figure 9-6
,
,
∆tREC
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15
pF; input rise/fall time (10% to 90%) on
TXD =1 ns; ΔtREC = tBIT(RXD) - tBIT(BUS)
See Figure 9-6
Receiver timing symmetry with tBIT(TXD)
200 ns
-45
15
ns
GPIO Channel
tPLH, tPHL Propagation delay time
11
3.5
2.2
2.2
25
10
5
ns
ns
ns
ns
PWD
Pulse Width distortion, |tPLH- tPHL|
tr
tf
Output signal rise time
Output signal fall time
5
8.12 Insulation Characteristics Curves
600
2000
1800
1600
1400
1200
1000
800
VI = 5.5 V
VI = 3.6 V
500
400
300
200
100
0
600
400
200
0
0
50
100
Ambient Temperature (èC)
150
200
0
50
100
Ambient Temperature (èC)
150
200
D002
D001
Figure 8-1. Thermal Derating Curve for Limiting
Current per VDE
Figure 8-2. Thermal Derating Curve for Limiting
Power per VDE
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8.13 Typical Characteristics
VDD = VIO , VISOIN = VISOOUT, CL(RXD) = 15 pF , RL = 60 Ω, TA = 25°C unless otherwise noted.
82
80
78
76
74
72
70
68
82
80
78
76
74
72
70
68
250kbps
500kbps
1Mbps
2Mbps
5Mbps
VDD=4.5V
VDD=5V
VDD=5.5V
-40
-20
VDD = 5 V
0
20
40
60
80
100 120 140
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Temperature (C)
Data Rate (Mbps)
STB = Low VISOOUT = 5 V
VISOOUT = 5 V
STB = Low
Figure 8-4. VDD Supply Current vs Temperature
Figure 8-3. VDD Supply Current vs Datarate
5.5
5.3
5.1
4.9
4.7
4.5
4.3
4.1
3.9
3.7
3.5
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
IN=Low
IN=High
VIO=1.8V
VIO=2.5V
VIO=3.3V
VIO=5V
-40
-20
0
20
40
60
80
100 120 140
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Temperature (C)
Data Rate (Mbps)
VDD = 5 V
STB = High VISOOUT = 5 V
VISOOUT = 5 V
STB = Low
Figure 8-6. VIO Standby Current vs Temerature
Figure 8-5. VIO Supply Current vs Datarate
5.2
5.0
4.8
4.6
4.4
4.2
4.0
155
150
145
140
135
130
250kbps
500kbps
1Mbps
2Mbps
5Mbps
VIO=1.8V
VIO=2.5V
VIO=3.3V
VIO=5V
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (C)
Temperature (C)
VDD = 5 V
CL = 100 pF
STB = Low VISOOUT = 5 V
VDD = 5 V
STB = Low VISOOUT = 5 V
Figure 8-7. VIOI Non-standby Current vs Temperature
Figure 8-8. Loop Delay (Recessive to Dominant) vs Temperature
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8.13 Typical Characteristics (continued)
VDD = VIO , VISOIN = VISOOUT, CL(RXD) = 15 pF , RL = 60 Ω, TA = 25°C unless otherwise noted.
185
180
175
170
165
2.35
2.30
2.25
2.20
2.15
VIO=1.8V
VIO=2.5V
VIO=3.3V
VIO=5V
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (C)
Temperature (C)
VDD = 5 V
STB = Low
VDD = 5 V
CL = 100 pF
STB = Low VISOOUT = 5 V
Figure 8-10. Dominant state differential output voltage vs
Temperature
Figure 8-9. Loop Delay (Dominant to Recessive) vs Temperature
800
700
600
500
VITR
VITF
Vhys
400
300
200
100
0
-40
-20
0
20
40
60
80
100
120
Temperature (C)
VDD = 5 V
STB = Low
VDD = 5 V
STB = Low
Figure 8-12. Dominant Timeout vs Temperature
Figure 8-11. Receiver differential threshold voltage vs
Temperature
Figure 8-13. Glitch Free Power Up on VDD
Figure 8-14. Typical TXD, RXD, CANH and CANL Waveforms at
500 kbps
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8.13 Typical Characteristics (continued)
VDD = VIO , VISOIN = VISOOUT, CL(RXD) = 15 pF , RL = 60 Ω, TA = 25°C unless otherwise noted.
Figure 8-16. Typical TXD, RXD, CANH and CANL Waveforms at
5 Mbps
Figure 8-15. Typical TXD, RXD, CANH and CANL Waveforms at
2 Mbps
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9 Parameter Measurement Information
IO(CANH)
CANH
II
TXD
0 or
VISOIN
VOD
RL
VO(CANH)
V
O(CANL)
+
2
CANL
IO(CANL)
GND1
GND2
VI
VOC
VO(CANH)
VO(CANL )
GND1
GND2
Figure 9-1. Driver Voltage, Current and Test Definitions
Dominant
V
O
(CANH)
» 3.5 V
Recessive
2.5 V
»
V
1.5 V
O (CANL)
»
Figure 9-2. Bus Logic State Voltage Definitions
Vcc
0 V
CANH
CANL
V
Vcc/2
Vcc/2
I
TXD
RL
VO
CL
t
t
PLH
PHL
V
O(D)
90%
10%
0.9V
VI
V
O
0.5V
(SEE NOTE A)
V
t
t
f
O(R)
r
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty
cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
Figure 9-3. Driver Test Circuit and Voltage Waveforms
CANH
IO
VI(CANH) VI(CANL)
RXD
+
VIC
VID
CANL
=
2
VI(CANH)
VO
VI(CANL)
GND2
GND1
Figure 9-4. Receiver Voltage and Current Definitions
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CANH
CANL
I
O
3.5 V
RXD
V
2.4 V
I
2 V
1.5 V
t
t
pHL
pLH
V
V
OH
O
V
CL(RXD)
90 %
I
0.7 Vcc 1
(SEE NOTE A)
0.3 Vcc 1
1 .5 V
V
O
10 %
V
t
t
OL
f
r
GND 1
GND 2
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle,
tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
Figure 9-5. Receiver Test Circuit and Voltage Waveforms
Table 9-1. Receiver Differential Input Voltage Threshold Test
INPUT
VCANL
OUTPUT
VCANH
-11.5 V
12.5 V
-8.55 V
9.45 V
-8.75 V
9.25 V
-11.8 V
12.2 V
Open
|VID|
1000 mV
1000 mV
900 mV
900 mV
500 mV
500 mV
400 mV
400 mV
X
RXD
-12.5 V
11.5 V
-9.45 V
8.55 V
-9.25 V
8.75 V
-12.2 V
11.8 V
Open
L
L
VOL
L
L
H
H
H
H
H
VOH
VI
70%
TXD
CANH
30%
30%
0V
tBIT(TXD)
TXD
5 x tBIT
VI
CL
RL
CANL
tBIT(BUS)
900 mV
VDIFF
RXD
500 mV
CL(RXD)
GND1
VO
VOH
70%
RXD
30%
tBIT(RXD)
VOL
Figure 9-6. tLOOP and CAN FD Timing Parameter Measurement
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V
ISOIN
V
I
CANH
TXD
0 V
R
V
C
OD
L
L
V
OD(D)
CANH
(see Note A)
GND 1
900 mV
V
I
V
OD
500 mV
tTXD_DTO
0 V
A. The input pulse is supplied by a generator having the following characteristics: tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
Figure 9-7. Dominant Time-out Test Circuit and Voltage Waveforms
IOS
200 ꢀs
IOS
CANH
TXD
VBUS
IOS
+
VBUS
CANL
VBUS
0V
0V
œ
GND2
or
VBUS
VBUS
Figure 9-8. Driver Short-Circuit Current Test Circuit and Waveforms
(Connectedto VISOO UT onPCB)
VIO
VISOIN
10 µF
0.1 µF
CANH
0.1 µF
10 µF
VIO
+
VOH or VOL
œ
TXD
GND1
60 ꢀ
S 1
CANL
GND1
RXD
STB
+
VOH or VOL
CL
15 pF(1)
œ
GND1
GND2
+ VCM
œ
Figure 9-9. Common-Mode Transient Immunity Test Circuit
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V
CCI
V
50%
I
50%
IN
OUT
0 V
V
t
t
PHL
PLH
Input Generator
(See Note A)
C
L
V
I
V
50 ꢀ
O
See Note B
OH
90%
10%
50%
50%
V
O
V
OL
t
r
t
f
Copyright © 2016, Texas Instruments Incorporated
A. VCCI and VCCO refers to the power supplies VIO and VISOIN, respectively. CL = 15 pF and The input pulse is supplied by a generator
having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3ns, ZO = 50 Ω. At the input, 50 Ω resistor is required
to terminate Input Generator signal. It is not needed in actual application.
B. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 9-10. Switching Characteristics Test Circuit and Voltage Waveforms
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10 Detailed Description
10.1 Overview
The ISOW1044 has signal isolation channels, power isolation with integrated transformer and CAN transceiver
all integrated in one package. ISOW1044 supports maximum signaling rate up to 1Mbps for CAN, and 5 Mbps
for CAN FD. Functional Block Diagram shows functional block diagram of ISOW1044.
10.2 Power Isolation
The integrated isolated DC-DC converter uses advanced circuit and on-chip layout techniques to reduce
radiated emissions and achieve upto 47% typical efficiency. The integrated transformer uses thin film polymer
as the insulation barrier. In case bus communication is not needed, the DC-DC converter can be switched off
using EN pin to save power. The output voltage, VISOOUT, is monitored and feedback information is conveyed to
the primary side through a dedicated isolation channel. The duty cycle of the primary switching stage is adjusted
accordingly. The fast feedback control loop of the power converter ensures low overshoots and undershoots
during load transients. Undervoltage lockout (UVLO) with hysteresis is integrated on the VIO, VDD and VISOOUT
supplies which ensures robust fails-safe system performance under noisy conditions. An integrated soft-start
mechanism ensures controlled inrush current and avoids any overshoot on the output during power up.
10.3 Signal Isolation
The integrated signal isolation channels for CAN tranceiver and GPIIO employ an ON-OFF keying (OOK)
modulation scheme to transmit the digital data across a silicon-dioxide based isolation barrier. The transmitter
sends a high frequency carrier across the barrier to represent one state and sends no signal to represent the
other state. The receiver demodulates the signal after signal conditioning and produces the output through
a buffer stage. The signal-isolation channels incorporate advanced circuit techniques to maximize the CMTI
performance and minimize the radiated emissions from the high frequency carrier and IO buffer switching. Figure
10-3 shows a functional block diagram of a typical signal isolation channel.
In order to keep any noise coupling from power converter away from signal path, power supplies on side1
for power converter (VDD) and signal path(VIO) are kept separate. Similarly on side2, power converter output
(VISOOUT ) needs to be connected to power supply for CAN (VISOIN) externally on PCB. For more details, refer to
Layout guidelines section.
10.4 CAN Transceiver
The ISOW1044 device includes a digitally isolated CAN transceiver that offers ±58-V DC bus fault protection
and ±12-V common-mode voltage range. The device supports up to 5-Mbps data rate in CAN FD mode allowing
much faster transfer of payload compared to classic CAN. The power converter operates from a 5-V supply on
side 1 (VDD) and a 5-V supply on side 2 (VISOOUT). The logic supply VIO on side 1 can operate from 1.71-V
up to 5.5-V. This wide VIO supply range is of particular advantage for applications operating in harsh industrial
environments because the low voltage on side 1 enables the connection to low voltage microcontrollers for
power conservation, whereas the 5 V on side 2 maintains a high signal-to-noise ratio of the bus signals.
The ISOW1044 supports a standby mode and remote BUS Wake-UP (WUP). The STB pin can be supplied from
either the system processor or from a static system voltage source. In standby mode, the CAN driver and main
receiver are switched off and bidirectional CAN communication is not possible. The DC-DC converter, low-power
receiver, and bus monitor circuits are still enabled to allow for RXD wake-up requests via the CAN bus. The CAN
bus pins are weakly pulled to GND in this mode. If normal mode is the only intended mode of operation than the
STB pin can be tied directly to GND.
10.4.1 Remote Wake Request via Wake-Up Pattern (WUP) in Standby Mode
The ISOW1044 supports a remote wake-up request that is used to indicate to the host controller that the bus is
active and the node should return to normal operation.
The device uses the multiple filtered dominant wake-up pattern (WUP) from the ISO 11898-2:2016 standard to
qualify bus activity. Once a valid WUP has been received, the wake request is indicated to the controller by a
falling edge and low period corresponding to a filtered dominant on the RXD output of the ISOW1044.
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The WUP consists of a filtered dominant pulse, followed by a filtered recessive pulse, and finally by a second
filtered dominant pulse. The first filtered dominant initiates the WUP, and the bus monitor then waits on a filtered
recessive; other bus traffic does not reset the bus monitor. Once a filtered recessive is received the bus monitor
is waiting for a filtered dominant and again, other bus traffic does not reset the bus monitor. Immediately upon
reception of the second filtered dominant the bus monitor recognizes the WUP and drives the RXD output low
every time an additional filtered dominant signal is received from the bus.
For a dominant or recessive to be considered filtered, the bus must be in that state for more than the
tWK_FILTER time. Due to variability in tWK_FILTER the following scenarios are applicable. Bus state times less than
tWK_FILTER(MIN) are never detected as part of a WUP and thus no wake request is generated. Bus state times
between tWK_FILTER(MIN) and tWK_FILTER(MAX) may be detected as part of a WUP and a wake-up request may be
generated. Bus state times greater than tWK_FILTER(MAX) are always detected as part of a WUP, and thus a wake
request is always generated. See Figure 10-1 for the timing diagram of the wake-up pattern.
The pattern and tWK_FILTER time used for the WUP prevents noise and bus stuck dominant faults from causing
false wake-up requests while allowing any valid message to initiate a wake-up request.
The ISO 11898-2:2016 standard has defined times for a short and long wake-up filter time. The tWK_FILTER timing
for the device has been picked to be within the minimum and maximum values of both filter ranges. This timing
has been chosen such that a single bit time at 500 kbps, or two back-to-back bit times at 1 Mbps triggers the
filter in either bus state. Any CAN frame at 500 kbps or less would contain a valid WUP.
For an additional layer of robustness and to prevent false wake-ups, the device implements a wake-up timeout
feature. For a remote wake-up event to successfully occur, the entire WUP must be received within the timeout
value t ≤ tWK_TIMEOUT. If not, the internal logic is reset and the transceiver remains in its current state without
waking up. The full pattern must then be transmitted again, conforming to the constraints mentioned in this
section. See Figure 10-1 for the timing diagram of the wake-up pattern with wake timeout feature.
Bus Wake via RXD
Wake Up Pattern (WUP) received in t < tWK_Timeout
Request
Filtered
Dominant
Filtered
Dominant
Filtered
Recessive
Waiting for
Filtered
Dominant
Waiting for
Filtered
Recessive
Bus
Bus VDiff
RXD
≥ tWK_FILTER
≥ tWK_FILTER
≥ tWK_FILTER
≥ tWK_FILTER
Filtered Dominant RXD Output
Bus Wake Via RXD Requests
Figure 10-1. Wake-Up Pattern (WUP) with tWK_TIMEOUT
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10.5 Functional Block Diagram
VISOIN
VIO
IN
Tx
Tx
Tx
Rx
Rx
Rx
Rx
Tx
OUT
TXD
STB
RXD
CANH
CANL
D
R
GNDIO
GISOIN
VISOOUT
VDD
VSIN
EN/FLT
DC-DC Secondary
DC-DC Primary
GND1
GND2
Galvanic Isolation
Barrier
Figure 10-2. Block Diagram
Receiver
Transmitter
TX IN
OOK
Modulation
TX IN
SiO based
2
RX OUT
TX Signal
Conditioning
RX Signal
Conditioning
Envelope
Detection
Capacitive
Isolation
Barrier
Carrier signal through
isolation barrier
Emissions
Reduction
Techniques
RX OUT
Oscillator
Figure 10-3. Signal Isolation channel
10.6 Feature Description
10.6.1 CAN Bus States
The CAN bus has two logical states during operation: recessive and dominant. A dominant bus state occurs
when the bus is driven differentially and corresponds to a logic low on the TXD and RXD pins. A recessive bus
state occurs when the bus is biased to VCC/2 via the high-resistance internal input resistors (RIN) of the receiver
and corresponds to a logic high on the TXD and RXD pins.
A dominant state overwrites the recessive state during arbitration. Multiple CAN nodes may be transmitting a
dominant bit at the same time during arbitration, and in this case the differential voltage of the bus is greater than
the differential voltage of a single driver.
The ISOW1044 transceiver implements a standby (STB ) mode which enables a third bus state where the bus
pins are weakly biased to ground via the high resistance internal resistors of the receiver.
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Normal Mode
Standby Mode
CANH
VDIFF
VDIFF
CANL
Recessive
Dominant
Recessive
Time, t
Figure 10-4. Bus States (Physical Bit Representation)
CANH
2.5V
A
RXD
Bias
Unit
B
GND
CANL
Figure 10-5. Simplified Recessive Common Mode Bias and Receiver
A. A - Normal Mode B - Standby Mode
10.6.2 Digital Inputs and Outputs: TXD (Input) and RXD (Output)
The VIO supply for the isolated digital input and output side of the device can be supplied by 1.8-V, 2.5-V, 3.3-V,
and 5-V supplies and therefore the digital inputs and outputs are 1.8-V, 2.5-V, 3.3-V, and 5-V compatible.
10.6.3 TXD Dominant Timeout (DTO)
The TXD DTO circuit prevents the transceiver from blocking network communication in the event of a hardware
or software failure where the TXD pin is held dominant longer than the timeout period, tTXD_DTO. The DTO circuit
timer starts on a falling edge on the TXD pin. The DTO circuit disables the CAN bus driver if no rising edge
occurs before the timeout period expires, which frees the bus for communication between other nodes on the
network. The CAN driver is activated again when a recessive signal occurs on the TXD pin, clearing the TXD
DTO condition. The receiver and RXD pin still reflect activity on the CAN bus, and the bus terminals are biased
to the recessive level during a TXD dominant timeout.
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TXD fault stuck dominant
Example: PCB failure or bad software
Fault is repaired and transmission
capability is restored
TXD
(driver)
tTXD_DTO
Driver disabled freeing bus for other nodes
Bus would be stuck dominant, blocking communication for the
whole network but TXD DTO prevents this and frees the bus for
communication after the tTXD_DTO time.
Normal CAN
communication
CAN
Bus
Signal
tTXD_DTO
Communication from
other bus nodes
Communication from
repaired nodes
RXD
(receiver)
Communication from
local node
Communication from
other bus nodes
Communication from
repaired nodes
Figure 10-6. Example Timing Diagram for TXD DTO
Note
The minimum dominant TXD time (tTXD_DTO) allowed by the TXD DTO circuit limits the minimum
possible transmitted data rate of the device. The CAN protocol allows a maximum of eleven
successive dominant bits (on TXD) for the worst case, where five successive dominant bits are
followed immediately by an error frame. This, along with the tTXD_DTO minimum, limits the minimum
data rate. Calculate the minimum transmitted data rate with Equation 1.
Minimum Data Rate = 11 / tTXD_DTO
(1)
10.6.4 Power-Up and Power-Down Behavior
The ISOW1044 has built-in under-voltage lockout (UVLO) on all supplies (VDD, VIO and VISOOUT) with positive-
going and negative-going thresholds and hysteresis. Both the power converter supply (VDD) and Logic supply
(VIO) need to be present for the device to work. If either of them is below its UVLO, both the signal path and the
power converter are disabled.
Assuming VIO is above its UVLO+, when the VDD voltage crosses the positive-going UVLO threshold during
power-up, the DC-DC converter initializes and the power converter duty cycle is increased in a controlled
manner. This soft-start scheme limits primary peak currents drawn from the VDD supply and charges the VISOOUT
output in a controlled manner, avoiding overshoots. CAN BUS is in high impedance state in this duration.
When the UVLO positive-going threshold is crossed on the secondary side VISOOUT pin, the feedback channel
starts providing feedback to the primary controller. The regulation loop takes over and CAN drive output,
Received data output (RXD) and gneral purpose logic channel (OUT) take their respective states defined by the
inputs to the device i.e. Standby (STB), Driver data to be transmitted TXD, and general purpose logic input IN
respectively. Designers should consider a sufficient time margin (typically 5 ms with 10-µF load capacitance) to
allow this power up sequence before any usable system functionality.
When either of VDD or VIO is lost, the primary side DC-DC controller turns off when the UVLO lower threshold is
reached. The VISOOUT capacitor then discharges depending on the isolation channels and BUS load.
10.6.5 Protection Features
The ISOW1044 device has multiple protection features to create a robust system level solution.
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•
The first feature is an Enable/Fault protection feature. This EN/FLT pin can be used as either an input pin to
enable or disable the integrated DC-DC power converter or as an output pin which works as an alert signal if
the power converter is not operating properly. In the /Fault use case, a fault is reported if VDD > 7 V, VDD < 2.5
V, or if the junction temperature >170°C. When a fault is detected, this pin will go low, disabling the DC-DC
converter to prevent any damage.
5 kΩ
Powers Down CAN Transceiver
and DC-DC Converter.
EN/FLT
MCU OUTPUT
IQ < 1 mA Typical
MCU INPUT
Fault Reported If
VDD < 2.5 V
VDD > 7 V
Junction Temp > 170° C
Figure 10-7. EN Fault Pin Diagram
•
An over-voltage clamp feature is present on VISOOUT which will clamp the voltage at 6 V if there is an increase
in voltage seen. For device reliability, it is recommended that VISOOUT stays lower than the over-clamp voltage
for device reliability.
•
•
Over-Voltage Lock Out (OVLO) on VDD will occur when a voltage higher than 7 V on VDD is seen. At OVLO,
the device will go into a low power state and the EN/FLT pin will go low.
In cases of overload or short on power converter output VISOOUT, maximum duty cycle of power converter is
limited. In cases of driver bus short circuit due to the external power supply cable shorting to the bus cable,
short circuit current protection on CAN chip restricts the bus current to ±115 mA maximum.
Thermal protection is also integrated to help prevent the device from getting damaged under such scenarios.
An increase in the die temperature is monitored and the device is disabled when the die temperature
becomes 165 ℃ (typical), thus disabling the short condition. The device is re-enabled when the junction
temperature becomes 155 ℃ (typical). If an overload or output short-circuit condition prevails, this protection
cycle is repeated. Care should be taken in the system design to prevent repeated or prolonged exposure to
bus shorts as this exposes the device to high junction temperatures for extreme amounts of time affecting
device reliability.
•
10.6.6 Floating Pins, Unpowered Device
The ISOW1044 is designed to be ideal passive or no load to the CAN bus if it is unpowered. The bus pins
(CANH, CANL) have extremely low leakage currents when the device is unpowered to avoid loading down the
bus which is critical if some nodes of the network are unpowered while the rest of the of network remains in
operation.
The device has internal pull-ups on critical pins (TXD and STB) which places the device into known states if the
pin floats. This internal bias should not be relied upon by design though, especially in noisy environments, but
instead should be considered a failsafe protection feature. When a CAN controller supporting open drain outputs
is used, an adequate external pull-up resistor must be used to ensure that the TXD output of the CAN controller
maintains adequate bit timing to the input of the CAN transceiver. See Table 10-3 for more details.
10.6.7 Glitch-Free Power Up and Power Down
Communication on the bus that already exist between a master node and slave node in a CAN network must not
be disturbed when a new node is swapped in or out of the network. No glitches on the bus should occur when
the device is:
•
•
•
Hot plugged into the network in an unpowered state
Hot plugged into the network in a powered state and recessive state
Powered up or powered down in a recessive state when already connected to the bus
The ISOW1044 device meets above criteria and does not cause any false data toggling on the bus when
powered up or powered down in a recessive state with supply ramp rates >= 50 us.
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10.7 Device Functional Modes
Table 10-1 lists the supply configuration for these devices:
Table 10-1. Supply configuration Function Table
INPUTS
VIO
OUTPUTS
BUS OUTPUT (CANH/
CANL)
(2)
VDD
< VDD(UVLO+)
>VDD(UVLO+)
5 V
EN/FLT
RXD
VISOOUT
Recessive
(Default High)
>VIO(UVLO+)
<VIO(UVLO+)
X
High-Z
OFF
Recessive
(Default High)
X
H or Open
L
High-Z
Invalid Operation
Per Device Mode (1) and
TXD
1.71 V to 5.5 V
1.71 V to 5.5 V
Mirrors Bus
5 V
Recessive
(Default High)
5 V
High-Z
OFF
(1) At Normal mode (STB = L), BUS OUTPUT follows TXD. Otherwise if at Standby mode (STB = H or Open), BUS OUTPUT is High-Z.
(2) VISOOUT shorted to VISOIN on PCB. GND2 and GISOIN pins are shorted together and EN/FLT = High.
Table 10-2 shows the different driver functional modes:
Table 10-2. Driver Functional Table
INPUTS
EN/FLT
OUTPUTS
CANL (3)
(1)
VDD
VIO
STB
INPUT TXD
L
CANH (3)
DRIVEN BUS STATE
Dominant
H
Z
L
Z
L
H or Open
Recessive
H or Open
L
Weak pull-down to
ground
PU
PU
H or Open
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Weak pull-down to
ground
Weak pull-down to
ground
PD
PU
PU
X
X
X
X
X
X
Hi-Z
Hi-Z
PD(2)
Invalid Operation
(1) PU=Powered up, PD=Powered down; H=high level; L=Low level; X=Irrelevant; Z = common-mode (recessive) biased to VISOIN/2 ,
Hi-Z=High impedance state
(2) A strongly driven input signal on TXD can weakly power the floating VIO through an internal protection diode and cause an
undetermined output.
(3) VISOOUT shorted to VISOIN on PCB and GND2 and GISOIN pins are shorted together and EN/FLT = High
At Normal mode (STB = L), the CAN outputs follow the logic states at data input, TXD. A logic low at the TXD
input causes the CAN output to go dominant. Therefore the differential output voltage defined by Equation 2 is
positive. A logic high at the TXD input causes the CAN BUS to go recessive. Therefore the differential output
voltage defined by Equation 2 is negative.
VOD = VCANH – VCANL
(2)
At Standby mode (STB = H or Open), both outputs go to the high-impedance (Hi-Z) state. The logic state at the
TXD pin is irrelevant when this mode. The driver is disabled (bus outputs are in the Hi-Z) by default when the
STB pin is left open. The TXD pin has an internal pullup resistor.
Table 10-3 shows the different receiver functional modes:
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Table 10-3. Receiver Functional Table
INPUTS
OUTPUT
CAN DIFFERENTIAL
(1)
VDD
VIO
EN/FLT
STB
INPUTS VID = VCANH
VCANL
-
BUS STATE
RXD (3)
VID > 0.9 V
Dominant
Undefined
Recessive
Dominant
Undefined
Recessive
Open
L
Undefined
H
L
0.5 V< VID < 0.9 V
VID < 0.5 V
H or Open
VID > 1.15 V
PU
PU
H (L if a remote wake
event occurred)
H or Open
0.4 V< VID < 1.15 V
VID < 0.4 V
X
X
X
X
Open (VID = 0 V)
H
Hi-Z
L
X
X
X
X
X
X
PD
PU
PU
X
Hi-Z
PD(2)
X
Invalid Operation
(1) PU=Powered up, PD=Powered down; H=high level; L=Low level; X=Irrelevant; Hi-Z=High impedance state
(2) A strongly driven input signal on TXD can weakly power the floating VIO through an internal protection diode and cause an
undetermined output.
(3) VISOOUT shorted to VISOIN on PCB. GND2 and GISOIN pins are shorted together and EN/FLT = High
At Normal mode (STB = L), the receiver output, RXD, goes low when the differential input voltage defined by
Equation 3 is greater than the positive input threshold, VIT+. The receiver output, RXD, goes high when the
differential input voltage defined by Equation 3 is less than the negative input threshold, VIT– . If the VID voltage
is between the VIT+ and VIT– thresholds, the output is indeterminate.
VID = VCANH – VCANL
(3)
At Standby mode (STB = H or Open), RXD output goes high and if a remote wake-up event occurs, it goes low.
Other device feature functional states are shown inTable 10-4 and Table 10-5 below:
Table 10-4. DC-DC Converter Enable/Disable
INPUTS
OUTPUT
VISOOUT
5 V
VDD
PU
PU
VIO
PU
PU
EN/FLT
H or Open
L
OFF
Table 10-5. General Purpose Logic Input/Output
INPUTS
OUTPUT
CommentsComments
(1) (2)
VDD
VIO
EN/FLT
IN
H
OUT
H
Output channel assumes
logic state governed by IN
H or Open
L
L
PU
PU
Open
X
L
Hi-Z
Default state
L
X
X
Device is in disabled state
when either of VDD or VIO is
missing
PD
PU
PU
PD
X
Hi-Z
X
Invalid Operation
(1) PU = Powered Up; PD = Powered Down; H = Logic High; L= Logic Low; X = Irrelevant, Hi-Z = High Impedance (OFF) state
(2) VISOOUT shorted to VISOIN on PCB. GND2 and GISOIN pins are shorted together and EN=High
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10.8 Device I/O Schematics
TXD, STB
VIO
VIO
IN
VIO
VIO
VIO
VIO
VIO
500 kꢀ
985 ꢀ
985 ꢀ
IN
TXD, STB
500 kꢀ
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
EN/FLT
VIO
RXD
VIO
VIO
VIO
VIO
550 kꢀ
EN/FLT
~20 ꢀ
RXD
1mA
GND1
GND1
GND1
GND1
GNDIO
OUT
VISOIN
~20 ꢀ
OUT
GISOIN
Figure 10-8. Device I/O schematics
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11 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
11.1 Application Information
The ISOW1044 device can be used with other components from Texas Instruments such as a microcontroller
and a linear voltage regulator to form a fully isolated CAN interface. Typically two power supplies isolated from
each other are needed to power up both sides of Isolated CAN device. Due to the integrated DC-DC converter in
the device, the isolated supply is generated inside the device that can be used to power isolated side of the CAN
device and peripherals on isolated side, thus saving board space.
11.2 Typical Application
The ISOW1044 device is suitable for applications that have limited board space and desire more integration.
It is also suitable for very high voltage applications, where power transformers meeting the required isolation
specifications are bulky and expensive. The device can be used in applications with a host micro-controller
or FPGA that includes the link layer portion of the CAN protocol. Figure 11-1 shows a typical application
configuration for 5 V controller applications. The bus termination is shown for illustrative purposes. The
ISOW1044 device meets 8 kV contact ESD (Electrostatic discharge) per IEC 61000-4-2 standalone with no
external components on bus. If the application requires the usage of Common mode choke (CMC) , then use of
Transient voltage suppressor (TVS) is a must to achieve 8kV IEC ESD.
4.7k
Extra current
~20mA
8
FB
10μF
0.1μF
1
EN/FLT
20
V
VISOIN
IO
Other field
circuitry
0.1μF
15
6
4
3
GISOIN
GNDIO
VIO
16
17
GISOIN
GISOIN
GPIO1
MCU
STB
ISOW1044
Optional
Termination
TXD
TXD
19
CANH
CAN
BUS
5
2
RXD
RXD
18
14
CANL
GPIO2
IN
NC
L1
N
OUT
7
DGND
13
VSIN
PSU
FB
FB
FB
FB
9
12
11
VDD
VISOOUT
5V
PE
10
GND
GND1
GND2
10µF
1µF 10nF
10nF 1µF 10µF
Optional bus protection
Galvanic
Isolation Barrier
Notes:
1. Keep 10 nF bypass capacitors close to VDD and VISOOUT pins (< 1 mm) for opꢀmum Radiated emissions performance
2. GND1 and GNDIO need be shorted directcly. GND2 and GISOIN need be shorted directly, or through ferrite beads.
3. All GISOIN pins (pin 15, 16, 17) need be shorted on PCB for opꢀmum IEC-ESD performance.
4. VSIN and VISOOUT must be shorted on PCB.
Figure 11-1. Application circuit for ISOW1044
11.2.1 Design Requirements
Unlike an optocoupler-based solution, which requires several external components to improve performance,
provide bias, or limit current, the ISOW1044 device only requires external bypass capacitors to operate as
shown in above application diagram.
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Because of very-high current flowing through the device VDD and VISOOUT supplies, higher decoupling capacitors
typically provide better noise and ripple performance. Although a 10-µF capacitor is adequate, higher decoupling
capacitors (such as 47 µF) on both the VDD and VISOOUT pins to the respective grounds are strongly
recommended to achieve the best performance.
11.2.2 Detailed Design Procedure
11.2.2.1 Bus Loading, Length and Number of Nodes
The ISO 11898-2 Standard specifies a maximum bus length of 40 m and maximum stub length of 0.3 m.
However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to
a bus. A large number of nodes requires transceivers with high input impedance such as the ISOW1044
transceiver.
Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO
11898-2 Standard. These organizations and standards have made system-level trade-offs for data rate, cable
length, and parasitic loading of the bus. Examples of some of these specifications are ARINC825, CANopen,
DeviceNet, and NMEA2000.
The ISOW1044 device is specified to meet the 1.5-V requirement with a 50-Ω load, incorporating the worst
case including parallel transceivers. The differential input resistance of the device is a minimum of 30 kΩ. If 100
ISOW1044 transceivers are in parallel on a bus, this requirement is equivalent to a 300-Ω differential load worst
case. That transceiver load of 300 Ω in parallel with the 60 Ω gives an equivalent loading of 50 Ω. Therefore,
the ISOW1044 device theoretically supports up to 100 transceivers on a single bus segment. However, for CAN
network design margin must be given for signal loss across the system and cabling, parasitic loadings, network
imbalances, ground offsets and signal integrity, therefore a practical maximum number of nodes is typically much
lower. Bus length may also be extended beyond the original ISO 11898 standard of 40 m by careful system
design and data-rate tradeoffs. For example, CAN open network design guidelines allow the network to be up to
1 km with changes in the termination resistance, cabling, less than 64 nodes, and a significantly lowered data
rate.
This flexibility in CAN network design is one of the key strengths of the various extensions and additional
standards that have been built on the original ISO 11898-2 CAN standard. Using this flexibility requires the
responsibility of good network design and balancing these tradeoffs.
11.2.2.2 CAN Termination
The ISO11898 standard specifies the interconnect to be a single twisted pair cable (shielded or unshielded) with
120-Ω characteristic impedance (ZO). Resistors equal to the characteristic impedance of the line should be used
to terminate both ends of the cable to prevent signal reflections. Unterminated drop-lines (stubs) connecting
nodes to the bus should be kept as short as possible to minimize signal reflections. The termination may be in a
node, but if nodes are removed from the bus, the termination must be carefully placed so that it is not removed
from the bus.
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Node 1
Node 2
Node 3
Node n
(with termination)
MCU or DSP
MCU or DSP
MCU or DSP
MCU or DSP
CAN
Controller
CAN
Controller
CAN
Controller
CAN
Controller
CAN
Transceiver
CAN
Transceiver
CAN
Transceiver
CAN
Transceiver
RTERM
RTERM
Figure 11-2. Typical CAN Bus
Termination may be a single 120-Ω resistor at the end of the bus, either on the cable or in a terminating
node. If filtering and stabilization of the common-mode voltage of the bus is desired, then split termination can
be used as below termination concepts. Split termination improves the electromagnetic emissions behavior of
the network by eliminating fluctuations in the bus common-mode voltages at the start and end of message
transmissions.
Standard Termination
Split Termination
CANH
CANH
RTERM / 2
CAN
Transceiver
CAN
Transceiver
RTERM
CSPLIT
RTERM / 2
CANL
CANL
Figure 11-3. CAN Bus Termination Concepts
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11.2.3 Application Curve
Red: Peak vertical scan. Green: Peak horizontal scan
VDD = 5 V
VISOOUT = 5 V
Data rate = 1 Mbps
Figure 11-4. ISOW1044 Radiated Emissions versus CISPR32B line
11.2.4 Insulation Lifetime
Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides; See Figure 11-5 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced
insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million
(ppm). Even though the expected minimum insulation lifetime is 20 years at the specified working isolation
voltage, VDE reinforced certification requires additional safety margin of 20% for working voltage and 87.5% for
lifetime which translates into minimum required insulation lifetime of 37.5 years at a working voltage that's 20%
higher than the specified value. Figure 11-6 shows the intrinsic capability of the isolation barrier to withstand high
voltage stress over its lifetime. Based on the TDDB data, the intrinsic capability of the insulation is 1000 VRMS
with a lifetime of 1184 years.
A
Vcc 1
Vcc 2
Time Counter
> 1 mA
DUT
GND 1
GND 2
V
S
Oven at 150 °C
Figure 11-5. Test Setup for Insulation Lifetime Measurement
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Figure 11-6. Insulation Lifetime Projection Data
12 Power Supply Recommendations
To make sure that operation is reliable at all data rates and supply voltages, adequate decoupling capacitors
must be located as close to supply pins as possible. Power converter input VDD and output VISOOUT supply pins
should have high frequency ceramic capacitors 10 nF and bulk capacitors 10 μF atleast close to the pins. Signal
path supply pins, VIO and VISOIN , should have 100 nF or higher value ceramic bypass capacitors close to device
pins. ISOW10144 can consume typical peak pulse currents of upto 250mA under fully loaded conditions for short
durations (10s of µs) from the power source that is powering VDD of ISOW1044. Please make sure the current
limit of upstream power device is atleast 300mA typical.
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13 Layout
13.1 Layout Guidelines
Figure 11-1 shows the recommended placement and routing of device bypass capacitors. Below guidelines must
be followed to achieve low emissions design:
1. High frequency bypass capacitors 10 nF must be placed close to VDD and VISOOUT pins, within 1 mm
distance away from device pins. This is very essential for optimised radiated emissions performance. Ensure
that these capacitors are 0402 size so that they offer least inductance (ESL).
2. Bulk capacitors of atleast 10 μF must be placed on power converter input (VDD) and output (VISOOUT) supply
pins after the 10 nF capacitor with a distance of 2 - 4 mm, as shown in Layout Example.
3. Traces on VDD and GND1 must be symmetric till bypass capacitors. Similarly traces on VISOOUT and GND2
must be symmetric.
4. Place two 0402 size Ferrite beads (Part number: BLM15EX331SN1) on power supply pins, one between
VISOOUT and VISOIN and the other between GND2 (pin 11) and GND2(pin 15), as shown in example PCB
layout, so that any high frequency noise from power converter output sees a high impedance before it goes
to other components on PCB.
5. Do not have any metal traces or ground pour within 4 mm of power converter output terminals VISOOUT
(pin12) and GND2 (pin11).
6. Place the CAN BUS protection and filtering circuitry close to the bus connector to prevent transients,
ESD, and noise from propagating onto the board. This layout example shows an optional transient voltage
suppression (TVS) diode, D1, which may be implemented if the system-level requirements exceed the
specified rating of the transceiver. This example also shows two optional 68pF bus filter capacitors
7. Common mode choke or ferrite beads on bus terminals (CANH/CANL) can minimise any high frequency
noise that can couple of CAN bus cable which can act as antenna and amplify that noise. This will improve
Radiated emissions performance on a system level.
8. Following the layout guidelines of EVM as much as possible is highly recommended for a low radiated
emissions design. EVM Link is available in Related Documentation.
13.2 Layout Example
Optional
Protection and
Termination
Ground plane on side2
0.1 µF
10 µF
68 pF
C
ISOW1044
<2mm
VIO
<2mm
VISOIN
0.1 µF
C
C
FB5
Input Supply 1
20
19
1
C
IN
CANH
CANL
2
CAN
BUS
D1
TXD
3
4
18
17
STB
GISOIN
C
RXD
GNDIO
5
68 pF
16 GISOIN
6
GISOIN
OUT
15
14
13
12
11
NC
EN/FLT
VDD
7
Ground
plane on
side2
VSIN
8
2-4mm
1 µF
<1mm
10 nF
10 nF
1 µF 10 µF
10 µF
FB4
Input Supply 2
Input Ground
FB1
FB2
9
VISOOUT
GND2
C
C
C
C
C
C
FB3
GND1
10
Ground plane on
side 1
2-4mm
<1mm
Keep-out zone
for any metal
Figure 13-1. Layout example
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14 Device and Documentation Support
14.1 Documentation Support
14.1.1 Related Documentation
For related documentation see the following:
•
•
•
Texas Instruments, Digital Isolator Design Guide
Texas Instruments, Isolation Glossary
ISOW1044DFM Evaluation board
14.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
14.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
14.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
14.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
14.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
15 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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29-Jan-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISOW1044BDFMR
ISOW1044DFMR
XISOW1044DFMR
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
DFM
DFM
DFM
20
20
20
850
850
850
RoHS & Green
RoHS & Green
TBD
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Call TI
-40 to 125
-40 to 125
-40 to 125
ISOW1044
ISOW1044
NIPDAU
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jan-2022
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISOW1044BDFMR
ISOW1044DFMR
SOIC
SOIC
DFM
DFM
20
20
850
850
330.0
330.0
24.4
24.4
10.85 13.4
10.85 13.4
4.0
4.0
16.0
16.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ISOW1044BDFMR
ISOW1044DFMR
SOIC
SOIC
DFM
DFM
20
20
850
850
350.0
350.0
350.0
350.0
43.0
43.0
Pack Materials-Page 2
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