ISOW1412_V01 [TI]
ISOW14x2 5-kVRMS Reinforced Isolated RS-485/RS-422 Transceiver with Integrated Low-Emissions, Low-Noise, High-Efficiency DC-DC Converter;型号: | ISOW1412_V01 |
厂家: | TEXAS INSTRUMENTS |
描述: | ISOW14x2 5-kVRMS Reinforced Isolated RS-485/RS-422 Transceiver with Integrated Low-Emissions, Low-Noise, High-Efficiency DC-DC Converter |
文件: | 总49页 (文件大小:3829K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ISOW1412, ISOW1432
SLLSF86B – MAY 2018 – REVISED OCTOBER 2021
ISOW14x2 Isolated RS-485/RS-422 Transceiver with Integrated Low-Emissions, Low-
Noise, High-Efficiency DC-DC Converter
– UL 1577 component recognition program
– IEC 62368-1, IEC 61010-1, IEC 60601-1 and
1 Features
•
Meets or exceeds the requirements of the TIA/
EIA-485A standard
Data rates
GB 4943.1-2011 certifications
2 Applications
•
•
•
•
•
•
Factory automation
Building automation
Industrial transport
Solar inverters, protection relay
Motor drives
– ISOW1412 : 500 kbps
– ISOW1432 : 12 Mbps
Integrated low-emissions DC-DC converter with
low-emissions, low-noise
– Meets CISPR 32 Class B and EN 55032 Class
B with margin on a two-layer PCB
– Low frequency power converter at 25 MHz
enabling low noise performance
Additional 2 Mbps GPIO channel
High efficiency output power
•
3 Description
The ISOW14x2 devices are galvanically-isolated
RS-485/RS-422 transceivers with a built-in isolated
DC-DC converter, that eliminates the need for a
separate isolated power supply in space constrained
isolated designs. The low-emissions, isolated DC-
DC converter meets CISPR 32 radiated emissions
Class B standard with just two ferrite beads on
a simple two-layer PCB. Additional 20 mA output
current can be used to power other circuits on the
board. An integrated 2 Mbps GPIO channel helps
remove any additional digital isolator or optocoupler
for diagnotstics, LED indication or supply monitoring.
•
•
– Typical efficiency: 46%
– VISOOUT accuracy: ±5%
– Additional output current: 20 mA
Independent power supply for RS-485 & DC-DC
– Logic supply (VIO): 1.71 V to 5.5 V
– Power converter supply ( VDD): 3 V to 5.5 V
RS-485 with PROFIBUS compatibility
– Open, short, and idle bus failsafe
– 1/8 unit load: up to 256 nodes on bus
– Glitch-free power up and power down
Reinforced and Basic isolation options
High CMTI: 100-kV/µs (typical)
High ESD bus protection
– HBM: ±16 kV
– IEC 61000-4-2 contact discharge: ±8 kV
Operating temperature range: -40°C to 125°C
Current limit and thermal shutdown
20-pin wide SOIC package
•
•
Device Information
ISOW1412
ISOW1432
ISOW1412B
ISOW1432B
•
•
•
FEATURE
Protection Level
Surge Test Voltage
Isolation Rating
Working Voltage
Package(1)
Reinforced
10 kVPK
Basic
7.8 kVPK
5000 VRMS
5000 VRMS
•
•
•
1000 VRMS/1500VPK 1000 VRMS/1500VPK
DFM (20)
DFM (20)
Body Size
12.83mm x 7.5mm
12.83mm x 7.5mm
•
Section 8.6:
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
– VDE reinforced and basic insulation per DIN
VDE V 0884-11:2017-01
VCC
VIO
VISOIN
Must be connected on PCB,
not connected internally
DE
Y
D
Signal
R
Signal
Isolation
Z
RS485
RS485 Bus
B
MCU
Isolation
RE
A
GISOIN
GNDIO
VISOOUT
GND2
DC-DC
Primary
DC-DC
Secondary
VDD
GND1
Galvanic Isolation
Barrier
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
ISOW1412, ISOW1432
SLLSF86B – MAY 2018 – REVISED OCTOBER 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description Continued....................................................3
6 Device Comparison Table ..............................................3
7 Pin Configuration and Functions...................................4
8 Specifications.................................................................. 6
8.1 Absolute Maximum Ratings........................................ 6
8.2 Recommended Operating Conditions.........................7
8.3 Thermal Information....................................................7
8.4 Power Ratings.............................................................8
8.5 Insulation Specifications............................................. 9
8.6 Safety-Related Certifications.................................... 10
8.7 Safety Limiting Values...............................................10
8.8 Electrical Characteristics...........................................11
8.9 Supply Current Characteristics at VISOOUT = 3.3 V...13
8.10 Supply Current Characteristics at VISOOUT = 5 V...15
8.11 Switching Characteristics at VISOOUT = 3.3 V..........16
8.12 Switching Characteristics at VISOOUT = 5 V.............18
8.13 Insulation Characteristics Curves........................... 19
8.14 Typical Characteristics............................................20
9 Parameter Measurement Information..........................25
10 Detailed Description....................................................28
10.1 Overview.................................................................28
10.2 Power Isolation....................................................... 28
10.3 Signal Isolation........................................................28
10.4 RS-485....................................................................28
10.5 Functional Block Diagram.......................................29
10.6 Feature Description.................................................29
10.7 Device Functional Modes........................................31
10.8 Device I/O Schematics............................................34
11 Application and Implementation................................ 35
11.1 Application Information............................................35
11.2 Typical Application.................................................. 36
12 Power Supply Recommendations..............................38
13 Layout...........................................................................40
13.1 Layout Guidelines................................................... 40
13.2 Layout Example...................................................... 40
14 Device and Documentation Support..........................41
14.1 Documentation Support.......................................... 41
14.2 Receiving Notification of Documentation Updates..41
14.3 Support Resources................................................. 41
14.4 Trademarks.............................................................41
14.5 Electrostatic Discharge Caution..............................41
14.6 Glossary..................................................................41
15 Mechanical, Packaging, and Orderable
Information.................................................................... 41
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (May 2018) to Revision A (May 2021)
Page
•
Updated data sheet to include ISOW1432 device..............................................................................................1
Changes from Revision A (May 2021) to Revision B (October 2021)
Page
•
Changed ISOW1412 from Advanced Information to Production Data................................................................1
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5 Description Continued
Two options of data rates are provided: ISOW1412 is optimized for maximum 500 kbps and ISOW1432 is
suitable for maximum 12 Mbps data rate. These devices do not require any external components other than
bypass capacitors to realize an isolated RS-485 port, ideal for long distance communications. Isolation breaks
the ground loop between the communicating nodes, allowing for a much larger common mode voltage range.
Both signal and power paths are 5-kVRMS isolated per UL1577 and are qualified for reinforced and basic
isolation per VDE, TUV, CSA and CQC.
The ISOW14x2 can operate from a single supply voltage of 3 V to 5.5 V by connecting VIO and VDD together on
PCB. If lower logic levels are required, 1.71 V to 5.5 V logic supply (VIO) can be separated and independent from
the power converter supply (VDD) of 3 V to 5.5 V. These devices support a wide operating ambient temperature
range from –40°C to +125°C and are available in 20-pin DFM (SOIC-20 footprint compatible package) offering a
minimum of 8-mm creepage and clearance.
6 Device Comparison Table
Part number
Isolation
Duplex
Full
Data Rate
500 kbps
12 Mbps
Package
ISOW1412/ISOW1412B
ISOW1432/ISOW1432B
Reinforced/Basic
Reinforced/Basic
20-DFM(SOIC)
20-DFM(SOIC)
Full
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7 Pin Configuration and Functions
VIO
A
B
Z
1
2
3
20
19
18
D
DE
R
Y
4
5
6
17
16
15
RE
VISOIN
GNDIO
GISOIN
OUT
IN
7
14
EN/FLT
VDD
MODE
VISOOUT
GND2
8
13
12
11
9
GND1
10
Figure 7-1. ISOW14x2 20-pin DFM Top View
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Table 7-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
VIO
NO.
1
--
I
Side 1 logic supply
Data input
D
2
DE
3
I
Driver enable. If pin is floating, driver is disabled (internal pull-down resistor)
Received data output
R
4
O
I
RE
5
Receiver enable. If pin is floating, receiver buffer is disabled (internal pull-up resistor)
Ground connections for VIO . GNDIO and GND1 need be shorted directly on PCB.
General purpose logic output
GNDIO
OUT
6
--
O
7
Multi-function power converter enable input pin or fault output pin. Can only be used as either an
input pin or an output pin.
•
If it's used as Power converter enable input pin, it enables and disables the integrated
DC-DC power converter. Connect directly to microcontroller or through a series current
limiting resistor to use as an enable input pin. DC-DC power converted is enabled when EN
is high (connected to VIO) and disabled when low (connected to GND1). If EN is floating,
DC-DC converter is enabled (internal pull-up resistor)
EN/FLT
8
I/O
•
If it's used as Fault output pin, it gives an alert signal if power converter is not operating
properly. This pin is active low. Connect to microcontroller through a 5 kΩ or greater pull-up
resistor in order to use as a fault outpin pin.
VDD
9
--
--
Side 1 DC-DC converter power supply
GND1
10
Ground connection for VIO. GNDIO and GND1 need be shorted directly on PCB.
Ground connection for VISOOUT. GND2 and GISOIN need be shorted direclty on PCB, or
connected through a ferrite bead.
GND2
11
12
--
--
Isolated power converter output voltage. VISOOUT and VISOIN need be shorted directly on PCB, or
connected through a ferrite bead.
VISOOUT
Mode select. For RS-485 transceiver to operate at 3.3V supply, connect MODE to GND2.
For RS-485 transceiver to operate in 5V supply PROFIBUS mode, connect MODE to VISOOUT
(internal pull-down resistor)
MODE
13
I
IN
14
15
I
General purpose logic input
Ground connections for VISOIN. GND2 and GISOIN need be shorted direclty on PCB, or
connected through a ferrite bead.
GISOIN
--
Side 2 supply voltage for RS485. VISOOUT and VISOIN need be shorted directly on PCB, or
connected through a ferrite bead.
VISOIN
16
--
Y
Z
B
A
17
18
19
20
O
O
I
RS-485 driver non-inverting output
RS-485 driver inverting output
RS-485 receiver inverting input
RS-485 receiver non-inverting input
I
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
–0.5
–0.5
MAX
UNIT
V
VDD
Power converter supply voltage
6
6
VISOIN
Isolated supply voltage, input supply for RS-485 transceiver
V
Isolated supply voltage, Power converter output at RS485 mode (MODE =
GND2)
VISOOUT
VISOOUT
–0.5
–0.5
4
6
V
V
Isolated supply voltage, Power converter output at Profibus mode (MODE
= VISOOUT
)
VIO
Logic supply voltage
–0.5
–12
–0.5
-0.5
-0.5
–15
–40
–65
6
15
V
V
VBUS
Voltage on bus pins (A, B, Y, Z with respect to GND2)
Logic I/O voltage level (D, DE, RE, R, EN, OUT)
VIO + 0.5(3)
VISOIN + 0.5
VISOOUT + 0.5
15
V
VLOGIC_IO IN
MODE
V
V
IO
Output current on R and OUT pins
Junction temperature
mA
°C
°C
TJ
150
Tstg
Storage temperature
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the deviceat these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground pin (GND1 or GND2). All voltage values
except differential I/O bus voltages are peak voltage values.
(3) The maximum voltage must not be greater than 6 V.
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8.2 Recommended Operating Conditions
MIN
1.71
2.25
3
NOM
MAX
1.89
5.5
UNIT
1.8-V operation
VIO
Logic supply voltage
V
2.5-V, 3.3-V, and 5-V operation
VDD
Power converter supply voltage
5.5
V
V
VDD(UVLO+) Positive threshold when power converter supply is rising
VDD(UVLO-) Positive threshold when power converter supply is falling
VHYS1(UVLO) Power converter supply voltage hysteresis
2.8
2.55
0.25
2.93
2.40
0.15
V
V
VIO(UVLO+)
VIO(UVLO-)
Rising threshold of logic supply voltage
Falling threshold of logic supply voltage
1.7
V
1
75
V
VHYS2(UVLO) Logic supply voltage hysteresis
VBUS Input voltage at any bus terminal (seperately w.r.t GND2 or common mode)
125
mV
V
–7
12
High-level input voltage (D, DE, EN, and RE inputs)
High- level input voltage (IN input)
0.7 × VIO
VIO
V
VIH
0.7 ×
VISOIN
VISOIN
V
V
V
Low-level input voltage (D, DE, EN, and RE inputs)
Low- level input voltage (IN input)
0
0
0.3 × VIO
VIL
0.3 ×
VISOIN
VID
Differential input voltage (receiver terminals A w.r.t B)
Output current, driver (Y, Z)
–12
–60
–4
12
60
4
V
IO(DRV)
mA
mA
mA
VIO = 4.5 to 5.5 V
VIO = 3 to 3.6 V
-2
2
IO
Output current, R and OUT pins
VIO = 2.25 to 2.75 V, 1.71 to 1.89
V
-1
1
mA
RL
Differential load resistance on bus
Signaling rate
54
Ω
1/tUI
1/tUI
DR
ISOW1412
ISOW1432
500
12
2
kbps
Mbps
Mbps
Signaling rate
Data rate for GPIO channel
Power up time after applying input
supply(Isolated output supply reaches
90% of setpoint and data transmission can
start after this)
tpwrup
5
ms
Ambient operating temperature (MODE= GND2), no extra current availalbe on
VISOUT
–40
–40
–40
–40
–40
125
105
125
105
85
°C
°C
°C
°C
°C
(1)
Ambient operating temperature (MODE= GND2), 20 mA extra current available
(1)
on VISOUT
Ambient operating temperature (MODE= VISOOUT), 50% duty cycle on DE, no
TA
(1)
extra current available on VISOUT
Ambient operating temperature (MODE= VISOOUT), no extra current available
(1)
on VISOUT
Ambient operating temperature (MODE= VISOOUT), 20 mA extra current
(1)
available on VISOUT
(1) Extra current is only available at VDD=5 V ± 10% mode
8.3 Thermal Information
ISOW14x2
THERMAL METRIC(1)
DFM
20 PINS
68.5
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
RθJC(top)
20.9
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UNIT
SLLSF86B – MAY 2018 – REVISED OCTOBER 2021
ISOW14x2
DFM
20 PINS
44.8
THERMAL METRIC(1)
RθJB
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
13
ΨJB
44
RθJC(bot)
--
(1) For more informationabout traditional and new thermal metrics, see theSemiconductor andIC Package Thermal Metrics application
report.
8.4 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1060
490
UNIT
mW
PD
Maximum power dissipation (both sides)
Maximum power dissipation (side-1)
VDD = VIO = 5.5V, MODE = VISOOUT, TJ = 150°C,
Y-Z load = 54Ω||50pF, Y shorted to A, Z shorted
to B(loopback), Load on R = 15pF, Input a 250kHz
PD1
mW
50% duty cycle square wave to D pin with VDE
VIO, VRE = GND1, ISOW1412
=
PD2
Maximum power dissipation by (side-2)
570
mW
PD
Maximum power dissipation (both sides)
Maximum power dissipation (side-1)
VDD= VIO= 5.5V, MODE= VISOOUT, TJ=150°C, Y-Z
load= 54Ω||50pF, Y shorted to A, Z shorted to
B(loopback), Load on R=15pF, Input a 6MHz 50%
1110
510
mW
mW
PD1
duty cycle square wave to D pin with VDE=VIO
VRE=GND1, ISOW1432
,
PD2
Maximum power dissipation by (side-2)
610
mW
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8.5 Insulation Specifications
PARAMETER
TEST CONDITIONS
VALUE
UNIT
GENERAL
CLR
CPG
External clearance(1)
External creepage(1)
Shortest terminal-to-terminal distance through air
> 8
> 8
mm
mm
Shortest terminal-to-terminal distance across the package
surface
Minimum internal gap (internal clearance – capacitive
signal isolation)
> 17
DTI
CTI
Distance through the insulation
um
V
Minimum internal gap (internal clearance- transformer
power isolation)
> 120
Comparative tracking index
Material group
DIN EN 60112 (VDE 0303-11); IEC 60112
According to IEC 60664-1
> 600
I
Rated mains voltage ≤ 150 VRMS
Rated mains voltage ≤ 300 VRMS
Rated mains voltage ≤ 600 VRMS
Rated mains voltage ≤ 1000 VRMS
I-IV
I-IV
I-IV
I-III
Overvoltage category per IEC 60664-1
DIN VDE V 0884-11:2017-01(2)
VIORM Maximum repetitive peak isolation voltage
AC voltage (bipolar)
1500
1000
1500
7071
VPK
VRMS
VDC
AC voltage (sine wave) Time dependent dielectric
breakdown (TDDB) test
VIOWM
Maximum working isolation voltage
DC voltage
VTEST = VIOTM, t = 60 s (qualification);
VTEST = 1.2 × VIOTM, t = 1 s (100% production)
VIOTM
VIOSM
VIOSM
Maximum transient isolation voltage
VPK
Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 10 kVPK (qualification)
Maximum surge isolation voltage ISOW14x2(3)
Maximum surge isolation voltage ISOW14x2B(3)
6250
6000
VPK
VPK
Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.3 × VIOSM = 7.8 kVPK (qualification)
Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM , tm = 10 s
≤ 5
≤ 5
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
ISOW14x2: Vpd(m) = 1.6 × VIORM , tm = 10 s. ISOW14x2B:
Vpd(m) = 1.2 × VIORM , tm = 10 s
qpd
Apparent charge(4)
pC
Method b1: At routine test (100% production) and
preconditioning (type test)
Vini = 1.2 × VIOTM, tini = 1 s;
≤ 5
ISOW14x2: Vpd(m) = 1.875 × VIORM , tm = 1 s. ISOW14x2B:
Vpd(m) = 1.5 × VIORM , tm = 1 s
CIO
RIO
Barrier capacitance, input to output(5)
Isolation resistance, input to output(5)
VIO = 0.4 sin (2πft), f = 1 MHz
VIO = 500 V, TA = 25°C
~3.5
> 1012
> 1011
> 109
pF
Ω
VIO = 500 V, 100°C ≤ TA ≤ 125°C
VIO = 500 V at TS = 150°C
Ω
Ω
Pollution degree
Climatic category
2
40/125/21
UL 1577
VTEST = VISO = 5000 VRMS, t = 60 s (qualification); VTEST
1.2 × VISO = 6000 VRMS, t = 1 s (100% production)
=
VISO
Withstand isolation voltage
5000
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become
equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these
specifications.
(2) ISOW14x2 is suitable for safe electrical insulation and ISOW14x2B is suitable for basic electrical insulation only within the safety
ratings.. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-terminal device
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8.6 Safety-Related Certifications
VDE
CSA
UL
TUV
CQC
Certified according to IEC
62368-1, IEC 61010-1 and
IEC 60601-1
Certified under UL 1577
Component Recognition
Program
Certified ccording to EN
61010-1:2010/ A1:2019 and
EN 62368-1:2014
Certified according to DIN
VDE V 0884-11 :2017-01
Plan to certify according to
GB4943.1-2011
Per CSA62368-1:19, IEC
62368-1:2018 Ed. 3,
CSA 61010-1-12+A1 and
IEC 61010-1 3rd Ed.,
ISOW14x2 (Reinforced): 600
VRMS, ISOW14x2B (Basic):
1000 VRMS maximum
working voltage (pollution
degree 2, material group I,
ambient temperature 90 ℃),
2 MOPP (Means of
Patient Protection) per CSA
60601- 1:14 . IEC 60601-1
(ISOW14x2 only) Ed.3+A1,
250 VRMS maximum working
voltage
Maximum transient isolation
ISOW14x2 (Reinforced):
5000 VRMS reinforced
insulation per EN
61010-1:2010/A1:2019 and
EN 62368-1:2014 up to
working voltage of 600
VRMS . ISOW14x2B (Basic):
1000 VRMS
voltage 7071 VPK
;
Maximum repetitive peak
isolation voltage, 1500
VPK; Maximum surge
isolation voltage, ISOW14x2:
6250 VPK (Reinforced),
ISOW14x2B:
Reinforced insulation, Altitude ≤
5000 m, Tropical Climate, 700
VRMS maximum working voltage.
Single protection, 5000 VRMS
6000 VPK (Basic)
Certification number:
40040142. ISOW1432
planned
Certificate number:
CQC21001297517. ISOW1432
planned
Master Contract Number:
220991. ISOW1432 planned ISOW1432 planned
File number: E181974.
Client ID number: 77311.
ISOW1432 planned
8.7 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RθJA = 68.5°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C , See
Figure 8-1
332
IS
Safety input, output, or supply current(1)
mA
RθJA = 68.5°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C , See
Figure 8-1
507
PS
TS
Safety input, output, or total power(1)
Safety temperature(1)
RθJA = 68.5°C/W, TJ = 150°C, TA = 25°C , See Figure 8-2
1826
150
mW
°C
(1) The maximum safety temperature,TS, has the same value as the maximum junction temperature,TJ, specified for the device. The
IS and PS parameters represent the safety current and safety power respectively.The maximum limits of IS and PS should not
beexceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board
forleaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA +RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
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8.8 Electrical Characteristics
Over recommended operating conditions, typical values are at VDD = VIO = 3.3 V and TA =25°C, GND1 = GNDIO, GND2 =
GISOIN (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Device
MODE=GND2, DE=GND1, D, RE and IN
floating
Isolated output supply voltage
Isolated output supply voltage
3.135
4.75
3.3V
5
3.465
5.25
V
V
V
V
V
V
VISOOUT
MODE=VISOOUT, DE=GND1, D, RE and IN
floating
Output high voltage on OUT
pin
VIO = 5 V ± 10%, IOH = –4 mA, IN=VISOIN
VIO = 3.3 V ± 10% , IOH = –2 mA, IN=VISOIN
VIO = 2.5 V ± 10% , IOH = –1 mA, IN=VISOIN
VIO = 1.8 V ± 5%, IOH = –1 mA, IN=VISOIN
VIO – 0.4
VIO – 0.3
VIO – 0.2
VIO – 0.2
Output high voltage on OUT
pin
VOH
Output high voltage on OUT
pin
Output high voltage on OUT
pin
Output low voltage on OUT pin VIO = 5 V ± 10%, IOL = 4 mA, IN=GND2
Output low voltage on OUT pin VIO = 3.3 V ± 10% , IOL = 2 mA, IN=GND2
Output low voltage on OUT pin VIO = 2.5 V ± 10%, IOL = 1 mA, IN=GND2
Output low voltage on OUT pin VIO = 1.8 V ± 5%, IOL = 1 mA, IN=GND2
0.4
0.3
0.2
0.2
25
V
V
VOL
V
V
II
II
Input current, IN
Input current, EN
IN at 0 V or VISOIN
EN at 0 V or VIO
–25
–25
µA
µA
25
High-level common-mode
transient immunity
Driver and receiver path, VCM = 1000 V, see
Figure 9-4
|CMH|
100
100
kV/µs
kV/µs
Low-level common-mode
transient immunity
Driver and receiver path, VCM = 1000 V, see
Figure 9-4
|CML|
Driver
Unloaded bus, VDD = 3 V to 3.6 V with
MODE=GND2, or 4.5 V to 5.5 V with
MODE= VISOOUT
1.5
VISOIN
RL = 60 Ω, –7 V ≤ VTEST ≤ 12 V (see Figure
9-1), VDD = 3 V to 3.6 V, MODE = GND2
1.5
2
VISOIN
VISOIN
VISOIN
VISOIN
Differential output voltage
magnitude
|VOD
|
V
RL = 100 Ω (see Figure 9-2) (RS-422
load), VDD = 3 V to 3.6 V, MODE = GND2
RL = 54 Ω (see Figure 9-2) (RS-485 load),
VDD = 3 V to 3.6 V, MODE = GND2
1.5
2.1
Differential output voltage
magnitude
RL = 54 Ω, VDD = 4.5 V to 5.5 V, MODE =
VISOOUT , see Figure 9-2
|VOD
|VOD
|VOD
|
|
|
V
V
V
RL = 100 Ω (see Figure 9-2) (RS-422
load), VDD = 4.5 V to 5.5 V, MODE =
VISOOUT
Differential output voltage
magnitude
2.1
VISOIN
Differential output voltage
magnitude
RL = 60 Ω, –7 V ≤ VTEST ≤ 12 V (see Figure
9-1), VDD = 4.5 V to 5.5V, MODE = VISOOUT
2.1
VISOIN
Change in differential output
voltage between the two states
Δ|VOD
|
RL = 54 Ω or 100 Ω (see Figure 9-2)
–200
200
3
mV
V
VOC
Common-mode output voltage RL = 54 Ω or 100 Ω (see Figure 9-2)
Change in steady-state
ΔVOC(SS) common-mode output voltage RL = 54 Ω or 100 Ω (see Figure 9-2)
between the two states
1 0.5 × VISOIN
–200
200
mV
Peak-to-peak common mode
output voltage
RL = 54 Ω or 100 Ω,
VISOIN=VISOOUT=3.3V, see Figure 9-2
VOC(PP)
IOS
400
180
mV
mA
VDE = VIO, VD=VIO or GND1, –7 V ≤ Y or Z ≤
12 V, or Y shorted to Z, see Figure 9-10
Short-circuit output current
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Over recommended operating conditions, typical values are at VDD = VIO = 3.3 V and TA =25°C, GND1 = GNDIO, GND2 =
GISOIN (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
II
Input current , D, DE
VD, VDE at 0 V or VIO
–25
25
µA
Receiver
VDE = 0 V, VISOIN = 0 V or 3.3 V or 5V,
ISOW1412 or ISOW1432, VA or VB = –7 V to
12 V, other input at 0 V
II1
Bus input current
–100
125
µA
Positive-going input-threshold
voltage
VTH+
–7 V ≤ VCM ≤ 12 V
–7 V ≤ VCM ≤ 12 V
See(1)
–200
–78
–20
mV
Negative-going input-threshold
voltage
VTH–
Vhys
–141
63
See(1)
mV
mV
Input hysteresis (VTH+ – VTH–
)
–7 V ≤ VCM ≤ 12 V
40
VIO = 5 V ± 10%, IOH = –4 mA, VID ≥ 200 mV
VIO – 0.4
VIO = 3.3 V ± 10%, IOH = –2 mA, VID ≥ 200
mV
VIO – 0.3
VOH
Output high voltage on R pin
V
V
VIO = 2.5 V ± 10% , IOH = –1 mA, VID ≥ 200
mV
VIO – 0.2
VIO – 0.2
VIO = 1.8 V ± 5%, IOH = –1 mA, VID ≥ 200 mV
VIO = 5 V ± 10%, IOL = 4 mA, VID ≤ –200 mV
0.4
0.3
VIO = 3.3 V ± 10%, IOL = 2 mA, VID ≤ –200
mV
VOL
Output low voltage on R pin
VIO = 2.5 V ± 10% , IOL = 1 mA, VID ≤ –200
mV
0.2
0.2
1
VIO = 1.8 V ± 5%, IOL = 1 mA, VID ≤ –200 mV
VR = 0 V or VIO, VRE = VIO
Output high-impedance current
on R pin
IOZ
–1
µA
µA
II(RE)
Input current on RE pin
VRE at 0 V or VIO
–25
25
(1) The VTH+ voltage is specified to be greater than the VTH– voltage by at least the Vhys voltage under any specific conditions.
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8.9 Supply Current Characteristics at VISOOUT = 3.3 V
over recommended operating conditions, VDD = VIO = 3 to 5.5 V, MODE=GND2, GND1 = GNDIO, GND2 = GISOIN (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power converter disabled
Power converter supply
current
IDD
IIO
EN=GND1, D, DE, RE floating
EN=GND1, D, DE, RE floating
0.23
0.24
0.45
0.55
mA
mA
Logic supply current
Power converter supply current: Driver enabled, receiver disabled
VDE = VIO, VRE = VIO, bus load = 120 Ω, VD= VIO, VDD
56
69
62
69
90
76
84
111
64
69
90
79
84
113
77
109
86
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
= 5 V ± 10%, A and B floating
Power converter supply
current
IDD
VDE = VIO, VRE = VIO, bus load = 120 Ω, VD= VIO, VDD
= 3.3 V ± 10%, A and B floating
VDE = VIO, VRE = VIO, bus load = 120 Ω || 50 pF, D =
500-kbps square wave 50% duty, VDD = 5 V ± 10%
VDE = VIO, VRE = VIO, bus load = 100 Ω || 50 pF, D =
500-kbps square wave 50% duty, VDD = 5 V ± 10%
88
VDE = VIO, VRE = VIO, bus load = 54 Ω || 50 pF, D =
500-kbps square wave 50% duty, VDD = 5 V ± 10%
122
131
131
158
87
Power converter supply
current, ISOW1412
IDD
VDE = VIO, VRE = VIO, bus load = 120 Ω || 50 pF, D =
500-kbps square wave 50% duty, VDD = 3.3 V ± 10%
VDE = VIO, VRE = VIO, bus load = 100 Ω || 50 pF, D =
500-kbps square wave 50% duty, VDD = 3.3 V ± 10%
VDE = VIO, VRE = VIO, bus load = 54 Ω || 50 pF, D =
500-kbps square wave 50% duty, VDD = 3.3 V ± 10%
VDE = VIO, VRE = VIO, bus load = 120 Ω || 50 pF, D =
12-Mbps square wave 50% duty, VDD = 5 V ± 10%
VDE = VIO, VRE = VIO, bus load = 100 Ω || 50 pF, D =
12-Mbps square wave 50% duty, VDD = 5 V ± 10%
94
VDE = VIO, VRE = VIO, bus load = 54 Ω || 50 pF, D =
12-Mbps square wave 50% duty, VDD = 5 V ± 10%
117
129
135
156
Power converter supply
current, ISOW1432
IDD
VDE= VIO, VRE = VIO, bus load = 120 Ω || 50 pF, D =
12-Mbps square wave 50% duty, VDD = 3.3 V ± 10%
VDE= VIO, VRE = VIO, bus load = 100 Ω || 50 pF, D =
12-Mbps square wave 50% duty, VDD = 3.3 V ± 10%
VDE = VIO, VRE = VIO, bus load = 54 Ω || 50 pF, D =
12-Mbps square wave 50% duty, VDD = 3.3 V ± 10%
Power converter supply current: Driver disabled, receiver enabled
VDE = VGND1, VRE= VGND1, Y and Z bus loaded and
unloaded, A-B = square wave 500-kbps 50% duty VD=
VGND1, VDD = 5 V ± 10%, CL on R = 15 pF
16
18
15
17
28
30
24
27
Power converter supply
current, ISOW1412
IDD
mA
mA
VDE = VGND1, VRE= VGND1, Y and Z bus loaded and
unloaded, A-B = square wave 500-kbps 50% duty VD=
VGND1, VDD = 3.3 V ± 10%, CL on R = 15 pF
VDE = VGND1, VRE= VGND1, Y and Z bus loaded and
unloaded, A-B = square wave 12-Mbps 50% duty VD=
VGND1, VDD = 5 V ± 10%, CL on R = 15 pF
Power converter supply
current, ISOW1432
IDD
VDE = VGND1, VRE= VGND1, Y and Z bus loaded and
unloaded, A-B = square wave 12-Mbps 50% duty VD=
VGND1, VDD = 3.3 V ± 10%, CL on R = 15 pF
Power converter supply current: Driver enabled, receiver enabled
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over recommended operating conditions, VDD = VIO = 3 to 5.5 V, MODE=GND2, GND1 = GNDIO, GND2 = GISOIN (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDE = VIO, VRE= VGND1, Y and Z bus load = 120 Ω || 50
pF, loopback(1), D = 500-kbps 50% duty, VDD = 5 V ±
10%, CL on R = 15 pF
63
102
Power converter supply
current, ISOW1412
IDD
mA
VDE = VIO, VRE= VGND1, Y and Z bus load = 120 Ω || 50
pF, loopback(1), D = 500-kbps 50% duty, VDD = 3.3 V ±
10%, CL on R = 15 pF
77
66
84
129
91
VDE = VIO, VRE= VGND1, Y and Z bus load = 120 Ω ||
50 pF, loopback(1), D = 12-Mbps 50% duty, VDD = 5 V ±
10%, CL on R = 15 pF
Power converter supply
current, ISOW1432
IDD
mA
VDE = VIO, VRE= VGND1, Y and Z bus load = 120 Ω || 50
pF, loopback(1), D = 12-Mbps 50% duty, VDD = 3.3 V ±
10%, CL on R = 15 pF
136
Logic supply current: Driver disabled, receiver disabled
IIO Logic supply current VDE = VGND1, VRE = VIO , VD = VIO, VIO= 3.3 V ± 10%
Logic supply current: Driver enabled, Receiver enabled, static
3.2
4
6.0
6.8
mA
mA
VDE = VIO, VRE= VGND1, VD = VIO, loopback(1), VIO= 3.3
V ± 10%
IIO
Logic supply current
Logic supply current: Driver enabled, receiver enabled, dynamic
Logic supply current,
ISOW1412
VDE = VIO, VRE= VGND1, D = 500-kbps 50% duty
IIO
IIO
4.6
4.6
7.2
7.2
mA
mA
square wave, loopback(1), VIO = 3.3 V ± 10%
Logic supply current,
ISOW1432
VDE = VIO, VRE = VGND1 , D = 12-Mbps 50% duty
square wave, loopback(1), VIO = 3.3 V ± 10%
(1) The output of the driver is connected to the input of a receiverin a loopback mode.
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8.10 Supply Current Characteristics at VISOOUT = 5 V
over recommended operating conditions, VDD = VIO = 4.5 V to 5.5 V, MODE=VISOOUT , GND1 = GNDIO, GND2 = GISOIN
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power converter disabled
Power converter supply
current
IDD
IIO
EN=GND1, D, DE, RE floating
EN=GND1, D, DE, RE floating
0.23
0.24
0.45
0.55
mA
mA
Logic supply current
Power converter supply current: Driver enabled, receiver disabled
Power converter supply
current
VDE = VIO, VRE = VIO, bus load = 120 Ω, VD= VIO, VDD
= 5 V ± 10%, A and B floating
IDD
97
123
175
77
160
205
292
108
214
mA
mA
mA
mA
mA
VDE = VIO, VRE = VIO, bus load = 120 Ω || 50 pF, D =
500-kbps square wave 50% duty, VDD = 5 V ± 10%
Power converter supply
current, ISOW1412
IDD
VDE = VIO, VRE = VIO, bus load = 54 Ω || 50 pF, D =
500-kbps square wave 50% duty, VDD = 5 V ± 10%
VDE = VIO, VRE = VIO, bus load = 120 Ω || 50 pF, D =
12-Mbps square wave 50% duty, VDD = 5 V ± 10%
Power converter supply
current, ISOW1432
IDD
VDE = VIO, VRE = VIO, bus load = 54 Ω || 50 pF, D =
12-Mbps square wave 50% duty, VDD = 5 V ± 10%
164
Power converter supply current: Driver disabled, receiver enabled
VDE= VGND1, VRE= VGND1, Y and Z bus loaded and
unloaded, A-B = square wave 500-kbps 50% duty VD=
VIO, VDD= 5 V ± 10%, CL on R = 15 pF
Power converter supply
current
IDD
17
19
31
26
mA
mA
VDE= VGND1, VRE= VGND1, Y and Z bus loaded and
unloaded, A-B = square wave 12-Mbps 50% duty
(ISOW1432) VD= VIO, VDD= 5 V ± 10%, CL on R =
15 pF
Power converter supply
current
IDD
Power converter supply current: Driver enabled, receiver enabled
VDE = VIO, VRE= VGND1, Y and Z bus load = 120 Ω || 50
Power converter supply
current, ISOW1412
IDD
pF, loopback(1), D = 500-kbps 50% duty, VDD = 5 V ±
10%, CL on R = 15 pF
123
112
207
135
mA
mA
VDE = VIO, VRE= VGND1, Y and Z bus load = 120 Ω ||
50 pF, loopback(1), D = 12-Mbps 50% duty, VDD = 5 V ±
10%, CL on R = 15 pF
Power converter supply
current, ISOW1432
IDD
(1) The output of the driver is connected to the input of a receiverin a loopback mode.
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8.11 Switching Characteristics at VISOOUT = 3.3 V
Min / Max specifications are over recommended operating conditions, typical values are at VDD = VIO = 3.3 V, MODE=GND2
( VISOOUT= 3.3V), GND1 = GNDIO, GND2 = GISOIN, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Driver: 500-kbps device (ISOW1412)
tr, tf
Differential output rise time and fall time
RL = 54 Ω, CL = 50 pF, see Figure 9-3
RL = 54 Ω, CL = 50 pF, see Figure 9-3
RL = 54 Ω, CL = 50 pF, see Figure 9-3
See Figure 9-5 and Figure 9-6
190
300
450
3
600
610
40
ns
ns
ns
ns
ns
tPHL, tPLH Propagation delay
PWD
Pulse width distortion(1), |tPHL - tPLH
|
tPHZ, tPLZ Disable time
tPZH, tPZL Enable time
Receiver: 500-kbps device (ISOW1412)
56
200
600
See Figure 9-5 and Figure 9-6
280
tr, tf
Output rise time and fall time
CL = 15 pF, see Figure 9-7
CL = 15 pF, see Figure 9-7
CL = 15 pF, see Figure 9-7
See Figure 9-8 and Figure 9-9
See Figure 9-8 and Figure 9-9
4
135
15
ns
ns
ns
ns
ns
tPHL, tPLH Propagation delay
60
2
PWD
Pulse width distortion(1), |tPHL - tPLH
|
tPHZ, tPLZ Disable time
tPZH, tPZL Enable time
Driver: 12-Mbps device (ISOW1432)
9
30
8
30
tr, tf
tPHL
tPLH
Differential output rise time and fall time
Propagation delay
RL = 54 Ω, CL = 50 pF, see Figure 9-3
RL = 54 Ω, CL = 50 pF, see Figure 9-3
RL = 54 Ω, CL = 50 pF, see Figure 9-3
RL = 54 Ω, CL = 50 pF, see Figure 9-3
RL = 54 Ω, CL = 50 pF, see Figure 9-3
See Figure 9-5 and Figure 9-6
6
15
49
49
52
1
25
125
125
125
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Propagation delay
tPHL, tPLH Propagation delay
PWD
tPHZ
tPLZ
Pulse width distortion(1), |tPHL - tPLH
|
Disable time
Disable time
35
35
36
46
36
48
125
125
125
150
150
150
See Figure 9-5 and Figure 9-6
tPHZ, tPLZ Disable time
See Figure 9-5 and Figure 9-6
tPZH
tPZL
Enable time
Enable time
See Figure 9-5 and Figure 9-6
See Figure 9-5 and Figure 9-6
tPZH, tPZL Enable time
See Figure 9-5 and Figure 9-6
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Min / Max specifications are over recommended operating conditions, typical values are at VDD = VIO = 3.3 V, MODE=GND2
( VISOOUT= 3.3V), GND1 = GNDIO, GND2 = GISOIN, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Receiver: 12-Mbps device (ISOW1432)
tr, tf
tPHL
tPLH
Output rise time and fall time
Propagation delay
CL = 15 pF, see Figure 9-7
CL = 15 pF, see Figure 9-7
CL = 15 pF, see Figure 9-7
CL = 15 pF, see Figure 9-7
CL = 15 pF, see Figure 9-7
See Figure 9-8 and Figure 9-9
See Figure 9-8 and Figure 9-9
See Figure 9-8 and Figure 9-9
See Figure 9-8 and Figure 9-9
See Figure 9-8 and Figure 9-9
See Figure 9-8 and Figure 9-9
4
120
120
120
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
59
59
42
1.7
7
Propagation delay
tPHL, tPLH Propagation delay
PWD
tPHZ
tPLZ
Pulse width distortion(1), |tPHL - tPLH
|
Disable time
Disable time
30
6
30
tPHZ, tPLZ Disable time
9
30
tPZH
tPZL
Enable time
Enable time
6
30
5
30
tPZH, tPZL Enable time
GPIO channel
8
30
tPHL, tPLH Propagation delay time
227
20
1
347
110
4
ns
ns
ns
ns
PWD
Pulse width distortion, |tPHL - tPLH|
See Figure 9-11
tr
tf
Output signal rise time
Output signal fall time
1
4
(1) Also known as pulse skew.
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8.12 Switching Characteristics at VISOOUT = 5 V
Min / Max specifications are over recommended operating conditions, typical values are at VDD = VIO = 5 V, MODE=VISOOUT
( VISOOUT= 5 V), GND1 = GNDIO, GND2 = GISOIN, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Driver: 500-kbps device (ISOW1412)
tr, tf
Differential output rise time and fall time
RL = 54 Ω, CL = 50 pF, see Figure 9-3
RL = 54 Ω, CL = 50 pF, see Figure 9-3
RL = 54 Ω, CL = 50 pF, see Figure 9-3
See Figure 9-5 and Figure 9-6
200
300
400
2
600
610
40
ns
ns
ns
ns
ns
tPHL, tPLH Propagation delay
PWD
Pulse width distortion(1), |tPHL – tPLH
|
tPHZ, tPLZ Disable time
tPZH, tPZL Enable time
Receiver: 500-kbps device (ISOW1412)
30
200
600
See Figure 9-5 and Figure 9-6
115
tr, tf
Output rise time and fall time
CL = 15 pF, see Figure 9-7
CL = 15 pF, see Figure 9-7
CL = 15 pF, see Figure 9-7
See Figure 9-8 and Figure 9-9
See Figure 9-8 and Figure 9-9
4
135
20
ns
ns
ns
ns
ns
tPHL, tPLH Propagation delay
49
2
PWD
Pulse width distortion(1), |tPHL – tPLH
|
tPHZ, tPLZ Disable time
tPZH, tPZL Enable time
Driver: 12-Mbps device (ISOW1432)
8
30
7
30
tr, tf
tPHL
tPLH
Differential output rise time and fall time
Propagation delay
RL = 54 Ω, CL = 50 pF, see Figure 9-3
RL = 54 Ω, CL = 50 pF, see Figure 9-3
RL = 54 Ω, CL = 50 pF, see Figure 9-3
RL = 54 Ω, CL = 50 pF, see Figure 9-3
RL = 54 Ω, CL = 50 pF, see Figure 9-3
See Figure 9-5 and Figure 9-6
7
15
40
40
40
2
25
125
125
125
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Propagation delay
tPHL, tPLH Propagation delay
PWD
tPHZ
tPLZ
Pulse width distortion(1), |tPHL – tPLH
|
Disable time
Disable time
30
30
28
34
25
33
125
125
125
150
150
150
See Figure 9-5 and Figure 9-6
tPHZ, tPLZ Disable time
See Figure 9-5 and Figure 9-6
tPZH
tPZL
Enable time
Enable time
See Figure 9-5 and Figure 9-6
See Figure 9-5 and Figure 9-6
tPZH, tPZL Enable time
See Figure 9-5 and Figure 9-6
Receiver: 12-Mbps device (ISOW1432)
tr, tf
tPHL
tPLH
Output rise time and fall time
Propagation delay
CL = 15 pF, see Figure 9-7
CL = 15 pF, see Figure 9-7
CL = 15 pF, see Figure 9-7
CL = 15 pF, see Figure 9-7
CL = 15 pF, see Figure 9-7
See Figure 9-8 and Figure 9-9
See Figure 9-8 and Figure 9-9
See Figure 9-8 and Figure 9-9
See Figure 9-8 and Figure 9-9
See Figure 9-8 and Figure 9-9
See Figure 9-8 and Figure 9-9
6
120
120
120
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
55
52
2.5
5
Propagation delay
tPHL, tPLH Propagation delay
PWD
tPHZ
tPLZ
Pulse width distortion(1), |tPHL – tPLH
|
Disable time
Disable time
30
5
30
tPHZ, tPLZ Disable time
8
30
tPZH
tPZL
Enable time
Enable time
4
30
4
30
tPZH, tPZL Enable time
GPIO channel
7
30
tPHL, tPLH Propagation delay time
227
20
347
110
4
ns
ns
ns
ns
PWD
Pulse width distortion, |tPHL - tPLH|
See Figure 9-11
tr
tf
Output signal rise time
Output signal fall time
2.2
2.2
4
(1) Also known as pulse skew.
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8.13 Insulation Characteristics Curves
600
2000
1800
1600
1400
1200
1000
800
VI = 5.5 V
VI = 3.6 V
500
400
300
200
100
0
600
400
200
0
0
50
100
Ambient Temperature (èC)
150
200
0
50
100
Ambient Temperature (èC)
150
200
D001
D002
Figure 8-1. Thermal Derating Curve for Limiting
Current per VDE
Figure 8-2. Thermal Derating Curve for Limiting
Power per VDE
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8.14 Typical Characteristics
120
100
80
60
40
20
0
5.2
5.1
5
Open Load
54 Load
120 Load
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.2
Open Load
54 Load
120 Load
100
150
200
250
300
350
400
450
500
100
150
200
250
300
350
400
450
500
Data Rate (kbps)
VDD = 3.3 V
DE = VIO
Data Rate (kbps)
VDD = 3.3 V
DE = VIO
MODE = GND2
TA = 25°C
RE = GND1
MODE = GND2
TA = 25°C
RE = GND1
Figure 8-3. ISOW1412 VDD Supply Current vs. Data
Rate - RS485 Mode
Figure 8-4. ISOW1412 VIO Supply Current vs. Data
Rate - RS485 Mode
120
6
Open Load
54 Load
120 Load
Open Load
54 Load
120 Load
110
100
5.5
5
90
80
70
60
50
40
30
20
4.5
4
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Tempearture (C)
Tempearture (C)
MODE = GND2
DE = VIO
VDD = 3.3 V
RE = GND1
MODE = GND2
DE = VIO
VDD = 3.3 V
RE = GND1
Figure 8-5. ISOW1412 VDD Current vs.
Temperature - RS485 Mode
Figure 8-6. ISOW1412 VIO Current vs. Temperature
- RS485 Mode
440
390
tPLH
tPHL
tPLH
tPHL
435
430
425
420
415
410
405
400
380
370
360
350
-40 -25 -10
5
20 35 50 65 80 95 110 125
-45 -30 -15
0
15 30 45 60 75 90 105 120
Temperature (C)
Temperature (C)
MODE = GND2
VDD = 3.3 V
LOAD = 54 Ω ||
50pF
MODE = VISOOUT
VDD = 5 V
LOAD = 54 Ω ||
50pF
DE = VIO
DE = VIO
Figure 8-7. ISOW1412 Driver Propagation Delay vs.
Temperature - RS485 Mode
Figure 8-8. ISOW1412 Driver Propagation Delay vs.
Temperature - Profibus Mode
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80
70
65
60
55
50
tPLH
tPHL
tPLH
tPHL
75
70
65
60
55
50
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (C)
Temperature (C)
MODE = GND2
LOAD = 54 Ω ||
50pF
VDD = 3.3 V
RE = GND1
MODE = VISOOUT
LOAD = 54 Ω ||
50pF
VDD = 5 V
RE = GND1
Figure 8-9. ISOW1412 Receiver Propagation Delay Figure 8-10. ISOW1412 Receiver Propagation Delay
vs. Temperature - RS485 Mode vs. Temperature - Profibus Mode
MODE = GND2
LOAD = 54 Ω ||
50pF
VDD = 3.3 V
TA = 25°C
DE = VIO
MODE = VISOOUT
VDD = 5 V
TA = 25°C
DE = VIO
LOAD = 54 Ω || 50pF
Figure 8-12. ISOW1412 Driver Propagation Delay -
RS485 Mode
Figure 8-11. ISOW1412 Driver Propagation Delay -
Profibus Mode
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MODE = VISOOUT
LOAD = 54 Ω ||
50pF
VDD = 5 V
TA = 25°C
RE = GND1
MODE = GND2
VDD = 3.3 V
TA = 25°C
RE = GND1
LOAD = 54 Ω || 50pF
Figure 8-14. Receiver Propagation Delay - RS485
Mode
Figure 8-13. ISOW1412 Receiver Propagation Delay
- Profibus Mode
3.5
5
4.5
4
VOH
VOL
3
2.5
2
3.5
3
2.5
2
VOH
VOL
1.5
1
1.5
1
0.5
0
0.5
0
0
10
20
30
40
50
60
0
10
20
30
40
50
60
DE = VIO
Driver Output Current (mA)
Driver Output Current (mA)
MODE = GND2
LOAD = 54 Ω
VDD = 3.3 V
DE = VIO
MODE = VISOOUT
LOAD = 54 Ω
VDD = 5 V
TA = 25°C
TA = 25°C
Figure 8-15. ISOW1412 Driver output voltage vs.
Driver output current - RS485 Mode
Figure 8-16. ISOW1412 Driver output voltage vs.
Driver output current - Profibus Mode
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5
5
4.75
4.5
4.25
4
4.5
4
MODE = GND
MODE = VISOOUT
MODE = GND
MODE = VISOOUT
3.5
3
3.75
3.5
3.25
3
2.5
-15
-40 -25 -10
5
20 35 50 65 80 95 110 125
-12
-9
-6
-3
0
Temperature (C)
High Level Output Current (IOH) (mA)
RE = GND1
LOAD = -2 mA (RS485
RE = GND1
Load = 54 Ω TA = 25°C
Mode), -4mA (Profibus Mode)
Figure 8-17. ISOW1412 Receiver Buffer High Level
output voltage vs. High Level output current -
RS485 & Profibus Mode
Figure 8-18. ISOW1412 Receiver Buffer High Level
output voltage vs. Temperature - RS485 & Profibus
Mode
1
0.8
0.6
0.4
0.3
0.25
0.2
MODE = GND
MODE = VISOOUT
0.15
0.1
0.2
MODE = GND
MODE = VISOOUT
0
0.05
-0.2
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (C)
0
2
4
6
8
10
12
14
16
Low Level Output Current (IOL) (mA)
RE = GND1 LOAD = 2 mA (RS485 Mode),
4mA (Profibus Mode)
RE = GND1 LOAD = 54 Ω TA = 25°C
Figure 8-19. ISOW1412 Receiver Buffer Low Level
output voltage vs. Low Level output current -
RS485 & Profibus Mode
Figure 8-20. ISOW1412 Receiver Buffer Low Level
output voltage vs. Temperature - RS485 & Profibus
Mode
400
VDD = 5 V, VISOOUT = 5 V
VDD = 3.3 V, VISOOUT = 3.3 V
380
360
340
320
300
280
260
240
220
200
180
160
140
120
100
100 140 180 220 260 300 340 380 420 460 500
Data Rate (kbps)
MODE = GND2
RE = GND1
D = VIO
DE = VIO
LOAD = 54 Ω ||
50pF
For PWD ≤±5%
TA = 25°C
TA = 25°C
Figure 8-21. ISOW1412 Receiver VID vs. Data Rate
- RS485 & Profibus Mode
Figure 8-22. Glitch-free Power up/down- RS485
Mode
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MODE = VISOOUT
TA = 25°C
D = VIO
DE = VIO
LOAD = 54 Ω || 50pF
Figure 8-23. Glitch-free Power up/down- Profibus Mode
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9 Parameter Measurement Information
In this section, GND1 = GNDIO, GND2 = GISOIN unless otherwise noted.
VISOIN
DE = VIO
Y
RL
VOD
D = 0 or
VIO
VTEST
Z
+
œ
GND2
Figure 9-1. Driver Voltages
RL(1) / 2
Y
0 V or
VIO
Y
VY
VZ
D
VOD
RL(1) / 2
Z
Z
VOC
VOC
GND2
ûVOC(SS)
VOC(PP)
A. RL = 100 Ω for RS-422, RL = 54 Ω for RS-485
Figure 9-2. Driver Voltages
VIO
DE = VIO
VI
50%
VOD
Y
(1)
CL
50 pF 20%
RL
54 ꢀ 1%
D
tPHL
tPLH
VOD (H)
VOD (L)
Input
Generator
90%
90%
Z
50 ꢀ
VI
0 V
10%
0 V
VOD
10%
tr
GND1
tf
A. CL includes fixture and instrumentation capacitance
Figure 9-3. Driver Switching Specifications
VIO
DE
VISOIN (Connected to VISOOUT on PCB)
10 µF
10 µF
VIO
0.1 µF
0.1 µF
GND1
Y
+
VOH or VOL
D
54 ꢀ
54 ꢀ
Z
A
œ
GND1
1.5 V or 0 V
0 V or 1.5 V
R
RE
B
+
VOH or VOL
œ
CL
15 pF(1)
1 kꢀ
GND1
GND2
+ VCM
œ
A. Includes probe and fixture capacitance
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B. Pass-fail criteria: Device is tested in both half-duplex and full-duplex conditions. Both the signal path and power path should be in
specification compliant region during the application of CMTI pulse. This means no bit flips on R, and both VISOOUT and Driver VOD
should be within specifications mentioned in electrical characterisitcs table.
Figure 9-4. Common Mode Transient Immunity (CMTI)—Full Duplex
Y
S1
VIO
D
VO
50 % 50 %
VI
Z
DE
0 V
VOH
(1)
CL
50 pF
RL
110 ꢀ
tPZH
90%
Input
Generator
50 ꢀ
50%
VI
VO
≈ 0 V
tPHZ
GND2
GND1
A. CL includes fixture and instrumentation capacitance
Figure 9-5. Driver Enable and Disable Times
VISOIN
RL
110 ꢀ
VIO
Y
50 % 50 %
VI
D
0 V
S1
tPZL
tPLZ
(1)
CL
50 pF
Z
DE
VISOIN
VO
50%
10%
Input
Generator
VOL
50 ꢀ
VI
GND2
GND1
Figure 9-6. Driver Enable and Disable Times
3 V
50 %
50 %
A
VI
R
VO
0 V
VOH
B
Input
Generator
(1)
CL
15 pF
1.5 V
50 ꢀ
tPLH
tPHL
VI
RE
90%
50%
10%
50%
VO
VOL
tr
tf
A. CL includes fixture and instrumentation capacitance
Figure 9-7. Receiver Switching Specifications
VISOIN
50%
VI
0 V
tPZH
tPHZ
VOH
≈ 0 V
VIO
90%
VO
50%
tPZL
tPLZ
VO
50%
10%
VOL
Figure 9-8. Receiver Enable and Disable Times
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VIO
0 V
VIO
VI
50%
A
B
1 kꢀ
0 V or 1.5 V
R
VO
CL
15 pF
S1
tPZH
1.5 V or 0 V
VOH
≈ 0 V
VIO
A at 1.5 V
B at 0 V
S1 to GND
VO
50%
RE
Input
Generator
tPZL
VI
50 ꢀ
A at 0 V
B at 1.5 V
S1 to VIO
VO
50%
VOL
Figure 9-9. Receiver Enable and Disable Times
Y
Y
Steady-State
Logic Input
(1 or 0)
Steady State
Logic Input
(1 or 0)
œ7 V ≤ V ≤ 12 V
I(1)
G
C
G
Z
V
Z
C
GND
A. The driver should not sustain any damage with this configuration
GND
Figure 9-10. Short-Circuit Current Limiting
VISOIN
V
50%
I
50%
IN
OUT
0 V
t
t
PHL
PLH
Input Generator
(See Note A)
C
L
V
I
V
50 ꢀ
O
V
See Note B
OH
90%
10%
50%
50%
V
O
V
OL
t
t
f
r
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO
=
50 Ω. At the input, 50-Ω resistor is required to terminate the input generator signal. The resistor is not required in the actual application.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 9-11. GPIO Channel: Switching Characteristics Test Circuit and Voltage Waveforms
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10 Detailed Description
10.1 Overview
The ISOW14x2 family of devices has signal isolation channels, power isolation with integrated transformer and
RS-485 transceiver all integrated in one package. ISOW1412 supports maximum signaling rate up to 500 kbps,
while ISOW1432 is designed for 12 Mbps maximum data rate. Figure 10-1 shows functional block diagram of
ISOW14x2 family of devices.
10.2 Power Isolation
The integrated isolated DC-DC converter uses advanced circuit and on-chip layout techniques to reduce
radiated emissions and achieve up to 46% typical efficiency. The integrated transformer uses thin film polymer
as the insulation barrier. Output voltage of power converter can be controlled to 3.3 V or 5 V using MODE pin.
In case bus communication is not needed, the DC-DC converter can be switched off using EN (enable) pin to
save power. The output voltage, VISOOUT, is monitored and feedback information is conveyed to the primary side
through a dedicated isolation channel. The duty cycle of the primary switching stage is adjusted accordingly.
The fast feedback control loop of the power converter ensures low overshoots and undershoots during load
transients. Undervoltage lockout (UVLO) with hysteresis is integrated on the VIO, VDD and VISOOUT supplies
which ensures robust fails-safe system performance under noisy conditions. An integrated soft-start mechanism
ensures controlled inrush current and avoids any overshoot on the output during power up.
10.3 Signal Isolation
The integrated signal isolation channels employ an ON-OFF keying (OOK) modulation scheme to transmit the
digital data across a silicon-dioxide based isolation barrier. The transmitter sends a high frequency carrier
across the barrier to represent one state and sends no signal to represent the other state. The receiver
demodulates the signal after signal conditioning and produces the output through a buffer stage. The signal-
isolation channels incorporate advanced circuit techniques to maximize the CMTI performance and minimize the
radiated emissions from the high frequency carrier and IO buffer switching. Figure 10-2 shows a functional block
diagram of a typical signal isolation channel.
In order to keep any noise coupling from power converter away from signal path, power supplies on side1
for power converter (VDD) and signal path(VIO) are kept separate. Similarly on side2, power converter output
(VISOOUT ) needs to be connected to power supply for RS-485 (VISOIN) externally on PCB. For more details, refer
to Layout guidelines section.
10.4 RS-485
In a typical RS-485 network, multiple nodes may be connected on the bus and the distance of communicating
nodes can be as far as 4000-5000 feet. While communicating at such large distances, usual common mode of
non-isolated RS-485 transceiver is not sufficient. ISOW14x2 has integrated isolation barrier with upto 1500 Vpk
working voltage rating. Isolation breaks the ground loop between the communicating nodes and allows for data
transfer in the presence of large ground potential differences. These devices have a higher typical differential
output voltage (VOD) than traditional transceivers for better noise immunity. A minimum differential output voltage
of 2.1 V is specified when VISOIN is configured for 5 V supply which meets the requirements for PROFIBUS
applications.
The ISOW14x2 family of devices is suitable for applications that have limited board space and require more
integration. Only external bypass capacitors are needed to fully realize an isolated RS-485 port. This family of
devices is also suitable for very-high voltage applications, where power transformers for discrete isolated supply
meeting the required isolation specifications are bulky and expensive. Though the device family is full-duplex, it
can also be used for half-duplex applications by connecting driver output (Y , Z) to receiver input (A , B) on PCB-
this helps to reduce cabling costs. For more details, refer to Application Information.
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10.5 Functional Block Diagram
VIO
DE
VISOIN
VISOIN
Tx
Rx
Y
Z
Tx
Rx
Rx
Tx
D
R
B
A
Full Duplex
GND
RE
Rx
Tx
OUT
IN
GNDIO
GISOIN
GNDIO
GISOIN
VDD
MODE
VISOOUT
DC-DC
Primary
DC-DC
Secondary
EN/FLT
GND1
GND2
Figure 10-1. Block Diagram
Receiver
Transmitter
TX IN
OOK
Modulation
TX IN
SiO based
2
RX OUT
TX Signal
Conditioning
RX Signal
Conditioning
Envelope
Detection
Capacitive
Isolation
Barrier
Carrier signal through
isolation barrier
Emissions
Reduction
Techniques
RX OUT
Oscillator
Figure 10-2. Signal Isolation channel
10.6 Feature Description
10.6.1 Power-Up and Power-Down Behavior
The ISOW14x2 family of devices has built-in under-voltage lockout (UVLO) on all supplies (VDD, VIO and
VISOOUT) with positive-going and negative-going thresholds and hysteresis. Both the power converter supply
(VDD) and Logic supply (VIO) need to be present for the device to work. If either of them is below its UVLO, both
the signal path and the power converter are disabled.
Assuming VIO is above its UVLO+, when the VDD voltage crosses the positive-going UVLO threshold during
power-up, the DC-DC converter initializes and the power converter duty cycle is increased in a controlled
manner. This soft-start scheme limits primary peak currents drawn from the VDD supply and charges the VISOOUT
output in a controlled manner, avoiding overshoots. RS-485 driver output is in high impedance state in this
duration. When the UVLO positive-going threshold is crossed on the secondary side VISOOUT pin, the feedback
channel starts providing feedback to the primary controller. The regulation loop takes over and RS-485 drive
output, Received data output R and general purpose logic output OUT take their respective states defined by
the inputs to the device i.e. Driver enable(DE), Driver data to be transmitted D, Receiver enable RE and general
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purpose logic input IN respectively. Designers should consider a sufficient time margin (typically 5 ms with 10-µF
load capacitance) to allow this power up sequence before any usable system functionality.
When either of VDD or VIO is lost, the primary side DC-DC controller turns off when the UVLO lower threshold is
reached. The VISOOUT capacitor then discharges depending on the isolation channels and RS-485 load.
10.6.2 Protection Features
The ISOW14x2 family of devices has multiple protection features to create a robust system level solution.
•
The first feature is an Enable/Fault protection feature. This EN/FLT pin can be used as either an input pin to
enable or disable the integrated DC-DC power converter or as an output pin which works as an alert signal if
the power converter is not operating properly. In the /Fault use case, a fault is reported if VDD > 7 V, VDD < 2.5
V, or if the junction temperature >170°C. When a fault is detected, this pin will go low, disabling the DC-DC
converter to prevent any damage.
≥ 5 kꢀ
Powers Down RS-485 Transceiver
and DC-DC Converter.
IQ < 1 mA Typical
EN/FLT
MCU OUTPUT
MCU INPUT
Fault Reported If
VDD < 2.5 V
VDD > 7 V
Junction Temp > 170° C
Figure 10-3. EN Fault Pin Diagram
•
An over-voltage clamp feature is present on VISOOUT which will clamp the voltage at 6 V at Profibus mode
(MODE = VISOOUT ) or 4V at RS485 mode (MODE = GND2), if there is an increase in voltage seen. For
device reliability, it is recommended that VISOOUT stays lower than the over-clamp voltage for device reliability.
Over-Voltage Lock Out (OVLO) on VDD will occur when a voltage higher than 7 V on VDD is seen. At OVLO,
the device will go into a low power state and the EN/FLT pin will go low.
•
•
These devices are protected against output overload and short circuit. In cases of overload or short on power
converter output VISOOUT, maximum duty cycle of power converter is limited. In cases of driver bus short
circuit due to the external power supply cable shorting to the bus cable, or due to bus contention, short circuit
current protection on RS-485 chip restricts the bus current to ±250 mA maximum.
•
Thermal protection is also integrated to help prevent the device from getting damaged under such scenarios.
An increase in the die temperature is monitored and the device is disabled when the die temperature
becomes 165℃ (typical), thus disabling the short condition. The device is re-enabled when the junction
temperature becomes 155℃ (typical). If an overload or output short-circuit condition prevails, this protection
cycle is repeated. Care should be taken in the system design to prevent repeated or prolonged exposure to
bus shorts as this exposes the device to high junction temperatures for extreme amounts of time affecting
device reliability.
10.6.3 Failsafe Receiver
The differential receiver of the ISOW14x2 devices has failsafe protection from invalid bus states caused by:
•
•
•
Open bus conditions such as a broken cable or a disconnected connector
Shorted bus conditions such as insulation breakdown of a cable that shorts the twisted-pair
Idle bus conditions that occur when no driver on the bus is actively driving.
The differential input of the RS-485 receiver is 0 in any of these conditions for a terminated transmission line.
The receiver outputs a failsafe logic-high state on R pin so that the output of the receiver is determinate. The
receiver thresholds are offset in the receiver design so that the indeterminate range does not include a 0 V
differential. See Receiver functional table for more details.
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10.6.4 Glitch-Free Power Up and Power Down
Communication on the bus that already exist between a master node and slave node in an RS-485 network must
not be disturbed when a new node is swapped in or out of the network. No glitches on the bus should occur
when the device is:
•
•
•
Hot plugged into the network in an unpowered state
Hot plugged into the network in a powered state and disabled state
Powered up or powered down in a disabled state when already connected to the bus
The ISOW14x2 devices meet above criteria and do not cause any false data toggling on the bus when powered
up or powered down in a disabled state with supply ramp rates >= 50 us.
10.7 Device Functional Modes
Table 10-1 lists the supply configuration for these devices:
Table 10-1. Supply configuration Function Table
INPUTS
OUTPUT
(1)
(3)
VDD
VIO
EN/FLT
MODE
VISOOUT
OFF
< VDD(UVLO+)
>VDD(UVLO+)
5 V
>VIO(UVLO+)
<VIO(UVLO+)
1.71 V to 5.5 V
X
X
Invalid Operation
5 V
High(shorted to VISOOUT
)
H or Open
Low(shorted to GND2) or floating
5 V or 3.3 V
1.71 V to 5.5 V
3.3 V
(2)
3.3 V
X
1.71 V to 5.5 V
X
High(shorted to VISOOUT
X
)
Invalid Operation
OFF
L
(1) VDD= 3.3 V, MODE shorted to VISOOUT(essentially VISOOUT = 5 V) is an invalid operation
(2) The MODE pin has a weak pulldown internally. Therefore for VISOOUT = 3.3 V, the MODE pin should be strongly connected to the
GND2 pin in noisy system scenarios.
(3) VISOOUT shorted to VISOIN on PCB. GND2 and GISOIN pins are shorted to each other and EN=High
Table 10-2 shows the driver functional modes:
Table 10-2. Driver Functional Table
INPUTS
OUTPUTS(3)
(1)
VDD
VIO
EN/FLT
D
H
DE
H
Y, A
H
Z, B
L
L
H
L
H
H or Open
X
L
Hi-Z
Hi-Z
H
Hi-Z
Hi-Z
L
PU
PU
X
Open
H
Open
X
L
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
PD
PU
PU
X
X
PD(2)
X
X
Invalid Operation
(1) PU=Powered up, PD=Powered down; H=high level; L=Low level; X=Irrelevant; Hi-Z=High impedance state
(2) A strongly driven input signal on D, DE or RE can weakly power the floating VIO through an internal protection diode and cause an
undetermined output.
(3) VISOOUT shorted to VISOIN on PCB and both GND2 pins are shorted to each other and EN=High
When the driver enable pin, DE, is logic high, the differential outputs, Y and Z, follow the logic states at data
input, D. A logic high at the D input causes the Y output to go high and the Z output to go low. Therefore the
differential output voltage defined by Equation 1 is positive.
VOD = VY – VZ
(1)
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A logic low at the D input causes the Z output to go high and the Y output to go low. Therefore the differential
output voltage defined by Equation 1 is negative. A logic low at the DE input causes both outputs to go to the
high-impedance (Hi-Z) state. The logic state at the D pin is irrelevant when the DE input is logic low. The DE pin
has an internal pulldown resistor to ground. The driver is disabled (bus outputs are in the Hi-Z) by default when
the DE pin is left open. The D pin has an internal pullup resistor. The Y output goes high and the Z output goes
low when the D pin is left open while the driver enabled.
Table 10-3 shows the receiver functional modes:
Table 10-3. Receiver Functional Table
INPUTS
OUTPUT
R (3)
Differential Input VID
VA- VB
=
(1)
VDD
VIO
EN/FLT
RE
VID > VIT+
L
L
H
VIT- < VID < VIT+
Indeterminate
VID < VIT-
L
L
H or Open
PU
PU
X
H
Hi-Z
Hi-Z
H
X
Open
L
Open, Short, Idle
L
X
X
X
X
X
H
PD
PU
PU
X
H or Open
L
X
Hi-Z
X
PD(2)
Invalid Operation
X
(1) PU=Powered up, PD=Powered down; H=high level; L=Low level; X=Irrelevant; Hi-Z=High impedance state
(2) A strongly driven input signal on D, DE or RE can weakly power the floating VIO through an internal protection diode and cause an
undetermined output.
(3) VISOOUT shorted to VISOIN on PCB and both GND2 pins are shorted to each other and EN/FLT=High
The receiver is enabled when the receiver enable pin, RE, is logic low. The receiver output, R, goes high when
the differential input voltage defined by Equation 2 is greater than the positive input threshold, VTH+
.
VID = VA – VB
(2)
The receiver output, R, goes low when the differential input voltage defined by Equation 2 is less than the
negative input threshold, VTH– . If the VID voltage is between the VTH+ and VTH– thresholds, the output is
indeterminate. The receiver output is in the Hi-Z state and the magnitude and polarity of VID are irrelevant when
the RE pin is logic high or left open. The internal biasing of the receiver inputs causes the output to go to a
failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted to one
another (short-circuit), or the bus is not actively driven (idle bus).
Other device feature functional states in shown in Table 10-4 and Table 10-5 below:
Table 10-4. DC-DC Converter Enable/Disable
INPUTS
OUTPUT
VISOOUT
VDD
PU
PU
VIO
PU
PU
EN/FLT
H or Open
L
3.3 V or 5 V depending on MODE pin
setting
OFF
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Table 10-5. General Purpose Logic Input/Output
INPUTS
OUTPUT
Comments
(1) (2)
VDD
VIO
EN/FLT
IN
H
OUT
H
Output channel assumes
logic state governed by IN
H or Open
L
L
PU
PU
Open
X
L
Hi-Z
Default state
L
X
X
Device is in disabled state
when either of VDD or VIO is
missing
PD
PU
PU
PD
X
Hi-Z
X
Invalid Operation
(1) PU = Powered Up; PD = Powered Down; H = Logic High; L= Logic Low; X = Irrelevant, Hi-Z = High Impedance (OFF) state
(2) VISOOUT shorted to VISOIN on PCB. GISOIN and GND2 pins are shorted to each other and EN/FLT=High
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10.8 Device I/O Schematics
D, RE
VIO
VIO
DE
VIO
VIO
VIO
VIO
VIO
500 kꢀ
985 ꢀ
985 ꢀ
DE
D, RE
500 kꢀ
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
IN
EN/FLT
VIO
VISOIN
VISOIN
VISOIN
VIO
VIO
VIO
550 kꢀ
985 ꢀ
EN/FLT
IN
500 kꢀ
GISOIN
1mA
GND1
GISOIN
GISOIN
GND1
GND1
GND1
MODE
R, OUT
VIO
VISOOUT
VISOOUT
VISOOUT
~20 ꢀ
985 ꢀ
R or
OUT
MODE
500 kꢀ
GND2
GND2
GND2
GNDIO
Figure 10-4. Device I/O schematics
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11 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
11.1 Application Information
The ISOW14x2 devices are designed for bidirectional data transfer on multipoint RS-485 networks. An RS-485
bus has multiple transceivers that connect in parallel to a bus cable. Both cable ends are terminated with a
termination resistor, RT, to remove line reflections. The value of RT matches the characteristic impedance, Z0, of
the cable. This method, known as parallel termination, lets higher data rates be used over a longer cable length.
Full-duplex implementation shown in Figure 9-1 requires two signal pairs (four wires). Full-duplex implementation
lets each node to transmit data on one pair while simultaneously receiving data on the other pair.
Y
Z
A
B
RT
R
RE
DE
D
R
RE
DE
D
ISOW14x2
Master
ISOW14x2 Slave
B
A
Z
Y
RT
RT
A
B
Z
Y
Figure 11-1. Typical RS-485 network with Full-duplex Isolated transceivers
Figure 9-2 below, shows ISOW14x2 devices used in half duplex configuration. Driver outputs Y and Z are
shorted to A and B respectively. This reduces overall cabling requirements. Also DE/RE are shorted to each
other, and at a time, any node acts as either a driver or a receiver. Split termination is also shown in this
configuration which helps to boost network immunity in noisy environments by providing common-mode noise
filtering and also reduces radiated emissions by providing low impedance path to earth to the bus common mode
excursions.
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Integrated isolation barrier allows for communication between
nodes with ground potential differences of up to 1500 V
R
D
R
A
B
A
B
RE
DE
RE
100pF 60
60
60
100pF
ISOW14x2
ISOW14x2
60
DE
D
GND2
GND2
A
B
A
B
GND2
GND2
Figure 11-2. Typical RS-485 Network With Half-Duplex Isolated Transceivers
11.2 Typical Application
4.7 k
8
EN/FLT
0.1 …F
FB
0.1 …F
10 …F
1
16
15
V
VISOIN
IO
6
GNDIO
GISOIN
VIO
4
3
5
R
A
GPIO1
GPIO2
20
19
MCU
DE
B
RS-485
BUS
ISOW14x2
18
17
RE
Z
Y
2
7
L1 3.3 V
GPIO3
GPIO4
D
DGND
OUT
13
N
MODE
VISOOUT
PSU
FB
FB
FB
FB
9
12
11
5 V
PE
VDD
GND1
GND2
Extra Current
~20 mA
10
GND
10 µF 1 µF 10 nF
10 nF 1 µF 10 µF
Other Field
Circuitry
Galvanic
Isolation Barrier
Notes:
1. Extra current is only available in VDD = 5 V +/- 10% mode.
2. Keep 10 nF bypass capacitors close to VDD and VISOOUT pins (< 1 mm) for optimum radiated emissions performance.
3. GND1 and GNDIO must be shorted directly. GND2 and GISOIN must be shorted directly, or through ferrite beads.
Figure 11-3. Application circuit for ISOW14x2
11.2.1 Design Requirements
Unlike an optocoupler-based solution, which requires several external components to improve performance,
provide bias, or limit current, the ISOW14x2 devices only require external bypass capacitors to operate as
shown in above application diagram. Because of high peak currents flowing through VDD and VISOOUT supplies,
bulk capacitance of minimum 10 μF is recommended on both pins. Higher values of bulk capacitors will
attenuate noise and ripple further, enhancing performance.
11.2.2 Detailed Design Procedure
The RS-485 bus is a robust electrical interface suitable for long-distance communications. The RS-485 interface
can be used in a wide range of applications with varying requirements of distance of communication, data rate,
and number of nodes.
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11.2.2.1 Data Rate, Bus Length and Bus Loading
The RS-485 standard has typical curves similar to those shown in Figure 11-4. These curves show the inverse
relationship between signaling rate and cable length. If the data rate of the payload between two nodes is lower,
the cable length between the nodes can be longer. Use below Figure as a guideline for cable selection, data
rate, cable length and subsequent jitter budgeting.
10000
5%, 10%, and 20% Jitter
1000
Conservative
Characteristics
100
10
100
1k
10k
100 k
1M
10M
100 M
Data Rate (bps)
Figure 11-4. Cable length vs Data rate characteristics
The current supplied by the driver must supply into a load because the output of the driver depends on
this current. Add transceivers to the bus to increase the total bus loading. The RS-485 standard specifies a
hypothetical term of a unit load (UL) to estimate the maximum number of possible bus loads. The UL represents
a load impedance of approximately 12 kΩ. Standard-compliant drivers must be able to drive 32 of these ULs.
The ISOW14x2 devices have 1/8 UL impedance transceiver and can connect up to 256 nodes to the bus.
11.2.2.2 Stub Length
In an RS-485 network, the distance between the transceiver inputs and the cable trunk is known as the stub. The
stub should be as short as possible when a node is connected to the bus. Stubs are a non-terminated piece of
bus line that can introduce reflections of varying phase as the length of the stub increases. The electrical length,
or round-trip delay, of a stub should be less than one-tenth of the rise time of the driver as a general guideline.
Therefore, the maximum physical stub length (L(STUB)) is calculated as shown in Equation 3.
L(STUB) ≤ 0.1 × tr × v × c
(3)
where:
•
•
•
tr is the 10/90 rise time of the driver.
c is the speed of light (3 × 108 m/s).
v is the signal velocity of the cable or trace as a factor of c.
11.2.2.3 Insulation Lifetime
Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides as shown in below TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced
insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million
(ppm). Even though the expected minimum insulation lifetime is 20 years at the specified working isolation
voltage, VDE reinforced certification requires additional safety margin of 20% for working voltage and 87.5% for
lifetime which translates into minimum required insulation lifetime of 37.5 years at a working voltage that's 20%
higher than the specified value.
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A
Vcc 1
Vcc 2
Time Counter
> 1 mA
DUT
GND 1
GND 2
V
S
Oven at 150 °C
Figure 11-5. Test Setup for Insulation Lifetime Measurement
The insulation lifetime projection data shows the intrinsic capability of the isolation barrier to withstand high
voltage stress over its lifetime. Based on the TDDB data, the intrinsic capability of the insulation is 1000 VRMS
with a lifetime of 1184 years.
Figure 11-6. Insulation Lifetime Projection Data
12 Power Supply Recommendations
To make sure that operation is reliable at all data rates and supply voltages, adequate decoupling capacitors
must be located as close to supply pins as possible. Power converter input VDD and output VISOOUT supply pins
should have high frequency ceramic capacitors 10 nF and bulk capacitors 10 μF atleast close to the pins. Signal
path supply pins, VIO and VISOIN, should have 100 nF or higher value ceramic bypass capacitors close to device
pins. ISOW1412 can consume typical peak pulse currents of upto 250 mA under fully loaded conditions for short
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durations (10s of µs) from the power source that is powering VDD of ISOW1412. Please make sure the current
limit of upstream power device is at least 300 mA typical.
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13 Layout
13.1 Layout Guidelines
Figure 11-1 shows the recommended placement and routing of device bypass capacitors. Below guidelines must
be followed to achieve low emissions design:
1. High frequency bypass capacitors 10 nF must be placed close to VDD and VISOOUT pins, less than 1 mm
distance away from device pins. This is very essential for optimised radiated emissions performance. Ensure
that these capacitors are 0402 size so that they offer least inductance (ESL).
2. Bulk capacitors of atleast 10 µF must be placed on power converter input (VDD) and output (VISOOUT) supply
pins.
3. Traces on VDD and GND1 must be symmetric till bypass capacitors. Similarly traces on VISOOUT and GND2
must be symmetric.
4. Place two 0402 size Ferrite beads (Part number: BLM15EX331SN1) on power supply pins, one between
VISOOUT and VISOIN and the other between GND2 (11) and GISOIN(15), as shown in example PCB layout,
so that any high frequency noise from power converter output sees a high impedance before it goes to other
components on PCB.
5. Do not have any metal traces or ground pour within 4 mm of power converter output terminals VISOOUT
(pin12) and GND2 (pin11). MODE pin is also in VISOOUT domain and should be shorted to either pin 11 or pin
12 for output voltage selection.
6. Common mode choke or ferrite beads on bus terminals (Y/Z/A/B) can minimise any high frequency noise
that can couple of RS-485 bus cable which can act as antenna and amplify that noise. This will improve
Radiated emissions performance on a system level.
7. Following the layout guidelines of EVM as much as possible is highly recommended for a low radiated
emissions design. EVM Link is available in Related Documentation.
13.2 Layout Example
ISOW14x2
<2mm
VIO
0.1 µF
FB5
Input Supply 1
A
B
20
19
1
R
R
C
D
DE
R
2
RS-485
BUS
Z
Y
3
4
18
17
16
15
14
13
12
11
0.1 µF
10 µF
VISOIN
5
RE
<2mm
C
C
GISOIN
GNDIO
6
OUT
EN/FLT
VDD
7
IN
Ground
plane on
side2
MODE
8
2-4mm
<1mm
10 µF
1 µF
10 nF
10 µF
1 µF
10 nF
FB4
Input Supply 2
Input Ground
FB1
FB2
9
VISOOUT
GND2
C
C
C
C
C
C
FB3
GND1
10
Ground plane on
side 1
2-4mm
<1mm
Keep-out zone
for any metal
Figure 13-1. Layout example
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14 Device and Documentation Support
14.1 Documentation Support
14.1.1 Related Documentation
For related documentation see the following:
•
•
•
Texas Instruments, Digital Isolator Design Guide
Texas Instruments, Isolation Glossary
ISOW1412DFM Evaluation board
14.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
14.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
14.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
14.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
14.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
15 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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29-Jan-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISOW1412BDFMR
ISOW1412DFMR
XISOW1432DFMR
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
DFM
DFM
DFM
20
20
20
850
850
850
RoHS & Green
RoHS & Green
TBD
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Call TI
-40 to 125
-40 to 125
-40 to 125
ISOW1412
ISOW1412
NIPDAU
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jan-2022
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISOW1412BDFMR
ISOW1412DFMR
SOIC
SOIC
DFM
DFM
20
20
850
850
330.0
330.0
24.4
24.4
10.85 13.4
10.85 13.4
4.0
4.0
16.0
16.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ISOW1412BDFMR
ISOW1412DFMR
SOIC
SOIC
DFM
DFM
20
20
850
850
350.0
350.0
350.0
350.0
43.0
43.0
Pack Materials-Page 2
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