FX006 [TI]
具有 2 位 VID 的 3.3V/5V 输入、D-CAP+™ 模式同步降压 FET 转换器 | RGE | 24 | -40 to 85;
| 型号： | FX006 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 2 位 VID 的 3.3V/5V 输入、D-CAP+™ 模式同步降压 FET 转换器 | RGE | 24 | -40 to 85 开关 控制器 开关式稳压器 开关式控制器 电源电路 转换器 开关式稳压器或控制器 |
| 文件： | 总27页 (文件大小：1672K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS51462
www.ti.com
SLUSAQ1 –DECEMBER 2011
3.3-V/5-V Input, D-CAP+™ Mode Synchronous Step-Down Integrated FETs Converter
With 2-Bit VID
Check for Samples: TPS51462
1
FEATURES
DESCRIPTION
The TPS51462 is a fully integrated synchronous buck
regulator employing D-CAP+™. It is used for up to
5-V step-down where system size is at its premium,
performance and optimized BOM are must-haves.
2
•
Integrated FETs Converter w/TI Proprietary
D-CAP+™ Mode Architecture
•
•
Minimum External Parts Count
Support all MLCC Output Capacitor and
SP/POSCAP
This device fully supports Intel system agent
applications with integrated 2-bit VID function.
•
•
•
Auto Skip Mode
The TPS51462 also features two switching frequency
settings (700 kHz and 1 MHz), skip mode, pre-bias
startup, programmable external capacitor soft-start
time/voltage transition time, output discharge, internal
VBST Switch, 2-V reference (±1%), power good and
enable.
Selectable 700-kHz and 1-MHz Frequency
Small 4 mm × 4 mm, 24-Pin, QFN Package
APPLICATIONS
•
Low-Voltage Applications Stepping Down from
5-V or 3.3-V Rail
The TPS51462 is available in a 4 mm × 4 mm,
24-pin, QFN package (Green RoHs compliant and Pb
free) and is specified from -40°C to 85°C.
•
Notebook/Desktop Computers
+5V
ENABLE
VID0
VID1
PGOOD
18
17
16
15
14
13
19 PGND
20 PGND
21 PGND
22 VIN
BST 12
SW 11
SW 10
TPS51462
VCCSA
SW
SW
SW
9
8
7
23 VIN
VIN
24 VIN
1
2
3
4
5
6
VCCSASNS
UDG-11143
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
D-CAP+ is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
TPS51462
SLUSAQ1 –DECEMBER 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
MINIMUM
QUANTITY
TA
PACKAGE(2)
ORDERING NUMBER
PINS
OUTPUT SUPPLY
ECO PLAN
TPS51462RGER
TPS51462RGET
24
24
Tape and reel
Mini reel
3000
Green (RoHS and
no Pb/Br)
Plastic QFN
(RGE)
-40°C to 85°C
250
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the TI
website at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
THERMAL INFORMATION
TPS51462
THERMAL METRIC(1)
UNITS
RGE (24) PIN
θJA
Junction-to-ambient thermal resistance
38.3
44.7
16
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.8
ψJB
16.1
5.4
θJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
MIN
UNIT
MAX
7.0
VIN, EN, MODE
–0.3
–0.3
–0.3
–0.3
–1.0
–2.0
–3.5
–0.3
–0.3
–0.3
V5DRV, V5FILT, VBST (with respect to SW)
7.0
Input voltage range
VBST
12.5
3.6
V
VID0, VID1
VOUT
3.6
SW
7.0
SW (transient 20 ns and E=5 µJ)
Output voltage range
Electrostatic Discharge
COMP, SLEW, VREF
3.6
0.3
V
V
PGND
PGOOD
7.0
Human Body Model (HBM)
2000
500
150
150
300
Charged Device Model (CDM)
Storage temperature
Junction temperature
Tstg
TJ
–55
–40
˚C
˚C
˚C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
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SLUSAQ1 –DECEMBER 2011
RECOMMENDED OPERATING CONDITIONS
VALUE
UNIT
MIN
–0.1
–0.1
–0.1
–0.1
–0.8
–0.8
–0.1
–0.1
–0.1
-40
TYP
MAX
6.5
VIN, EN, MODE
V5DRV, V5FILT, VBST(with respect to SW)
VBST
5.5
Input voltage range
11.75
3.5
V
VID0, VID1
VOUT
2.0
SW
6.5
COMP, SLEW, VREF
PGOOD
3.5
Output voltage range
V
6.5
PGND
0.1
Ambient temperature range, TA
85
°C
ELECTRICAL CHARACTERISTICS
over recommended free-air temperature range, VVIN = 5.0 V, VV5DRV = VV5FILT = 5 V, MODE = OPEN, PGND = GND (unless
otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY: VOLTAGE, CURRENTS AND 5 V UVLO
IVINSD
VIN shutdown current
5VIN supply voltage
5VIN supply current
5VIN shutdown current
V5FILT UVLO
EN = 'LO'
0.02
5.0
1.6
10
5
5.5
3.0
50
µA
V
V5VIN
V5DRV and V5FILT voltage range
EN =’HI’, V5DRV + V5FILT supply current
EN = ‘LO’, V5DRV + V5FILT shutdown current
Ramp up; EN = 'HI'
4.5
I5VIN
mA
µA
V
I5VINSD
VV5UVLO
VV5UVHYS
VVREFUVLO
VVREFUVHYS
VPOR5VFILT
4.2
4.3
440
1.8
100
2.3
4.5
V5FILT UVLO hysteresis
REF UVLO(1)
REF UVLO hysteresis(1)
Falling hysteresis
mV
V
Rising edge of VREF, EN = 'HI'
mV
V
Reset
OVP latch is reset by V5FILT falling below the reset threshold
1.5
3.1
VOLTAGE FEEDBACK LOOP: VREF, VOUT, AND VOLTAGE GM AMPLIFIER
VOUTTOL
VVREF
GM
VOUT accuracy
VVOUT = 0.8V, No droop
–1.5%
0%
2
1.5%
VREF
IVREF = 0 µA, TA = 25°C
V
mS
mV
µA
Transconductance
Differential mode input voltage
1
VDM
0
80
5
ICOMPSRC
VOFFSET
RDSCH
f–3dbVL
COMP pin maximum sourcing current VCOMP = 2 V
–80
0
Input offset voltage
TA = 25°C
–5
mV
Ω
Output voltage discharge resistance
–3dB Frequency(1)
42
6
MHz
CURRENT SENSE: CURRENT SENSE AMPLIFIER, OVER CURRENT AND ZERO CROSSING
Gain from the current of the low-side FET to PWM comparator
when PWM = "OFF"
ACSINT
Internal current sense gain
43
50
57 mV/A
IOCL
Positive overcurrent limit (valley)
Negative overcurrent limit (valley)
Zero crossing comp internal offset
6.6
–6
0
A
A
IOCL(neg)
VZXOFF
mV
DRIVERS: BOOT STRAP SWITCH
RDSONBST Internal BST switch on-resistance
IBSTLK Internal BST switch leakage current
IVBST = 10 mA, TA = 25°C
5
10
1
Ω
VVBST = 14 V, VSW = 7 V, TA = 25°C
µA
(1) Ensured by design, not production tested.
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ELECTRICAL CHARACTERISTICS (continued)
over recommended free-air temperature range, VVIN = 5.0 V, VV5DRV = VV5FILT = 5 V, MODE = OPEN, PGND = GND (unless
otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX UNIT
PROTECTION: OVP, UVP, PGOOD, and THERMAL SHUTDOWN
PGOOD deassert to lower
VPGDLL
VPGHYSHL
VPGDLH
VPGHYSHH
VINMINPG
VOVP
Measured at the VOUT pin w/r/t VSLEW
82%
84%
8%
86%
(PGOOD → Low)
PGOOD high hysteresis
PGOOD de-assert to higher
(PGOOD → Low)
Measured at the VOUT pin w/r/t VSLEW
114%
116%
-8%
118%
PGOOD high hysteresis
Minimum VIN voltage for valid
PGOOD
Measured at the VIN pin with a 2-mA sink current on PGOOD
pin
0.9
118%
66%
1.3
1.5
122%
70%
V
OVP threshold
UVP threshold
Measured at the VOUT pin w/r/t VSLEW
120%
68%
Measured at the VOUT pin w/r/t VSLEW, device latches OFF,
begins soft-stop
VUVP
THSD
Thermal shutdown(2)
Thermal Shutdown hysteresis(2)
Latch off controller, attempt soft-stop.
125
10
°C
°C
THSD(hys)
Controller re-starts after temperature has dropped
TIMERS: ON-TIME, MINIMUM OFF TIME, SS, AND I/O TIMINGS
VVIN = 5 V, VVOUT = 0.8 V, fSW = 667 kHz, fixed VID mode
VVIN = 5 V, VVOUT = 0.8 V, fSW = 1 MHz, fixed VID mode
240
160
ns
ns
tONESHOTC
PWM one-shot(2)
VVIN = 5 V, VVOUT = 0.8 V, fSW = 1 MHz, DRVL on,
SW = PGND, VVOUT < VSLEW
tMIN(off)
Minimum OFF time(2)
357
3
ns
ms
ms
PGOOD startup delay time (2)(excl.
SLEW ramp up time)
Delay starts from VOUT = VID code 00 and excludes SLEW
ramp up time
tPGDDLY
tPGDPDLYH
PGOOD high propagation delay
time(2)
50 mV over drive, rising edge
0.8
1
1.2
tPGDPDLYL
tOVPDLY
PGOOD low propagation delay time(2) 50 mV over drive, falling edge
10
µs
µs
OVP delay time(2)
Time from the VOUT pin out of +20% of VSLEW to OVP fault
0.2
Undervoltage fault enable delay (excl. Time from (VOUT = VID code 00) going high to undervoltage
tUVDLYEN
3
ms
SLEW ramp up time)(2)
UVP delay time(2)
fault is ready
tUVPDLY
ISLEW
Time from the VOUT pin out of –30% of VSLEW to UVP fault
CSS = 10 nF assuming voltage slew rate of 1 mV/µs
8.5
10
µs
Soft-start and voltage transition
9
11
µA
LOGIC PINS: I/O VOLTAGE AND CURRENT
VPGDPD
IPGDLKG
VENH
VENL
PGOOD pull down voltage
PGOOD leakage current
EN logic high
PGOOD low impedance, ISINK = 4 mA, VVIN = VV5FILT = 4.5 V
PGOOD high impedance, forced to 5.5 V
EN, VCCP logic
0.3
1
V
µA
V
–1
0
0.8
EN logic low
EN, VCCP logic
0.3
1
V
IEN
EN input current
VID logic high
µA
V
VVIDH
VVIDL
VID0, VID1
VID0, VID1
MODE 3
0.8
VID logic low
0.3
0.47
0.65
1.85
V
0.37
0.55
1.75
0.42
0.60
1.80
15
VMODETH
MODE threshold voltage(3)
MODE 4
V
MODE 7
IMODE
RPD
MODE current
µA
kΩ
VID pull-down resistance
10
(2) Ensured by design, not production tested.
(3) See Table 3 for descriptions of MODE parameters.
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SLUSAQ1 –DECEMBER 2011
RGE PACKAGE
24
23
20
19
22
21
1
2
3
4
5
6
18 V5DRV
17 V5FILT
16 PGOOD
15 VID1
14 VID0
GND
VREF
COMP
TPS51462
SLEW
VOUT
Thermal Pad
13 EN
MODE
9
10
7
8
11
12
PIN FUNCTIONS
PIN
I/O
DESCRIPTION
NO.
19
20
21
22
23
24
1
NAME
PGND
I
Power ground. Source terminal of the rectifying low-side power FET.
VIN
I
Power supply input pin. Drain terminal of the switching high-side power FET.
GND
VREF
COMP
SLEW
VOUT
MODE
–
O
O
I/O
I
Signal ground.
2
2.0-V reference output. Connect a 0.22-µF ceramic capacitor to GND.
Connect series R-C to the VREF pin for loop compensation.
3
4
Program the startup and voltage transition time using an external capacitor via 10-µA current source.
Output voltage monitor input pin.
5
6
I
Allows selection of switching frequencies and output voltage. (See Table 3)
7
8
9
SW
I/O
Switching node output. Connect to the external inductor.
10
11
12
Power supply for internal high-side gate driver. Connect a 0.1-µF bootstrap capacitor between this pin and
the SW pin.
BST
I
I
13
14
15
16
17
18
EN
Enable of the SMPS.
VID0
I
2-bit VID input.
VID1
PGOOD
V5FILT
V5DRV
O
I
Power good output. Connect pull-up resistor.
5-V power supply for analog circuits.
I
5-V power supply for the gate driver.
Thermal Pad
–
Connect directly to system GND plane with multiple vias.
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SLUSAQ1 –DECEMBER 2011
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BLOCK DIAGRAM
14 VID0
10 mA
00
01
10
11
15 VID1
+
16 PGOOD
VREFIN +8/16 %
+
+
+
VREFIN –32%
UV
EN 13
+
OV
VREFIN –8/16 %
15 mA
VREFIN +20%
COMP
3
4
Control Logic
On-Time
and LL
UVP
OVP
6
MODE
Selection
VS
+
12 BST
22 VIN
+
PWM
SLEW
VCS
VIN
23
VREF
VOUT
2
5
Bandgap
24 VIN
8 R
7
8
9
SW
SW
SW
+
CS
+
OC
PGND
XCON
tON
R
One-
Shot
10 SW
11 SW
SW
18 V5DRV
Sense
ZC
17 V5FILT
+
Discharge
19 PGND
20 PGND
21 PGND
GND
1
TPS51462
UDG-11209
Table 1. Intel SA VID
VID 0
VID 1
VCCSA
0
0
0
1
1
0
0.9 V
1
1
0
1
0.80 V (1)MODE = Open
0.85 V (1)MODE = 33 kΩ
0.725 V
0.675 V
(1) 0.8 V for 2012/2013 SV processors and 0.85 V for 2012 LV/ULV
processors.
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SLUSAQ1 –DECEMBER 2011
TPS51462 APPLICATION DIAGRAM
N E
E D O M
T U O V
W E L S
0 D I V
1 D I V
D O O G P
T L I F 5 V
V R D 5 V
P M O C
F E R V
D N G
Figure 1. Application Schematic Using Non-Droop Configuration
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SLUSAQ1 –DECEMBER 2011
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Application Circuit List of Materials
Recommended part numbers for key external components for the circuit in Figure 1 are listed in Table 2.
Table 2. Key External Component Recommendations
(Figure 1)
FUNCTION
MANUFACTURER
Nec-Tokin
PART NUMBER
Output Inductor
MPCG0740LR42C
ECJ2FB0J226M
Panasonic
Ceramic Output Capacitors
Murata
GRM21BR60J226ME39L
8
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SLUSAQ1 –DECEMBER 2011
APPLICATION INFORMATION
Functional Overview
The TPS51462 is a D-CAP+™ mode adaptive on-time converter. The output voltage is set using a 2-bit DAC that
outputs a reference voltage in accordance with the code defined in Table 1. VID-on-the-fly transitions are
supported with the slew rate controlled by a single capacitor on the SLEW pin. The converter automatically runs
in discontinuous conduction mode (DCM) to optimize light-load efficiency. Two switching frequency selections
are provided, (700 kHz and 1 MHz) to enable optimization of the power chain for the cost, size and efficiency
requirements of the design.
In adaptive on-time converters, the controller varies the on-time as a function of input and output voltage to
maintain a nearly constant frequency during steady-state conditions. In conventional constant on-time converters,
each cycle begins when the output voltage crosses to a fixed reference level. However, in the TPS51462, the
cycle begins when the current feedback reaches an error voltage level which is the amplified difference between
the reference voltage and the feedback voltage.
PWM Operation
Referring to Figure 2, in steady state, continuous conduction mode, the converter operates in the following way.
Starting with the condition that the top FET is off and the bottom FET is on, the current feedback (VCS) is higher
than the error amplifier output (VCOMP). VCS falls until it hits VCOMP, which contains a component of the output
ripple voltage. VCS is not directly accessible by measuring signals on pins of TPS51462. The PWM comparator
senses where the two waveforms cross and triggers the on-time generator.
Current
Feedback
V
CS
V
COMP
V
REF
t
ON
t
Time (ms)
UDG-10187
Figure 2. D-CAP+™ Mode Basic Waveforms
The current feedback is an amplified and filtered version of the voltage between PGND and SW during low-side
FET on-time. The TPS51462 also provides a single-ended differential voltage (VOUT) feedback to increase the
system accuracy and reduce the dependence of circuit performance on layout.
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PWM Frequency and Adaptive on Time Control
In general, the on-time (at the SW node) can be estimated by Equation 1.
V
1
OUT
t
=
´
ON
V
f
SW
IN
where
•
fSW is the frequency selected by the connection of the MODE pin
(1)
The on-time pulse is sent to the top FET. The inductor current and the current feedback rises to peak value.
Each ON pulse is latched to prevent double pulsing. Switching frequency settings are shown in Table 3.
Non-Droop Configuration
The TPS51462 offers a non-droop solution only. The benefit of a non-droop approach is that load regulation is
flat, therefore, in a system where tight DC tolerance is desired, the non-droop approach is recommended. For the
Intel system agent application, non-droop is recommended as the standard configuration.
The non-droop approach can be implemented by connecting a resistor and a capacitor between the COMP and
the VREF pins. The purpose of the type II compensation is to obtain high DC feedback gain while minimizing the
phase delay at unity gain cross over frequency of the converter.
The value of the resistor (RC) can be calculated using the desired unity gain bandwidth of the converter, and the
value of the capacitor (CC) can be calculated by knowing where the zero location is desired. An application tool
that calculates these values is available from your local TI Field Application Engineer.
Figure 3 shows the basic implementation of the non-droop mode using the TPS51462.
GMV = 1 mS
RC
CC
VSLEW
+
LOUT
+
GMC= 1 mS
–
Driver
+
ESR
RDS(on)
PWM
Comparator
+
ROUT
RLOAD
4 kW
COUT
+
VREF
–
UDG-11208
Figure 3. Non-Droop Mode Basic Implementation
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Figure 4 shows the load regulation of the system agent rail using non-droop configuration.
Figure 5 shows the transient response of TPS51462 using non-droop configuration where COUT = 4 × 22 µF. The
applied step load is from 0 A to 2 A.
0.90
TA = 25°C
VIN = 5 V
0.85
0.80
Mode 3
Mode 4
Mode 7
Mode 8
0.75
0.1
1
10
Output Current (A)
G008
Figure 4. 0.8 V/0.85 V Load Regulation (VIN = 5 V)
Non-Droop Configuration
Figure 5. Non-Droop Configuration Transient
Response
Table 3. Mode Parameter Table
VID1 = 1
VID0 = 0
(V)
SWITCHING
FREQUENCY (fSW
MODE
MODE CONNECTION
)
3
4
7
8
22 kΩ
33 kΩ
100 kΩ
Open
700 kHz
1 MHz
0.80
0.85
0.85
0.80
700 kHz
1 MHz
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Light Load Power Saving Features
The TPS51462 has an automatic pulse-skipping mode to provide excellent efficiency over a wide load range.
The converter senses inductor current and prevents negative flow by shutting off the low-side gate driver. This
saves power by eliminating re-circulation of the inductor current. Further, when the bottom FET shuts off, the
converter enters discontinuous mode, and the switching frequency decreases, thus reducing switching losses as
well.
Voltage Slewing
The TPS51462 ramps the SLEW voltage up and down to perform the output voltage transitioning. The timing is
independent of switching frequency, as well as output resistive and capacitive loading. It is set by a capacitor
from SLEW pin to GND, called CSLEW, together with an internal current source of 10 µA. The slew rate is used to
set the startup and voltage transition rate.
I
SLEW
C
=
SLEW
SR
(2)
C
´ 0.9V
SLEW
t
=
SS
I
SLEW
where
•
ISLEW = 10 µA (nom)
•
SR is the target output voltage slew rate, per Intel specification between 0.5 mV/µs and 10 mV/µs
(3)
For the current reference design, an SR of 1 mV/µs is targeted. The CSLEW is calculated to be 10 nF. The slower
slew rate is desired to minimize large inductor current perturbation during startup and voltage transitioning thus
reducing the possibility of acoustic noise.
After the power up, when VID1 is transitioning from 0 to 1, TPS51462 follows the SLEW voltage entering the
forced PWM mode to actively discharge the output voltage from 0.9 V to 0.8 V. The actual output voltage slew
rate is approximately the same as the set slew rate while the bandwidth of the converter supports it and there is
no overcurrent triggered by additional charging current flowing into the output capacitors. After SLEW transition is
completed, PWM mode is maintained for 64 µs (16 clock cycles when the frequency is 1 MHz) to ensure voltage
regulation.
Protection Features
The TPS51462 offers many features to protect the converter power chain as well as the system electronics.
5-V Undervoltage Protection (UVLO)
The TPS51462 continuously monitors the voltage on the V5FILT pin to ensure that the voltage level is high
enough to bias the device properly and to provide sufficient gate drive potential to maintain high efficiency. The
converter starts with approximately 4.3 V and has a nominal of 440 mV of hysteresis. If the 5-V UVLO limit is
reached, the converter transitions the phase node into a 3-state function. And the converter remains in the off
state until the device is reset by cycling 5 V until the 5-V POR is reached (2.3-V nominal). The power input does
not have an UVLO function
Power Good Signals
The TPS51462 has one open-drain power good (PGOOD) pin. During startup, there is a 3 ms power good delay
starting from the output voltage reaching the regulation point (excluding soft-start ramp-up time). And there is
also a 1 ms power good high propagation delay. The PGOOD pin de-asserts as soon as the EN pin is pulled low
or an undervoltage condition on V5FILT is detected. The PGOOD signal is blanked during VID voltage transitions
to prevent false triggering during voltage slewing.
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Output Overvoltage Protection (OVP)
In addition to the power good function described above, the TPS51462 has additional OVP and UVP thresholds
and protection circuits.
An OVP condition is detected when the output voltage is approximately 120% × VSLEW. In this case, the
converter de-asserts the PGOOD signals and performs the overvoltage protection function. The converter
remains in this state until the device is reset by cycling 5 V until the 5-V POR threshold (2.3 V nominal) is
reached.
Output Undervoltage Protection (UVP)
Output undervoltage protection works in conjunction with the current protection described in the Overcurrent
Protection and Overcurrent Limit sections. If the output voltage drops below 70% of VSLEW, after an 8-µs delay,
the device latches OFF. Undervoltage protection can be reset only by EN or a 5-V POR.
Overcurrent Protection
Both positive and negative overcurrent protection are provided in the TPS51462:
•
•
Overcurrent Limit (OCL)
Negative OCL (level same as positive OCL)
Overcurrent Limit
If the sensed current value is above the OCL setting, the converter delays the next ON pulse until the current
drops below the OCL limit. Current limiting occurs on a pulse-by-pulse basis. The TPS51462 uses a valley
current limiting scheme where the DC OCL trip point is the OCL limit plus half of the inductor ripple current. The
minimum valley OCL is 6 A over process and temperature.
During the overcurrent protection event, the output voltage likely droops until the UVP limit is reached. Then, the
converter de-asserts the PGOOD pin, and then latches OFF after an 8-µs delay. The converter remains in this
state until the device is reset by EN or a 5VFILT POR.
1
I
= IOCL valley
)
+
´IP-P
OCL(dc)
(
2
(4)
Negative OCL
The negative OCL circuit acts when the converter is sinking current from the output capacitor(s). The converter
continues to act in a valley mode, the absolute value of the negative OCL set point is typically -6.5 A.
Thermal Protection
Thermal Shutdown
The TPS51462 has an internal temperature sensor. When the temperature reaches a nominal 125°C, the device
shuts down until the temperature cools by approximately 10°C. Then the converter restarts.
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Startup and VID Transition Timing Diagrams
1.05-V Rail
0.95 V
VCCP
EN
Internal Enable
(3)
VID1
(3)
VID0
SLEW (1 mV/ms)
VOUT
VCCSA_PGOOD
(2)
Reset Time
(1)
UNCORE_PWRGD
260 ms
900 ms
4 ms
2.5 ms
UDG-10191
Figure 6. Fixed VID/Fixed Step Startup and VID Toggle Timing Diagram for 2011 Intel Platform
For Figure 6:
(1) Includes VCCA, VCCAXG, and VDDQ power rails.
(2) Processor reset: VID transition must be completed by this time.
(3) 1-kΩ pull-down resistor required.
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1.05-V Rail
0.95 V
VCCP
EN
100ms
Internal Enable
(3)
VID1
(3)
VID0
SLEW (1 mV/ms)
VOUT
VCCSA_PGOOD
(2)
Reset Time
(1)
UNCORE_PWRGD
260 ms
900 ms
4 ms
2.5 ms
UDG-10192
Figure 7. Fixed VID/Fixed Step Startup and VID Toggle Timing Diagram for 2012 Intel Platform
For Figure 7:
(1) Includes VCCA, VCCAXG, and VDDQ power rails.
(2) Processor reset: VID transition must be completed by this time.
(3) 1-kΩ pull-down resistor required.
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SLUSAQ1 –DECEMBER 2011
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TYPICAL CHARACTERISTICS
90
90
TA = 25°C
VIN = 3.3 V
TA = 25°C
VIN = 5 V
80
70
60
50
80
70
60
50
40
Mode 3
Mode 4
Mode 7
Mode 8
Mode 3
Mode 4
Mode 7
Mode 8
40
0.01
0.1
Output Current (A)
1
10
0.01
0.1
Output Current (A)
1
10
G001
G002
Figure 8. Efficiency vs. Output Current
Figure 9. Efficiency vs. Output Current
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
Mode 3
Mode 4
Mode 7
Mode 8
Mode 3
Mode 4
Mode 7
Mode 8
TA = 25°C
VIN = 3.3 V
TA = 25°C
VIN = 5 V
0.1
1
10
0.1
1
10
Output Current (A)
Output Current (A)
G003
G004
Figure 10. Power Loss vs. Output Current
Figure 11. Power Loss vs. Output Current
140
120
100
80
60
50
40
30
20
360
310
260
Gain
210
160
10
0
60
Phase
-10
110
60
40
-20
-30
-40
-50
OTP Boundary
Direct Current SOA
Pulse Current (50 µs) SOA
25°C
-10°C
20
10
85°C
0
-40
1
2
3
4
5
6
7
1000
10 k
100 k
1 M
10 M
Output Current (A)
G000
Frequency (Hz)
Figure 12. Bode Plot, Non-Droop Mode
Figure 13. Safe Operating Area
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TYPICAL CHARACTERISTICS (continued)
Figure 14. Mode=8, IOUT = 0 A, VID Transitioning
Figure 15. Mode=8, IOUT = 3 A, VID Transitioning
Figure 16. Mode = 8, OCL
Figure 17. Mode=4, OCL
Figure 18. Mode= 8, IOUT = 3 A, Soft-Start
Figure 19. Mode= 4, IOUT = 3 A, Soft-Start
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DESIGN PROCEDURE
The simplified design procedure is done for a non-droop application using the TPS51462 converter.
Step One
Determine the specifications.
The System Agent Rail requirements provide the following key parameters:
1. V00 = 0.90 V
2. V10 = 0.80 V
3. ICC(max) = 6 A
4. IDYN(max) = 2 A
5. ICC(tdc) = 3 A
Step Two
Determine system parameters.
The input voltage range and operating frequency are of primary interest. For example:
1. VIN = 5 V
2. fSW = 1 MHz
Step Three
Determine inductor value and choose inductor.
Smaller values of inductor have better transient performance but higher ripple and lower efficiency. Higher values
have the opposite characteristics. It is common practice to limit the ripple current to 25% to 50% of the maximum
current. In this case, use 25%:
I
= 6A ´0.25 = 1.5A
P-P
(5)
At fSW = 1 MHz, with a 5-V input and a 0.80-V output:
æ
ö
æ
5 - 0.8 ´
( ) ç
ö
V
0.8
10
V
- V
´
)
10
ç
ç
è
÷
÷
ø
(
÷
÷
ø
IN
ç
f
(
´ V
1´ 5
)
)
IN
(
V ´ dT
SW
è
L =
=
=
= 0.45mH
I
I
1.5A
P-P
P-P
(6)
For this application, a 0.42-µH, 1.55-mΩ inductor from NEC-TOKIN with part number MPCG0740LR42C is
chosen.
Step Four
Set the output voltage.
The output voltage is determined by the VID settings. The actual voltage set point for each VID setting is listed in
Table 1. No external resistor dividers are needed for this design.
Step Five
Calculate CSLEW
.
VID pin transition and soft-start time is determined by CSLEW and 10 µA of internal current source.
ISLEW
10mA
CSLEW
=
=
= 10nF
1mV
SRDAC
ms
(7)
The slower slew rate is desired to minimize large inductor current perturbation during startup and voltage
transition, thus reducing the possibility of acoustic noise.
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Given the CSLEW, use Equation 8 to calculate the soft start time.
C
´ 0.9V
10nF´0.9V
SLEW
t
=
=
= 900 ms
SS
I
10mA
SLEW
(8)
(9)
Step Six
Calculate OCL.
The DC OCL level of TPS51462 design is determined by Equation 9,
1
1
´IP-P = 6A + ´1.5A = 6.75A
IOCL dc = IOCL valley
)
+
( )
(
2
2
The minimum valley OCL is 6 A over process and temperature, and IP-P = 1.5 A, the minimum DC OCL is
calculated to be 6.75A.
Step Seven
Determine the output capacitance.
To determine COUT based on transient and stability requirement, first calculate the the minimum output
capacitance for a given transient.
Equation 11 and Equation 10 can be used to estimate the amount of capacitance needed for a given dynamic
load step/release. Please note that there are other factors that may impact the amount of output capacitance for
a specific design, such as ripple and stability. Equation 11 and Equation 10 are used only to estimate the
transient requirement, the result should be used in conjunction with other factors of the design to determine the
necessary output capacitance for the application.
æ
ç
ö
÷
V
´ t
SW
2
VOUT
L ´ DI
´
+ t
MIN off
LOAD max
(
)
( )
ç
è
V
÷
ø
IN min
(
)
C
=
OUT min_under
(
)
æ
ç
ç
è
ö
÷
÷
ø
æ
ç
ö
÷
V
- V
VOUT
IN min
(
)
2´ DV
´
´ t
- t
´ V
VOUT
SW
LOAD insert
(
MIN off
( )
)
ç
è
V
÷
ø
IN min
(
)
(10)
(11)
2
L
´ DI
(
OUT
)
LOAD max
(
)
C
=
OUT min_over
(
)
2´ DV
´ V
VOUT
LOAD release
(
)
Equation 10 and Equation 11 calculate the minimum COUT for meeting the transient requirement, which is
72.9 µF assuming the following:
•
•
±3% voltage allowance for load step and release
MLCC capacitance derating of 60% due to DC and AC bias effect
In this reference design, 4, 22-µF capacitors are used in order to provide this amount of capacitance.
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Step Eight
Determine the stability based on the output capacitance COUT
.
In order to achieve stable operation. The 0-dB frequency, f0 should be kept less than 1/5 of the switching
frequency (1 MHz). (See Figure 3)
G
R
1
M
C
f =
´
´
= 150kHz
0
2p
C
OUT
R
S
where
•
RS = RDS(on) × GMC × RLOAD
(12)
(13)
.
f ´R ´ 2p´ C
OUT
150kHz ´53mW ´ 2p´88mF
0
S
R
=
=
» 5kW
C
G
1mS
M
Using 4, 22-µF capacitors, the compensation resistance, RC can be calculated to be approximately 5 kΩ.
The purpose of the comparator capacitor (CC) is to reduce the DC component to obtain high DC feedback gain.
However, as it causes phase delay, another zero to cancel this effect at f0 is needed. This zero can be
determined by values of CC and the compensation resistor, RC.
f
1
0
f
=
=
Z
2p´R ´ C
10
C
C
(14)
And since RC has previously been derived, the value of CC is calculated to be 2.2 nF. In order to further boost
phase margin, a value of 3.3-nF is chosen for this reference design.
Step Nine
Select decoupling and peripheral components.
For TPS51462 peripheral capacitors use the following minimum values of ceramic capacitance. X5R or better
temperature coefficient is recommended. Tighter tolerances and higher voltage ratings are always appropriate.
•
•
•
•
•
V5DRV decoupling ≥ 2.2 µF, ≥ 10 V
V5FILT decoupling ≥ 1 µF, ≥10 V
VREF decoupling 0.22 µF to 1 µF, ≥ 4 V
Bootstrap capacitors ≥ 0.1 µF, ≥ 10 V
Pull-up resistors on PGOOD, 100 kΩ
Layout Considerations
Good layout is essential for stable power supply operation. Follow these guidelines for an efficient PCB layout.
•
Connect PGND pins (or at least one of the pins) to the thermal PAD underneath the device. Also connect
GND pin to the thermal PAD underneath the device. Use four vias to connect the thermal pad to internal
ground planes.
•
•
Place VIN, V5DRV, V5FILT and 2VREF decoupling capacitors as close to the device as possible.
Use wide traces for the VIN, VOUT, PGND and SW pins. These nodes carry high current and also serve as
heat sinks.
•
•
Place feedback and compensation components as close to the device as possible.
Keep analog signals (SLEW, COMP) away from noisy signals (SW, VBST).
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Dec-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS51462RGER
TPS51462RGET
ACTIVE
ACTIVE
VQFN
VQFN
RGE
RGE
24
24
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS51462RGER
TPS51462RGET
VQFN
VQFN
RGE
RGE
24
24
3000
250
330.0
180.0
12.4
12.4
4.25
4.25
4.25
4.25
1.15
1.15
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS51462RGER
TPS51462RGET
VQFN
VQFN
RGE
RGE
24
24
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
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