FX007_技术文档

TPS51650, TPS59650

www.ti.com

SLUSAV7 –JANUARY 2012

Dual-Channel (3-Phase CPU/2-Phase GPU) SVID, D-CAP+™ Step-Down Controller for

IMVP-7 V_COREwith Two Integrated Drivers

1

FEATURES

APPLICATIONS

2

•

Intel IMVP-7 Serial VID (SVID) Compliant

Supports CPU and GPU Outputs

•

IMVP-7 V_COREApplications for Adapter,

Battery, NVDC or 3-V, 5-V, and 12-V Rails

•

CPU Channel One-Phase, Two-Phase, or

Three-Phase

DESCRIPTION

The TPS51650 and TPS59650 are dual-channel, fully

SVID compliant IMVP-7 step-down controllers with

two integrated gate drivers. Advanced control

features such as D-CAP™+ architecture with

overlapping pulse support (undershoot reduction,

USR) and overshoot reduction (OSR) provide fast

transient response, lowest output capacitance and

high efficiency. All of these controllers also support

single-phase operation for light loads. The full

compliment of IMVP-7 I/O is integrated into the

controllers including dual PGOOD signals, ALERT

and VR_HOT. Adjustable control of V_COREslew rate

and voltage positioning round out the IMVP-7

features. In addition, the controllers' CPU channel

includes two high-current FET gate drivers to drive

high-side and low-side N-channel FETs with

exceptionally high speed and low switching loss. The

TPS51601 driver is used for the third phase of the

CPU and the two phases of the GPU channel.

•

One-Phase or Two-Phase GPU Channel

Full IMVP-7 Mobile Feature Set Including

Digital Current Monitor

•

8-Bit DAC with 0.250-V to 1.52-V Output Range

Optimized Efficiency at Light and Heavy Loads

V_COREOvershoot Reduction (OSR)

V_COREUndershoot Reduction (USR)

Accurate, Adjustable Voltage Positioning

8 Independent Frequency Selections per

Channel (CPU/GPU)

•

Patent Pending AutoBalance™ Phase

Balancing

•

Selectable 8-Level Current Limit

3-V to 28-V Conversion Voltage Range

Two Integrated Fast FET Drivers w/Integrated

Boost FET

These controllers are packaged in a space-saving,

thermally enhanced 48-pin QFN and are rated to

operate from –10°C to 105°C.

•

Selectable Address (TPS59650 only)

Small 6 × 6 , 48-Pin, QFN, PowerPAD™

Package

SIMPLIFIED APPLICATION

Internal

FET Driver

3-phase CPU

Controller

TPS51601

FET Driver

CPU Power Stage

VCC_CPU

Internal

FET Driver

IMVP-7

SVID Interface

Processor

TPS51601

FET Driver

2-phase GPU

Controller

TPS51601

FET Driver

GPU Power Stage

VCC_GFX

TPS51650

UDG-12003

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

D-CAP+, PowerPAD, D-CAP are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS51650, TPS59650

SLUSAV7 –JANUARY 2012

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION⁽¹⁾⁽²⁾

ORDERABLE

NUMBER

TRANSPORT

MEDIA

MINIMUM

QUANTITY

T_A

PACKAGE

PINS

ECO PLAN

TPS51650RSLT

TPS51650RSLR

TPS59650RSLT

TPS59650RSLR

250

2500

250

–10°C to 105°C

Green (RoHS and

no Sb/Br)

Plastic Quad Flat

Pack (QFN)

48

Tape-and-reel

–40°C to 105°C

2500

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾⁽²⁾

over operating free-air temperature range (unless otherwise noted)

MIN TYP MAX UNIT

VBAT

–0.3

–6.0

–0.3

32

CSW1, CSW2

V

CDH1 to CSW1; CDH2 to CSW2; CBST1 to CSW1; CBST2 to CSW2

6.0

CTHERM, CCOMP, CF-IMAX, GF-IMAX, GCOMP, GTHERM,

V5DRV, V5

–0.3

6.0

Input voltage

V

COCP-R, CCSP1, CCSP2, CCSP3, CCSN1, CCSN2, CCSN3, CVFB,

CGFB, V3R3, VR_ON, VCLK, VDIO, SLEWA, GGFB, GVFB, GCSN1,

GCSP1, GOCP-R

–0.3

3.6

PGND

–0.3

2

0.3

1.8

3.6

6.0

VREF

Output voltage

CPGOOD, ALERT, VR_HOT, GPGOOD

CPWM3, GPWM1, GPWM2, GSKIP, CDL1, CDL2

(HBM) QSS 009-105 (JESD22-A114A)

(CDM) QSS 009-147 (JESD22-C101B.01)

V

kV

V

Electrotatic discharge

500

-40

Operating junction temperature, T_J

Storage temperature, T_stg

125 °C

150 °C

-55

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to the network ground terminal unless otherwise noted.

THERMAL INFORMATION

TPS51650

TPS59650

THERMAL METRIC⁽¹⁾

UNITS

RSL

48 PINS

θ_JA

Junction-to-ambient thermal resistance

31.7

19.8

7.1

θ_JCtop

θ_JB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.3

ψ_JB

7.1

θ_JCbot

2.1

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

2

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SLUSAV7 –JANUARY 2012

RECOMMENDED OPERATING CONDITIONS

MIN

–0.1

–3.0

TYP

MAX UNIT

VBAT

28

30

CSW1, CSW2

CDH1 to CSW1; CDH2 to CSW2; CBST1 to CSW1; CBST2 to

CSW2

–0.1

5.5

V5DRV, V5

4.5

3.1

5.5

3.5

V3R3

Input voltage

CCOMP, GCOMP

CTHERM, GTHERM

CF-IMAX, GF-IMAX, COCP-R, GOCP-R

–0.1

0.1

2.5

3.6

1.7

V

0.1

CCSP1, CCSP2, CCSP3, CCSN1, CCSN2, CCSN3, CVFB, CGFB,

GGFB, GVFB, GCSN1, GCSP1, GCSN2, GCSP2

–0.1

1.7

VR_ON, VCLK, VDIO, SLEWA

–0.1

–10

3.5

0.1

PGND

VREF

1.72

V_V3R3

V_V5

Output voltage

CPGOOD, ALERT, VR_HOT, GPGOOD,

CPWM3, GPWM1, GSKIP, CDL1, CDL2

TPS51650

V

105

Operating free air temperature, T_A

°C

TPS59650

–40

105

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TPS51650, TPS59650

SLUSAV7 –JANUARY 2012

www.ti.com

ELECTRICAL CHARACTERISTICS

over recommended free-air temperature range, V_V5= V_V5DRV= 5.0 V; V_V3R3= 3.3 V; V_xGFB= V_PGND= V_GND, V_xVFB= V_CORE

(Unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY: CURRENTS, UVLO AND POWER-ON RESET

I_V5+ I_V5DRV, V_VDAC< V_xVFB< (V_VDAC+ 100 mV),

VR_ON = ‘HI’

V5 supply current CPU: 3-phase

active GPU: 2-phase active

I_V5-5

7.5

5.5

11.0

mA

I_V5+ I_V5DRV, V_VDAC< V_xVFB< (V_VDAC+ 100 mV),

VR_ON = ‘HI’, V_GCSP2= 3.3 V

V5 supply current CPU: 3-phase

active GPU: OFF

I_V5-3

I_V5+ I_V5DRV, V_VDAC< V_xVFB< (V_VDAC+ 100 mV),

VR_ON = ‘HI’, SetPS = PS3

V5 supply current CPU: 3-phase

active GPU: 2-phase active⁽¹⁾

I_V5-PS3

I_V5STBY

V_UVLOH

V_UVLOL

V5DRV standby current

V5 UVLO 'OK' Threshold

V5 UVLO fault threshold

VR_ON = ‘LO’, I_V5+ I_V5DRV

Ramp up, VR_ON=’HI’,

10

4.35

4.10

20

4.50

4.30

µA

V

4.25

3.95

Ramp down, VR_ON = ’HI’,

V

V5 Power-ON Reset fault

latch⁽²⁾

V_PORV5

1.2

1.9

0.5

2.5

V

I_V3R3

V3R3 supply current

SVID bus idle, VR_ON = ‘HI’

VR_ON = ‘LO’

1.0

10

mA

µA

V

I_V3R3SBY

V_3UVLOH

V_3UVLOL

V_PORV3R3

V3R3 standby current

V3R3 UVLO 'OK' threshold

V3R3 UVLO fault threshold

Ramp up, VR_ON=’HI’,

Ramp down, VR_ON = ’HI’,

2.5

2.4

2.9

2.7

3.0

2.8

V

V3R3 Power-ON Reset fault

latch⁽²⁾

1.2

1.9

2.5

V

REFERENCES: DAC, VREF, VBOOT AND DRVL DISCHARGE FOR BOTH CPU AND GPU

V_VIDSTP

VID step size

Change VID0 HI to LO to HI

5

mV

0.25 ≤ V_xVFB≤ 0.595V,

I_{xPU_CORE}= 0 A, 0°C ≤ T_A≤ 85°C

TPS51650

TPS59650

TPS51650

TPS59650

TPS51650

–6

–7.5

–5

6

7.5

0.25 ≤ V_xVFB≤ 0.595V,

I_{xPU_CORE}= 0 A,

–40°C ≤ T_A≤ 105°C

V_DAC1

xVFB tolerance

0.6 ≤ V_xVFB≤ 0.995V,

I_{xPU_CORE}= 0 A, 0°C ≤ T_A≤ 85°C

5

mV

0.6 ≤ V_xVFB≤ 0.995V,

I_{xPU_CORE}= 0 A,

–40°C ≤ T_A≤ 105°C

–7.5

–0.5%

7.5

1.000V ≤ V_xVFB≤ 1.520 V,

I_{xPU_CORE}= 0 A, 0°C ≤ T_A≤ 85°C

0.5%

V_DAC2

xVFB tolerance

VREF Output

1.000V ≤ V_xVFB≤ 1.520 V,

I_{xPU_CORE}= 0 A,

–40°C ≤ T_A≤ 105°C

TPS59650 –0.75%

0.75%

1.745

V_VREF

4.5 V ≤ V_V5≤ 5.5 V, I_VREF= 0 A

0 µA ≤ I_VREF≤ 500 µA

1.655

1.700

–0.1

0.1

V

V_VREFSRCVREF output source

–4

mV

V_VREFSNK

V_DLDQ

VREF output sink

–500 µA ≤ I_VREF≤ 0 µA

4

DRVL discharge threshold

Soft-stop transistor turns on at this point.

200

300

VOLTAGE SENSE: xVFB AND xGFB FOR BOTH CPU AND GPU

I_xVFB

xVFB input bias current

xGFB input bias current

xGFB/GND gain

V_xVFB= 2 V, V_xGFB= 0 V

20

-20

1

40

µA

I_xGFB

-40

A_GAINGND

V/V

(1) 3-phase CPU goes to 1-phase in PS3 2-phase GPU goes to 1-phase in PS3

(2) Specified by design. Not production tested.

4

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SLUSAV7 –JANUARY 2012

ELECTRICAL CHARACTERISTICS (continued)

over recommended free-air temperature range, V_V5= V_V5DRV= 5.0 V; V_V3R3= 3.3 V; V_xGFB= V_PGND= V_GND, V_xVFB= V_CORE

(Unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CURRENT SENSE: OVERCURRENT, ZERO CROSSING, VOLTAGE POSITIONING AND PHASE BALANCING

TPS51650

TPS59650

TPS51650

TPS59650

TPS51650

TPS59650

TPS51650

TPS59650

TPS51650

TPS59650

TPS51650

TPS59650

TPS51650

TPS59650

TPS51650

TPS59650

4.6

3.9

7.0

9.2

R_xOCP-R= 20 kΩ

R_xOCP-R= 24 kΩ

R_xOCP-R= 30 kΩ

R_xOCP-R= 39 kΩ

R_xOCP-R= 56 kΩ

R_xOCP-R= 75 kΩ

R_xOCP-R= 100 kΩ

R_xOCP-R= 150 kΩ

7.6

10.0

14.0

19.0

25.0

32.0

40.0

49.0

12.1

16.2

21.2

27.2

34.5

42.5

51.9

6.7

11.6

11.0

16.5

15.6

22.3

21.2

29.2

28.3

37.1

35.6

46.1

45.6

OCP voltage (valley current

limit)

V_OCPP

mV

V_{IMAX_MIN}= 133 mV, value of xIMAX,

V_IMAX= V_REF× I_MAX/ 255

20

A

V_IMAX

IMAX values both channels

CS pin input bias current

V_{IMAX_MAX}= 653mV, value of xIMAX

CSPx and CSNx

98

A

I_CS

–1.0

0.2

1.0

µA

xVFB input bias current,

discharge

I_xVFBDQ

End of soft-stop, xVFB = 100 mV

xVFB = 1 V

90

125

180

µA

µS

TPS51650

TPS59650

486

480

497

518

Droop amplifier

transconductance

G_M-DROOP

(V_CSP1– V_CSN1) = (V_CSP2– V_CSN2) =

(V_CSP3– V_CSN3) = V_{OCPP_MIN}

I_{BAL_TOL}

A_CSINT

Internal current share tolerance

Internal current sense gain

–3%

+3%

Gain from CSPx – CSNx to PWM comparator

11.65

12.00

12.30

V/V

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ELECTRICAL CHARACTERISTICS (continued)

over recommended free-air temperature range, V_V5= V_V5DRV= 5.0 V; V_V3R3= 3.3 V; V_xGFB= V_PGND= V_GND, V_xVFB= V_CORE

(Unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

TIMERS: SLEW RATE, ISLEW, ADDR, ON-TIME AND I/O TIMING

V_BOOT> 0 V, SLEWRATE = 12 mV/µs, no faults,

t_STARTUP1

Start-up time

time from VR_ON until the controller responds to

SVID commands

5

ms

SLEWRATE = 12mV/µs, VR_ON goes ‘HI’,

VR_ON goes ‘LO = ‘Soft-stop’

SL_STRTSTPxVFB slew soft-start / soft-stop

1.25

1.50

1.75 mV/µs

VSLEWA ≤ 0.30V (Also disables SVID CLK timer)

V_SLEWA= 0.4 V

10.0

3

12.0

4

14.5

5

V_SLEWA= 0.6 V

7

8

10

0.75 V ≤ V_SLEWA≤ 0.85 V

V_SLEWA= 1.0 V

10.0

12.0

16

20

23

26

14.5

SL_SET

Slew rate setting

mV/µs

V_SLEWA= 1.2 V

V_SLEWA= 1.4 V

V_SLEWA= 1.6 V

Time from xVFB out of +220 mV VDAC boundary

to xPGOOD low.

t_PGDDGLTOxPGOOD deglitch time

t_PGDDGLTUxPGOOD deglitch time

5

15

µs

Time from xVFB out of -315 mV VDAC boundary

to xPGOOD low.

50

100

TPS51650

TPS59650

TPS51650

TPS59650

TPS51650

TPS59650

TPS51650

TPS59650

TPS51650

TPS59650

TPS51650

TPS59650

TPS51650

TPS59650

TPS51650

TPS59650

300

298

245

243

210

208

184

181

169

166

153

150

140

137

130

127

317

261

223

196

181

164

151

140

340

284

242

216

201

184

171

160

R_CF= 20 kΩ, V_BAT= 12 V,

V_DAC= 1.1 V (250 kHz)

R_CF= 24 kΩ, V_BAT= 12 V,

V_DAC= 1.1 V (300 kHz)

R_CF= 30 kΩ, V_BAT= 12 V,

V_DAC= 1.1 V (350 kHz)

R_CF= 39 kΩ, V_BAT= 12 V,

V_DAC= 1.1 V (400 kHz)

t_{TON_CPU}

CPU on-time

ns

R_CF= 56 kΩ, V_BAT= 12 V,

V_DAC= 1.1 V (450 kHz)

R_CF= 75 kΩ, V_BAT= 12 V,

V_DAC= 1.1 V (500 kHz)

R_CF= 100 kΩ, V_BAT= 12 V,

V_DAC= 1.1 V (550 kHz)

R_CF= 150 kΩ, V_BAT= 12 V,

V_DAC= 1.1 V (600 kHz)

6

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ELECTRICAL CHARACTERISTICS (continued)

over recommended free-air temperature range, V_V5= V_V5DRV= 5.0 V; V_V3R3= 3.3 V; V_xGFB= V_PGND= V_GND, V_xVFB= V_CORE

(Unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

TIMERS: SLEW RATE, ISLEW, ADDR, ON-TIME AND I/O TIMING (Continued)

TPS51650

TPS59650

TPS51650

TPS59650

TPS51650

TPS59650

TPS51650

TPS59650

TPS51650

TPS59650

TPS51650

TPS59650

TPS51650

TPS59650

TPS51650

TPS59650

282

280

233

231

208

205

185

182

172

169

158

154

147

145

141

134

323

270

236

210

195

178

166

157

150

377

319

280

248

230

211

203

193

225

R_GF= 20 kΩ, V_BAT= 12 V,

V_DAC= 1.1 V (275 kHz)

R_GF= 24 kΩ, V_BAT= 12 V,

V_DAC= 1.1 V (330 kHz)

R_GF= 30 kΩ, V_BAT= 12 V,

V_DAC= 1.1 V (385 kHz)

R_GF= 39 kΩ, V_BAT= 12 V,

V_DAC= 1.1 V (440 kHz)

t_{TON_GPU}

GPU on-time

ns

R_GF= 56 kΩ, V_BAT= 12 V,

V_DAC= 1.1 V (495 kHz)

R_GF= 75 kΩ, V_BAT= 12 V,

V_DAC= 1.1 V (550 kHz)

R_GF= 100 kΩ, V_BAT= 12 V,

V_DAC= 1.1 V (605 kHz)

R_GF= 150 kΩ, V_BAT= 12 V,

V_DAC= 1.1 V (660 kHz)

t_MIN

Controller minimum off time

Fixed value

ns

ACK of SetVID-x command to start of voltage

ramp

t_VCCVID

VID change to xVFB change⁽³⁾

2

µs

t_VRONPGD

t_VRTDGLT

R_SFTSTP

VR_ON low to xPGOOD low

VR_HOT deglitch time

60

0.2

100

0.5

ns

ms

Ω

Soft-stop transistor resistance

Connect to CVFB, GVFB

500

740

1100

PROTECTION: OVP, UVP PGOOD, VR_HOT, ‘FAULTS OFF’ AND INTERNAL THERMAL SHUTDOWN

Fixed OVP voltage threshold

voltage

V_OVPH

V_PGDH

V_PGDL

VCSN1 or VGCSN > V_OVPHfor 1 µs, DRVL → ON

1.67

190

1.72

220

1.77

245

V

Measured at the xVFB pin wrt/VID code,

device latches OFF

xPGOOD high threshold

mV

Measured at the xVFB pin wrt/VID code,

device latches OFF

xPGOOD low threshold

–348

–315

–278

bit0 of xTHERM register = high

755

657

611

569

532

498

783

680

638

598

559

523

810

707

665

624

585

549

bit1 of xTHERM register also is high

bit2 of xTHERM register also is high

bit3 of xTHERM register also is high

bit4 of xTHERM register also is high

bit5 of xTHERM register also is high

IMVP-7 thermal bit voltage

definition

V_THERM

mV

bit6 of xTHERM register also is high,

ALERT goes low

462

430

455

514

481

bit7 of xTHERM register also is high,

VR_HOT goes low

455

410

CDLx goes low, CDHx goes low

Leakage current, V_xTHERM= 1 V

373

428

2

I_THRM

TH_INT

THERM current

–2

µA

°C

Internal controller thermal

Shutdown⁽³⁾

Latch off controller

155

20

Controller thermal SD

hysteresis⁽³⁾

TH_HYS

Cooling required before converter can be reset

°C

(3) Specified by design. Not production tested.

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ELECTRICAL CHARACTERISTICS (continued)

over recommended free-air temperature range, V_V5= V_V5DRV= 5.0 V; V_V3R3= 3.3 V; V_xGFB= V_PGND= V_GND, V_xVFB= V_CORE

(Unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LOGIC (VCLK, VDIO, ALERT, VR_HOT, VR_ON) INTERFACE PINS: I/O VOLTAGE AND CURRENT

VDIO, ALERT, VR_HOT, pull-down resistance at

0.31 V

R_RSVIDL

R_RPGDL

I_VRTTLK

Open drain pull down resistance

4

8

36

13

50

Ω

Open drain pull down resistance xPGOOD pull-down resistance at 0.31 V

VR_HOT, xPGOOD, Hi-Z leakage,

Open drain leakage current

-2

0.2

2

µA

apply 3.3-V in off state

V_IL

Input logic low

VCLK, VDIO

0.45

V

V_IH

Input logic high

0.65

(4)

V_HYST

V_{VR_ONL}

V_{VR_ONH}

I_{VR_ONH}

Hysteresis voltage

VR_ON logic low

VR_ON logic high

I/O 3.3 V leakage

50

mV

V

0.3

25

0.8

8

V

Leakage current , V_{VR_ON}= 1.1 V

µA

OVERSHOOT AND UNDERSHOOT REDUCTION (OSR/USR) THRESHOLD SETTING

V_XOCP-R= 0.2 V

V_XOCP-R= 0.4 V

V_XOCP-R= 0.6 V

106

156

207

257

308

409

510

610

40

V_XOCP-R= 0.8 V

V_XOCP-R= 1.0 V

V_XOCP-R= 1.2 V

V_XOCP-R= 1.4 V

V_XOCP-R= 1.6 V

V_XOCP-R= 0.2 V

V_XOCP-R= 0.4 V

V_XOCP-R= 0.6 V

V_XOCP-R= 0.8 V

V_XOCP-R= 1.0 V

V_XOCP-R= 1.2 V

V_XOCP-R= 1.4 V

V_XOCP-R= 1.6 V

OSR voltage set (COCP-R pin

for CPU GOCP-R for GPU)

V_OSR

mV

60

80

120

160

200

240

OFF

USR voltage set (COCP-R pin

for CPU GOCP-R for GPU)

V_USR

mV

V_{OSR_ON}/V USR enabled (both CPU and

GSKIP voltage at start-up

0.15

1.1

GPU)

USR_ON

USR OFF setting (both CPU

V_{USR_OFF}

and GPU)

0.4

1.4

V

OSR OFF setting (both CPU

V_{OSR_OFF}

and GPU)

GSKIP voltage at start-up

All settings

(5)

V_OSRHYS

OSR/USR voltage hysteresis

5

mV

(4) Specified by design. Not production tested.

(5) Specified by design. Not production tested.

8

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ELECTRICAL CHARACTERISTICS (continued)

over recommended free-air temperature range, V_V5= V_V5DRV= 5.0 V; V_V3R3= 3.3 V; V_xGFB= V_PGND= V_GND, V_xVFB= V_CORE

(Unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DRIVERS: HIGH-SIDE, LOW-SIDE, CROSS CONDUCTION PREVENTION AND BOOST RECTIFIER

(V_CBSTx– V_CSWx) = 5 V, ‘HI’ state,

(V_VBST– V_VDRVH) = 0.25 V

1.2

0.8

2.5

R_DRVH

DRVH On-resistance

Ω

(V_CBSTx– V_CSWx) = 5 V, ‘LO’ state,

(V_DRVH– V_CSWx) = 0.25 V

V_CDHx= 2.5 V, (V_CBSTx– V_CSWx) = 5 V, Source

V_CDHx= 2.5 V, (V_CBSTx– V_CSWx) = 5 V, Sink

2.2

15

0.9

0.4

2.7

6

A

I_DRVH

DRVH sink/source current⁽⁶⁾

DRVH transition time

40

2

ns

t_DRVH

CDHx 10% to 90% or 90% to 10%, C_CDHx= 3 nF

‘HI’ State, (V_V5DRV– V_VDRVL) = 0.25 V

‘LO’ State, (V_VDRVL– V_PGND)= 0.2 V

V_CDLx= 2.5 V, Source

R_DRVL

DRVL ON resistance

Ω

1

A

I_DRVL

DRVL sink/source current⁽⁶⁾

DRVL transition time

V_CDLx= 2.5 V, Sink

V_CDLx90% to 10%, C_CDLx= 3 nF

V_CDLx10% to 90%, C_CDLx= 3 nF

V_CSWxfalls to 1 V to V_CDLxrises to 1 V

CDLx falls to 1 V to CDHx rises to 1 V

(V_V5DRV– V_VBST), I_F= 5 mA

15

25

10

0.1

40

t_DRVL

ns

8

5

t_NONOVLP

Driver non overlap time

R_DS(on)

I_BSTLK

BST on-resistance

22

1

Ω

BST switch leakage current

V_VBST= 34 V, V_CSWx= 28 V

µA

PWM and SKIP OUTPUT: I/O Voltage and Current

V_PWML

V_PWMH

V_SKIPL

xPWMy output low level

xPWMy output high level

xSKIP low-level output voltage

xSKIP high-level output voltage

xPWM leakage

0.3

0.1

V

4.2

V

V_SKIPH

V_PW(leak)

V

Tri-state, V_xPWMx= 5 V

µA

(6) Specified by design. Not production tested.

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DEVICE INFORMATION

RSL PACKAGE

48 PINS

(TOP VIEW)

1

2

36

35

34

33

32

31

30

29

28

27

26

25

CTHERM

CPWM3

GPWM2

GPWM1

GSKIP

COCP-R

CF-IMAX

CCSP1

CCSN1

CCSN2

CCSP2

CCSP3

CCSN3

CCOMP

CVFB

3

4

5

GTHERM

GCSN2

GCSP2

GCSP1

GCSN1

GCOMP

GVFB

6

TPS51650

7

8

9

10

11

12

CGFB

GGFB

PIN FUNCTIONS

I/O

DESCRIPTION

NAME

NO.

19

46

39

5

ALERT

CBST1

CBST2

CCSN1

CCSN2

CCSN3

O

I

SVID interrupt line, open drain. Route between VCLK and VDIO to prevent cross-talk.

Top N-channel FET bootstrap voltage input for CPU phase 1.

I

Top N-channel bootstrap voltage input for CPU phase 2.

Negative current sense inputs for the CPU converter. Connect to the most negative node of current sense

resistor or inductor DCR sense network. CCSN1 has a secondary OVP comparator.

6

I

O

I

9

CCOMP

CCSP1

CCSP2

CCSP3

CDH1

10

4

Output of GM error amplifier for the CPU converter. A resistor to VREF sets the droop gain.

Positive current sense inputs for the CPU converter. Connect to the most positive node of current sense resistor

or inductor DCR sense network. Tie CCSP3, 2 or 1 (in that order) to V3R3 to disable the phase. Tie CCSP1 to

V3R3 to run the GPU converter only.

7

8

47

38

44

41

O

Top N-channel FET gate drive output for CPU phase 1.

Top N-channel FET gate drive output for CPU phase 2.

Synchronous N-channel FET gate drive output for CPU phase 1.

Synchronous N-channel FET gate drive output for CPU phase 2.

CDH2

CDL1

CDL2

10

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I/O

DESCRIPTION

Voltage divider to VREF. A resistor to GND sets the operating frequency of the CPU converter. The voltage level

NAME

NO.

CF-IMAX

3

I

sets the maximum operating current of the CPU converter. The IMAX value is an 8-bit A/D where V_IMAX= V_REF

I_MAX/ 255. Both are latched at start-up.

×

Voltage sense return tied for the CPU converter. Tie to GND with a 10-Ω resistor to close feedback when the

microprocessor is not in the socket.

CGFB

12

2

Resistor to GND (R_COCP) selects 1 of 8 OCP levels (per phase, latched at start-up) of the CPU converter. Also,

voltage on this pin sets 1 of 8 USR/OSR levels for CPU converter.

COCP-R

I

CPGOOD

CSW1

17

45

40

36

O

IMVP-7_PWRGD output for the CPU converter. Open-drain.

I/O Top N-channel FET gate drive return for CPU phase 1.

I/O Top N-channel FET gate drive return for CPU phase 2.

CSW2

CPWM3

O

PWM control for the external driver, 5V logic level.

Thermal sensor connection for the CPU converter. A resistor connected to VREF forms a divider with an NTC

thermistor connected to GND.

CTHERM

CVFB

1

I/O

Voltage sense line tied directly to V_COREof the CPU converter. Tie to V_COREwith a 10-Ω resistor to close

feedback when µP is not in the socket. The soft-stop transistor is on this pin

11

I

GCOMP

GCSN1

GCSN2

GCSP1

27

28

31

29

O

I

Output of g_Merror amplifier for the GPU converter. A resistor to VREF sets the droop gain.

Negative current sense input for the GPU converter. Connect to the most negative node of current sense resistor

or inductor DCR sense network.

I

Positive current sense input for the GPU converter. Connect to the most positive node of current sense resistor

or inductor DCR sense network. Tie GCSP2 to V3R3 to disable the phase. Tie GCSP1 and GCSP2 to V3R3 to

disable completely the GPU converter.

GCSP2

GGFB

30

I

Voltage sense return tied for the GPU converter. Tie to GND with a 10-Ω resistor to close feedback when the

microprocessor is not in the socket.

25

24

I

Voltage divider to VREF. R to GND sets the operating frequency of the GPU converter. The voltage level sets

GF-IMAX

the maximum operating current of the GPU converter. The IMAX value is an 8-bit A/D where V_IMAX= V_REF

I_MAX/ 255. Both are latched at start-up.

×

13

I

Resistor to GND (R_GOCP) selects 1 of 8 OCP levels (per phase, latched at start-up) of the GPU converter. Also,

voltage on this pin sets 1 of 8 USR/OSR levels for GPU converter.

GOCP-R

GPGOOD

GPWM1

GPWM2

23

34

35

33

O

IMVP-7_PWRGD output for the GPU converter. Open-drain.

PWM control input for the external driver for the two phases of GPU channel (5-V logic level).

Skip mode control of the external driver for the GPU converter; 5-V logic level. Logic HI = FCCM; LO = SKIP. A

defined voltage level on this pin at start-up can turn OSR OFF or USR OFF.

GSKIP

32

26

I/O Thermal sensor input for the GPU converter. A resistor connected to VREF forms a divider with an NTC

thermistor connected to GND.

GTHERM

I

Voltage sense line tied directly to V_GFXof the GPU converter. Tie to V_GFXwith a 10-Ω resistor to close feedback

GVFB

PGND

when the microprocessor is not in the socket. The soft-stop transistor is on this pin

42

22

–

Synchronous N-channel FET gate drive return.

I

The voltage at start-up sets 1 of 7 slew rates for both converters. The SLOW rate is SLEWRATE/4. Soft-start

and soft-stop rates are SLEWRATE/8. This value is latched at start-up. For TPS59650, the resistor to GND sets

the base SVID address.

SLEWA

V5

48

43

I

5-V power input for analog circuits; connect through resistor to 5-V plane and bypass to GND with ≥1 µF ceramic

capacitor

Power input for the gate drivers; connected with an external resistor to V5F; decouple with a ≥2.2 µF ceramic

V5DRV

V3R3

capacitor.

15

37

I

3.3-V power input; bypass to GND with ≥1 µF ceramic cap.

Provides VBAT information to the on-time circuits for both converters. A 10-kΩ series resistor protects the

VBAT

adjacent pins from inadvertent shorts due to solder bridges or mis-probing during test.

VCLK

VDIO

18

20

14

16

21

I

SVID clock. 1-V logic level.

I/O SVID digital I/O line. 1-V logic level.

VREF

VR_ON

O

I

1.7-V, 500-µA reference. Bypass to GND with a 0.22-µF ceramic capacitor.

IMVP-7 VR enable; 1V I/O level; 100-ns de-bounce. Regulator enters controlled soft-stop when brought low.

O

IMVP-7 thermal flag open drain output – active low. Typically pulled up to 1-V logic level through 56 Ω. Fall time

< 100 ns. 1-ms de-glitch using consecutive 1-ms samples.

VR_HOT

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I/O

DESCRIPTION

Thermal pad and analog circuit reference; tie to a quiet area in the system ground plane with multiple vias.

NAME

NO.

PAD

GND

–

12

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TYPICAL CHARACTERISTICS

3-Phase Configuration, 94-A CPU

0.70

1.10

V_IN= 9 V

PS = PS0

PS = PS1

0.68

0.65

0.62

0.60

0.57

0.55

0.53

0.50

V_VID= 1.05 V

V_IN=20 V

Spec Maximum

Spec Minimum

V_VID= 0.6 V

1.05

1.00

0.95

0.90

0.85

0.80

V_IN= 9 V

V_IN=20 V

Spec Maximum

Spec Minimum

0

10

20

30

40

50

60

70

80

90 100

0

2

4

6

8

10

12

14

16

18 20

Output Current (A)

G001

G002

Figure 1. Output Voltage vs. Load Current in PS0

Figure 2. Output Voltage vs. Load Current in PS1

95

PS = PS0

V_VID= 1.05 V

PS = PS1

V_VID= 0.6 V

90

85

80

75

70

65

90

85

80

75

70

65

V_IN= 9 V

V_IN= 20 V

V_IN= 9 V

V_IN= 20 V

0

10

20

30

40

50

60

70

80

90

0

2

4

6

8

10

12

14

16

18 20

Output Current (A)

G003

G004

Figure 3. Efficiency vs. Load Current in PS0

Figure 4. Efficiency vs. Load Current in PS1

Figure 5. Switching Ripple in PS0, V_IN= 9 V

Figure 6. Switching Ripple in PS0, V_IN= 20 V

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TYPICAL CHARACTERISTICS

3-Phase Configuration, 94-A CPU (continued)

Figure 7. Load Transient: V_IN= 9 V , Load-step = 66 A

Figure 8. Load Transient, V_IN= 20 V, Load step = 66 A

Figure 9. Load Transient, V_IN= 9 V, Load step = 66 A

Figure 10. Load Transient, V_IN= 20 V, Load step = 66 A

Figure 11. Start-Up and PGOOD

Figure 12. Soft-Stop

14

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TYPICAL CHARACTERISTICS

3-Phase Configuration, 94-A CPU (continued)

Figure 13. Dynamic VID: V_IN= 20 V, SetVIDSlow = 0.6 V,

Figure 14. Dynamic VID: V_IN= 20 V, SetVIDFast = 0.6 V,

SetVIDFast = 1.05 V

SetVIDSlow = 1.05 V

Figure 15. Dynamic VID: V_IN= 20 V, SetVIDDecay = 0.6 V,

SetVIDFast = 1.05 V

Figure 16. PS Change: V_IN= 20 V, PS0 to PS1 Toggle

50

40

225

180

135

90

0.0045

225

180

135

90

V_IN= 20 V

Magnitude

Phase

Target

0.0040

0.0035

0.0030

0.0025

0.0020

0.0015

0.0010

0.0005

30

20

10

45

0

−10

−20

−30

−40

−50

−45

−90

−135

−180

−225

−45

−90

−135

−180

−225

GAIN

PHASE

100

1k

10k

100k

1M

100

1k

10k

100k

1M

Frequency (Hz)

G005

G006

Figure 17. Gain-Phase Bode Plot

Figure 18. Output Impedance

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TYPICAL CHARACTERISTICS

2-Phase Configuration, 46-A GPU

1.2500

1.2000

1.1500

0.6500

PS = PS0

V_VID= 1.23 V

PS = PS1

V_VID= 0.6 V

0.6250

0.6000

0.5750

0.5500

1.1000

V_IN= 9 V

V_IN=20 V

Spec Maximum

Spec Minimum

V_IN=20 V

Spec Maximum

Spec Minimum

1.0500

1.0000

0.5250

0.5000

0

5

10

15

20

25

30

35

40

45 50

0

2

4

6

8

10

12

14

16

18 20

Output Current (A)

G007

G008

Figure 19. Output Voltage Vs. Load Current in PS0

Figure 20. Output Voltage Vs. Load Current in PS0

100

95

PS = PS0

V_VID= 1.23 V

PS = PS1

V_VID= 0.6 V

90

85

80

75

70

65

60

55

95

90

85

80

75

V_IN= 9 V

V_IN= 20 V

V_IN= 9 V

V_IN= 20 V

0

5

10

15

20

25

30

35

40

45 50

0

2

4

6

8

10

12

14

16

18 20

Output Current (A)

G009

G010

Figure 21. Efficiency Vs. Load Current in PS0

Figure 22. SEfficiency Vs. Load Current in PS0

Figure 23. Switching Ripple in PS0, V_IN= 9 V

Figure 24. Switching Ripple in PS0, V_IN= 20 V

16

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TYPICAL CHARACTERISTICS

2-Phase Configuration, 46-A GPU (continued)

Figure 25. Load Transient, V_IN= 9 V, Load Step = 37 A

Figure 26. Load Transient, V_IN= 20 V, Load Step = 37 A

Figure 27. Load Transient, V_IN= 9 V, Load Step = 37 A

Figure 28. Load Transient, V_IN= 20 V, Load Step = 37 A

Figure 29. Start-Up and PGOOD

Figure 30. Soft-Stop

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TYPICAL CHARACTERISTICS

2-Phase Configuration, 46-A GPU (continued)

Figure 31. Dynamic VID: V_IN= 20 V, SetVIDSlow = 0.6 V,

Figure 32. Dynamic VID: V_IN= 20 V, SetVIDDecay = 0.6 V,

SetVIDFast = 1.05 V

SetVIDSlow = 1.05 V

Figure 33. Dynamic VID: V_IN= 20 V, SetVIDDecay = 0.6 V,

SetVIDFast 1.05 V

Figure 34. PS Change: V_IN= 20 V, PS0 to PS1 Toggle

50

40

225

V_IN= 20 V

180

30

135

90

20

10

45

0

−10

−20

−30

−45

−90

−135

−180

−225

GAIN

PHASE

−40

−50

100

1k

10k

100k

1M

Frequency (Hz)

G011

Figure 35. Output Impedance

18

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FUNCTIONAL BLOCK DIAGRAM

CCOMP

10

CPWM1

CPWM2

CPWM3

CF-IMAX

Ramp

Comparator

On-Time

1

43 V5DRV

46 CBST1

CVFB 11

+

A

Gm

+

CLK1

CLK2

CLK3

CGFB 12

47 CDH1

Smart

Driver

+

CLK

Error

Phase

Manager

On-Time

2

CCSP1

4

DAC0

Amplifier

Integrator

45 CSW1

+

IS1

IS2

Acs

44 CDL1

42 PGND

CCSN1

CCSP2

5

6

USR

OSR

OSR/USR

On-Time

3

+

Current

Sharing

Circuitry

39

Acs

CBST2

+

ISHARE

CCSN2

CCSP3

7

8

+

38 CDH2

40 CSW2

41 CDL2

36 CPWM3

Smart

Driver

?

+

COCP

CPx

CVD

GISUM

GIS1

GIS2

GIS3

+

IS3

CPU

Acs

Logic Protection

and Status Circuitry

CCSN3

9

GCOMP 27

CPWM1

CPWM2

CPWM3

CF-IMAX

Ramp

Comparator

On-Time

1

GVFB 26

GGFB 25

GCSP1 29

34 GPWM1

35 GPWM2

+

A

Gm

+

CLK1

CLK2

+

CLK

Error

Phase

Manager

On-Time

2

DAC0

Amplifier

Integrator

+

IS1

IS2

Acs

GCSN1 28

GCSP2 30

USR

OSR

OSR/USR

33 GSKIP

+

Current

Sharing

Circuitry

Acs

+

ISHARE

GCSN2 31

+

?

GOCP

GPx

VR_ON 16

CPGOOD 17

VCLK 18

CPU

GVD

GISUM

GIS1

GIS2

Logic Protection

and Status Circuitry

DAC0

and

DAC1

DAC0

DAC1

ALERT 19

VDIO 20

SVID

Interface

VR_HOT 21

GPGOOD 23

TPS51650

TPS59650

22

3

24

1

32

2

13 14

15

48

Pad

UDG-12016

V3R3

V5

GND

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APPLICATION INFORMATION

GFX_GSNS

CPU_GSNS

CPU_VSNS

GFX_VSNS

GSCN1

GSCP1

GCSP2

GCSN2

CCSN3

CCSP3

CCSP2

CCSN2

CCSN1

CCSP1

Figure 36. Application Diagram for 3-Phase CPU, 2-Phase GPU with Inductor DCR Current Sense

20

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CCSP3

VIN

CCSN3

1

2

V5DRV

VCC_CORE

CPWM3

V5DRV

+

CPU Phase 3

Figure 37. Application for 3-Phase CPU with Inductor DCR Current Sense

GCSP1

VIN

GCSN1

1

2

GSKIP

VGFX_CORE

GPWM1

V5DRV

+

GPU Phase 1

Figure 38. Application for 1-Phase GPU with Inductor DCR Current Sense

GCSP2

VIN

GCSN2

1

2

V5DRV

VGFX_CORE

GPWM2

V5DRV

+

GPU Phase 2

Figure 39. Application for 2-Phase GPU with Inductor DCR Current Sense

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GFX_GSNS

GFX_VSNS

CPU_GSNS

CPU_VSNS

GSCN1

GSCP1

GCSP2

GCSN2

CCSN3

CCSP3

CCSP2

CCSN2

CCSN1

CCSP1

Figure 40. Application for Inductor DCR Current Sense Application Diagram for 2-Phase CPU and GPU

Disabled

22

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Table 1. Key External Component Recommendations

FUNCTION

MANUFACTURER

Texas Instruments

COMPONENT NUMBER

High-side MOSFET

Low-side MOSFET

Powerblock MOSFET

CSD17302Q5A

CSD17303Q5

Texas Instruments

Panasonic

CSD87350Q5D

ETQP4LR36AFC

MPCH1040LR36,

MPCG1040LR36

NEC-Tokin

TOKO

Inductors

FDUE1040J-H-R36,

FCUL1040xxR36

ALPS

GLMDR3601A

Panasonic

Sanyo

EEFLXOD471R4

2TPLF470M4E

Bulk Output Capacitors

KEMET

Murata

T528Z477M2R5AT

GRM21BR60J106KE19L

GRM21BR60J226ME39L

ECJ2FB0J106K

Murata

Ceramic Output Capacitors

Panasonic

ECJ2FB0J226K

NCP15WF104F03RC,

NCP18WF104F03RC

Murata

NTC Thermistors

Sense Resistors

Panasonic

Vishay

ERTJ1VS104F, ERTJ0ES104F

WSK0612L7500FEA

Stackpole

CSSK0612FTL750

DETAILED DESCRIPTION

Functional Overview

The TPS51650 and TPS59650 are a DCAP+™ mode adaptive on-time controllers.

The output voltage is set using a DAC that outputs a reference in accordance with the 8-bit VID code defined in

Intel IMVP-7 PWM Specification document. In adaptive on-time converters, the controller varies the on-time as a

function of input and output voltage to maintain a nearly constant frequency during steady-state conditions. In

conventional voltage-mode constant on-time converters, each cycle begins when the output voltage crosses to a

fixed reference level. However, in these devices, the cycle begins when the current feedback reaches an error

voltage level which corresponds to the amplified difference between the DAC voltage and the feedback output

voltage. In the case of two-phase or three-phase operation, the current feedback from all the phases is summed

up at the output of the internal current-sense amplifiers.

This approach has two advantages:

•

The amplifier DC gain sets an accurate linear load-line; this is required for CPU core applications.

The error voltage input to the PWM comparator is filtered to improve the noise performance.

In addition, the difference of the DAC-to-output voltage and the current feedback goes through an integrator to

give a more or less linear load-line even at light loads where the inductor current is in discontinuous conduction

mode (DCM).

In a steady-state condition, the phases of the TPS51650 and TPS59650 switch 180° phase-displacement for

two-phase mode and 120° phase-displacement for three-phase mode. The phase displacement is maintained

both by the architecture (which does not allow both high-side gate drives to be on in any condition except

transients) and the current ripple (which forces the pulses to be spaced equally). The controller forces current

sharing adjusting the on-time of each phase. Current balancing requires no user intervention, compensation, or

extra components.

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User Selections

After the 5-V and the 3.3-V power are applied to the controller, the controller must be enabled by the VR_ON

signal going high to the VCCIO logic level. At this time, the following information is latched and cannot be

changed anytime during operation. The ELECTRICAL CHARACTERISTICS table defines the values of each of

the selections.

•

Operating Frequency. The resistor from CF-IMAX pin to GND sets the frequency of the CPU channel. The

resistor from GF-IMAX to GND sets the frequency of the GPU channel. See the EC Table for the resistor

settings corresponding to each frequency selection. It is to be noted that the operating frequency is a

quasi-fixed frequency in the sense that the ON time is fixed based on the input voltage (at the VBAT pin) and

output voltage (set by VID). The OFF time varies based on various factors such as load and power-stage

components.

•

Maximum Current Limit (I_CC(max)) Information. The I_CC(max)information of the CPU, which can be set by the

voltage on the CF-IMAX pin. The I_CC(max)information of the GPU channel, which can be set by the voltage on

the GF-IMAX pin.

•

Overcurrent Protection (OCP) Level. The resistor from COCP-R to GND sets the OCP level of the CPU

channel. The resistor from GOCP-R to GND sets the OCP level of the GPU channel.

Overshoot Reduction (OSR) and Undershoot Reduction (USR) Levels. The voltage on COCP-R pin sets

the OSR and USR level for CPU channel. The voltage on GOCP-R sets the OSR and USR level on GPU

channel. At start-up time, a voltage level (defined in EC Table) detected on GSKIP pin is used to turn OSR

only OFF, or USR only OFF, for both CPU and GPU channels. A voltage level of less than 300 mV makes

both OSR and USR active.

•

Slew Rate. The SetVID-Fast slew rate is set by the voltage on the SLEWA pin. The rate is the same for both

the CPU and GPU channels. The SetVID-Slow is ¼ of the SetVID-Fast rate.

Base SVID Address: The resistor to GND from SLEWA pin sets the base SVID address.

Table 2. Key Selections Summary⁽¹⁾

SELECTION

RESISTANCE (kΩ)

BASE

ADDRESS

VOLTAGE

SETTING (V)

(V_SLEWA)

SLEW RATE (V)

FREQUENCY

OCP

OSR / USR

Least overshoot,

least undershoot

20

Lowest

0000

0.2

12

24

30

0010

0100

0110

1000

1010

1100

0.4

0.6

0.8

1.0

1.2

1.4

4

8

39

12

16

20

23

Rising

56

75

100

Maximum overshoot,

maximum undershoot

150

Highest

1110

1.6

26

(1) See ELECTRICAL CHARACTERISTICS table for complete settings and values.

Table 3. Active Channels and Phases

CCSP1

CS

CCSN1

CS

CCSP2

CS

CCSN2

CS

CCSP3

CS

CCSN3

CS

GCSP1

n/a

CGSN1

n/a

GCSP2

n/a

CGSN2

n/a

3

2

CS

3.3 V

GND

n/a

GND

n/a

CPU

(Active Phases)

1

CS

3.3 V

GND

n/a

GND

n/a

OFF

2

3.3 V

n/a

GND

n/a

CS

GPU

(Active Phases)

1

n/a

CS

3.3 V

GND

OFF

n/a

3.3 V

GND

24

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PWM Operation

Referring to the FUNCTIONAL BLOCK DIAGRAM and Figure 41, in continuous conduction mode, the converter

operates as shown in Figure 41.

V_CORE

I_SUM

V_COMP

SW_CLK

Phase 1

Phase 2

Phase 3

Time

UDG-11031

Figure 41. D-CAP+ Mode Basic Waveforms

Starting with the condition that the hig-side FETs are off and the low-side FETs are on, the summed current

feedback (I_SUM) is higher than the error amplifier output (V_COMP). I_SUMfalls until it reaches the V_COMPlevel, which

contains a component of the output ripple voltage. The PWM comparator senses where the two waveform values

cross and triggers the on-time generator. This generates the internal SW_CLK. Each SW_CLK corresponds to

one switching ON pulse for one phase.

During single-phase operation, every SW_CLK generates a switching pulse on the same phase. Also, I_SUM

voltage corresponds to just a single-phase inductor current.

During multi-phase operation, the SW_CLK is distributed to each of the phases in a cycle. Using the summed

inductor current and then cyclically distributing the ON-pulses to each phase automatically yields the required

interleaving of 360/N, where N is the number of phases.

Current Sensing

The TPS51650 and TPS59650 provide independent channels of current feedback for every phase. This

increases the system accuracy and reduces the dependence of circuit performance on layout compared to an

externally summed architecture. The current sensing topology can be Inductor DCR Sensing, which yields the

best efficiency, or Resistor Current Sensing, which provides the most accuracy across wide temperature range.

DCR sensing can be optimized by using a NTC thermistor to reduce the variation of current sense with

temperature.

The pins CCSP1, CCSN1, CCSP2, CCSN2 and CCSP3, CCSN3 are used for the three phases of the CPU

channel. The pins GCSP1, GCSN1 and GCSP2 and GCSN2 are for the two-phase GPU channel.

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Setting the Load-line (DROOP)

V

VID

Slope of Loadline R

LL

V

= R x I

LL CC

DROOP

I

CC

UDG-11032

Figure 42. Load Line

R_{CS eff}´ A_CS´I_CC

( )

V_DROOP= R_LL´I_CC

=

R_DROOP´ G_M

where

•

ACS is the gain of the current sense amplifier

R_CS(eff)is the effective current sense resistance, whether a sense resistor or inductor DCR is used

I_CCis the load current

R_DROOPis the value of resistor from the DROOP pin to VREF

G_Mis the gain of the droop amplifier

(1)

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Load Transients

When there is a sudden load increase, the output voltage immediately drops. This is reflected as a rising voltage

on the COMP pin. This forces the PWM pulses to come in sooner and more frequent which causes the inductor

current to rapidly increase. As the inductor current reaches the new load current, a steady-state operating

condition is reached and the PWM switching resumes the steady-state frequency.

When there is a sudden load release, the output voltage rises. This is reflected as a falling voltage on the COMP

pin. This delays the PWM pulses until the inductor current reaches the new load current level. At that point,

switching resumes and steady-state switching continues.

For simplicity, neither Figure 43, nor Figure 44 show the ripple on the Output V_COREnor the COMP waveform.

LOAD

V_CORE

I_SUM

COMP

I_SUM

COMP

SW_CLK

Phase 1

Phase 2

Phase 3

Time

UDG-11034

UDG-11033

Figure 43. Operation During Load Transient

(Insertion)

Figure 44. Operation During Load Transient

(Release)

Overshoot Reduction (OSR)

In low duty-cycle synchronous buck converters, an overshoot condition results from the output inductor having a

too little voltage (V_CORE) with which to respond to a transient load release.

In Figure 45, a single phase converter is shown for simplicity. In an ideal converter, with typical input voltage of

12 V and 1.2-V output, the inductor has 10.8 V (12 V – 1.2 V) to respond to a transient load increase, but only

1.2 V with which to respond once the load releases.

12 V

+

10.8 V

–

1.2 V

L

1.2 V

–

+

C

UDG-11035

Figure 45. Synchronous Converter

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When the overshoot reduction feature is enabled, the output voltage increases beyond a value that corresponds

to a voltage difference between the ISUM voltage and the COMP voltage, exceeding the specified OSR voltage

specified in the ELECTRICAL CHARACTERISTICS. At that instant, the low-side drivers are turned OFF. When

the low-side driver is turned OFF, the energy in the inductor is partially dissipated by the body diodes. As the

overshoot reduces, the low-side drivers are turned ON again.

Figure 46 shows the overshoot without OSR. Figure 47 shows the overshoot with OSR. The overshoot reduces

by approximately 23 mV. This shows that reduced output capacitance can be used while continuing to meet the

specification. Note the low-side driver turning OFF briefly during the overshoot.

Figure 46. 43-A Load Transient Release Without

OSR Enabled.

Figure 47. 43-A Load Transient Release With OSR

Enabled

Undershoot Reduction (USR)

When the transient load increase becomes quite large, it becomes difficult to meet the energy demanded by the

load especially at lower input voltages. Then it is necessary to quickly increase the energy tin the inductors

during the transient load increase. This is achieved in these devices by enabling pulse overlapping. In order to

maintain the interleaving of the multi-phase configuration and yet be able to have pulse-overlapping during

load-insertion, the undershoot reduction (USR) mode is entered only when necessary. This mode is entered

when the difference between COMP voltage and ISUM voltage exceeds the USR voltage level specified in the

ELECTRICAL CHARACTERISTICS table.

Figure 48 shows the performance with undershoot reduction. Figure 49 shows the performance without

undershoot reduction and that it is possible to eliminate undershoot by enabling the undershoot reduction. This

allows reduced output capacitance to be used and still meet the specification.

When the transient condition is over, the interleaving of the phases is resumed. For Figure 48, note the

overlapping pulses for Phase 1 and Phase 2 with USR enabled.

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Figure 48. Performance for a 43-A Load Transient

Release Without USR Enabled

Figure 49. Performance for a 43-A Load Transient

Release With USR Enabled

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AutoBalance™ Current Sharing

The basic mechanism for current sharing is to sense the average phase current, then adjust the pulse width of

each phase to equalize the current in each phase. (See Figure 50.)

The PWM comparator (not shown) starts a pulse when the feedback voltage meets the reference. The VBAT

voltage charges C_t(ON)through R_t(ON). The pulse is terminated when the voltage at C_t(ON)matches the t_(ON)

reference, normally the DAC voltage (V_DAC).

The circuit operates in the following fashion, using Figure 50 as the block diagram. First assume that the 5-µs

averaged value of I1 = I2 = I3. In this case, the PWM modulator terminates at V_DAC, and the normal pulse width

is delivered to the system. If instead, I1 > I_AVG, then an offset is subtracted from V_DAC, and the pulse width for

Phase 1 is shortened, reducing the current in Phase 1 to compensate. If I1 < I_AVG, then a longer pulse is

produced, again compensating on a pulse-by-pulse basis.

VBAT 37

R_T(on)

V_DAC

CCSP1

CCSN1

4

5

K x (I1-I_AVG

)

+

PWM1

PWM2

PWM3

+

5 ms

Filter

+

Current

Amplifier

C_T(on)

I_AVG

R_T(on)

V_DAC

+

CCSP2

CCSN2

7

6

K x (I2-I_AVG

5 ms

Filter

+

Current

Amplifier

C_T(on)

I_AVG

Averaging

Circuit

I_AVG

R_T(on)

V_DAC

+

CCSP3

CCSN3

8

9

K x (I3-I_AVG

5 ms

Filter

+

Current

Amplifier

C_T(on)

I_AVG

UDG-11036

Figure 50. Schematic Representation of AutoBalance Current Sharing

Dynamic VID and Power-State Changes

In IMVP-7, there are 3 basic types of VID changes:

•

SetVID-Fast

SetVID-Slow

SetVID-Decay

SetVID-Fast change and a SetVID-Slow change automatically puts the power state in PS0. A SetVID-Decay

change automatically puts the power state in PS2.

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The CPU operates in the maximum phase mode when it is in PS0. This means when the CPU channel of the

controller is configured as 3-phase, all 3 phases are active in PS0. When configured in 2-phase mode, the two

phases are active in PS0. But in PS1, PS2 and PS3, the operation is in single-phase mode. Additionally, the

CPU channel in PS0 mode operates in forced continuous conduction mode (FCCM). But in PS1, PS2 and PS3,

the CPU channel operates in diode emulation (DE) mode for additional power savings and higher efficiency.

The single-phase GPU section always operates in diode emulation (DE) mode in all PS states.

The slew rate for a SetVID-Fast is the slew rate set at the SLEWA pin. This slew rate is defined in the

ELECTRICAL CHARACTERISTICS table. The SetVID-Slow is ¼ of the SetVID-Fast slew rate. On a

SetVID-Decay the output voltage decays by the rate of the load current or 1/8 of the slew rate whichever is

slower.

Additionally, on a SetVID-Fast change for a VID-up transition, the gain of the g_Mamplifier is increased to speed

up the response of the output voltage to meet the Intel timing requirement. So, it is possible to observe an

overshoot at the output voltage on a VID-up transition. This overshoot is allowed by the Intel specification.

XXX

Table 4. VID (continued)

Table 4. VID

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

40

41

42

0.405

0.410

0.415

0.420

0.425

0.430

0.435

0.440

0.445

0.450

0.455

0.460

0.465

0.470

0.475

0.480

0.485

0.490

0.495

0.500

0.505

0.510

0.515

0.520

0.525

0.530

0.535

0.540

0.545

0.550

0.555

0.560

0.565

0.570

0.575

VID VID VID VID VID VID VID VID

HEX V_DAC

7

0

6

0

5

0

4

0

1

3

0

1

0

1

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

0.000

0.250

0.255

0.260

0.265

0.270

0.275

0.280

0.285

0.290

0.295

0.300

0.305

0.310

0.315

0.320

0.325

0.330

0.335

0.340

0.345

0.350

0.355

0.360

0.365

0.370

0.375

0.380

0.385

0.390

0.395

0.400

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Table 4. VID (continued)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

0.580

0.585

0.590

0.595

0.600

0.605

0.610

0.615

0.620

0.625

0.630

0.635

0.640

0.645

0.650

0.655

0.660

0.665

0.670

0.675

0.680

0.685

0.690

0.695

0.700

0.705

0.710

0.715

0.720

0.725

0.730

0.735

0.740

0.745

0.750

0.755

0.760

0.765

0.770

0.775

0.780

0.785

0.790

0.795

0.800

0.805

0.810

0.815

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

73

0.820

0.825

0.830

0.835

0.840

0.845

0.850

0.855

0.860

0.865

0.870

0.875

0.880

0.885

0.890

0.895

0.900

0.905

0.910

0.915

0.920

0.925

0.930

0.935

0.940

0.945

0.950

0.955

0.960

0.965

0.970

0.975

0.980

0.985

0.990

0.995

1.000

1.005

1.010

1.015

1.020

1.025

1.030

1.035

1.040

1.045

1.050

1.055

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

80

81

82

83

84

85

86

87

88

89

8A

8B

8C

8D

8E

8F

90

91

92

93

94

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

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Table 4. VID (continued)

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

1.060

1.065

1.070

1.075

1.080

1.085

1.090

1.095

1.100

1.105

1.110

1.115

1.120

1.125

1.130

1.135

1.140

1.145

1.150

1.155

1.160

1.165

1.170

1.175

1.180

1.185

1.190

1.195

1.200

1.205

1.210

1.215

1.220

1.225

1.230

1.235

1.240

1.245

1.250

1.255

1.260

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

D3

D4

D5

D6

D7

D8

D9

DA

DB

1.300

1.305

1.310

1.315

1.320

1.325

1.330

1.335

1.340

DC 1.345

DD 1.350

DE

DF

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

F1

F2

F3

F4

F5

F6

F7

F8

F9

FA

FB

FC

FD

FE

FF

1.355

1.360

1.365

1.370

1.375

1.380

1.385

1.390

1.395

1.400

1.405

1.410

1.415

1.420

1.425

1.430

1.435

1.440

1.445

1.450

1.455

1.460

1.465

1.470

1.475

1.480

1.485

1.490

1.495

1.500

1.505

1.510

1.515

1.520

1

CC 1.265

CD 1.270

CE

CF

D0

D1

D2

1.275

1.280

1.285

1.290

1.295

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Gate Driver

The TPS51650 and TPS59650 incorporate two internal strong, high-performance gate drives with adaptive

cross-conduction protection. These drivers are for two phases in the CPU channel. The third phase of the CPU

and the single-phase GPU channel require external drivers.

The internal driver in these devices uses the state of the CDLx and CSWx pins to be sure the high-side or

low-side FET is OFF before turning the other ON. Fast logic and high drive currents (up to 8-A typical) quickly

charge and discharge FET gates to minimize dead-time to increase efficiency. The high-side gate driver also

includes an integrated boost FET instead of merely a diode to increase the effective drive voltage for higher

efficiency. An adaptive zero-crossing technique, which detects the switch-node voltage before turning OFF the

low-side FET, is used to minimize losses during DCM operation.

Input Under Voltage Protection (5V and 3.3V)

The TPS51650 and TPS59650 continuously monitor the voltage on the V5DRV, V5 and V3R3 pin to be sure the

value is high enough to bias the device properly and provide sufficient gate drive potential to maintain high

efficiency. The converter starts with approximately 4.4-V and has a nominal 200 mV of hysteresis. The input

(V_BAT) does not have a UVLO function, so the circuit operates with power inputs as low as approximately 3 x

V_CORE

.

Power Good (CPGOOD and GPGOOD)

These devices have two open-drain power good pins that follow the requirements for IMVP-7. CPGOOD is used

for the CPU channel output voltage and GPGOOD is used for the GPU channel output voltage. Both of these

signals are active high. The upper and the lower limits for the output voltage for xPGOOD active are:

•

Upper: V_DAC+220 mV

Lower : V_DAC-315 mV

xPGOOD goes inactive (low) as soon as the VR_ON pin is pulled low or an undervoltage condition on V5 or

V3R3 is detected. The xPGOOD signals are masked during DAC transitions to prevent false triggering during

voltage slewing.

Output Undervoltage Protection

Output undervoltage protection works in conjunction with the current protection described below. If V_COREdrops

below the low PGOOD threshold, then the drivers are turned OFF until VR_ON is cycled.

Overcurrent Protection

The TPS51650 and TPS59650 use a valley current limiting scheme, so the ripple current must be considered.

The DC current value at OCP is the OCP limit value plus half of the ripple current. Current limiting occurs on a

phase-by-phase and pulse-by-pulse basis. If the voltage between xCSPx and xCSNx is above the OCP value,

the converter delays the next ON pulse until it drops below the OCP limit. For inductor current sensing circuits,

the voltage between xCSPx and xCSNx is the inductor DCR value multiplied by the resistor divider which is part

of the NTC compensation network. As a result, a wide range of OCP values can be obtained by changing the

resistor divider value. In general, use the highest OCP setting possible with the least attenuation in the resistor

divider to provide as much signal to the device as possible. This provides the best performance for all

parameters related to current feedback.

In OCP mode, the voltage drops until the UVP limit is reached. Then, the converter sets the xPGOOD to inactive,

and the drivers are turned OFF. The converter remains in this state until the device is reset by the VR_ON.

Overvoltage Protection

An OVP condition is detected when V_COREis more than 220 mV greater than V_DAC. In this case, the converter

sets xPGOOD inactive, and turns ON the drive for the Low-side FET. The converter remains in this state until the

device is reset by cycling VR_ON. However, because of the dynamic nature of IMVP-7 systems, the +220 mV

OVP threshold is blanked much of the time. In order to provide protection to the processor 100% of the time,

there is a second OVP level fixed at 1.7 V which is always active. If the fixed OVP condition is detected, the

PGOOD are forced inactive and the low-side FETs are tuned ON. The converter remains in this state until

VR_ON is cycled.

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Over Temperature Protection

Two types of thermal protection are provided in these devices:

•

VR_HOT

Thermal Shutdown

VR_HOT

The VR_HOT signal is an Intel-defined open-drain signal that is used to protect the V_COREpower chain. To use

VR_HOT, place an NTC thermistor at the hottest area of the CPU channel and connect it from CTHERM pin to

GND. Similarly for GPU channel, place the NTC thermistor at the hottest area and connect it from GTHERM to

GND. Also, connect a resistor from VREF to GTHERM and CTHERM. As the temperature increases, the

xTHERM voltage drops below the THERM threshold, VR_HOT is activated. A small capacitor may be connected

to the xTHERM pins for high frequency noise filtering.

lists the thermal zone register bits based on the xTHERM pin voltage.

Table 5. Thermal Zone Register Bits

OUTPUT IS

SHUTDOWN

VR_HOT

ASSERTED

xTHERM THRESHOLD VOLTAGE FOR THE TEMPERATURE

ZONE REGISTER BITS TO BE ASSERTED.

SVID ALERT ASSERTED

b7

b6

b5

b4

b3

b2

b1

b0

410 mV

455 mV

458 mV

523 mV

559 mV

598 mV

638 mV 680 mV

783 mV

Thermal Shutdown

When the xTHERM pin voltage continues to drop even after VR_HOT is asserted, the drivers turn OFF and the

output is shutdown. These devices also have an internal temperature sensor. When the temperature reaches a

nominal 155°C, the device shuts down until the temperature cools approximately 20°C. Then, the circuit can be

re-started by cycling VR_ON.

Setting the Maximum Processor Current (I_CC(max)

)

The TPS51640 controller allows the user to set the maximum processor current with the multi-function pins

CF-IMAX and GF-IMAX. The voltage on the CF-IMAX and GF-IMAX at start-up sets the maximum processor

current (I_CC(max)) for CPU and GPU respectively.

The R_CFand R_GFare resistors to GND from CF-IMAX and GF-IMAX respectively to select the frequency setting.

R_CIMAXis the resistor from VREF to CF-IMAX and R_GIMAXis the resistor from VREF to GF-IMAX.

Equation 2 describes the setting the I_CC(max)for the CPU channel and Equation 3 describes the setting the

I_CC(max)for the GPU channel.

æ

ç

è

ö

÷

ø

R

CF

I

= 255´

CC max CPU

)

(

R

+ R

CF

CIMAX

(2)

(3)

æ

ç

è

ö

÷

ø

R

GF

I

= 255´

CC max GPU

)

(

R

+ R

GIMAX

GF

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DESIGN STEPS

The design procedure using the TPS51650, TPS59650, and TPS59641 is very simple . An excel-based

component value calculation tool is available. Contact your local TI representative to get a copy of the

spreadsheet.

The procedure is explained here below with the following design example:

Table 6. Design Example Specifications

CPU V_CORESPECIFICATIONS

GFX V_CORESPECIFICATIONS

Phases

Input voltage range

VHFM

3

9 V to 20 V

0.9 V

2

9 V to 20 V

1.23 V

46 A

I_CC(max)

94 A

I_DYN(max)

66 A

38 A

I_CC(tdc)

52

37.5

Load-line

1.9 mV/A

10 mV/µs

3.9 mV/A

10 mV/µs

Fast slew rate (minimum)

Step One: Select switching frequency.

The CPU channel switching frequency is selected by a resistor from CF-IMAX to GND (R_CF) and GPU channel

switching frequency is selected by a resistor from GF-IMAX to GND (R_GF). The frequency is an approximate

frequency and is expected to vary based on load and input voltage.

Table 7. Switching Frequency Selection

SELECTION

CPU CHANNEL

GPU CHANNEL

RESISTANCE (kΩ)

FREQUENCY (kHz)

20

24

250

300

350

400

450

500

550

600

275

330

385

440

495

550

605

660

30

39

56

75

100

150

This desig defines the switching frequency for the CPU channel as 300 kHz and defines the GPU channel as 385

kHz. Therefore,

•

R_CF= 21 kΩ

R_GF= 24 kΩ

Step Two: Set I_CC(max)

The I_CC(max)is set by the voltage on CF-IMAX for CPU channel and GF-IMAX for GPU channel. This is set by the

resistors from VREF to CF-IMAX (R_CMAX) and from VREF to GF-IMAX (R_GMAX

)

From Equation 2 and Equation 3,

•

R_CMAX= 42.2 kΩ

R_GMAX= 110 kΩ

Step Three: Set the slew rate.

The slew rate is set by the voltage setting on SLEWA pin. For a minimum slew rate of 10 mV/ms, the voltage on

the SLEWA pin must be less than 0.3 V. Because the SLEWA pin also sets the base address (for the

TPS59650), the simple way to meet this is by having a 20-kΩ resistor from SLEWA to GND.

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Step Four: Determine inductor value and choose inductor.

Smaller values of inductor have better transient performance but higher ripple and lower efficiency. Higher values

have the opposite characteristics. It is common practice to limit the ripple current to 20% to 40% of the maximum

current per phase. This example uses a ripple current of 30%.

94A

I

=

´ 0.3 = 9.4A

P-P

3

(4)

(5)

V ´ dT

L =

I

P-P

where

•

V = V_IN-MAX– V_HFM= 19.1 V

dT = V_HFM/ (f × V_IN-MAX) = 150 ns

I_P-P= 9.4 A

Using those calculations, L = 0.304 µH.

An inductance value of 0.36 µH is chosen as this is a commonly used inductor for V_COREapplication. The

inductor must not saturate during peak loading conditions.

I

æ

ç

ö

÷

CC max

(

I

)

P-P

I

=

+

´1.2 = 43.2A

SAT

ç

è

÷

ø

N

2

PHASE

(6)

The factor of 1.2 allows for current sensing and current limiting tolerances; the factor of 1.25 is the Intel 25%

momentary OCP requirement.

The chosen inductor should have the following characteristics:

•

An inductance to current curve ratio equal to 1 (or as close possible). Inductor DCR sensing is based on the

idea L/DCR is approximately a constant through the current range of interest.

•

Either high saturation or soft saturation.

Low DCR for improved efficiency, but at least 0.7 mΩ for proper signal levels.

DCR tolerance as low as possible for load-line accuracy.

For this application, a 0.36-µH, 0.825-mΩ inductor is chosen. Because the per phase current for GPU is same as

CPU, the same inductor for GPU channel is chosen.

Step Five: Determine current sensing method.

The TPS51650 and TPS59650 support both resistor sensing and inductor DCR sensing. Inductor DCR sensing

is chosen. For resistor sensing, substitute the resistor value (0.75 mΩ recommended for a 3-phase 94-A

application) for RCS in the subsequent equations and skip Step Four.

Step Six: Design the thermal compensation network and selection of OCP .

In most designs, NTC thermistors are used to compensate thermal variations in the resistance of the inductor

winding. This winding is generally copper, and so has a resistance coefficient of 3900 PPM/°C. NTC thermistors,

on the other hand, have very non-linear characteristics and need two or three resistors to linearize them over the

range of interest. The typical DCR circuit is shown in Figure 51.

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L

R_DCR

I

R_SEQU

R_NTC

R_SERIES

R_PAR

C_SENSE

CSP

CSN

UDG-11039

Figure 51. Typical DCR Sensing Circuit

In this circuit, the voltage across the C_SENSEcapacitor exactly equals the voltage across the R_DCRresistor when

Equation 7 is true.

L

= C

´R

EQ

SENSE

R

DCR

where

•

R_EQis the series/parallel combination of R_SEQU, R_NTC, R_SERIESand R_PAR

(7)

(8)

(9)

R_{P _N}

R_EQ

=

R

_SEQU+ R_{P _N}

R

´ R

+ R

(

+ R

)

PAR

NTC

SERIES

R

=

P _N

R

PAR

NTC

SERIES

C_SENSEcapacitor type should be stable over temperature. Use X7R or better dielectric (C0G preferred).

Because calculating these values by hand is difficult, TI has a spreadsheet using the Excel Solver function

available to calculate them. Contact a local TI representative to get a copy of the spreadsheet.

In this design, the following values are input into the CPU section of the spreadsheet

•

L = 0.36 µH

R_DCR= 0.825 mΩ

Load Line, R_IMVP= -1.9 mΩ

Minimum overcurrent limit = 112 A

Thermistor R₂₅= 100 kΩ and "B" value = 4250 kΩ

In this design, the following values are input into the GPU section of the spreadsheet

•

L = 0.36 µH

R_DCR= 0.825 mΩ

Load Line, R_IMVP= -3.9 mΩ

Minimum overcurrent limit = 59 A

Thermistor R₂₅= 100 kΩ and "B" value = 4250 kΩ

The spreadsheet then calculates the OCP (overcurrent protection) setting and the values of R_SEQU, R_SERIES

,

R_PAR, and C_SENSE. In this case, the OCP setting is the resistor value selection of 56 kΩ from COCP-I to GND and

GOCP-I to GND. The nearest standard component values are:

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•

R_SEQU= 17.8 kΩ;

R_SERIES= 28.7 kΩ;

R_PAR= 162 kΩ

C_SENSE=33 nF

Note the effective divider ratio for the inductor DCR. The effective current sense resistance (R_CS(eff)) is shown in

Equation 10.

R_{P _N}

R_{CS eff}= R_DCR

´

( )

R

_SEQU+ R_{P _N}

where

•

R_{P_N}is the series/parallel combination of R_NTC, R_SERIESand R_PAR

.

(10)

(11)

R_{CS eff}´ A_CS

( )

0.66mW ´12

R_GDROOP

=

= 4.12kW

R_LL´ G_M

3.9mW ´0.497mS

R_CS(eff)is 0.66 mΩ.

Step Seven: Set the load-line.

The load-line for CPU channel is set by the resistor, R_CDROOPfrom CCOMP to VREF. The load-line for GPU

channel is set by the resistor, R_GDROOPfrom the GCOMP pin to VREF. Using the Equation 1, the droop setting

resistors are calculated in Equation 12 and Equation 13.

R_{CS eff}´ A_CS

( )

0.66mW ´12

R_CDROOP

=

= 8.45kW

R_LL´ G_M

1.9mW ´0.497mS

(12)

(13)

R_{CS eff}´ A_CS

( )

0.66mW ´12

R_GDROOP

=

= 4.12kW

R_LL´ G_M

3.9mW ´0.497mS

Step Eight: Programming the CTHERM and GTHERM pins.

The CTHERM and GTHERM pins should be set so that the resistor divider voltage would be greater than 458

mV at normal operation. For VR_HOT to be asserted, the xTHERM pin voltage should fall below 458 mV. The

NTC resistor from xTHERM to GND is chosen as 100 kΩ with a B of 4250K. With this, for a VR_HOT assertion

temperature of 105°C, the resistor from xTHERM to VREF can be calculated as 15.4 kΩ.

Step Nine:Determine the output capacitor configuration.

For the output capacitor, the Intel Power Delivery Guidelines gives the output capacitor recommendations. Using

these devices, it is possible to meet the load transient with lower capacitance by using the OSR and USR

feature. Eight settings are available and this selection must to be tuned based on transient measurement.

Table 8. OSR/USR Selection Settings

INDUCTOR DCR

0.8 mW to 0.9 mW

1.0 mW to 1.1 mW

3-PHASE QC SETTING (V)

2-PHASE SV SETTING (V)

1.0

1.2

0.8

1.0

The resistor from COCP-R to VREF and GOCP-R to VREF can be calculated based on the above voltage setting

and the COCP-R to GND and GOCP-R to GND resistor selected in Step Six. The resistor values are calculated

as 39.2 kΩ for COCP-R to VREF and 2.4 kΩ for GOCP-R to VREF.

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PCB LAYOUT GUIDELINE

SCHEMATIC REVIEW

Because the voltage and current feedback signals are fully differential it is a good idea to double check their

polarity.

•

CCSP1/CCSN1

CCSP2/CCSN2

GCSP1/GCSN1

GCSP2/GCSN2

VCCSENSE to CVFB/VSSSENSE to CGFB (for CPU)

VCCGTSENSE to GVFB/VSSGTSENSE to GGFB (for GPU)

Also, note the order of the current sense inputs on Pin 4 to Pin 9 as the second phase has a reverse order.

CAUTION

Separate noisy driver interface lines from sensitive analog interface lines: (This is the

MOST CRITICAL LAYOUT RULE)

The TPS51650 and TPS59650 make this as easy as possible. The pin-out arrangement for TPS51650 is shown

in Figure 52. The driver outputs clearly separated from the sensitive analog and digital circuitry. The driver has a

separate PGND and this should be directly connected to the decoupling capacitor that connects from V5DRV to

PGND. The thermal pad of the package is the analog ground for these devices and should NOT be connected

directly to PGND (Pin 42).

Figure 52. Packaging Layout Arranged by Function

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Given the physical layout of most systems, the current feedback (xCSPx, xCSNx) may have to pass near the

power chain. Clean current feedback is required for good load-line, current sharing, and current limiting

performance of these devices, so please take the following precautions:

•

Make a Kelvin connection to the pads of the resistor or inductor used for current sensing. See Figure 53 for a

layout example.

•

Run the current feedback signals as a differential pair to the device.

Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane.

Put the compensation capacitor for DCR sensing (C_SENSE) as close to the CS pins as possible.

Place any noise filtering capacitors directly underneath these devices and connect to the CS pins with the

shortest trace length possible.

Noisy

Quiet

Inductor

Outline

LL_x

V_CORE

CSNx

CSPx

R

SEQ

R

SERIES

Thermistor

UDG-11038

Figure 53. Make Kelvin Connections to the Inductor for DCR Sensing

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Minimize High-Current Loops

Figure 54 shows the primary current loops in each phase, numbered in order of importance.

The most important loop to minimize the area of is Loop 1, the path from the input capacitor through the high and

low side FETs, and back to the capacitor through ground.

Loop 2 is from the inductor through the output capacitor, ground and Q2. The layout of the low side gate drive

(Loops 3a and 3b) is important. The guidelines for gate drive layout are:

•

Make the low-side gate drive as short as possible (1 inch or less preferred).

Make the DRVL width to length ratio of 1:10, wider (1:5) if possible.

If changing layers is necessary, use at least two vias.

V_BAT

C_B

C_IN

1

Q1

4b

DRVH

4a

L

V_CORE

LL

2

Q2

C_D

DRVL

3a

C_OUT

3b

PGND

UDG-11040

Figure 54. Major Current Loops to Minimize

Power Chain Symmetry

The TPS51650 and TPS59650 do not require special care in the layout of the power chain components. This is

because independent isolated current feedback is provided. If it is possible to lay out the phases in a symmetrical

manner, then please do so. The current feedback from each phase must be clean of noise and have the same

effective current sense resistance.

Place analog components as close to the device as possible.

Place components close to the device in the following order.

1. CS pin noise filtering components

2. xCOMP pin compensation components

3. Decoupling capacitors for VREF, V3R3, V5

4. xTHERM filter capacitor

5. xOCP-R resistors

6. xF-IMAX resistors

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Grounding Recommendations

These devices have separate analog and power grounds, and a thermal pad. The normal procedure for

connecting these is:

•

The thermal pad is the analog ground.

DO NOT connect the thermal pad to Pin 42 directly as Pin 42 is the PGND which is the Gate driver

Ground.

•

Pin 42 (PGND) must be connected directly to the gate driver decoupling capacitor ground terminal.

Tie the thermal pad (analog ground pin) to a ground island with at least 4 small vias or one large via.

All the analog components can connect to this analog ground island.

The analog ground can be connected to any quiet spot on the system ground. A quiet area is defined as a

area where no power supply switching currents are likely to flow. This applies to both the V_COREregulator and

other regulators. Use a single point connection from analog ground to the system ground

•

Make sure the low-side FET source connection and the decoupling capacitors have plenty of vias.

Decoupling Recommendations

•

Decouple V5IN to PGND with at least a 2.2 µF ceramic capacitor.

Decouple V5 and V3R3 with 1 µF to AGND with leads as short as possible,

VREF to AGND with 0.33 µF, with short leads also

Conductor Widths

•

Follow Intel guidelines with respect to the voltage feedback and logic interface connection requirements.

Maximize the widths of power, ground and drive signal connections.

For conductors in the power path, be sure there is adequate trace width for the amount of current flowing

through the traces.

•

Make sure there are sufficient vias for connections between layers. A good guideline is to use a minimum of 1

via per ampere of current.

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PACKAGE MATERIALS INFORMATION

www.ti.com

9-Mar-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS51650RSLR

TPS51650RSLT

TPS59650RSLR

TPS59650RSLT

VQFN

RSL

48

2500

250

330.0

180.0

330.0

180.0

16.4

6.3

1.5

12.0

16.0

Q2

2500

250

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Mar-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS51650RSLR

TPS51650RSLT

TPS59650RSLR

TPS59650RSLT

VQFN

RSL

48

2500

250

346.0

210.0

346.0

210.0

346.0

185.0

346.0

185.0

33.0

35.0

33.0

35.0

2500

250

Pack Materials-Page 2

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厂家：	TEXAS INSTRUMENTS
描述：	适用于 IMVP-7 VCORE 的双通道（三相 CPU/两相 GPU）SVID、D-CAP+ 降压控制器 \| RSL \| 48 \| -10 to 105 开关控制器开关式稳压器开关式控制器电源电路开关式稳压器或控制器
文件：	总50页 (文件大小：1645K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FX007 [TI]

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