DS250DF410ABMT [TI]
25Gbps 多速率 4 通道重定时器 | ABM | 101 | -40 to 85;型号: | DS250DF410ABMT |
厂家: | TEXAS INSTRUMENTS |
描述: | 25Gbps 多速率 4 通道重定时器 | ABM | 101 | -40 to 85 接口集成电路 |
文件: | 总100页 (文件大小:2761K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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DS250DF410
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
DS250DF410 25Gbps 多速率 4 通道重定时器
1 特性
2 应用
1
•
•
具有集成信号调节功能的四通道多速率重定时器
•
•
•
•
针对前端口光学模块的抖动消除
有源电缆组件
所有通道均可独立锁定在 20.2752 至 25.8Gbps 的
范围内(包括 10.3125Gbps、12.5Gbps 等子速
率)
背板/中板长度延长
IEEE802.3bj 100GbE、Infiniband EDR 和 OIF-
CEI-25G-LR/MR/SR/VSR 电气接口
•
•
超低延迟:25.78125Gbps 数据速率下的典型延迟
< 500ps
•
SFP28、QSFP28、CFP2/CFP4、CDFP
单电源,无需低抖动参考时钟,最大限度减少电源
去耦以降低电路板布线复杂程度并节省物料清单
(BOM) 成本
3 说明
DS250DF410 是一款具有集成信号调节功能的四通道
多速率重定时器。该器件用于扩展有损且存在串扰的远
距离高速串行链路的延伸长度并提升稳定性,同时实现
不高于 10-15 的比特误码率 (BER)。
•
•
•
•
集成 2×2 交叉点
自适应性连续时间线性均衡器 (CTLE)
自适应判决反馈均衡器 (DFE)
带有 3 抽头有限冲激响应 (FIR) 滤波器的低抖动发
射器
DS250DF410 各通道的串行数据速率均可独立锁定在
20.2752Gbps 至 25.8Gbps 的连续范围内或者支持的
任意子速率(速率的一半和四分之一),包括
10.3125Gbps 和 12.5Gbps 等关键数据速率,因此该
器件支持独立通道前向纠错 (FEC) 直通。
•
•
•
组合式均衡,在 12.9GHz 频率下支持 35dB 以上的
通道损耗
可调节发送幅值:205mVppd 至 1225mVppd(典
型值)
片上眼图张开度监视器 (EOM),PRBS 模式校验器
/发生器
器件信息(1)
器件型号
封装
ABM (101)
封装尺寸(标称值)
•
•
支持 JTAG/AC-JTAG 边界扫描
DS250DF410
6.00mm × 6.00mm
小型 6mm × 6mm BGA 封装,可轻松实现直通布
线
(1) 如需了解所有可用封装,请参阅产品说明书末尾的可订购产品
附录。
简化原理图
RX0P
TX0P
TX0N
CDR
RX
RX
TX
RX0N
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
RX3P
RX3N
TX3P
TX3N
2.5V or
3.3V
CDR
TX
VDD
SMBus
Slave mode
1 kΩ
To other open-drain
interrupt pins
EN_SMB
INT_N
SDA(1)
NC_TEST
To system
SMBus
SDC(1)
Address straps
ADDR0
(pull-up, pull-
ADDR1
down, or float)
25 MHz
To next device‘s
CAL_CLK_IN
CAL_CLK_IN
READ_EN_N
CAL_CLK_OUT
ALL_DONE_N
SMBus Slave
mode
Float for SMBus Slave
mode, or connect to next
device‘s READ_EN_N for
SMBus Master mode
2.5V
GND
VDD
1ꢀF
(2x)
0.1ꢀF
(4x)
(1) SMBus signals need to be pulled up elsewhere in the system.
1
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。 有关适用的官方英文版本的最新信息,请访问 www.ti.com,其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SNLS456
DS250DF410
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 (续).............................................................. 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 8
7.1 Absolute Maximum Ratings ...................................... 8
7.2 ESD Ratings.............................................................. 8
7.3 Recommended Operating Conditions....................... 8
7.4 Thermal Information.................................................. 9
7.5 Electrical Characteristics........................................... 9
8
9
Detailed Description ............................................ 17
8.1 Overview ................................................................. 17
8.2 Functional Block Diagram ....................................... 17
8.3 Feature Description................................................. 18
8.4 Device Functional Modes........................................ 29
8.5 Programming........................................................... 30
8.6 Register Maps......................................................... 32
Application and Implementation ........................ 76
9.1 Application Information............................................ 76
9.2 Typical Applications ............................................... 76
10 Power Supply Recommendations ..................... 90
11 Layout................................................................... 90
11.1 Layout Guidelines ................................................. 90
11.2 Layout Example .................................................... 90
12 器件和文档支持 ..................................................... 92
12.1 文档支持................................................................ 92
12.2 文档支持................................................................ 92
12.3 接收文档更新通知 ................................................. 92
12.4 支持资源................................................................ 92
12.5 商标....................................................................... 92
12.6 静电放电警告......................................................... 92
12.7 Glossary................................................................ 92
13 机械、封装和可订购信息....................................... 92
7.6 Timing Requirements, Retimer Jitter
Specifications........................................................... 13
7.7 Timing Requirements, Retimer Specifications........ 14
7.8 Timing Requirements, Recommended Calibration
Clock Specifications................................................. 14
7.9 Recommended SMBus Switching Characteristics
(Slave Mode)............................................................ 14
7.10 Recommended SMBus Switching Characteristics
(Master Mode).......................................................... 15
7.11 Recommended JTAG Switching Characteristics .. 15
7.12 Typical Characteristics ......................................... 16
4 修订历史记录
注:之前版本的页码可能与当前版本有所不同。
Changes from Revision C (February 2019) to Revision D
Page
•
首次公开发布 .......................................................................................................................................................................... 1
2
版权 © 2016–2019, Texas Instruments Incorporated
DS250DF410
www.ti.com.cn
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
5 说明 (续)
DS250DF410 具备一个单电源,能够最大限度地减少外部组件的数量。这些 特性 可降低 PCB 布线的复杂程度并
节省 BOM 成本。
DS250DF230 的高级均衡 特性 包括:一个低抖动 3 抽头发送有限冲激响应 (FIR) 滤波器、一个自适应连续时间线
性均衡器 (CTLE) 以及一个自适应判决反馈均衡器 (DFE)。支持针对具有多个连接器且存在串扰的有损互连和背板
进行扩展。集成的时钟和数据恢复 (CDR) 功能可重置抖动预算并对高速串行数据进行重定时, 非常适用于前端口
光学模块 以重置抖动容许量并重定时高速串行数据。DS250DF410 对每个通道对采用 2x2 交叉点,可为主机同时
提供通道交叉、扇出和多路复用选项。
DS250DF410 可通过 SMBus 或外部 EEPROM 进行配置。单个 EEPROM 最多可由 16 个器件使用“公共通道”格
式共享。非破坏性片上眼图监视器和 PRBS 发生器/校验器为系统内诊断提供支持。
Copyright © 2016–2019, Texas Instruments Incorporated
3
DS250DF410
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
www.ti.com.cn
6 Pin Configuration and Functions
ABM Package
101-Pin FC/CSP
Top View
Pin Functions
PIN
INTERNAL
PULL-UP/
PULL-DOWN
TYPE
DESCRIPTION
NAME
NO.
HIGH SPEED DIFFERENTIAL I/Os
RX0N
A10
A11
A7
Input
Input
Input
Input
None
None
None
None
Inverting and non-inverting differential
inputs to the equalizer. An on-chip 100-Ω
termination resistor connects RXP to
RXN. These inputs need to be AC
coupled.(1)
RX0P
RX1N
RX1P
Inverting and non-inverting differential
inputs to the equalizer. An on-chip 100-Ω
termination resistor connects RXP to
RXN. These inputs need to be AC
coupled.(1)
A8
(1) High-speed pins do not have short-circuit protection. High-speed pins should be AC-coupled.
4
Copyright © 2016–2019, Texas Instruments Incorporated
DS250DF410
www.ti.com.cn
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
Pin Functions (continued)
PIN
INTERNAL
PULL-UP/
PULL-DOWN
TYPE
DESCRIPTION
NAME
NO.
RX2N
A4
Input
None
Inverting and non-inverting differential
inputs to the equalizer. An on-chip 100-Ω
termination resistor connects RXP to
RXN. These inputs need to be AC
coupled.(1)
RX2P
RX3N
RX3P
A5
A1
A2
Input
Input
Input
None
None
None
Inverting and non-inverting differential
inputs to the equalizer. An on-chip 100-Ω
termination resistor connects RXP to
RXN. These inputs need to be AC
coupled.(1)
TX0N
TX0P
TX1N
TX1P
TX2N
TX2P
TX3N
TX3P
L10
L11
L7
Output
Output
Output
Output
Output
Output
Output
Output
None
None
None
None
None
None
None
None
Inverting and non-inverting 50-Ω driver
outputs. Compatible with AC-coupled
differential inputs. These outputs need to
be AC coupled.(1)
Inverting and non-inverting 50-Ω driver
outputs. Compatible with AC-coupled
differential inputs. These outputs need to
be AC coupled.(1)
L8
L4
Inverting and non-inverting 50-Ω driver
outputs. Compatible with AC-coupled
differential inputs. These outputs need to
be AC coupled.(1)
L5
L1
Inverting and non-inverting 50-Ω driver
outputs. Compatible with AC-coupled
differential inputs. These outputs need to
be AC coupled.(1)
L2
CALIBRATION CLOCK PINS
25 MHz (±100 PPM) 2.5-V single-ended
clock from external oscillator. No stringent
phase noise or jitter requirements on this
clock. Used to calibrate VCO frequency
range.
Weak pull-up in
JTAG mode. Weak
pull-down in
CAL_CLK_IN/
JTAG_TDI
Input, 2.5V
CMOS
F1
functional mode
In JTAG mode (EN_SMB = 1 kΩ to
GND), this is JTAG Test Data In (TDI).
2.5-V buffered replica of calibration clock
input (pin E1) for connecting multiple
devices in a daisy-chained fashion.
In JTAG mode (EN_SMB = 1 kΩ to
GND), this is JTAG Test Data Out (TDO).
CAL_CLK_OUT/
JTAG_TDO
Output, 2.5V
CMOS
F11
None
None
SYSTEM MANAGEMENT BUS (SMBus) PINS
ADDR0
D11
Input, 4-level
Input, 4-level
4-level strap pins used to set the SMBus
address of the device. The pin state is
read on power-up. The multi-level nature
of these pins allows for 16 unique device
addresses. The four strap options include:
0: 1 kΩ to GND
R: 20 kΩ to GND
F: Float
1: 1 kΩ to VDD
Weak pull-up in
JTAG mode
ADDR1/JTAG_TRS
D1
Refer to Device SMBus Address for more
information.
In JTAG mode (EN_SMB = 1 kΩ to
GND), ADDR1 is JTAG Test Reset
(TRS).
Copyright © 2016–2019, Texas Instruments Incorporated
5
DS250DF410
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
www.ti.com.cn
Pin Functions (continued)
PIN
INTERNAL
TYPE
PULL-UP/
PULL-DOWN
DESCRIPTION
NAME
NO.
Four-level 2.5-V input used to select
between SMBus master mode (float) and
SMBus slave mode (high). The four
defined levels are:
0: 1 kΩ to GND - JTAG mode; certain
pins take on JTAG functionality
R: 20 kΩ to GND - RESERVED, TI test
mode
EN_SMB
G1
Input, 4-level
None
F: Float - SMBus Master Mode
1: 1 kΩ to VDD - SMBus Slave Mode
SMBus data input / open drain output.
External 2-kΩ to 5-kΩ pull-up resistor is
required as per SMBus interface
I/O, 3.3V
LVCMOS, Open
Drain
SDA
G11
H11
None
None
standard. This pin is 3.3V-tolerant.
SMBus clock input / open drain clock
output. External 2-kΩ to 5-kΩ pull-up
resistor is required as per SMBus
interface standard. This pin is 3.3V-
tolerant.
I/O, 3.3V
LVCMOS, Open
Drain
SDC
SMBus MASTER MODE PINS
Indicates the completion of a valid
EEPROM register load operation when in
SMBus Master Mode (EN_SMB=Float):
High = External EEPROM load failed or
incomplete
Output,
LVCMOS
ALL_DONE_N
E1
None
Low = External EEPROM load successful
and complete
When in SMBus slave mode
(EN_SMB=1), this output reflects the
status of the READ_EN_N input.
SMBus Master Mode (EN_SMB=Float):
When asserted low, initiates the SMBus
master mode EEPROM read function.
Once EEPROM read is complete
(indicated by assertion of ALL_DONE_N
low), this pin can be held low for normal
device operation.
SMBus Slave Mode (EN_SMB=1): When
asserted low, this causes the device to be
held in reset (SMBus state machine reset
and register reset). This pin should be
pulled high or left floating for normal
operation in SMBus Slave Mode.
This pin is 3.3V-tolerant.
Input, 3.3V
LVCMOS
READ_EN_N
E11
Weak pull-up
MISCELLANEOUS PINS
Open-drain 3.3-V tolerant active-low
interrupt output. This pin is pulled low
when an interrupt occurs. The events
which trigger an interrupt are
programmable through SMBus registers.
INT_N can be connected in a wired-OR
fashion with other device's interrupt pin. A
single pull-up resistor in the 2-kΩ to 5-kΩ
range is adequate for the entire INT_N
net.
Output,
LVCMOS, Open
Drain
INT_N
H1
None
6
Copyright © 2016–2019, Texas Instruments Incorporated
DS250DF410
www.ti.com.cn
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
Pin Functions (continued)
PIN
INTERNAL
PULL-UP/
PULL-DOWN
TYPE
DESCRIPTION
NAME
NO.
No pull-up in JTAG Reserved TI test pins. During normal
TEST0/JTAG_TCK
D10
Input, LVCMOS mode. Weak pull-up (non-test-mode) operation, these pins are
in functional mode. configured as inputs and therefore they
are not affected by the presence of a
signal. These pins may be left floating,
tied to GND, or connected to a 2.5-V
(max) output.
TEST1/JTAG_TMS
D2
Input, LVCMOS
Weak pull-up
In JTAG mode (EN_SMB = 1 kΩ to
GND), TEST0 is JTAG Test Clock (TCK)
and TEST1 is JTAG Test Mode Select
(TMS).
TEST2
TEST3
TEST4
E10
E2
Input, LVCMOS
Input, LVCMOS
Input, LVCMOS
Weak pull-up
Weak pull-up
Weak pull-up
Reserved TI test pins. During normal
(non-test-mode) operation, these pins are
configured as inputs and therefore they
are not affected by the presence of a
signal. These pins may be left floating,
tied to GND, or connected to a 2.5-V
(max) output.
H10
TEST5
H2
Input, LVCMOS
Weak pull-up
POWER
A3, A6, A9, B1, B2, B3,
B4, B5, B6, B7, B8, B9,
B10, B11, C1, C6, C11,
D6, E3, E5, E7, E9, F3,
F4, F5, F6, F7, F8, F9,
Ground reference. The GND pins on this
device should be connected through a
low-resistance path to the board GND
plane.
GND
Power
None
G2, G3, G5, G7, G9, G10,
H6, J1, J6, J11, K1, K2,
K3, K4, K5, K6, K7, K8,
K9, K10, K11, L3, L6, L9
Power supply, VDD = 2.5 V ±5%. TI
recommends connecting at least six de-
coupling capacitors between the
DS250DF410’s VDD plane and GND as
close to the DS250DF410 as possible.
For example, four 0.1-μF capacitors and
two 1-μF capacitors directly beneath the
device or as close to the VDD pins as
possible. The VDD pins on this device
should be connected through a low-
resistance path to the board VDD plane.
C3, C9, D3, D4, D5, D7,
D8, D9, H3, H4, H5, H7,
H8, H9, J3, J9
VDD
Power
None
Copyright © 2016–2019, Texas Instruments Incorporated
7
DS250DF410
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
MAX
UNIT
V
VDDABSMAX
VIO2.5V,ABSMAX
VIO3.3V,ABSMAX
VINABSMAX
VOUTABSMAX
TJABSMAX
Supply voltage (VDD)
2.75
2.75
4.0
2.5 V I/O voltage (LVCMOS, CMOS and Analog)
V
Open Drain Voltage (SDA, SDC, INT_N) and LVCMOS Input Voltage (READ_EN_N)
Signal input voltage (RXnP, RXnN)
V
2.75
2.75
150
150
V
Signal output voltage (TXnP, TXnN)
Junction temperature
V
ºC
ºC
Tstg
Storage temperature
–40
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2 kV
may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX UNIT
2.625
VDD
Supply voltage, VDD to GND. DC plus AC power should not exceed these limits.
Supply noise, DC to < 50 Hz, sinusoidal(1)
Supply noise, 50 Hz to 10 MHz, sinusoidal(1)
Supply noise, >10 MHz, sinusoidal(1)
2.375
V
NVDD
NVDD
NVDD
TrampVDD
TJ
250 mVpp
20 mVpp
10 mVpp
μs
VDD supply ramp time, from 0V to 2.375V
Operating junction temperature
150
-40
110
85(2)
2.625
3.6
ºC
ºC
V
TA
Operating ambient temperature
-40
VIO2.5V
VIO3.3V,INT_N
VIO3.3V
2.5 V I/O voltage (LVCMOS, CMOS and Analog)
Open Drain LVCMOS I/O voltage (INT_N)
Open Drain LVCMOS I/O voltage (SDA, SDC)
2.375
V
2.375
3.6
V
(1) Steps must be taken to ensure the combined AC plus DC supply noise meets the specified VDD supply voltage limits.
(2) Steps must be taken to ensure the operating junction temperature range and ambient temperature stay-in-lock range (TEMPLOCK+
TEMPLOCK-) are met. Refer to Electrical Characteristics for more details concerning TEMPLOCK+ and TEMPLOCK-
,
.
8
Copyright © 2016–2019, Texas Instruments Incorporated
DS250DF410
www.ti.com.cn
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
7.4 Thermal Information
DS250DF410
THERMAL METRIC(1)
CONDITIONS/ASSUMPTIONS(2)
FC/CSP (ABM)
101 PINS
34.2
UNIT
4-Layer JEDEC Board
10-Layer 8-in x 6-in Board
20-Layer 8-in x 6-in Board
30-Layer 8-in x 6-in Board
4-Layer JEDEC Board
16.7
RθJA
Junction-to-ambient thermal resistance
°C/W
15.6
14.6
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
7.8
°C/W
°C/W
4-Layer JEDEC Board
13.7
4-Layer JEDEC Board
0.004
0.004
0.004
0.004
13.0
10-Layer 8-in x 6-in Board
20-Layer 8-in x 6-in Board
30-Layer 8-in x 6-in Board
4-Layer JEDEC Board
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
°C/W
°C/W
10-Layer 8-in x 6-in Board
20-Layer 8-in x 6-in Board
30-Layer 8-in x 6-in Board
11.7
ΨJB
11.5
11.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) No heat sink or airflow was assumed for these estimations. Depending on the application, a heat sink, faster airflow, and/or reduced
ambient temperature (<85 C) may be required in order to meet the maximum junction temperature specification per the Recommended
Operating Conditions.
7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Full-rate
MIN
20.2752
10.1376
5.0688
TYP
MAX
25.8
12.9
6.45
UNIT
Gbps
Gbps
Gbps
Rbaud
Input data rate
Half-rate
Quarter-rate
Single device reading its
configuration from an EEPROM.
Common channel configuration. This
time scales with the number of
devices reading from the same
EEPROM.
tEEPROM
EEPROM configuration load time
EEPROM configuration load time
Power-on reset assertion time
15(1)
40(1)
50
ms
ms
ms
Single device reading its
configuration from an EEPROM.
Unique channel configuration. This
time scales with the number of
devices reading from the same
EEPROM.
tEEPROM
Internal power-on reset (PoR)
stretch between stable power supply
and de-assertion of internal PoR.
The SMBus address is latched on
the completion of the PoR stretch,
and SMBus accesses are permitted.
tPOR
(1) From low assertion of READ_EN_N to low assertion of ALL_DONE_N. Does not include Power-On Reset time.
Copyright © 2016–2019, Texas Instruments Incorporated
9
DS250DF410
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
www.ti.com.cn
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
POWER SUPPLY
TEST CONDITIONS
MIN
TYP
241
233
MAX
UNIT
mW
With CTLE, full DFE, Tx FIR,
Driver, and Crosspoint enabled. Idle
power consumption not included.
305
With CTLE, full DFE, Tx FIR, and
Driver enabled; Crosspoint disabled.
Idle power consumption not
included.
mW
With CTLE, partial DFE (taps 1-2
only), Tx FIR, and Driver enabled;
Crosspoint and DFE taps 3-5
disabled. Idle power consumption
not included.
220
mW
With CTLE, Tx FIR, Driver, and
Crosspoint enabled; DFE disabled.
Idle power consumption not
included.
211
365
290
430
mW
mW
Power consumption per active
channel
Wchannel
Assuming CDR acquiring lock with
CTLE, full DFE, Tx FIR, Driver, and
Crosspoint enabled. Idle power
consumption not included.
Assuming CDR acquiring lock with
CTLE, Tx FIR, Driver, and
Crosspoint enabled; DFE disabled.
Idle power consumption not
included.
318
393
mW
PRBS checker power consumption
only(2)
220
230
302
315
mW
mW
PRBS generator power power
consumption only(2)
Total idle power consumption
Idle/static mode, power supplied, no
high-speed data present at inputs,
all channels automatically powered
down.
Wstatic_total
329
525
665
mW
With CTLE, full DFE, Tx FIR, Driver,
and Crosspoint enabled.
518
505
mA
mA
With CTLE, full DFE, Tx FIR, and
Driver enabled; Crosspoint disabled.
Active mode total device supply
current consumption
With CTLE, partial DFE (taps 1-2
only), Tx FIR, and Driver enabled;
Crosspoint and DFE taps 3-5
disabled.
Itotal
485
470
132
mA
mA
mA
With CTLE, Tx FIR, Driver, and
Crosspoint enabled. DFE disabled.
639
200
Idle/static mode. Power supplied, no
Idle mode total device supply current high-speed data present at inputs,
consumption
Istatic_total
all channels automatically powered
down.
LVCMOS DC SPECIFICATIONS
2.5-V LVCMOS pins
1.75
1.75
VDD
3.6
V
V
V
V
VIH
VIL
Input high-level voltage
Input low-level voltage
3.3-V LVCMOS pin (READ_EN_N)
2.5-V LVCMOS pins
GND
GND
0.7
3.3-V LVCMOS pin (READ_EN_N)
0.8
(2) To ensure optimal performance, it is recommended to not enable more than two PRBS blocks (checker and/or generator) per device.
10
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
High level (1) input voltage
4-level pins ADDR0, ADDR1, and
EN_SMB
0.95 ×
VDD
V
Float level input voltage
10K to GND input voltage
Low -evel (0) input voltage
4-level pins ADDR0, ADDR1, and
EN_SMB
0.67 ×
VDD
V
V
V
VTH
4-level pins ADDR0, ADDR1, and
EN_SMB
0.33 ×
VDD
4-level pins ADDR0, ADDR1, and
EN_SMB
0.1
VOH
VOL
IIH
High-level output voltage
Low-level output voltage
Input high leakage current
Input high leakage current
IOH = 4 mA
2
V
V
IOL = –4 mA
0.4
70
65
Vinput = VDD, Open drain pins
Vinput = VDD and CAL_CLK_IN pin
μA
μA
IIH
Vinput = VDD, ADDR[1:0] and
EN_SMB pins
IIH
Input high leakage current
65
15
μA
IIH
IIL
IIL
Input high leakage current
Input low leakage current
Input low leakage current
Vinput = VDD, READ_EN_N
Vinput = 0 V, Open drain pins
Vinput = 0 V, CAL_CLK_IN pins
μA
μA
μA
-15
-15
Vinput = 0 V, ADDR[1:0],
READ_EN_N, and EN_SMB pins
IIL
Input low leakage current
-115
μA
RECEIVER INPUTS (RXnP, RXnN)
VIDMax
Maximum input differential voltage
For normal operation
1225
<-18
<-14
mVppd
dB
Between 50 MHz and 3.69 GHz
Between 3.69 GHz and 12.9 GHz
Differential input return loss,
SDD11(3)
RLSDD11
dB
Differential to common-mode input
return loss, SDC11(3)
RLSDC11
RLSCD11
RLSCC11
Between 50 MHz and 12.9 GHz
Between 50 MHz and 12.9 GHz
<-23
<-22
dB
dB
Differential to common-mode input
return loss, SCD11(3)
Between 150 MHz and 10 GHz
Between 10 GHz and 12.9 GHz
<-11
<-10
dB
dB
Common-mode input return loss,
SCC11(3)
Minimum input peak-to-peak
amplitude level at device pins
required to assert signal detect.
25.78125Gbps with PRBS7 pattern
and 20dB loss channel
AC signal detect assert (ON)
threshold level
VSDAT
196
147
mVppd
mVppd
Maximum input peak-to-peak
amplitude level at device pins which
causes signal detect to de-assert.
25.78125Gbps with PRBS7 pattern
and 20dB loss channel
AC signal detect de-assert (OFF)
threshold level
VSDDT
TRANSMITTER OUTPUTS (TXnP, TXnN)
Measured with c(0)=7 setting
(Reg_0x3D[6:0]=0x07,
Reg_0x3E[6:0]=0x40,
REG_0x3F[6:0]=0x40). Differential
VOD
Output differential voltage amplitude measurement using an 8T pattern
(eight 1s followed by eight 0s) at
25.78125 Gbps with TXPn and
525
mVppd
TXNn terminated by 50 Ohms to
GND.
(3) Measured with an evaluation board which uses microstrip traces and low-loss dielectric with approximately 3 dB insertion loss at 12.9
GHz between the DS250DF410 and the measurement instrument.
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Measured with c(0)=31 setting
(Reg_0x3D[6:0]=0x1F,
Reg_0x3E[6:0]=0x40,
REG_0x3F[6:0]=0x40). Differential
VOD
Output differential voltage amplitude measurement using an 8T pattern
(eight 1s followed by eight 0s) at
25.78125 Gbps with TXPn and
1225
mVppd
TXNn terminated by 50 Ohms to
GND.
Differential output amplitude with TX
disabled
VODidle
VODres
< 11
< 50
mVppd
mVppd
Difference in VOD between two
adjacent c(0) settings. Applies to
VOD in the 525mVppd to
Output VOD resolution
1225mVppd range [c(0)>4].
With respect to signal ground.
Measured with PRBS9 data pattern.
Common-mode AC output noise
Vcm-TX-AC
6.5
17
mV, RMS
Measured with a 33GHz (-3dB) low-
pass filter.
20%-to-80% rise time and 80%-to-
20% fall time on a clock-like {11111
00000} data pattern at 25.78125
tr, tf
Output transition time
Gbps. Measured for ~800 mVppd
output amplitude and no
ps
equalization: Reg_0x3D=+13,
Reg_0x3E=0, REG_0x3F=0
Between 50 MHz and 5 GHz
Between 5 GHz and 12.9 GHz
<-14
<-13
dB
dB
Differential output return loss,
SDD22(4)
RLSDD22
Common-mode to differential output
return loss, SCD22(4)
RLSCD22
RLSDC22
Between 50 MHz and 12.9 GHz
Between 50 MHz and 12.9 GHz
<-22
<-22
dB
dB
Differential-to-common-mode output
return loss, SDC22(4)
Between 50 MHz and 10 GHz
Between 10 GHz and 12.9 GHz
<-9
dB
dB
Common-mode output return loss,
SCC22(4)
RLSCC22
<-12
SMBus ELECTRICAL CHARACTERISTICS (SLAVE MODE)
VIH
VIL
Input high-level voltage
Input low-level voltage
Input pin capacitance
Low-level output voltage
SDA and SDC
SDA and SDC
1.75
3.6
0.8
V
V
GND
CIN
VOL
15
pF
V
SDA or SDC, IOL = 1.25 mA
0.4
15
SDA or SDC, VINPUT = VIN, VDD,
GND
IIN
Input current
-15
μA
TR
TF
SDA rise time, read operation
SDA fall time, read operation
Pull-up resistor = 1 kΩ, Cb = 50pF
Pull-up resistor = 1 kΩ, Cb = 50pF
150
4.5
ns
ns
(4) Measured with an evaluation board which uses microstrip traces and low-loss dielectric with approximately 3 dB insertion loss at 12.9
GHz between the DS250DF410 and the measurement instrument.
12
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ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
7.6 Timing Requirements, Retimer Jitter Specifications
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Measured at 25.78125 Gbps to a
probability level of 1E-12 with
PRBS11 data pattern an evaluation
board traces de-embedded.
UIpp @
1E-12
JTJ
Output total jitter (TJ)
0.17
Measured at 25.78125 Gbps to a
probability level of 1E-12 with
PRBS11 data pattern an evaluation
board traces de-embedded
JRJ
Output random Jitter (RJ)
Output duty cycle distortion (DCD)
Jitter peaking
6
4
mUI RMS
mUIpp
dB
Measured at 25.78125 Gbps to a
probability level of 1E-12 with
PRBS11 data pattern an evaluation
board traces de-embedded
JDCD
JPEAK
JPEAK
Measured at 10.3125 Gbps with
PRBS7 data pattern. Peaking
frequency in the range of 1 to 6
MHz.
0.8
0.4
Measured at 25.78125 Gbps with
PRBS7 data pattern. Peaking
frequency in the range of 1 to 17
MHz.
Jitter peaking
dB
Data rate of 10.3125Gbps with
PRBS7 pattern
BWPLL
BWPLL
PLL bandwidth
PLL bandwidth
5.3
5.5
MHz
MHz
Data rate of 25.78125Gbps with
PRBS7 pattern
Measured at 25.78125 Gbps with
SJ frequency = 190 KHz, 30dB
input channel loss, PRBS31 data
pattern, 800 mVppd launch
amplitude, and 0.078 UIpp total
uncorrelated output jitter in addition
to the applied SJ. BER < 1E-12.
JTOL
JTOL
JTOL
Input jitter tolerance
Input jitter tolerance
Input jitter tolerance
9
1
UIpp
UIpp
UIpp
Measured at 25.78125 Gbps with
SJ frequency = 940 KHz, 30dB
input channel loss, PRBS31 data
pattern, 800 mVppd launch
amplitude, and 0.078 UIpp total
uncorrelated output jitter in addition
to the applied SJ. BER < 1E-12.
Measured at 25.78125 Gbps with
SJ frequency > 15MHz, 30dB input
channel loss, PRBS31 data pattern,
800 mVppd launch amplitude, and
0.078 UIpp total uncorrelated output
jitter in addition to the applied SJ.
BER < 1E-12.
0.3
CDR stay-in-lock ambient
temperature range, negative ramp.
85 °C starting ambient temperature,
ramp rate -3 °C/minute, 1.7
liters/sec airflow, 12 layer PCB.
TEMPLOCK- Maximum temperature change
below initial CDR lock acquisition
temperature.
115
125
°C
°C
CDR stay-in-lock ambient
temperature range, positive ramp.
TEMPLOCK+ Maximum temperature change
above initial CDR lock acquisition
temperature.
-40 °C starting ambient
temperature, ramp rate +3
°C/minute, 1.7 liters/sec airflow, 12
layer PCB.
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7.7 Timing Requirements, Retimer Specifications
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
No crosspoint; CDR enabled and
locked.
3.5UI +
125ps
ps
Input-to-output latency (propagation Crosspoint enabled; CDR enabled
3.5UI +
145ps
tD
ps
ps
delay) through a channel
and locked.
No crosspoint; CDR in raw (bypass)
mode.
< 145
Latency difference between
channels at full-rate. 25.78125 Gbps
data rate.
tSK
Channel-to-channel interpair skew
CDR lock acquisition time
< 30
ps
Measured at 25.78125 Gbps, Adapt
Mode = 1 (Reg_0x31[6:5]=0x1),
EOM timer = 0x5
tlock
< 100
< 100
ms
(Reg_0x2A[7:4]=0x5).
Measured at 10.3125 Gbps, Adapt
Mode = 1 (Reg_0x31[6:5]=0x1),
EOM timer = 0x5
tlock
CDR lock acquisition time
ms
(Reg_0x2A[7:4]=0x5).
7.8 Timing Requirements, Recommended Calibration Clock Specifications
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
PPM
CLKf
Calibration clock frequency
Calibration clock PPM tolerance
25
CLKPPM
-100
40%
100
Recommended/tolerable input duty
cycle
CLKIDC
50%
60%
Intrinsic duty cycle distortion of chip
calibration clock output at the
CAL_CLK_OUT pin, assuming 50%
duty cycle on CAL_CLK_IN pin.
Intrinsic calibration clock duty cycle
distortion
CLKODC
45%
55%
Assumes worst-case 60%/40% input
duty cycle on the first device.
CAL_CLK_OUT from first devuce
connects to CAL_CLK_IN of second
device, and so on until the last
device.
Number of devices which can be
cascaded from CAL_CLK_OUT to
CAL_CLK_IN
CLKnum
20
N/A
7.9 Recommended SMBus Switching Characteristics (Slave Mode)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
SDC clock frequency
Data hold time
TEST CONDITIONS
MIN
TYP
100
0.75
100
MAX
UNIT
kHz
ns
fSDC
10
400
tHD-DAT
tSU-DAT
Data setup time
ns
14
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ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
7.10 Recommended SMBus Switching Characteristics (Master Mode)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
SDC clock frequency
SDC low period
TEST CONDITIONS
MIN
260
TYP
303
1.90
1.40
0.6
MAX
346
UNIT
kHz
μs
fSDC
TLOW
1.66
1.22
2.21
1.63
THIGH
THD-STA
TSU-STA
THD-DAT
TSD-DAT
TSU-STO
TBUF
SDC high period
μs
Hold time start operation
Setup time start operation
Data hold time
μs
0.6
μs
0.6
μs
Data setup time
0.1
μs
Stop condition setup time
Bus free time between Stop-Start
SDC rise time
0.6
μs
1.3
μs
TR
Pull-up resistor = 1 kΩ
Pull-up resistor = 1 kΩ
300
300
ns
TF
SDC fall time
ns
7.11 Recommended JTAG Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ns
tTCK
tSU
TCK clock period
100
TDI, TMS setup time to TCK
TDI, TMS hold time to TCK
TCK falling edge to TDO
50
50
50
ns
tHD
ns
tDLY
ns
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7.12 Typical Characteristics
1.6
1.6
1.4
1.2
1
c(0)=7
c(0)=7
c(0)=16
c(0)=16
c(0)=31
1.4
c(0)=31
1.2
1
0.8
0.6
0.4
0.8
0.6
0.4
2.325
2.395
2.465
2.535
2.605
2.675
-40
-15
10
35
60
85
VDD Supply Voltage (V)
Ambient Temperature (°C)
C001
C002
图 1. Typical VOD vs Supply Voltage
图 2. Typical VOD vs Temperature
0.25
0.2
0.15
0.1
0.05
0
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
T = 25C, VDD = 2.35V
T = 25C, VDD = 2.65V
T = 95C, VDD = 2.35V
T = 95C, VDD = 2.65V
T = -40C, VDD = 2.35V
T = -40C, VDD = 2.65V
TJ, VDD = 2.35V
TJ, VDD = 2.65V
DJ, VDD = 2.35V
DJ, VDD = 2.65V
0
5
10
15
20
25
30
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
Main-Cursor
Temperature (degrees C)
C002
C001
图 3. Typical VOD vs FIR Main-Cursor
图 4. Typical Output Jitter vs Temperature
at 25.78125 Gbps
45
40
35
30
25
20
15
10
5
3
2.8
2.6
2.4
2.2
2
VDD = 2.35V
VDD = 2.5V
VDD = 2.65V
VDD = 2.35V
VDD = 2.5V
VDD = 2.65V
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
0.1
1
10
100
0.5
1
2
4
8
16
32
64
Frequency (MHz)
Frequency (MHz)
C003
C004
0.1 MHz to 100 MHz
T = 25°C
Input Random Jitter = 0.078 UIpp
0.5 MHz to 100 MHz
T = 25°C
Input Random Jitter = 0.078 UIpp
图 5. Typical Sinusoidal Input Jitter Tolerance for
图 6. Typical Input Jitter Tolerance for
30-dB Channel at 25.78125 Gbps
30-dB Channel at 25.78125 Gbps
16
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ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
8 Detailed Description
8.1 Overview
The DS250DF410 is a four-channel multi-rate retimer with integrated signal conditioning. Each of the four
channels operates independently. Each channel includes a continuous-time linear equalizer (CTLE) and a
Decision Feedback Equalizer (DFE), which together compensate for the presence of a dispersive transmission
channel between the source transmitter and the DS250DF410 receiver. The CTLE and DFE are self-adaptive.
Each channel includes an independent voltage-controlled oscillator (VCO) and phase-locked loop (PLL) which
produce a clean clock that is frequency-locked to the clock embedded in the input data stream. The high-
frequency jitter on the incoming data is attenuated by the PLL, producing a clean clock with substantially-reduced
jitter. This clean clock is used to re-time the incoming data, removing high-frequency jitter from the data stream
and reproducing the data on the output with significantly-reduced jitter.
Each channel of the DS250DF410 features an output driver with adjustable differential output voltage and output
equalization in the form of a three-tap finite impulse response (FIR) filter. The output FIR compensates for
dispersion in the transmission channel at the output of the DS250DF410.
Between each group of two adjacent channels (e.g. between channels 0 and 1, 2 and 3) is a full 2x2 cross-point
switch. This allows multiplexing and de-multiplexing/fanout applications for fail-over redundancy, as well as
cross-over applications to aid PCB routing.
Each channel also includes diagnostic features such as a Pseudo Random Bit Sequence (PRBS) pattern
generator and checker, as well as a non-destructive eye opening monitor (EOM). The EOM can be used to plot
the post-equalized eye at the input to the decision slicer or simply to read the horizontal eye opening (HEO) and
vertical eye opening (VEO).
The DS250DF410 is configurable through a single SMBus port. The DS250DF410 can also act as an SMBus
master to configure itself from an EEPROM. Up to sixteen DS250DF410 devices can share a single SMBus.
The sections which follow describe the functionality of various circuits and features within the DS250DF410. For
more information about how to program or operate these features, consult the DS250DF410 Programming
Guide.
8.2 Functional Block Diagram
One of Four Channels
To adjacent
channel
DFE
Term
Raw
Retimed
PRBS
RXnP
RXnN
TXnP
TXnN
CTLE+VGA
X-point
+
Sampler
TX FIR
Driver
PRBS
Gen
Signal
Detect
Voltage
Regulator
Eye
Monitor
PRBS
Checker
Voltage
Regulator
PFD, CDR,
and Divider
VCO
Channel Digital Core
CAL_CLK_IN
ADDRn
Buffer
CAL_CLK_OUT
SCL
SDA
Power-On
Reset
Always-On
10 MHz
Shared Digital Core
READ_EN_N
EN_SMB
ALL_DONE_N
INT_N
Shared Digital Core
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8.3 Feature Description
8.3.1 Device Data Path Operation
The DS250DF410 data path consists of several key blocks as shown in the functional block diagram. These key
circuits are:
•
•
•
•
•
•
•
•
Signal Detect
Continuous Time Linear Equalizer (CTLE)
Variable Gain Amplifier (VGA)
Cross-Point Switch
Decision Feedback Equalizer (DFE)
Clock and Data Recovery (CDR)
Calibration Clock
Differential Driver with FIR Filter
8.3.2 Signal Detect
The DS250DF410 receiver contains a signal detect circuit. The signal detect circuit monitors the energy level on
the receiver inputs and powers on or off the rest of the high-speed data path if a signal is detected or not. By
default, each channel allows the signal detect circuit to automatically power on or off the rest of the high speed
data path depending on the presence of an input signal. The signal detect block can be manually controlled in
the SMBus channel registers. This can be useful if it is desired to manually force channels to be disabled. For
information on how to manually operate the signal detect circuit refer to the DS250DF410 Programming Guide.
8.3.3 Continuous Time Linear Equalizer (CTLE)
The CTLE in the DS250DF410 is a fully-adaptive equalizer. The CTLE adapts according to a Figure of Merit
(FOM) calculation during the lock acquisition process. The FOM calculation is based upon the horizontal eye
opening (HEO) and vertical eye opening (VEO). Once the CDR locks and the CTLE adapts, the CTLE boost
level is frozen until a manual re-adapt command is issued or until the CDR re-enters the lock acquisition state.
The CTLE can be re-adapted by resetting the CDR.
The CTLE consists of 4 stages, with each stage having 2-bit boost control. This allows for 256 different boost
combinations. The CTLE adaption algorithm allows the CTLE to adapt through 16 of these boost combinations.
These 16 boost combinations comprise the EQ Table in the channel registers. See channel registers 0x40
through 0x4F. This EQ Table can be reprogrammed to support up to 16 of the 256 boost settings.
The boost levels can be set between 8 dB and 25 dB (at 12.89 GHz.)
8.3.4 Variable Gain Amplifier (VGA)
The DS250DF410 receiver implements a VGA. The VGA assists in the recovery of extremely small signals,
working in conjunction with the CTLE to equalize and scale amplitude. The VGA has 1-bit control via
Reg_0x8E[0], and the VGA is in the low-gain state (Reg_0x8E[0]=0) by default. In addition to the VGA, the CTLE
implements its own gain control via Reg_0x13[5] to adjust the DC amplitude similar to the VGA. For more
information on how to configure the VGA and EQ gain, refer to the DS250DF410 Programming Guide.
8.3.5 Cross-Point Switch
Each group of two adjacent channels in the DS250DF410 has a 2×2 cross-point that may be enabled to
implement a 2-to-1 mux, a 1-to-2 fanout, or an A-to-B/B-to-A lane cross. A cross-point exists between the
following channel pairs:
•
•
Channel 0 and Channel 1
Channel 2 and Channel 3
18
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Feature Description (接下页)
8.3.6 Decision Feedback Equalizer (DFE)
A 5-tap DFE can be enabled within the data path of each channel to assist with reducing the effects of crosstalk,
reflections, or post cursor inter-symbol interference (ISI). The DFE must be manually enabled, regardless of the
selected adapt mode. Once the DFE has been enabled it can be configured to adapt only during lock acquisition
or to adapt continuously. The DFE can also be manually configured to specified tap polarities and tap weights.
However, when the DFE is configured manually the DFE auto-adaption should be disabled. For many
applications with lower insertion loss (i.e. < 30 dB) lower crosstalk, and/or lower reflections, part or all of the DFE
can be disabled to reduce power consumption. The DFE can either be fully enabled (taps 1-5), partially enabled
(taps 1-2 only), or fully disabled (no taps).
The DFE taps are all feedback taps with 1UI spacing. Each tap has a specified boost weight range and polarity
bit.
表 1. DFE Tap Weights
DFE PARAMETER
Tap 1 Weight Range
Tap 2-5 Weight Range
Tap Weight Step Size
DECIMAL (REGISTER VALUE)
VALUE (mV) (TYP)
0 - 31
0 - 15
NA
0 – 217
0 – 105
7
0: (+) positive; feedback value creates a low-pass filter response, thus providing attenuation to
correct for negative-sign post-cursor ISI
Polarity
1: (-) negative; Feedback value creates a high-pass filter response, thus providing boost to correct
for positive-sign post-cursor ISI.
8.3.7 Clock and Data Recovery (CDR)
The CDR consists of a Phase Locked Loop (PLL), PPM counter, and Input and Output Data Multiplexers (mux)
allowing for retimed data, un-retimed data, PRBS generator and output muted modes.
By default, the equalized data is fed into the CDR for clock and data recovery. The recovered data is then output
to the FIR filter and differential driver together with the recovered clock which has been cleaned of any high-
frequency jitter outside the bandwidth of the CDR clock recovery loop. The bandwidth of the CDR defaults to 5.5
MHz (typ) in full-rate (divide-by-1) mode and 5.3 MHz (typ) in sub-rate mode. The CDR bandwidth is adjustable.
Refer to the DS250DF410 Programming Guide for more information on adjusting the CDR bandwidth. Users can
configure the CDR data to route the recovered clock and data to the PRBS checker. Users also have the option
of configuring the output of the CDR to send raw non-retimed data, or data from the pattern generator.
The CDR requires the following to be properly configured:
•
•
25 MHz calibration clock to run the PPM counter (CAL_CLK_IN).
Expected data rates must be programmed into the CDR either through the rate table or entered manually with
the corrected divider settings. Refer to the Programming Guide for more information on configuring the CDR
for different data rates.
8.3.8 Calibration Clock
The calibration clock is not part of the CDR’s PLL and thus is not used for clock and data recovery. The
calibration clock is connected only to the PPM counter for each CDR. The PPM counter constrains the allowable
lock ranges of the CDR according to the programmed values in the rate table or the manually entered data rates.
The host should provide an input calibration clock signal of 25 MHz frequency. Because this clock is not used for
clock and data recovery, there are no stringent jitter requirements placed on this 25 MHz calibration clock.
8.3.9 Differential Driver with FIR Filter
The DS250DF410 output driver has a three-tap finite impulse response (FIR) filter which allows for pre- and post-
cursor equalization to compensate for a wide variety of output channel media. The filter consists of a weighted
sum of three consecutive retimed bits as shown in the following diagram. C[0] can take on values in the range [-
31, +31]. C[-1] and C[+1] can take on values in the range [-15, 15].
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Retimed
Data
FIR filter
output
x
+
+
1 UI
Delay
C[-1]
Pre-cursor
x
1 UI
Delay
C[0]
Main-curosr
x
C[+1]
Post-cursor
图 7. FIR Filter Functional model
When utilizing the FIR filter, it is important to abide by the following general rules:
•
•
|C[-1]| + |C[0]| + |C[+1]| ≤ 31; the FIR tap coefficients absolute sum must be less or equal to 31
sgn(C[-1]) = sgn(C[+1]) ≠ sgn(C[0]), for high-pass filter effect; the sign for the pre-cursor and/or post-cursor
tap must be different from main-cursor tap to realize boost effect
•
sgn(C[-1]) = sgn(C[+1]) = sgn(C[0]), for low-pass filter effect; the sign for the pre-cursor and/or post-cursor tap
must be equal to the main-cursor tap to realize attenuation effect
The FIR filter is used to pre-distort the transmitted waveform to compensate for frequency-dependant loss in the
output channel. The most common way of pre-distorting the signal is to accentuate the transitions and de-
emphasize the non-transitions. The bit before a transition is accentuated via the pre-cursor tap, and the bit after
the transition is accentuated via the post-cursor tap. The figures below give a conceptual illustration of how the
FIR filter affects the output waveform. The following characteristics can be derived from the example waveforms.
•
•
•
•
VODpk-pk= v7 - v8
VODlow-frequency = v2 - v5
RpredB = 20 * log10 (v3 ⁄v2 )
RpstdB = 20 * log10 (v1 ⁄v2 )
Transmitted
Bits: 0
0
1
1
1
1
0
0
0
0
1
0
1
Differential
Voltage
v1
v7
v2
v3
0V
Time [UI]
v5
v6
v4
v8
图 8. Conceptual FIR Waveform With Post-Cursor Only
20
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Transmitted
Bits: 0
0
1
1
1
1
0
0
0
0
1
0
1
Differential
Voltage
v3
v7
v1
v2
0V
Time [UI]
v4
v5
v6
v8
图 9. Conceptual FIR Waveform With Pre-Cursor Only
Transmitted
Bits: 0
0
1
1
1
1
0
0
0
0
1
0
1
Differential
Voltage
v7
v1
v3
v2
0V
Time [UI]
v5
v6
v4
v8
图 10. Conceptual FIR Waveform With Both Pre- and Post-Cursor
8.3.9.1 Setting the Output VOD, Pre-Cursor, and Post-Cursor Equalization
The output differential voltage (VOD), pre-cursor, and post-cursor equalization of the driver is controlled by
manipulating the FIR tap settings. The main cursor tap is the primary knob for amplitude adjustment. The pre-
and post-cursor FIR tap settings can then be adjusted to provide equalization. To maintain a constant peak-to-
peak VOD, the user should adjust the main cursor tap value relative to the pre- and post-cursor tap changes so
as to maintain a constant absolute sum of the FIR tap values. The table below shows various settings for VOD
settings ranging from 205 mVpp to 1225 mVpp (typical). Note that the output peak-to-peak amplitude is a
function of the sum of the absolute values of the taps, whereas the low-frequency amplitude is purely a function
of the main-cursor value.
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RPST(dB)
表 2. Typical VOD and FIR Values
FIR SETTINGS
Peak-to Peak
RPRE(dB)
PRE-CURSOR:
REG_0x3E[6:0]
MAIN-CURSOR:
REG_0x3D[6:0]
POST-CURSOR:
VOD(V)
REG_0x3F[6:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-1
-2
-3
-4
0
0
0
0
0.205
0.260
0.305
0.355
0.395
0.440
0.490
0.525
0.565
0.610
0.650
0.685
0.720
0.760
0.790
0.825
0.860
0.890
0.925
0.960
0.985
1.010
1.040
1.075
1.095
1.125
1.150
1.165
1.190
1.205
1.220
1.225
0.960
0.960
0.960
0.960
0.960
0.960
0.960
0.960
0.960
0.960
0.960
0.960
0.960
1.165
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
1.0
1.6
2.4
3.3
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
2.1
2.5
3.1
3.8
4.7
5.8
7.2
9.0
11.6
NA
NA
NA
NA
1.1
+1
+2
0
+3
0
+4
0
+5
0
+6
0
+7
0
+8
0
+9
0
+10
+11
+12
+13
+14
+15
+16
+17
+18
+19
+20
+21
+22
+23
+24
+25
+26
+27
+28
+29
+30
+31
+18
+17
+16
+15
+14
+13
+12
+11
+10
18
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
0
17
0
16
0
15
0
26
-1
22
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表 2. Typical VOD and FIR Values (接下页)
FIR SETTINGS
Peak-to Peak
VOD(V)
RPRE(dB)
RPST(dB)
PRE-CURSOR:
MAIN-CURSOR:
REG_0x3D[6:0]
POST-CURSOR:
REG_0x3F[6:0]
REG_0x3E[6:0]
0
0
25
24
23
22
21
20
19
18
17
16
15
26
25
24
23
22
21
20
-2
-3
-4
-5
-6
-7
-8
-9
-10
-11
-12
0
1.165
1.165
1.165
1.165
1.165
1.165
1.165
1.165
1.165
1.165
1.165
1.165
1.165
1.165
1.165
1.165
1.165
1.165
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
0.7
1.2
1.5
2.0
2.6
3.2
4.0
1.3
1.8
2.2
2.7
3.3
3.9
4.7
5.7
6.9
8.4
10.1
NA
NA
NA
NA
NA
NA
NA
0
0
0
0
0
0
0
0
0
-1
-2
-3
-4
-5
-6
-7
0
0
0
0
0
0
The recommended pre-cursor and post-cursor settings for a given channel will depend on the channel
characteristics (mainly insertion loss) as well as the equalization capabilities of the downstream receiver. The
DS250DF410 receiver, with its highly-capable CTLE and DFE, does not require a significant amount of pre- or
post-cursor. The figures below give general recommendations for pre- and post-cursor for different channel loss
conditions. The insertion loss (IL) in these plots refers to the total loss between the link partner transmitter and
the DS250DF410 receiver.
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图 11. Guideline for Link Partner FIR Settings When IL ≤ 15 dB
图 12. Guideline for Link Partner FIR Settings When IL ≤ 25 dB
24
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图 13. Guideline for Link Partner FIR Settings When IL ≤ 35 dB
8.3.9.2 Output Driver Polarity Inversion
In some applications, it may be necessary to invert the polarity of the data transmitted from the retimer. To invert
the polarity of the data, read back the FIR polarity settings for the pre, main and post cursor taps and then invert
these bits.
8.3.10 Debug Features
8.3.10.1 Pattern Generator
Each channel in the DS250DF410 can be configured to generate a 16-bit user-defined data pattern or a pseudo
random bit sequence (PRBS). The user defined pattern can also be set to automatically invert every other 16-bit
symbol for DC balancing purposes. The DS250DF410 pattern generator supports the following PRBS
sequences:
•
•
•
•
•
•
•
•
PRBS – 27 - 1
PRBS – 29 - 1
PRBS – 211 - 1
PRBS – 215 - 1
PRBS – 223 - 1
PRBS – 231 - 1
PRBS – 258 - 1
PRBS – 263 - 1
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8.3.10.2 Pattern Checker
The pattern checker can be manually set to look for specific PRBS sequences and polarities or it can be set to
automatically detect the incoming pattern and polarity. The PRBS checker supports the same set of PRBS
patterns as the PRBS generator.
The pattern checker consists of an 11-bit error counter. The pattern checker uses 32- bit words, but every bit in
the word is checked for error, so the error count represents the count of single bit errors.
To read out the bit and error counters, the pattern checker must first be frozen. Continuous operation with
simultaneous read out of the bit and error counters is not supported in this implementation. Once the bit and
error counter is read, they can be un-frozen to continue counting.
8.3.10.3 Eye Opening Monitor
The DS250DF410’s Eye Opening Monitor (EOM) measures the internal data eye at the input of the decision
slicer and can be used for 2 functions:
1. Horizontal Eye Opening (HEO) and Vertical Eye Opening (VEO) measurement
2. Full Eye Diagram Capture
The HEO measurement is made at the 0V crossing and is read in channel register 0x27. The VEO measurement
is made at the 0.5 UI mark and is read in channel register 0x28. The HEO and VEO registers can be read from
channel registers 0x27 and 0x28 at any time while the CDR is locked. The following equations are used to
convert the contents of channel registers 0x27 and 0x28 into their appropriate units:
•
•
HEO [UI] = Reg_0x27 ÷ 32
VEO [mV] = Reg_0x28 x 3.125
A full eye diagram capture can be performed when the CDR is locked. The eye diagram is constructed within a
64 x 64 array, where each cell in the matrix consists of an 16-bit word representing the total number of hits
recorded at that particular phase and voltage offset. Users can manually adjust the vertical scaling of the EOM or
allow the state machine to control the scaling which is the default option. The horizontal scaling controlled by the
state machine and is always directly proportional to the data rate.
When a full eye diagram plot is captured, the retimer will shift out four 16-bit words of residual data that should
be discarded followed by 4096 16-bit words that make up the 64 × 64 eye plot. The first actual word of the eye
plot from the retimer is for (X, Y) position (0,0), which is the earliest position in time and the most negative
position in voltage. Each time the eye plot data is read out the voltage position is incremented. Once the voltage
position has incremented to position 63 (the most positive voltage), the next read will cause the voltage position
to reset to 0 (the most negative voltage) and the phase position to increment. This process will continue until the
entire 64 × 64 matrix is read out. 图 14 below shows the EOM read out sequence overlaid on top of a simple eye
opening plot. In this plot any hits are shown in green. This type of plot is helpful for quickly visualizing the HEO
and VEO. Users can apply different algorithms to the output data to plot density or color gradients to the output
data.
26
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63
127
4095
63
0
64
4032
63
图 14. EOM Full Eye Capture Readout
To manually control the EOM vertical range, remove scaling control from the state machine then select the
desired range:
Channel Reg 0x2C[6] → 0 (see 表 3).
表 3. Eye Opening Monitor Vertical Range Settings
CH REG 0x11[7:6] VALUE
EOM VERTICAL RANGE [mV]
2’b00
2'b01
2'b10
2'b11
±100
±200
±300
±400
The EOM operates as an under-sampled circuit. This allows the EOM to be useful in identifying over
equalization, ringing and other gross signal conditioning issues. However, the EOM cannot be correlated to a bit
error rate.
The EOM can be accessed in two ways to read out the entire eye plot:
•
•
Multi-byte reads can be used such that data is repeatedly latched out from channel register 0x25.
With single byte reads, the MSB are located in register 0x25 and the LSB are located in register 0x26. In this
mode, the device must be addressed each time a new byte is read.
To perform a full eye capture with the EOM, follow these steps below within the desired channel register set:
表 4. Eye Opening Monitor Full Eye Capture Instructions
STEP
REGISTER [bits]
0x67[5]
Operation
Write
VALUE
DESCRIPTION
Disable lock EOM lock monitoring
Set the desired EOM vertical range
1
0
0
0x2C[6]
Write
2
0x11[7:6]
Write
2'b--
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表 4. Eye Opening Monitor Full Eye Capture Instructions (接下页)
STEP
REGISTER [bits]
0x11[5]
Operation
Write
VALUE
DESCRIPTION
3
4
0
1
Power on the EOM
Enable fast EOM
0x24[7]
Write
Begin read out of the 64 x 64 array, discard first 4 words
Ch reg 0x24[0] is self-clearing.
0x24[0]
0x25
0x26
5
6
Read
1
0x25 is the MSB of the 16-bit word
0x26 is the LSB of the 16-bit word
0x25
0x26
Continue reading information until the 64 x 64 array is
complete.
Read
0x67[5]
0x2C[6]
0x11[5]
0x24[7]
Write
Write
Write
Write
1
1
1
0
Return the EOM to its original state. Undo steps 1-4
7
8.3.11 Interrupt Signals
The DS250DF410 can be configured to report different events as interrupt signals. These interrupt signals do not
impact the operation of the device, but merely report that the selected event has occurred. The interrupt bits in
the register sets are all sticky bits. This means that when an event triggers an interrupt the status bit for that
interrupt is set to logic HIGH. This interrupt status bit will remain at logic HIGH until the bit has been read. Once
the bit has been read it will be automatically cleared, which allows for new interrupts to be detected. The
DS250DF410 will report the occurrence of an interrupt through the INT_N pin. The INT_N pin is an open drain
output that will pull the line low when an interrupt signal is triggered.
Note that all available interrupts are disabled by default. Users must activate the various interrupts before they
can be used.
The interrupts available in the DS250DF410 are:
•
•
•
•
•
•
CDR loss of lock
CDR locked
Signal detect loss
Signal detected
PRBS pattern checker bit error detected
HEO/VEO threshold violation
When an interrupt occurs, share register 0x08 reports which channel generated the interrupt request. Users can
then select the channel(s) that generated the interrupt request and service the interrupt by reading the
appropriate interrupt status bits in the corresponding channel registers. For more information on reading interrupt
status, refer to the DS250DF410 Programming Guide.
8.3.12 JTAG Boundary Scan
The DS250DF410 supports JTAG and AC-JTAG boundary scan to facilitate in-system manufacturing tests. JTAG
mode is enabled with the EN_SMB as shown in 表 5. Refer to the DS250DF410 Product Folder for the boundary
scan description language (BSDL) file for the DS250DF410.
表 5. JTAG Mode pins
PIN
INTERNAL PULL-UP /
PULL-DOWN
JTAG MODE FUNCTIONALITY
(EN_SMB = 1 kΩ to GND)
NAME
NO.
F1
CAL_CLK_IN/JTAG_TDI
CAL_CLK_OUT/JTAG_TDO
ADDR1/JTAG_TRS
Weak pull-up
None
JTAG Test Data In (TDI)
JTAG Test Data Out (TDO)
JTAG Test Rset (TRS)
F11
D1
Weak pull-up
None
TEST0/JTAG_TCK
D10
D2
JTAG Test Clock (TCK)
TES1/JTAG_TMS
Weak pull-up
JTAG Test Mode Select (TMS)
28
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8.4 Device Functional Modes
8.4.1 Supported Data Rates
The DS250DF410 supports a wide range of input data rates, including divide-by-2 and divide-by-4 sub-rates. The
supported data rates are listed in 表 6. Refer to the DS250DF410 Programming Guide for information on
configuring the DS250DF410 for different data rates.
表 6. Supported Data Rates
DATA RATE RANGE
DIVIDER
CDR MODE
COMMENT
MIN
MAX
≥ 20.6 Gbps
≥ 10.3 Gbps
> 6.45 Gbps
≥ 5.15 Gbps
≥ 1.25 Gbps
≤ 25.8 Gbps
≤ 12.9 Gbps
< 10.3 Gbps
≤ 6.45 Gbps
< 5.15 Gbps
1
2
Enabled
Enabled
Disabled
Enabled
Disabled
N/A
4
Output jitter will be higher with CDR disabled.
Output jitter will be higher with CDR disabled.
N/A
8.4.2 SMBus Master Mode
SMBus master mode allows the DS250DF410 to program itself by reading directly from an external EEPROM.
When using the SMBus master mode, the DS250DF410 will read directly from specific location in the external
EEPROM. When designing a system for using the external EEPROM, the user needs to follow these specific
guidelines:
•
•
Maximum EEPROM size is 2048 Bytes
Minimum EEPROM size for a single DS250DF410 with individual channel configuration is 305 Bytes (3 base
header bytes + 12 address map bytes + 4 × 72 channel register bytes + 2 share register bytes; bytes are
defined to be 8-bits)
•
•
•
•
Set ENSMB = Float, for SMBus master mode
The external EEPROM device address byte must be 0xA0
The external EEPROM device must support 400kHz operation at 2.5-V or 3.3-V supply
Set the SMBus address of the DS250DF410 by configuring the ADDR0 and ADDR1 pins
When loading multiple DS250DF410 devices from the same EEPROM, use these guidelines to configure the
devices:
•
•
•
Configure the SMBus addresses for each DS250DF410 to be sequential. The first device in the sequence
must have an address of 0x30
Daisy chain READ_EN_N and ALL_DONE_N from one device to the next device in the sequence so that they
do not compete for the EEPROM at the same time.
If all of the DS250DF410 devices share the same EEPROM channel and share register settings, configure
the common channel bit in the base header to 1. With common channel configuration enabled, each
DS250DF410 device will configure all 4 channels with the same settings.
When loading a single DS250DF410 from an EEPROM, use these guidelines to configure the device:
•
Set the common channel bit to 0 to allow for individual channel configuration, or set the common channel bit
to 1 to load the same configuration settings to all channels.
•
•
When configuring individual channels, a 512, 1024 or 2048 Byte EEPROM must be used.
If there are more than three DS250DF410 devices on a PCB that require individual channel configuration,
then each device must have its own EEPROM.
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8.4.3 Device SMBus Address
The DS250DF410’s SMBus slave address is strapped at power up using the ADDR[1:0] pins. The pin state is
read on power up, after the internal power-on reset signal is de-asserted. The ADDR[1:0] pins are four-level
LVCMOS IOs, which provides for 16 unique SMBus addresses. The four levels are achieved by pin strap options
as follows:
•
•
•
•
0: 1 kΩ to GND
R: 10 kΩ to GND (20 kΩ also acceptable)
F: Float
1: 1 kΩ to VDD
表 7. SMBus Address Map
REQUIRED ADDRESS PIN STRAP VALUE
8-BIT WRITE ADDRESS [HEX]
ADDR1
ADDR0
0x30
0x32
0x34
0x36
0x38
0x3A
0x3C
0x3E
0x40
0x42
0x44
0x46
0x48
0x4A
0x4C
0x4E
0
0
0
R
F
1
0
0
R
R
R
R
F
F
F
F
1
0
R
F
1
0
R
F
1
0
1
R
F
1
1
1
8.5 Programming
8.5.1 Bit Fields in the Register Set
Many of the registers in the DS250DF410 are divided into bit fields. This allows a single register to serve multiple
purposes which may be unrelated. Often, configuring the DS250DF410 requires writing a bit field that makes up
only part of a register value while leaving the remainder of the register value unchanged. The procedure for
accomplishing this task is to read in the current value of the register to be written, modify only the desired bits in
this value, and write the modified value back to the register. Of course, if the entire register is to be changed,
rather than just a bit field within the register, it is not necessary to read in the current value of the register first. In
all register configuration procedures described in the following sections, this procedure should be kept in mind. In
some cases, the entire register is to be modified. When only a part of the register is to be changed, however, the
procedure described above should be used.
Most register bits can be read or written to. However, some register bits are constrained to specific interface
instructions.
Register bits can have the following interface constraints:
•
•
•
R - Read only
RW - Read/Write
RWSC - Read/Write, self-clearing
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Programming (接下页)
8.5.2 Writing to and Reading from the Global/Shared/Channel Registers
The DS250DF410 has 3 types of registers:
1) Global Registers – These registers can be accessed at any time and are used to select individual channel
registers, the shared registers or to read back the TI ID and version information.
2) Shared Registers – These registers are used for device-level configuration, status read back or control.
3) Channel Registers – These registers are used to control and configure specific features for each individual
channel. All channels have the same channel register set and can be configured independent of each other.
The global registers can be accessed at any time, regardless of whether the shared or channel register set is
selected. The DS250DF410 global registers are located on addresses 0xEF-0xFF. The function of the global
registers falls into the following categories:
•
•
•
Channel selection and share enabling – Registers 0xFC and 0xFF
Device and version information – Registers 0xEF-0xF3
Reserved/unused registers – all other addresses
Register 0xFC is used to select the channel registers to be written to. To select a channel, write a 1 to its
corresponding bit in register 0xFC. Note that more than one channel may be written to by setting multiple bits in
register 0xFC. However, when performing an SMBus read transaction only one channel can be selected at a
time. If multiple channels are selected in register 0xFC when attempting to perform an SMBus read, the device
will return 0xFF.
Register 0xFF bit 1 can be used to perform broadcast register writes to all channels. A single channel read-
modify broadcast write type commands can be accomplished by setting register 0xFF to 0x03 and selecting a
single channel in register 0xFC. This type of configuration allows for the reading of a single channel's register
information and then writing to all channels with the modified value. Register 0xFF bit 0 is used to select the
shared register page or the channel register page for the channels selected in register 0xFC.
TI repeaters/retimers have a vendor ID register (0xFE) which will always read back 0x03. In addition, there are
three device ID registers (0xF0, 0xF1, and 0xF3). These are useful to verify that there is a good SMBus
connection between the SMBus master and the DS250DF410.
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DS250DF410
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
www.ti.com.cn
8.6 Register Maps
Table 8. Global Registers
DEFAULT
ADDRESS
(HEX)
BITS
VALUE
(HEX)
MODE
EEPROM
FIELD NAME
DESCRIPTION
EF
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
0
0
0
0
1
1
1
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
R
R
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
SPARE
SPARE
SPARE
SPARE
R
R
R
CHAN_CONFIG_ID[3]
CHAN_CONFIG_ID[2]
CHAN_CONFIG_ID[1]
CHAN_CONFIG_ID[0]
VERSION[7]
TI device ID (Quad count).
DS250DF810: 0x0C
DS250DF410: 0x0E
R
R
R
F0
F1
F3
FB
FC
R
Version ID
R
VERSION[6]
R
VERSION[5]
R
VERSION[4]
R
VERSION[3]
R
VERSION[2]
R
VERSION[1]
R
VERSION[0]
R
DEVICE_ID[7]
DEVICE_ID[6]
DEVICE_ID[5]
DEVICE_ID[4]
DEVICE_ID[3]
DEVICE_ID[2]
DEVICE_ID[1]
DEVICE_ID[0]
CHAN_VERSION[3]
CHAN_VERSION[2]
CHAN_VERSION[1]
CHAN_VERSION[0]
SHARE_VERSION[3]
SHARE_VERSION[2]
SHARE_VERSION[1]
SHARE_VERSION[0]
RESERVED
Full device ID
R
R
R
R
R
R
R
R
Digital Channel Version
Digital Share Version
R
R
R
R
R
R
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
EN_CH7
Select channel 7 (DS250DF810 only)
Select channel 6 (DS250DF810 only)
Select channel 5 (DS250DF810 only)
Select channel 4 (DS250DF810 only)
EN_CH6
EN_CH5
EN_CH4
32
Copyright © 2016–2019, Texas Instruments Incorporated
DS250DF410
www.ti.com.cn
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
Register Maps (continued)
Table 8. Global Registers (continued)
DEFAULT
ADDRESS
(HEX)
BITS
VALUE
(HEX)
MODE
EEPROM
FIELD NAME
DESCRIPTION
Select channel 3
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
EN_CH3
EN_CH2
EN_CH1
EN_CH0
Select channel 2
Select channel 1
Select channel 0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
TI vendor ID
FD
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
FE
VENDOR_ID[7]
VENDOR_ID[6]
VENDOR_ID[5]
VENDOR_ID[4]
VENDOR_ID[3]
VENDOR_ID[2]
VENDOR_ID[1]
VENDOR_ID[0]
RESERVED
R
R
R
R
R
R
R
FF
RW
RW
RESERVED
RESERVED
RESERVED
EN_SHARE_Q1
Select shared registers for quad 1
(DS250DF810 only)
5
1
RW
N
4
3
2
0
0
0
RW
RW
RW
N
N
N
EN_SHARE_Q0
RESERVED
Select shared registers for quad 0
RESERVED
RESERVED
RESERVED
WRITE_ALL_CH
Allows user to write to all channels as
if they are the same, but only allows
read back from the channel specified
in 0xFC.
1
0
0
0
RW
RW
N
N
Note: EN_CH_SMB must be = 1 or
else this function is invalid.
EN_CH_SMB
1: Enables SMBUS access to the
channels specified in Reg_0xFC
0: The shared registers are selected
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33
DS250DF410
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
www.ti.com.cn
Table 9. Shared Registers
DEFAULT
ADDRESS
(HEX)
FIELD
BITS
VALUE
(HEX)
MODE
EEPROM
NAME
DESCRIPTION
SMBus Address
00
7
6
1
R
R
N
N
SMBUS_ADDR[3]
SMBUS_ADDR[2]
Strapped 7-bit addres is 0x18 +
SMBus_Addr[3:0]
1
5
4
0
0
0
1
0
1
1
0
0
0
1
0
0
0
R
R
N
N
N
N
N
N
N
N
N
N
N
N
N
N
SMBUS_ADDR[1]
SMBUS_ADDR[0]
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RST_I2C_REGS
3:0
7
R
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
01
R
6
R
5
R
4
R
3
R
2
R
1
R
0
R
02
03
04
7:0
7:0
7
RW
RW
RW
1: Reset shared registers. This bit is
self-clearing.
6
0
RWSC
N
0: Normal operation
RST_I2C_MAS
1: Reset for SMBus/I2C Master. This
bit is self-clearing.
5
4
0
0
RWSC
RW
N
N
0: Normal operation
FRC_EEPRM_RD
1: Force EEPROM Configuration
0: Normal operation
3
2
1
0
1
0
0
1
RW
RW
RW
RW
Y
N
N
N
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
05
DISAB_EEPRM_CFG
1: Disable Master Mode EEPROM
configuration (if not started; this bit is
not effective if EEPROM configuration
is already started)
7
0
RW
N
0: Normal operation
6:5
4
0
1
RW
R
N
N
RESERVED
RESERVED
EEPROM_READ_DONE
1: SMBus Master mode EEPROM
read complete
0: SMBus Master mode EEPROM
read not started or not complete
TEST0_AS_CAL_CLK_IN
CAL_CLK_INV_DIS
1: Use TEST0 as the input for the
25MHz CAL_CLK instead of
CAL_CLK_IN. This must be configured
for quad0 only.
0: Normal operation. Use
CAL_CLK_IN as the input for the
25MHz CAL_CLK.
3
0
RW
N
1: Disable the inversion of
CAL_CLK_OUT
2
0
RW
Y
0: Normal operation. CAL_CLK_OUT
is inverted with respect to
CAL_CLK_IN.
1
0
0
1
RW
RW
Y
Y
RESERVED
RESERVED
RESERVED
RESERVED
34
Copyright © 2016–2019, Texas Instruments Incorporated
DS250DF410
www.ti.com.cn
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
Table 9. Shared Registers (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
FIELD
NAME
BITS
MODE
EEPROM
DESCRIPTION
06
08
7:0
7
0
0
0
0
0
RW
R
N
N
N
N
N
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
INT_Q0C3
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
6
R
5
R
4
R
Interrupt from channel 3. For
DS250DF810, this applies to the quad
selected by Reg_0xFF[5:4].
3
2
1
0
0
0
R
R
R
N
N
N
INT_Q0C2
INT_Q0C1
INT_Q0C0
RESERVED
Interrupt from channel 2. For
DS250DF810, this applies to the quad
selected by Reg_0xFF[5:4].
Interrupt from channel 1. For
DS250DF810, this applies to the quad
selected by Reg_0xFF[5:4].
Interrupt from channel 0. For
DS250DF810, this applies to the quad
selected by Reg_0xFF[5:4].
0
0
0
R
R
N
Y
0A
0B
7:1
RESERVED
DIS_REFCLK_OUT
1: Disable CAL_CLK_OUT (high-Z)
0
0
RW
Y
0: Normal operation. Enable
CAL_CLK_OUT
7
6
0
0
RW
R
N
N
RESERVED
RESERVED
REFCLK_DET
1: 25MHz clock detected on
CAL_CLK_IN
0: No clock detected on CAL_CLK_IN
5
4
0
0
RW
RW
N
N
RESERVED
RESERVED
RESERVED
RESERVED
MR_REFCLK_DET_DIS
0: CAL_CLK_IN detection and status
reporting enabled (default)
3
0
RW
N
1: CAL_CLK_IN detection disabled
2
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
RW
RW
RW
RW
R
N
N
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
N
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
EECFG_CMPLT
EECFG_FAIL
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0
0C
0D
0E
7:0
7:0
7:2
1:0
7:0
7
RW
R
0F
10
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
6
5
4
3
2
1
0
11
7
11: Not valid
10: EEPROM load completed
successfully
01: EEPROM load failed after 64
attempts
6
0
R
N
00: EEPROM load in progress
Copyright © 2016–2019, Texas Instruments Incorporated
35
DS250DF410
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
www.ti.com.cn
Table 9. Shared Registers (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
FIELD
NAME
BITS
MODE
EEPROM
DESCRIPTION
5
4
3
2
1
0
0
0
0
0
0
0
R
R
R
R
R
R
N
N
N
N
N
N
EECFG_ATMPT[5]
EECFG_ATMPT[4]
EECFG_ATMPT[3]
EECFG_ATMPT[2]
EECFG_ATMPT[1]
EECFG_ATMPT[0]
REG_I2C_FAST
Number of attempts made to load
EEPROM image
12
1: EEPROM load uses Fast I2C Mode
(400 kHz)
7
1
RW
N
0: EEPROM load uses Standard I2C
Mode (100 kHz)
6
5
4
3
2
1
0
0
0
1
0
0
0
1
RW
RW
RW
RW
RW
RW
RW
N
N
N
N
N
N
N
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
36
版权 © 2016–2019, Texas Instruments Incorporated
DS250DF410
www.ti.com.cn
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
Table 10. Channel Registers, 0 to 39
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
00
7
6
5
4
3
0
0
0
0
0
RW
RW
RW
RW
RW
N
N
N
N
N
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RST_CORE
1: Reset the 10M core clock domain.
This is the main clock domain for all
the state machines
0: Normal operation
2
1
0
0
0
0
RW
RW
RW
N
N
N
RST_REGS
RST_VCO
1: Reset channel registers to power-up
defaults.
0: Normal operation
1: Resets the CDR S2P clock domain,
includes PPM counter, EOM counter.
0: Normal operation
RST_REFCLK
1: Resets the 25MHz reference clock
domain, includes PPM counter. Does
not work if 25MHz clock is not present.
0: Normal operation
01
7
6
0
0
R
R
N
N
SIGDET
Raw Signal Detect observation
POL_INV_DET
Indicates PRBS checker detected
polarity inversion in the locked data
sequence.
5
4
0
0
R
R
N
N
CDR_LOCK_LOSS_INT
PRBS_SEQ_DET[3]
1: Indicates loss of CDR lock after
having acquired it. Bit clears on read.
Feature must be enabled with
Reg_0x31[1]
Indicates the pattern detected on the
input serial stream
0xxx: No detect
3
2
1
0
0
0
R
R
R
N
N
N
PRBS_SEQ_DET[2]
PRBS_SEQ_DET[1]
PRBS_SEQ_DET[0]
1000: 7 bits PRBS sequence
1001: 9 bits PRBS sequence
1010: 11 bits PRBS sequence
1011: 15 bits PRBS sequence
1100: 23 bits PRBS sequence
1101: 31 bits PRBS sequence
1110: 58 bits PRBS sequence
1111: 63 bits PRBS sequence
0
7
0
0
R
R
N
N
SIG_DET_LOSS_INT
CDR_STATUS[7]
Loss of signal indicator, set once
signal is acquired and then lost. Clears
on read. Feature must be enabled with
reg_31[0]
02
This register is used to read the status
of internal signal.
Select what is observable on this bus
using Reg_0x0C[7:4]
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
N
N
N
N
N
N
N
CDR_STATUS[6]
CDR_STATUS[5]
CDR_STATUS[4]
CDR_STATUS[3]
CDR_STATUS[2]
CDR_STATUS[1]
CDR_STATUS[0]
Copyright © 2016–2019, Texas Instruments Incorporated
37
DS250DF410
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
www.ti.com.cn
Table 10. Channel Registers, 0 to 39 (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
03
04
05
06
07
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
EQ_BST0[1]
This register can be used to force an
EQ boost setting if used in conjunction
with channel Reg_0x2D[3].
EQ_BST0[0]
EQ_BST1[1]
EQ_BST1[0]
EQ_BST2[1]
EQ_BST2[0]
EQ_BST3[1]
EQ_BST3[0]
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
38
Copyright © 2016–2019, Texas Instruments Incorporated
DS250DF410
www.ti.com.cn
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
Table 10. Channel Registers, 0 to 39 (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
08
7
6
5
4
3
2
1
0
7
0
1
1
1
0
0
1
1
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
Y
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
REG_VCO_CAP_OV
09
Enable bit to override cap_cnt with
value in Reg_0x0B[4:0]
6
0
RW
Y
REG_SET_CP_LVL_LPF_OV
Enable bit to override lpf_dac_val with
value in Reg_0x1F[4:0]
5
4
0
0
RW
RW
Y
Y
REG_BYPASS_PFD_OV
0: Normal operation.
REG_EN_FD_PD_VCO_PDIQ_ Enable bit to override en_fd, pd_pd,
OV
pd_vco, pd_pdiq with Reg_0x1E[0],
Reg_0x1E[2], Reg_0x1C[0],
Reg_0x1C[1]
3
2
0
0
RW
RW
Y
Y
REG_EN_PD_CP_OV
REG_DIVSEL_OV
Enable bit to override pd_fd_cp and
pd_pd_cp with value in Reg_0x1B[1:0]
Enable bit to override divsel with value
in Reg_0x18[6:4]
1
0
7
6
0
0
0
0
RW
RW
RW
RW
Y
Y
Y
Y
RESERVED
RESERVED
RESERVED
RESERVED
0A
RESERVED
RESERVED
REG_EN_IDAC_PD_CP_OV_
Enable bit to override phase detector
AND_REG_EN_IDAC_FD_CP_ charge pump settings with
OV
Reg_0x1C[7:5]
Enable bit to override frequency
detector charge pump settings with
Reg_0x1C[4:2]
5
0
RW
Y
REG_DAC_LPF_HIGH_PHASE_ Enable bit to loop filter comparator trip
OV_
voltages with Reg_0x16[7:0]
AND_REG_DAC_LPF_LOW_PH
ASE_OV
4
3
0
0
RW
RW
Y
N
RESERVED
RESERVED
REG_CDR_RESET_OV
Enable CDR Reset override with
Reg_0x0A[2]
2
1
0
0
RW
RW
N
N
REG_CDR_RESET_SM
REG_CDR_LOCK_OV
CDR Reset override bit
Enable CDR lock signal override with
Reg_0x0A[0]
0
7
6
5
4
3
2
1
0
0
0
1
1
0
0
0
1
1
RW
RW
RW
RW
RW
RW
RW
RW
RW
N
Y
Y
Y
Y
Y
Y
Y
Y
REG_CDR_LOCK
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
CDR lock signal override bit
RESERVED
0B
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Copyright © 2016–2019, Texas Instruments Incorporated
39
DS250DF410
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
www.ti.com.cn
Table 10. Channel Registers, 0 to 39 (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
0C
7
6
5
4
3
2
1
0
7
0
0
0
0
0
0
0
0
1
RW
RW
RW
RW
RW
RW
RW
RW
RW
N
N
N
N
N
N
N
N
N
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
DES_PD
0D
1: De-serializer (for PRBS checker) is
powered down
0: De-serializer (for PRBS checker) is
enabled
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
1
0
1
1
0
1
0
0
1
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
N
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0E
0F
10
40
Copyright © 2016–2019, Texas Instruments Incorporated
DS250DF410
www.ti.com.cn
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
Table 10. Channel Registers, 0 to 39 (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
11
7
6
0
0
RW
RW
Y
Y
EOM_SEL_VRANGE[1]
EOM_SEL_VRANGE[0]
Manually set the EOM vertical range,
used with channel Reg_0x2C[6]:
00: ±100 mV
01: ±200 mV
10: ±300 mV
11: ±400 mV
5
1
RW
Y
EOM_PD
1: Normal operation. Eye opening
monitor (EOM) is automatically duty-
cycled.
0: EOM is force-enabled
4
3
0
0
RW
RW
N
Y
RESERVED
RESERVED
DFE_TAP2_POL
Bit forces DFE tap 2 polarity
1: Negative, boosts by the specified
tap weight
0: Positive, attenuates by the specified
tap weight
2
1
0
7
0
0
0
1
RW
RW
RW
RW
Y
Y
Y
Y
DFE_TAP3_POL
DFE_TAP4_POL
DFE_TAP5_POL
DFE_TAP1_POL
Bit forces DFE tap 3 polarity
1: Negative, boosts by the specified
tap weight
0: Positive, attenuates by the specified
tap weight
Bit forces DFE tap 4 polarity
1: Negative, boosts by the specified
tap weight
0: Positive, attenuates by the specified
tap weight
Bit forces DFE tap 5 polarity
1: Negative, boosts by the specified
tap weight
0: Positive, attenuates by the specified
tap weight
12
Bit forces DFE tap 1 polarity
1: Negative, boosts by the specified
tap weight
0: Positive, attenuates by the specified
tap weight
6
5
4
3
2
1
0
0
0
0
0
0
1
1
RW
RW
RW
RW
RW
RW
RW
N
Y
Y
Y
Y
Y
Y
RESERVED
RESERVED
DFE_WT1[4]
DFE_WT1[3]
DFE_WT1[2]
DFE_WT1[1]
DFE_WT1[0]
RESERVED
RESERVED
These bits force DFE tap 1 weight.
Manual DFE operation is required for
this to take effect by setting
Reg_0x15[7]=1.
If Reg_0x15[7]=0, the value defined
here is used as the initial DFE tap 1
weight during adaptation.
Copyright © 2016–2019, Texas Instruments Incorporated
41
DS250DF410
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
www.ti.com.cn
Table 10. Channel Registers, 0 to 39 (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
13
7
1
0
1
RW
N
EQ_PD_PEAKDETECT
1: Normal operation. Power down test
mode.
0: Test mode.
6
5
RW
RW
Y
Y
EQ_PD_SD
1: Power down signal detect.
0: Normal operation. Enable signal
detect.
EQ_HI_GAIN
1: Enable high DC gain mode in the
equalizer
0: Enable low DC gain mode in the
equalizer
(Refer to the Programming Guide for
more details)
4
1
RW
Y
EQ_EN_DC_OFF
1: Normal operation.
0: Disable DC offset compensation.
3
2
0
0
RW
RW
Y
Y
RESERVED
RESERVED
EQ_LIMIT_EN
1: Configures the final stage of the
equalizer to be a limiting stage.
0: Normal operation, final stage of the
equalizer is configured to be a non-
limiting stage.
1
0
7
0
0
0
RW
RW
RW
Y
Y
Y
RESERVED
RESERVED
RESERVED
RESERVED
14
EQ_SD_PRESET
1: Forces signal detect HIGH, and
force enables the channel. Should not
be set if bit 6 is set.
0: Normal Operation.
6
0
RW
Y
EQ_SD_RESET
1: Forces signal detect LOW and force
disables the channel. Should not be
set if bit 7 is set.
0: Normal Operation.
5
4
0
0
RW
RW
Y
Y
EQ_REFA_SEL1
EQ_REFA_SEL0
Controls the signal detect assert
levels.
(Refer to the Programming Guide for
more details)
3
2
0
1
RW
RW
Y
Y
EQ_REFD_SEL1
EQ_REFD_SEL0
Controls the signal detect de-assert
levels.
(Refer to the Programming Guide for
more details)
1
0
7
0
0
0
RW
RW
RW
N
N
Y
RESERVED
RESERVED
RESERVED
RESERVED
15
DFE_FORCE_EN
1: Enables manual DFE tap settings
0: Normal operation
6
5
4
3
0
0
1
0
RW
RW
RW
RW
N
N
Y
Y
RESERVED
RESERVED
RESERVED
DRV_PD
RESERVED
RESERVED
RESERVED
1: Powers down the high speed driver
0: Normal operation
2
1
0
0
0
0
RW
RW
RW
Y
Y
Y
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
42
Copyright © 2016–2019, Texas Instruments Incorporated
DS250DF410
www.ti.com.cn
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
Table 10. Channel Registers, 0 to 39 (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
16
17
18
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
0
1
1
1
1
0
1
0
0
0
1
1
0
1
1
0
0
1
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
PDIQ_SEL_DIV[2]
PDIQ_SEL_DIV[1]
PDIQ_SEL_DIV[0]
These bits will force the divider setting
if 0x09[2] is set.
000: Divide by 1
001: Divide by 2
010: Divide by 4
011: Divide by 8
100: Divide by 16
All other values are reserved.
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
1
1
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
N
Y
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
19
1A
Copyright © 2016–2019, Texas Instruments Incorporated
43
DS250DF410
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
www.ti.com.cn
Table 10. Channel Registers, 0 to 39 (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
1B
7
6
5
4
3
2
1
0
0
0
0
0
0
1
RW
RW
RW
RW
RW
RW
RW
N
N
N
N
N
N
Y
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
CP_EN_CP_PD
1: Normal operation, phase detector
charge pump enabled
0
1
RW
Y
CP_EN_CP_FD
1: Normal operation, frequency
detector charge pump enabled
1C
1D
1E
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
Y
Y
Y
EN_IDAC_PD_CP2
EN_IDAC_PD_CP1
EN_IDAC_PD_CP0
EN_IDAC_FD_CP2
EN_IDAC_FD_CP1
EN_IDAC_FD_CP0
RESERVED
Phase detector charge pump setting.
Override bit required for these bits to
take effect
Frequency detector charge pump
setting. Override bit required for these
bits to take effect
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
PFD_SEL_DATA_PRELCK[2]
PFD_SEL_DATA_PRELCK[1]
PFD_SEL_DATA_PRELCK[0]
Output mode for when the CDR is not
locked. For these values to take effect,
Reg_0x09[5] must be set to 0, which is
the default.
000: Raw Data
111: Mute (Default)
All other values are reserved. (Refer to
the Programming Guide for more
details)
4
3
0
1
RW
RW
N
Y
SER_EN
DFE_PD
1: Enable serializer (used for PRBS
Generator)
0: Normal operation. Disable serializer.
This bit must be cleared for the DFE to
be functional in any adapt mode.
1: (Default) DFE disabled.
0: DFE enabled
2
1
0
0
0
1
RW
RW
RW
Y
Y
Y
PFD_PD_PD
1: Power down PFD phase detector.
0: Normal operation. Enable PFD
phase detector.
EN_PARTIAL_DFE
PFD_EN_FD
1: Enable DFE taps 3-5. DFE_PD
must also be set to 0.
0: (Default) Disable DFE taps 3-5.
1: Normal operation. Enable PFD
frequency detector.
0: Disable PFD frequency detector.
44
Copyright © 2016–2019, Texas Instruments Incorporated
DS250DF410
www.ti.com.cn
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
Table 10. Channel Registers, 0 to 39 (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
1F
7
6
5
4
3
0
0
0
0
1
RW
RW
RW
RW
RW
N
N
N
Y
Y
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
MR_LPF_AUTO_ADJST_EN
1: Normal operation. Allow LPF to tune
to optimum value during fast-cap
search routine.
0: Otherwise LPF value is determined
by the Reg_0x9D.
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
RESERVED
RESERVED
RESERVED
DFE_WT5[3]
DFE_WT5[2]
DFE_WT5[1]
DFE_WT5[0]
DFE_WT4[3]
DFE_WT4[2]
DFE_WT4[1]
DFE_WT4[0]
DFE_WT3[3]
DFE_WT3[2]
DFE_WT3[1]
DFE_WT3[0]
DFE_WT2[3]
DFE_WT2[2]
DFE_WT2[1]
DFE_WT2[0]
EOM_OV
RESERVED
RESERVED
RESERVED
20
21
22
Bits force DFE tap 5 weight, manual
DFE operation required to take effect
by setting 0x15[7]=1.
Bits force DFE tap 4 weight, manual
DFE operation required to take effect
by setting 0x15[7]=1.
Bits force DFE tap 3 weight, manual
DFE operation required to take effect
by setting 0x15[7]=1.
Bits force DFE tap 2 weight, manual
DFE operation required to take effect
by setting 0x15[7]=1.
1: Override enable for EOM manual
control
0: Normal operation
6
0
RW
N
EOM_SEL_RATE_OV
1: Override enable for EOM rate
selection
0: Normal operation
5
4
3
2
1
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
N
N
N
N
N
N
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Copyright © 2016–2019, Texas Instruments Incorporated
45
DS250DF410
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
www.ti.com.cn
Table 10. Channel Registers, 0 to 39 (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
23
7
0
RW
N
EOM_GET_HEO_VEO_OV
1: Override enable for manual control
of the HEO/VEO trigger
0: Normal operation
6
1
RW
Y
DFE_OV
1: Normal operation; DFE must be
enabled in Reg_0x1E[3].
5
4
3
2
1
0
7
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
N
N
N
N
N
N
N
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
FAST_EOM
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
24
1: Enables fast EOM for full eye
capture. In this mode the phase DAC
and voltage DAC or the EOM are
automatically incremented through a
64 x 64 matrix. Values for each point
are stored in Reg_0x25 and
Reg_0x26.
0: Normal operation.
6
5
0
0
R
R
N
N
DFE_EQ_ERROR_NO_LOCK
DFE/CTLE SM quit due to loss of lock
GET_HEO_VEO_ERROR_NO_ get_heo_veo sees no hits at zero
HITS crossing
4
0
R
N
GET_HEO_VEO_ERROR_NO_ get_heo_veo cannot see a vertical eye
OPENING
opening
3
2
0
0
RW
N
N
RESERVED
DFE_ADAPT
RESERVED
RWSC
1: Manually start DFE adaption (self-
clearing).
0: Normal operation.
1
0
R
N
EOM_GET_HEO_VEO
1: Manually triggers HEO/VEO
measurement; feature must be
enabled with Reg_0x23[7]; the
HEO/VEO values are read from
Reg_0x27, Reg_0x28
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RWSC
R
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
EOM_START
1: Starts EOM counter, self-clearing
MSBs of EOM counter
25
EOM_COUNT15
EOM_COUNT14
EOM_COUNT13
EOM_COUNT12
EOM_COUNT11
EOM_COUNT10
EOM_COUNT9
EOM_COUNT8
EOM_COUNT7
EOM_COUNT6
EOM_COUNT5
EOM_COUNT4
EOM_COUNT3
EOM_COUNT2
EOM_COUNT1
EOM_COUNT0
R
R
R
R
R
R
R
26
R
LSBs of EOM counter
R
R
R
R
R
R
R
46
Copyright © 2016–2019, Texas Instruments Incorporated
DS250DF410
www.ti.com.cn
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
Table 10. Channel Registers, 0 to 39 (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
27
28
29
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
HEO7
HEO6
HEO5
HEO4
HEO3
HEO2
HEO1
HEO0
VEO7
VEO6
VEO5
VEO4
VEO3
VEO2
VEO1
VEO0
HEO value, requires CDR to be locked
for valid measurement
R
R
R
R
R
R
R
VEO value, requires CDR to be locked
for valid measurement
R
R
R
R
R
R
R
RW
R
RESERVED
RESERVED
EOM_VRANGE_SETTING[1]
EOM_VRANGE_SETTING[0]
Read the currently set Eye Monitor
Voltage Range:
11 - +/-400mV
R
10 - +/- 300mV
01 - +/- 200mV
00 - +/- 100mV"
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
1
1
0
1
0
RW
RW
RW
R
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
VEO[8]
VEO MSB value
HEO MSB value
R
HEO[8]
2A
RW
RW
RW
RW
RW
RW
RW
RW
EOM_TIMER_THR[3]
EOM_TIMER_THR[2]
EOM_TIMER_THR[1]
EOM_TIMER_THR[0]
VEO_MIN_REQ_HITS[3]
VEO_MIN_REQ_HITS[2]
VEO_MIN_REQ_HITS[1]
VEO_MIN_REQ_HITS[0]
The value of EOM_TIMER_THR[7:4]
controls the amount of time the Eye
Monitor samples each point in the eye.
(Refer to the Programming Guide for
more details)
Whenever the Eye Monitor is used to
measure HEO and VEO, the data is
sampled for some number of bits, set
by Reg_0x2A[7:4]. This register sets
the number of hits within that sample
size that is required before the EOM
will indicate a hit has occurred. This
filtering only affects the VEO
measurement.
Copyright © 2016–2019, Texas Instruments Incorporated
47
DS250DF410
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
www.ti.com.cn
Table 10. Channel Registers, 0 to 39 (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
2B
7
6
5
4
3
2
1
0
0
0
0
0
1
0
1
0
RW
RW
RW
RW
RW
RW
RW
RW
N
N
Y
Y
Y
Y
Y
Y
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
EOM_MIN_REQ_HITS[3]
EOM_MIN_REQ_HITS[2]
EOM_MIN_REQ_HITS[1]
EOM_MIN_REQ_HITS[0]
Whenever the Eye Monitor is used to
measure HEO and VEO, the data is
sampled for some number of bits, set
by Reg_0x2A[7:4]. This register sets
the number of hits within that sample
size that is required before the EOM
will indicate a hit has occurred. This
filtering only affects the HEO
measurement.
2C
7
6
1
1
RW
RW
N
Y
RELOAD_DFE_TAPS
VEO_SCALE
Causes DFE taps to load from last
adapted values
1: Normal operation. Scale VEO
based on EOM vrange.
5
4
1
1
RW
RW
Y
Y
DFE_SM_FOM1
DFE_SM_FOM0
This register defines the Figure of
Merit used when adapting the DFE:
00: not valid
01: SM uses only HEO
10: SM uses only VEO
11: SM uses both HEO and VEO
Additionally, if Reg_0x6E[6] is set to
'1', the Alternate FOM is used. This bit
takes precedence over DFE_SM_FOM
3
2
1
0
7
6
5
4
3
0
1
1
0
0
0
1
1
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
Y
DFE_ADAPT_COUNTER[3]
DFE_ADAPT_COUNTER[2]
DFE_ADAPT_COUNTER[1]
DFE_ADAPT_COUNTER[0]
RESERVED
DFE look-beyond count.
2D
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
REG_EQ_BST_OV
1: Allow override control of the EQ
setting by writing to Reg_0x03
0: Normal operation.
2
1
0
7
6
5
0
0
0
0
0
0
RW
RW
RW
RW
RW
R
Y
Y
Y
N
N
N
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
2E
RESERVED
RESERVED
EQ_BST3_BIT2_TO_EQ
Read-back of eq_BST3[2] driving the
EQ
4
3
2
0
0
0
RW
RW
RW
N
N
N
RESERVED
RESERVED
RESERVED
RESERVED
PRBS_PATTERN_SEL[2]
MSB for the PRBS_PATTERN_SEL
field. Lower bits are found on
Reg_0x30[1:0]. Refer to the Reg_0x30
description on this table.
1
0
0
0
RW
RW
N
N
RESERVED
RESERVED
RESERVED
RESERVED
48
Copyright © 2016–2019, Texas Instruments Incorporated
DS250DF410
www.ti.com.cn
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
Table 10. Channel Registers, 0 to 39 (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
2F
7
6
5
4
3
0
1
0
1
0
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
RESERVED
RESERVED
RATE[2]
RATE[1]
RATE[0]
INDEX_OV
Configure PPM register and divider for
a standard data rate.
(Refer to the Programming Guide for
more details)
If this bit is 1, then Reg_0x39 is to be
used as 4-bit index to the [15:0] array
of EQ settings. The EQ setting at that
index is loaded to the EQ boost
registers going to the analog and is
used as the starting point for adaption.
2
1
RW
Y
EN_PPM_CHECK
1: (Default) Enable the PPM to be
used as a qualifier when performing
Lock Detect
0: Remove the PPM check as a lock
qualifier.
1
0
0
0
RW
Y
N
RESERVED
RESERVED
RWSC
CTLE_ADAPT
1: Re-starts CTLE adaptation, self-
clearing
30
7
6
5
0
0
0
RW
RW
RW
N
Y
N
FREEZE_PPM_CNT
EQ_SEARCH_OV_EN
EN_PATT_INV
1: Freeze the PPM counter to allow
safe read asynchronously
1: Enables the EQ 'search" bit to be
forced by Reg_0x13[2]
1: Enable automatic pattern inversion
of successive 16 bit words when using
the "Fixed Pattern" generator option.
4
3
0
0
RW
RW
N
N
RELOAD_PRBS_CHKR
PRBS_EN_DIG_CLK
1: Force reload of seed into PRBS
checker LFSR without holding the
checker in reset.
This bit enables the clock to operate
the PRBS generator and/or the PRBS
checher. Toggling this bit is the
primary method to reset the PRBS
pattern generator and PRBS checker.
2
0
RW
N
PRBS_PROGPATT_EN
Enable a fixed data pattern output.
Requires that serializer is enabled with
Reg_0x1E[4]. PRBS generator and
checker should be disabled,
Reg_0x30[3]. The fixed data pattern is
set by Reg_0x7C and Reg_0x97.
Enable inversion of the pattern every
16 bits with Reg_0x30[5].
1
0
0
0
RW
RW
N
N
PRBS_PATTERN_SEL[1]
PRBS_PATTERN_SEL[0]
Selects the pattern output when using
the PRBS generator. Requires the
pattern generator to be configured
properly. The MSB for the
PRBS_PATTERN_SEL field is in
Reg_0x2E[2].
Use Reg_0x30[3] to enable the PRBS
generator.
000: 2^7-1 bits PRBS sequence
001: 2^9-1 bits PRBS sequence
010: 2^11-1 bits PRBS sequence
011: 2^15-1 bits PRBS sequence
100: 2^23-1 bits PRBS sequence
101: 2^31-1 bits PRBS sequence
110: 2^58-1 bits PRBS sequence
111: 2^63-1 bits PRBS sequence
Copyright © 2016–2019, Texas Instruments Incorporated
49
DS250DF410
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
www.ti.com.cn
Table 10. Channel Registers, 0 to 39 (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
PRBS_INT_EN
DESCRIPTION
31
7
0
RW
N
1: Enables interrupt for detection of
PRBS errors. The PRBS checker must
be properly configured for this feature
to work.
6
5
0
1
RW
RW
Y
Y
ADAPT_MODE[1]
ADAPT_MODE[0]
00: no adaption
01: adapt CTLE only
10: adapt CTLE until optimal, then
DFE, then CTLE again
11: adapt CTLE until lock, then DFE,
then EQ until optimal
Note: for ADAPT_MODE=2 or 3, the
DFE must be enabled by setting
Reg_0x1E[3]=0 and Reg_0x1E[1]=1.
(Refer to the Programming Guide for
more details)
4
3
0
0
RW
RW
Y
Y
EQ_SM_FOM[1]
EQ_SM_FOM[0]
CTLE (EQ) adaption state machine
figure of merit.
00: (Default) SM uses both HEO and
VEO
01: SM uses HEO only
10: SM uses VEO only
11: SM uses both HEO and VEO
Additionally, if Reg_0x6E[7]=1, the
Alternate FOM is used. Reg_0x6E[7]
takes precedence over EQ_SM_FOM.
2
1
0
0
RW
RW
N
Y
RESERVED
RESERVED
CDR_LOCK_LOSS_INT_EN
Enable for CDR Lock Loss Interrupt.
Observable in Reg_0x01[5]
0
0
RW
Y
SIGNAL_DET_LOSS_INT_EN
Enable for Signal Detect Loss
Interrupt. Observable in Reg_0x01[0]
32
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
HEO_INT_THRESH[3]
HEO_INT_THRESH[2]
HEO_INT_THRESH[1]
HEO_INT_THRESH[0]
VEO_INT_THRESH[3]
VEO_INT_THRESH[2]
VEO_INT_THRESH[1]
VEO_INT_THRESH[0]
HEO_THRESH[3]
These bits set the threshold for the
HEO and VEO interrupt. Each
threshold bit represents 8 counts of
HEO or VEO.
33
In adapt mode 3, the register sets the
minimum HEO and VEO required for
CTLE adaption, before starting DFE
adaption. This can be a max of 15.
HEO_THRESH[2]
HEO_THRESH[1]
HEO_THRESH[0]
VEO_THRESH[3]
VEO_THRESH[2]
VEO_THRESH[1]
VEO_THRESH[0]
50
Copyright © 2016–2019, Texas Instruments Incorporated
DS250DF410
www.ti.com.cn
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
Table 10. Channel Registers, 0 to 39 (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
PPM_ERR_RDY
DESCRIPTION
34
7
0
R
N
1: Indicates that a PPM error count is
read to be read from channel
Reg_0x3B and Reg_0x3C
6
0
RW
Y
LOW_POWER_MODE_DISABL By default, all blocks (except signal
E
detect) power down after 100 ms after
signal detect goes low. If set high, all
blocks get powered on after the signal
detect initially goes high.
5
4
1
1
RW
RW
Y
Y
LOCK_COUNTER[1]
LOCK_COUNTER[0]
After achieving lock, the CDR
continues to monitor the lock criteria. If
the lock criteria fail, the lock is
checked for a total of N number of
times before declaring an out of lock
condition, where N is set by this the
value in these registers, with a max
value of +3, for a total of 4. If during
the N lock checks, lock is regained,
then the lock condition is left HI, and
the counter is reset back to zero.
3
2
1
0
7
6
1
1
1
1
0
0
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
DFE_MAX_TAP2_5[3]
DFE_MAX_TAP2_5[2]
DFE_MAX_TAP2_5[1]
DFE_MAX_TAP2_5[0]
DATA_LOCK_PPM[1]
DATA_LOCK_PPM[0]
These four bits are used to set the
maximum value by which DFE taps 2-
5 are able to adapt with each
subsequent adaptation. Same used for
both polarities.
35
Modifies the value of the PPM delta
tolerance from channel Reg_0x64:
00 - ppm_delta[7:0] =1 x
ppm_delta[7:0]
01 - ppm_delta[7:0] =1 x
ppm_delta[7:0] + ppm_delta[3:1]
10 - ppm_delta[7:0] =2 x
ppm_delta[7:0]
11 - ppm_delta[7:0] =2 x
ppm_delta[7:0] + ppm_delta[3:1]
5
0
RW
N
GET_PPM_ERROR
Get PPM error from PPM_COUNT -
clears when done. Normally updates
continuously, but can be manually
triggered with read value from
Reg_0x3B and Reg_0x3C
4
3
2
1
0
7
6
0
1
1
1
1
0
0
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
N
Y
DFE_MAX_TAP1[4]
DFE_MAX_TAP1[3]
DFE_MAX_TAP1[2]
DFE_MAX_TAP1[1]
DFE_MAX_TAP1[0]
RESERVED
Limits DFE tap 1 maximum magnitude.
36
RESERVED
HEO_VEO_INT_EN
1: Enable HEO/VEO interrupt
capability
5
4
3
2
1
0
1
1
0
0
0
0
RW
RW
RW
RW
RW
RW
Y
Y
N
Y
N
N
REF_MODE[1]
REF_MODE[0]
RESERVED
RESERVED
RESERVED
RESERVED
11: Normal Operation. Refererence
mode 3.
RESERVED
RESERVED
RESERVED
RESERVED
Copyright © 2016–2019, Texas Instruments Incorporated
51
DS250DF410
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
www.ti.com.cn
Table 10. Channel Registers, 0 to 39 (continued)
DEFAULT
VALUE
(HEX)
ADDRESS
(HEX)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
37
38
39
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
R
R
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
Y
CTLE_STATUS[7]
Feature is reserved for future use
Feature is reserved for future use
RESERVED
CTLE_STATUS[6]
CTLE_STATUS[5]
CTLE_STATUS[4]
CTLE_STATUS[3]
CTLE_STATUS[2]
CTLE_STATUS[1]
CTLE_STATUS[0]
DFE_STATUS[7]
DFE_STATUS[6]
DFE_STATUS[5]
DFE_STATUS[4]
DFE_STATUS[3]
DFE_STATUS[2]
DFE_STATUS[1]
DFE_STATUS[0]
RESERVED
R
R
R
R
R
R
R
R
R
R
R
R
R
R
RW
RW
RW
MR_EOM_RATE[1]
MR_EOM_RATE[0]
With eom_ov = 1, these bits control
the Eye Monitor Rate:
11: Use for full rate, fastest
10: Use for 1/2 Rate
All other values are reserved
4
3
2
1
0
0
0
0
0
0
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
RESERVED
RESERVED
START_INDEX[3]
START_INDEX[2]
START_INDEX[1]
START_INDEX[0]
Start index for EQ adaptation
52
版权 © 2016–2019, Texas Instruments Incorporated
DS250DF410
www.ti.com.cn
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
Table 11. Channel Registers, 3A to A9
DEFAULT
VALUE
(Hex)
ADDRESS
(Hex)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
3A
3B
3C
3D
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
R
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
FIXED_EQ_BST0[1]
During adaptation, if the divider
setting is >2, then a fixed EQ setting
from this register will be used.
However, if channel Reg_0x6F[7] is
enabled, then an EQ adaptation will
be performed instead
FIXED_EQ_BST0[0]
FIXED_EQ_BST1[1]
FIXED_EQ_BST1[0]
FIXED_EQ_BST2[1]
FIXED_EQ_BST2[0]
FIXED_EQ_BST3[1]
FIXED_EQ_BST3[0]
PPM_COUNT[15]
PPM_COUNT[14]
PPM_COUNT[13]
PPM_COUNT[12]
PPM_COUNT[11]
PPM_COUNT[10]
PPM_COUNT[9]
PPM_COUNT[8]
PPM_COUNT[7]
PPM_COUNT[6]
PPM_COUNT[5]
PPM_COUNT[4]
PPM_COUNT[3]
PPM_COUNT[2]
PPM_COUNT[1]
PPM_COUNT[0]
EN_FIR_CURSOR
PPM count MSB
R
R
R
R
R
R
R
R
PPM count LSB
R
R
R
R
R
R
R
RW
1: Enable Pre- and Post-cursor FIR
0: Disable Pre- and Post-cursor FIR
(lower power)
6
0
RW
Y
FIR_C0_SGN
Main-cursor sign bit
0: positive
1: negative
5
4
3
2
1
0
7
6
0
1
1
0
1
0
0
1
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
RESERVED
FIR_C0[4]
RESERVED
Main-cursor magnitude
(Refer to the Programming Guide for
more details)
FIR_C0[3]
FIR_C0[2]
FIR_C0[1]
FIR_C0[0]
3E
FIR_PD_TX
FIR_CN1_SGN
Pre-cursor sign bit
1: negative
0: positive
5
4
3
2
1
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
RESERVED
RESERVED
FIR_CN1[3]
FIR_CN1[2]
FIR_CN1[1]
FIR_CN1[0]
RESERVED
RESERVED
Pre-cursor magnitude
(Refer to the Programming Guide for
more details)
Copyright © 2016–2019, Texas Instruments Incorporated
53
DS250DF410
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
www.ti.com.cn
Table 11. Channel Registers, 3A to A9 (continued)
DEFAULT
VALUE
(Hex)
ADDRESS
(Hex)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
3F
7
6
0
1
RW
RW
Y
Y
RESERVED
RESERVED
FIR_CP1_SGN
Post-cursor sign bit
1: negative
0: positive
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
RESERVED
RESERVED
RESERVED
RESERVED
FIR_CP1[3]
Post-cursor magnitude
(Refer to the Programming Guide for
more details)
FIR_CP1[2]
FIR_CP1[1]
FIR_CP1[0]
40
41
42
43
EQ_ARRAY_INDEX_0_BST0[1]
EQ_ARRAY_INDEX_0_BST0[0]
EQ_ARRAY_INDEX_0_BST1[1]
EQ_ARRAY_INDEX_0_BST1[0]
EQ_ARRAY_INDEX_0_BST2[1]
EQ_ARRAY_INDEX_0_BST2[0]
EQ_ARRAY_INDEX_0_BST3[1]
EQ_ARRAY_INDEX_0_BST3[0]
EQ_ARRAY_INDEX_1_BST0[1]
EQ_ARRAY_INDEX_1_BST0[0]
EQ_ARRAY_INDEX_1_BST1[1]
EQ_ARRAY_INDEX_1_BST1[0]
EQ_ARRAY_INDEX_1_BST2[1]
EQ_ARRAY_INDEX_1_BST2[0]
EQ_ARRAY_INDEX_1_BST3[1]
EQ_ARRAY_INDEX_1_BST3[0]
EQ_ARRAY_INDEX_2_BST0[1]
EQ_ARRAY_INDEX_2_BST0[0]
EQ_ARRAY_INDEX_2_BST1[1]
EQ_ARRAY_INDEX_2_BST1[0]
EQ_ARRAY_INDEX_2_BST2[1]
EQ_ARRAY_INDEX_2_BST2[0]
EQ_ARRAY_INDEX_2_BST3[1]
EQ_ARRAY_INDEX_2_BST3[0]
EQ_ARRAY_INDEX_3_BST0[1]
EQ_ARRAY_INDEX_3_BST0[0]
EQ_ARRAY_INDEX_3_BST1[1]
EQ_ARRAY_INDEX_3_BST1[0]
EQ_ARRAY_INDEX_3_BST2[1]
EQ_ARRAY_INDEX_3_BST2[0]
EQ_ARRAY_INDEX_3_BST3[1]
EQ_ARRAY_INDEX_3_BST3[0]
54
Copyright © 2016–2019, Texas Instruments Incorporated
DS250DF410
www.ti.com.cn
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
Table 11. Channel Registers, 3A to A9 (continued)
DEFAULT
VALUE
(Hex)
ADDRESS
(Hex)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
44
45
46
47
48
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
1
0
0
0
0
1
1
0
1
0
0
0
1
1
1
0
1
0
1
0
1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
EQ_ARRAY_INDEX_4_BST0[1]
EQ_ARRAY_INDEX_4_BST0[0]
EQ_ARRAY_INDEX_4_BST1[1]
EQ_ARRAY_INDEX_4_BST1[0]
EQ_ARRAY_INDEX_4_BST2[1]
EQ_ARRAY_INDEX_4_BST2[0]
EQ_ARRAY_INDEX_4_BST3[1]
EQ_ARRAY_INDEX_4_BST3[0]
EQ_ARRAY_INDEX_5_BST0[1]
EQ_ARRAY_INDEX_5_BST0[0]
EQ_ARRAY_INDEX_5_BST1[1]
EQ_ARRAY_INDEX_5_BST1[0]
EQ_ARRAY_INDEX_5_BST2[1]
EQ_ARRAY_INDEX_5_BST2[0]
EQ_ARRAY_INDEX_5_BST3[1]
EQ_ARRAY_INDEX_5_BST3[0]
EQ_ARRAY_INDEX_6_BST0[1]
EQ_ARRAY_INDEX_6_BST0[0]
EQ_ARRAY_INDEX_6_BST1[1]
EQ_ARRAY_INDEX_6_BST1[0]
EQ_ARRAY_INDEX_6_BST2[1]
EQ_ARRAY_INDEX_6_BST2[0]
EQ_ARRAY_INDEX_6_BST3[1]
EQ_ARRAY_INDEX_6_BST3[0]
EQ_ARRAY_INDEX_7_BST0[1]
EQ_ARRAY_INDEX_7_BST0[0]
EQ_ARRAY_INDEX_7_BST1[1]
EQ_ARRAY_INDEX_7_BST1[0]
EQ_ARRAY_INDEX_7_BST2[1]
EQ_ARRAY_INDEX_7_BST2[0]
EQ_ARRAY_INDEX_7_BST3[1]
EQ_ARRAY_INDEX_7_BST3[0]
EQ_ARRAY_INDEX_8_BST0[1]
EQ_ARRAY_INDEX_8_BST0[0]
EQ_ARRAY_INDEX_8_BST1[1]
EQ_ARRAY_INDEX_8_BST1[0]
EQ_ARRAY_INDEX_8_BST2[1]
EQ_ARRAY_INDEX_8_BST2[0]
EQ_ARRAY_INDEX_8_BST3[1]
EQ_ARRAY_INDEX_8_BST3[0]
Copyright © 2016–2019, Texas Instruments Incorporated
55
DS250DF410
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
www.ti.com.cn
Table 11. Channel Registers, 3A to A9 (continued)
DEFAULT
VALUE
(Hex)
ADDRESS
(Hex)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
49
4A
4B
4C
4D
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
1
0
1
1
0
0
0
1
1
1
0
1
0
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
1
1
1
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
EQ_ARRAY_INDEX_9_BST0[1]
EQ_ARRAY_INDEX_9_BST0[0]
EQ_ARRAY_INDEX_9_BST1[1]
EQ_ARRAY_INDEX_9_BST1[0]
EQ_ARRAY_INDEX_9_BST2[1]
EQ_ARRAY_INDEX_9_BST2[0]
EQ_ARRAY_INDEX_9_BST3[1]
EQ_ARRAY_INDEX_9_BST3[0]
EQ_ARRAY_INDEX_10_BST0[1]
EQ_ARRAY_INDEX_10_BST0[0]
EQ_ARRAY_INDEX_10_BST1[1]
EQ_ARRAY_INDEX_10_BST1[0]
EQ_ARRAY_INDEX_10_BST2[1]
EQ_ARRAY_INDEX_10_BST2[0]
EQ_ARRAY_INDEX_10_BST3[1]
EQ_ARRAY_INDEX_10_BST3[0]
EQ_ARRAY_INDEX_11_BST0[1]
EQ_ARRAY_INDEX_11_BST0[0]
EQ_ARRAY_INDEX_11_BST1[1]
EQ_ARRAY_INDEX_11_BST1[0]
EQ_ARRAY_INDEX_11_BST2[1]
EQ_ARRAY_INDEX_11_BST2[0]
EQ_ARRAY_INDEX_11_BST3[1]
EQ_ARRAY_INDEX_11_BST3[0]
EQ_ARRAY_INDEX_12_BST0[1]
EQ_ARRAY_INDEX_12_BST0[0]
EQ_ARRAY_INDEX_12_BST1[1]
EQ_ARRAY_INDEX_12_BST1[0]
EQ_ARRAY_INDEX_12_BST2[1]
EQ_ARRAY_INDEX_12_BST2[0]
EQ_ARRAY_INDEX_12_BST3[1]
EQ_ARRAY_INDEX_12_BST3[0]
EQ_ARRAY_INDEX_13_BST0[1]
EQ_ARRAY_INDEX_13_BST0[0]
EQ_ARRAY_INDEX_13_BST1[1]
EQ_ARRAY_INDEX_13_BST1[0]
EQ_ARRAY_INDEX_13_BST2[1]
EQ_ARRAY_INDEX_13_BST2[0]
EQ_ARRAY_INDEX_13_BST3[1]
EQ_ARRAY_INDEX_13_BST3[0]
56
Copyright © 2016–2019, Texas Instruments Incorporated
DS250DF410
www.ti.com.cn
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
Table 11. Channel Registers, 3A to A9 (continued)
DEFAULT
VALUE
(Hex)
ADDRESS
(Hex)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
4E
4F
50
51
52
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
EQ_ARRAY_INDEX_14_BST0[1]
EQ_ARRAY_INDEX_14_BST0[0]
EQ_ARRAY_INDEX_14_BST1[1]
EQ_ARRAY_INDEX_14_BST1[0]
EQ_ARRAY_INDEX_14_BST2[1]
EQ_ARRAY_INDEX_14_BST2[0]
EQ_ARRAY_INDEX_14_BST3[1]
EQ_ARRAY_INDEX_14_BST3[0]
EQ_ARRAY_INDEX_15_BST0[1]
EQ_ARRAY_INDEX_15_BST0[0]
EQ_ARRAY_INDEX_15_BST1[1]
EQ_ARRAY_INDEX_15_BST1[0]
EQ_ARRAY_INDEX_15_BST2[1]
EQ_ARRAY_INDEX_15_BST2[0]
EQ_ARRAY_INDEX_15_BST3[1]
EQ_ARRAY_INDEX_15_BST3[0]
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Copyright © 2016–2019, Texas Instruments Incorporated
57
DS250DF410
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
www.ti.com.cn
Table 11. Channel Registers, 3A to A9 (continued)
DEFAULT
VALUE
(Hex)
ADDRESS
(Hex)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
53
54
55
56
57
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
0
1
0
0
0
1
1
0
0
1
0
1
1
0
0
0
0
1
1
0
0
1
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
58
Copyright © 2016–2019, Texas Instruments Incorporated
DS250DF410
www.ti.com.cn
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
Table 11. Channel Registers, 3A to A9 (continued)
DEFAULT
VALUE
(Hex)
ADDRESS
(Hex)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
58
59
5A
5B
5C
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
1
0
1
0
1
1
1
0
1
0
1
1
1
0
1
0
1
1
0
1
0
0
1
0
1
1
1
0
1
0
1
1
1
0
1
0
1
0
1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Copyright © 2016–2019, Texas Instruments Incorporated
59
DS250DF410
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
www.ti.com.cn
Table 11. Channel Registers, 3A to A9 (continued)
DEFAULT
VALUE
(Hex)
ADDRESS
(Hex)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
5D
5E
5F
60
61
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
1
0
0
1
1
0
0
1
1
0
0
1
0
1
1
0
1
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Group 0 count LSB
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
GRP0_OV_CNT[7]
GRP0_OV_CNT[6]
GRP0_OV_CNT[5]
GRP0_OV_CNT[4]
GRP0_OV_CNT[3]
GRP0_OV_CNT[2]
GRP0_OV_CNT[1]
GRP0_OV_CNT[0]
CNT_DLTA_OV_0
Override enable for group 0 manual
data rate selection
6
5
4
3
2
1
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
GRP0_OV_CNT[14]
GRP0_OV_CNT[13]
GRP0_OV_CNT[12]
GRP0_OV_CNT[11]
GRP0_OV_CNT[10]
GRP0_OV_CNT[9]
GRP0_OV_CNT[8]
Group 0 count MSB
60
Copyright © 2016–2019, Texas Instruments Incorporated
DS250DF410
www.ti.com.cn
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
Table 11. Channel Registers, 3A to A9 (continued)
DEFAULT
VALUE
(Hex)
ADDRESS
(Hex)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
Group 1 count LSB
62
7
6
5
4
3
2
1
0
7
0
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
Y
GRP1_OV_CNT[7]
GRP1_OV_CNT[6]
GRP1_OV_CNT[5]
GRP1_OV_CNT[4]
GRP1_OV_CNT[3]
GRP1_OV_CNT[2]
GRP1_OV_CNT[1]
GRP1_OV_CNT[0]
CNT_DLTA_OV_1
63
Override enable for group 1 manual
data rate selection
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
GRP1_OV_CNT[14]
GRP1_OV_CNT[13]
GRP1_OV_CNT[12]
GRP1_OV_CNT[11]
GRP1_OV_CNT[10]
GRP1_OV_CNT[9]
GRP1_OV_CNT[8]
GRP0_OV_DLTA[3]
GRP0_OV_DLTA[2]
GRP0_OV_DLTA[1]
GRP0_OV_DLTA[0]
GRP1_OV_DLTA[3]
GRP1_OV_DLTA[2]
GRP1_OV_DLTA[1]
GRP1_OV_DLTA[0]
RESERVED
Group 1 count MSB
64
65
66
Sets the PPM delta tolerance for the
PPM counter lock check for group 0.
Must also program channel
Reg_0x67[7].
Sets the PPM delta tolerance for the
PPM counter lock check for group 1.
Must also program channel
Reg_0x67[6].
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Copyright © 2016–2019, Texas Instruments Incorporated
61
DS250DF410
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
www.ti.com.cn
Table 11. Channel Registers, 3A to A9 (continued)
DEFAULT
VALUE
(Hex)
ADDRESS
(Hex)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
67
7
6
5
0
0
1
RW
RW
RW
Y
Y
Y
GRP0_OV_DLTA[4]
GRP1_OV_DLTA[4]
HV_LOCKMON_EN
1: Enable periodic monitoring of
HEO/VEO for lock qualification.
0: Disable periodic HEO/VEO
monitoring for lock qualification.
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
0
1
0
1
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
68
69
6A
6B
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
VEO_LCK_THRSH[3]
VEO_LCK_THRSH[2]
VEO_LCK_THRSH[1]
VEO_LCK_THRSH[0]
HEO_LCK_THRSH[3]
HEO_LCK_THRSH[2]
HEO_LCK_THRSH[1]
HEO_LCK_THRSH[0]
RESERVED
VEO threshold to meet before lock is
established. The LSB step size is 4
counts of VEO.
HEO threshold to meet before lock is
established. The LSB step size is 4
counts of HEO.
RESERVED
FOM_A[6]
Alternate Figure of Merit variable A.
Max value for this register is 128.
FOM_A[5]
FOM_A[4]
FOM_A[3]
FOM_A[2]
FOM_A[1]
FOM_A[0]
62
Copyright © 2016–2019, Texas Instruments Incorporated
DS250DF410
www.ti.com.cn
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
Table 11. Channel Registers, 3A to A9 (continued)
DEFAULT
VALUE
(Hex)
ADDRESS
(Hex)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
6C
6D
6E
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
FOM_B[7]
FOM_B[6]
FOM_B[5]
FOM_B[4]
FOM_B[3]
FOM_B[2]
FOM_B[1]
FOM_B[0]
FOM_C[7]
FOM_C[6]
FOM_C[5]
FOM_C[4]
FOM_C[3]
FOM_C[2]
FOM_C[1]
FOM_C[0]
HEO adjustment for Alternate FoM,
variable B
VEO adjustment for Alternate FoM,
variable C
EN_NEW_FOM_CTLE
1: CTLE adaption state machine will
use the alternate FoM
HEO_ALT = (HEO-B)*A*2VEO_ALT
= (VEO-C)*(1-A)*2
The values of A,B,C are set in
channel Reg_0x6B, 0x6C, and 0x6D.
The value of A is equal to the
register value divided by 128.
The Alternate FoM = (HEOB)*A*2 +
(VEO-C)*(1-A)*2
6
0
RW
Y
EN_NEW_FOM_DFE
1: DFE adaption state machine will
use the alternate FoM.
HEO_ALT = (HEO-B)*A*2VEO_ALT
= (VEO-C)*(1-A)*2
The values of A,B,C are set in
channel Reg_0x6B, 0x6C, and 0x6D.
The value of A is equal to the
register value divided by 128
The Alternate FoM = (HEOB)*A*2 +
(VEO-C)*(1-A)*2
5
4
3
2
1
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
N
N
N
N
N
N
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Copyright © 2016–2019, Texas Instruments Incorporated
63
DS250DF410
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
www.ti.com.cn
Table 11. Channel Registers, 3A to A9 (continued)
DEFAULT
VALUE
(Hex)
ADDRESS
(Hex)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
6F
7
0
RW
Y
MR_EN_LOW_DIVSEL_EQ
Normally, during adaptation, if the
divider setting is >2, then a fixed EQ
setting, from Reg_0x3A will be used.
However, if Reg_0x6F[7]=1, then an
EQ adaptation will be performed
instead.
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
Y
Y
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
N
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
EQ_LB_CNT[3]
EQ_LB_CNT[2]
EQ_LB_CNT[1]
EQ_LB_CNT[0]
PRBS_INT
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
70
CTLE look-beyond count for
adaptation
71
When enabled by Reg_0x31[7], goes
HI if a PRBS stream is detected.
Clears on reading.
PRBS checker must be enabled with
Reg_0x30[3].
Once cleared, if a PRBS error
occurs, then the interrupt will again
go HI. Clears on reading.
If signal detect is lost, this is
considered a PRBS error, and the
interrupt will go HI. Clears on
reading.
6
5
4
3
2
1
0
7
6
5
4
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
N
N
N
N
N
N
N
N
N
N
N
RESERVED
RESERVED
DFE_POL_1_OBS
DFE_WT1_OBS[4]
DFE_WT1_OBS[3]
DFE_WT1_OBS[2]
DFE_WT1_OBS[1]
DFE_WT1_OBS[0]
RESERVED
DFE tap 1 polarity observation
DFE tap 1 weight observation
72
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
DFE_POL_2_OBS
Primary observation point for DFE
tap 2 polarity
3
2
1
0
0
0
0
0
R
R
R
R
N
N
N
N
DFE_WT2_OBS[3]
DFE_WT2_OBS[2]
DFE_WT2_OBS[1]
DFE_WT2_OBS[0]
Primary observation point for DFE
tap 2 weight
64
Copyright © 2016–2019, Texas Instruments Incorporated
DS250DF410
www.ti.com.cn
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
Table 11. Channel Registers, 3A to A9 (continued)
DEFAULT
VALUE
(Hex)
ADDRESS
(Hex)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
73
74
75
7
6
5
4
0
0
0
0
R
R
R
R
N
N
N
N
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
DFE_POL_3_OBS
Primary observation point for DFE
tap 3 polarity
3
2
1
0
7
6
5
4
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
N
N
N
N
N
N
N
N
DFE_WT3_OBS[3]
DFE_WT3_OBS[2]
DFE_WT3_OBS[1]
DFE_WT3_OBS[0]
RESERVED
Primary observation point for DFE
tap 3 weight
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
DFE_POL_4_OBS
Primary observation point for DFE
tap 4 polarity
3
2
1
0
7
6
5
4
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
N
N
N
N
N
N
N
N
DFE_WT4_OBS[3]
DFE_WT4_OBS[2]
DFE_WT4_OBS[1]
DFE_WT4_OBS[0]
RESERVED
Primary observation point for DFE
tap 4 weight
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
DFE_POL_5_OBS
Primary observation point for DFE
tap 5 polarity
3
2
1
0
7
6
5
4
3
2
1
0
7
0
0
0
0
0
0
1
0
0
0
0
1
0
R
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
N
DFE_WT5_OBS[3]
Primary observation point for DFE
tap 5 weight
R
DFE_WT5_OBS[2]
R
DFE_WT5_OBS[1]
R
DFE_WT5_OBS[0]
76
RW
RW
RW
RW
RW
RW
RW
RW
RW
POST_LOCK_VEO_THR[3]
POST_LOCK_VEO_THR[2]
POST_LOCK_VEO_THR[1]
POST_LOCK_VEO_THR[0]
POST_LOCK_HEO_THR[3]
POST_LOCK_HEO_THR[2]
POST_LOCK_HEO_THR[1]
POST_LOCK_HEO_THR[0]
PRBS_GEN_POL_EN
VEO threshold after LOCK is
established
HEO threshold after LOCK is
established
77
1: Force polarity inversion on
generated PRBS data
6
5
4
3
2
1
0
0
0
1
1
0
1
0
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
N
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Copyright © 2016–2019, Texas Instruments Incorporated
65
DS250DF410
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
www.ti.com.cn
Table 11. Channel Registers, 3A to A9 (continued)
DEFAULT
VALUE
(Hex)
ADDRESS
(Hex)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
78
7
6
5
0
0
0
R
R
R
N
N
N
RESERVED
RESERVED
RESERVED
RESERVED
SD_STATUS
Primary observation point for signal
detect status
4
3
0
0
R
R
N
N
CDR_LOCK_STATUS
CDR_LOCK_INT
Primary observation point for CDR
lock status
Requires that channel Reg_0x79[1]
be set.
1: Indicates CDR has achieved lock,
lock goes from LOW to HIGH. This
bit is cleared after reading. This bit
will stay set until it has been cleared
by reading.
2
0
R
N
SD_INT
Requires that channel Reg_0x79[0]
be set.
1: Indicates signal detect status has
changed. This will trigger when
signal detect goes from LOW to
HIGH or HIGH to LOW. This bit is
cleared after reading. This bit will
stay set until it has been cleared by
reading.
1
0
0
0
R
R
N
N
EOM_VRANGE_LIMIT_ERROR
HEO_VEO_INT
Goes high if GET_HEO_VEO
indicates high during adaptation
Requires that channel Reg_0x36[6]
be set.
1: Indicates that HEO/VEO dropped
below the limits set in channel
Reg_0x76 This bit is cleared after
reading. This bit will stay set until it
has been cleared by reading.
79
7
6
0
0
RW
RW
N
N
RESERVED
RESERVED
PRBS_CHKR_EN
1: Enable the PRBS checker.
0: Disable the PRBS checker
5
0
RW
N
PRBS_GEN_EN
1: Enable the pattern generator
0: Disable the pattern generator
4
3
2
1
1
0
0
0
RW
RW
RW
RW
N
N
N
Y
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
CDR_LOCK_INT_EN
1: Enable CDR lock interrupt,
observable in channel Reg_0x78[3]
0: Disable CDR lock interrupt
0
0
RW
Y
SD_INT_EN
1: Enable signal detect interrupt,
observable in channel Reg_0x78[3]
0: Disable signal detect interrupt
7A
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
N
N
N
N
N
N
N
N
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
66
Copyright © 2016–2019, Texas Instruments Incorporated
DS250DF410
www.ti.com.cn
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
Table 11. Channel Registers, 3A to A9 (continued)
DEFAULT
VALUE
(Hex)
ADDRESS
(Hex)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
7B
7C
7D
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
R
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
PRBS_FIXED[7]
PRBS_FIXED[6]
PRBS_FIXED[5]
PRBS_FIXED[4]
PRBS_FIXED[3]
PRBS_FIXED[2]
PRBS_FIXED[1]
PRBS_FIXED[0]
Pattern generator user defined
pattern LSB. MSB located at channel
Reg_0x97.
R
R
R
R
R
R
R
RW
CONT_ADAPT_HEO_CHNG_TH Limit for HEO change before
RS[3]
triggering a DFE adaption while
continuous DFE adaption is enabled.
6
5
4
3
2
1
0
1
0
0
1
0
0
0
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
CONT_ADAPT_HEO_CHNG_TH
RS[2]
CONT_ADAPT_HEO_CHNG_TH
RS[1]
CONT_ADAPT_HEO_CHNG_TH
RS[0]
CONT_ADAPT_VEO_CHNG_TH Limit for VEO change before
RS[3]
triggering a DFE adaption while
continuous DFE adaption is enabled.
(Refer to the Programming Guide for
more details)
CONT_ADAPT_VEO_CHNG_TH
RS[2]
CONT_ADAPT_VEO_CHNG_TH
RS[1]
CONT_ADAPT_VEO_CHNG_TH
RS[0]
7E
7
6
5
4
3
2
1
0
0
0
0
1
0
0
1
1
RW
RW
RW
RW
RW
RW
RW
RW
Y
Y
Y
Y
Y
Y
Y
Y
CONT_ADPT_TAP_INCR[3]
CONT_ADPT_TAP_INCR[2]
CONT_ADPT_TAP_INCR[1]
CONT_ADPT_TAP_INCR[0]
RESERVED
Limit for allowable tap increase from
the previous base point
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Copyright © 2016–2019, Texas Instruments Incorporated
67
DS250DF410
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
www.ti.com.cn
Table 11. Channel Registers, 3A to A9 (continued)
DEFAULT
VALUE
(Hex)
ADDRESS
(Hex)
BITS
MODE
EEPROM
FIELD NAME
EN_OBS_ALT_FOM
DESCRIPTION
7F
7
0
RW
N
1: Allows for alternate FoM
calculation to be shown in channel
registers Reg_0x27, Reg_0x28 and
Reg_0x29 instead of HEO and VEO
6
5
4
0
1
0
RW
RW
RW
N
Y
Y
RESERVED
RESERVED
RESERVED
RESERVED
EN_DFE_CONT_ADAPT
1: Continuous DFE adaption is
enabled
0: DFE adapts only during lock and
then freezes
(Refer to the Programming Guide for
more details)
3
1
RW
Y
CONT_ADPT_CMP_BOTH
1: If continuous DFE adaption is
enabled, a DFE adaption will trigger
if either HEO orVEO degrades
2
1
0
0
1
0
RW
RW
RW
Y
Y
Y
CONT_ADPT_COUNT[2]
CONT_ADPT_COUNT[1]
CONT_ADPT_COUNT[0]
Limit for number of weights the DFE
can look ahead in continuous
adaption.
(Refer to the Programming Guide for
more details)
80
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
81
68
Copyright © 2016–2019, Texas Instruments Incorporated
DS250DF410
www.ti.com.cn
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
Table 11. Channel Registers, 3A to A9 (continued)
DEFAULT
VALUE
(Hex)
ADDRESS
(Hex)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
82
7
0
RW
N
FREEZE_PRBS_CNTR
1: Freeze the PRBS error count to
allow for readback.
0: Normal operation. Error counters
is allowed to increment if the PRBS
checker is properly configured
6
5
0
0
RW
RW
N
N
RST_PRBS_CNTS
PRBS_PATT_OV
1: Reset the PRBS error counter.
0: Normal operation. Error counter is
released from reset.
1: Override PRBS pattern auto-
detection. Forces the pattern checker
to only lock onto the pattern defined
in Reg_0x82[4:2].
0: Normal operation. Pattern checker
will automatically detect the PRBS
pattern
4
3
2
0
0
0
RW
RW
RW
N
N
N
PRBS_PATT[2]
PRBS_PATT[1]
PRBS_PATT[0]
Used with the PRBS checker. Usage
is enabled with Reg_0x82[5]. Select
PRBS pattern to be checked:
000 - PRBS7
001 - PRBS9
010 - PRBS11
011 - PRBS15
100 - PRBS23
101 - PRBS31
110 - PRBS58
111 - PRBS63
1
0
0
0
RW
RW
N
N
PRBS_POL_OV
PRBS_POL
1: Override PRBS pattern auto
polarity detection. Forces the pattern
checker to only lock onto the polarity
defined in bit 0 of this register.
0: Normal operation, pattern checker
will automatically detect the PRBS
pattern polarity
Usage is enabled with
Reg_0x82[1]=1
0: Forced polarity = true
1: Forced polarity = inverted
83
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
PRBS_ERR_CNT[10]
PRBS_ERR_CNT[9]
PRBS_ERR_CNT[8]
PRBS_ERR_CNT[7]
PRBS_ERR_CNT[6]
PRBS_ERR_CNT[5]
PRBS_ERR_CNT[4]
PRBS_ERR_CNT[3]
PRBS_ERR_CNT[2]
PRBS_ERR_CNT[1]
PRBS_ERR_CNT[0]
PRBS checker error count
84
PRBS checker error count
Copyright © 2016–2019, Texas Instruments Incorporated
69
DS250DF410
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
www.ti.com.cn
Table 11. Channel Registers, 3A to A9 (continued)
DEFAULT
VALUE
(Hex)
ADDRESS
(Hex)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
85
86
87
88
89
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
70
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DS250DF410
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ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
Table 11. Channel Registers, 3A to A9 (continued)
DEFAULT
VALUE
(Hex)
ADDRESS
(Hex)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
8A
8B
8C
8D
8E
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
R
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
RESERVED
RESERVED
R
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
VGA_SEL_GAIN
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
R
R
R
R
R
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
VGA selection bit :
1: VGA high-gain mode
0: VGA low-gain mode
(Refer to the Programming Guide for
more details)
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Table 11. Channel Registers, 3A to A9 (continued)
DEFAULT
VALUE
(Hex)
ADDRESS
(Hex)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
8F
90
91
7
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
EQ_BST_TO_EQ[7]
Primary observation point for the EQ
boost setting.
R
EQ_BST_TO_EQ[6]
EQ_BST_TO_EQ5]
EQ_BST_TO_EQ[4]
EQ_BST_TO_EQ[3]
EQ_BST_TO_EQ[2]
EQ_BST_TO_EQ[1]
EQ_BST_TO_EQ[0]
RESERVED
5
R
4
R
3
R
2
R
1
R
0
R
7
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
6
RESERVED
5
RESERVED
4
RESERVED
3
RESERVED
2
RESERVED
1
RESERVED
0
RESERVED
7
RESERVED
6
RESERVED
5
RESERVED
4
RESERVED
3
RESERVED
2
RESERVED
1
RESERVED
0
RESERVED
92
93
94
95
7:0
7:0
7:0
7
RESERVED
RESERVED
RESERVED
SD_ENABLE
1: Force enable signal detect
0: Normal operation
6
5
0
0
RW
RW
N
N
SD_DISABLE
1: Force disable signal detect
0: Normal operation
DC_OFF_ENABLE
1: Force enable DC offset
compensation
0: Normal operation
4
0
RW
N
DC_OFF_DISABLE
1: Force disable DC offset
compensation
0: Normal operation
3
2
1
0
RW
RW
N
N
EQ_ENABLE
EQ_DISABLE
1: Force enable the CTLE
0: Normal operation
1: Force disable the CTLE
0: Normal operation
1
0
0
0
RW
RW
N
N
RESERVED
RESERVED
RESERVED
RESERVED
72
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DS250DF410
www.ti.com.cn
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
Table 11. Channel Registers, 3A to A9 (continued)
DEFAULT
VALUE
(Hex)
ADDRESS
(Hex)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
96
7
6
5
4
3
0
0
0
0
1
RW
RW
RW
RW
RW
N
N
N
N
Y
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
EQ_EN_LOCAL
RESERVED
RESERVED
RESERVED
1: Enable the ebuf for the local
output. Can be set independently of
other controls.
(Refer to the Programming Guide for
more details)
2
1
0
0
0
0
RW
RW
RW
Y
Y
Y
EQ_EN_FANOUT
EQ_SEL_XPNT
XPNT_SLAVE
1: Enable the ebuf for the fanout.
Can be set independently of other
controls.
(Refer to the Programming Guide for
more details)
1: Indicates to a channel where it is
getting its data from. 0 indicates
local. 1-indicates from the cross.
(Refer to the Programming Guide for
more details)
1: Indicates to a channel if it needs to
wait for the other channel to
complete its lock/adaptation. The
need for this condition comes up
when input of one channel is routed
to the other channel or multiple
channels.
(Refer to the Programming Guide for
more details)
97
7
6
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
R
R
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
PRBS_FIXED[15]
PRBS_FIXED[14]
PRBS_FIXED[13]
PRBS_FIXED[12]
PRBS_FIXED[11]
PRBS_FIXED[10]
PRBS_FIXED[9]
PRBS_FIXED[8]
RESERVED
Pattern generator user defined
pattern MSB. LSB located at channel
Reg_0x7C.
5
R
4
R
3
R
2
R
1
R
0
R
98
99
7:6
5:0
7
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
6
RESERVED
5
RESERVED
4
RESERVED
3
RESERVED
2
RESERVED
1
RESERVED
0
RESERVED
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Table 11. Channel Registers, 3A to A9 (continued)
DEFAULT
VALUE
(Hex)
ADDRESS
(Hex)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
9A
9B
9C
9D
9E
7
6
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
Y
Y
Y
Y
Y
Y
N
N
N
N
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
CP_EN_IDAC_PD[2]
CP_EN_IDAC_PD[1]
CP_EN_IDAC_PD[0]
CP_EN_IDAC_FD[2]
CP_EN_IDAC_FD[1]
CP_EN_IDAC_FD[0]
RESERVED
RESERVED
NOT USED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
Phase detector charge pump setting,
when override is enabled. See
reg_0C for other bits.
6
5
4
Frequency detector charge pump
setting, when override is enabled.
See reg_0C for other bits.
3
2
1
RESERVED
RESERVED
0
9F
A0
A1
A2
A3
A4
7:0
7:0
7:0
7:0
7:0
7:0
R
NOT USED
R
NOT USED
R
NOT USED
R
NOT USED
R
NOT USED
74
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DS250DF410
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ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
Table 11. Channel Registers, 3A to A9 (continued)
DEFAULT
VALUE
(Hex)
ADDRESS
(Hex)
BITS
MODE
EEPROM
FIELD NAME
DESCRIPTION
A5
7
6
5
0
0
1
RW
RW
RW
Y
Y
Y
PFD_SEL_DATA_PSTLCK[2]
PFD_SEL_DATA_PSTLCK[1]
PFD_SEL_DATA_PSTLCK[0]
Output mode for when the CDR is in
lock. For these values to take effect,
Reg_0x09[5] must be set to 0, which
is the default.
000: Raw Data
001: Retimed data (default)
100: PRBS Generator or Fixed
Pattern Generator Data
101: 10M clock
111: Mute
All other values are reserved. (Refer
to the Programming Guide for more
details)
4
3
2
1
0
7
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
N
N
N
N
N
N
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
INCR_HIST_TMR
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
A6
Provides an option to increase EOM
timer given by 0x2A[7:4] for
histogram collection by +8 for
selection values < 8
6
1
RW
Y
EOM_TMR_ABRT_ON_HIT
Enables faster scan through the eye-
matrix by moving on to the next
matrix point as soon as hit is
observed
Note: This bit does not affect when
slope measurement are in progress
5
4
0
0
RW
RW
Y
Y
SLP_MIN_REQ_HITS[1]
SLP_MIN_REQ_HITS[0]
Minimum required hit count for
registering a hit during slope
measurements.
3
0
RW
Y
LFT_SLP
0: allows slope measurement for the
right side of the eye
1: allows slope measurement for the
left side of the eye
2
0
RW
Y
TOP_SLP
0: allows slope measurement for the
bottom side of the eye
1: allows slope measurement for the
top side of the eye
1
0
1
1
RW
RW
Y
Y
DFE_BATHTUB_FOM
CTLE_BATHTUB_FOM
Enables slope-based bathtub FoM
for DFE adaptation
Enables slope-based bathtub FoM
for CTLE adaptation
A7
A8
A9
7:0
7:0
7:0
0
0
0
R
N
N
Y
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RW
RW
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DS250DF410
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DS250DF410 is a high-speed retimer which extends the reach of differential channels and cleans jitter and
other signal impairments in the process. It can be deployed in a variety of different systems from backplanes to
front ports to active cable assemblies. The following sections outline typical applications and their associated
design considerations.
9.2 Typical Applications
The DS250DF410 is typically used in the following application scenarios:
1. Front-Port Jitter Cleaning Applications
2. Active Cable Applications
3. Backplane and Mid-plane Applications
Line Card
Switch Fabric
25G-LR
x4
25G-VSR
x4
DS250DF410
DS250DF410
Optical
x4
25G-LR
SFP28/QSFP28
ASIC
ASIC
FPGA
FPGA
Active Copper
DS250DF410
x4
25G-LR
x4 25G
DS250DF410
QSFP28
Backplane/
Midplane
图 15. Typical Uses for the DS250DF410 in a System
76
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ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
Typical Applications (接下页)
9.2.1 Front-Port Jitter Cleaning Applications
The DS250DF410 has strong equalization capabilities that allow it to equalize insertion loss, reduce jitter, and
extend the reach of front-port interfaces. A single DS250DF410 can be used to support all four egress channels
for a 100GbE port. Another DS250DF410 can be used to support all four ingress channels for the same 100GbE
ports. Alternatively, a single DS250DF410 can be used to support all egress channels for four 25GbE ports, and
another DS250DF410 can be used to support all four ingress channels for the same four 25GbE ports.
For applications which require IEEE802.3 100GBASE-CR4 or 25GBASE-CR auto-negotiation and link training, a
linear repeater device such as the DS280BR810 (or similar) is recommended.
图 16 illustrates this configuration, and 图 17 shows an example simplified schematic for a typical front-port
application.
Network Interface Card (NIC) or Host Bus Adapter (HBA)
25G/28G-LR
25G/28G-VSR
DS250DF410
Optical or
fixed-rate Copper
x4
x4
DS250DF410
1 x 100GbE QSFP28
ASIC
PCIe
FPGA
Optical or Copper
25G/28G-LR
25G/28G-VSR
x4
Optical or Copper
Optical or Copper
DS250DF410
x4
DS250DF410
Optical or Copper
4 x 25GbE SFP28
or
2 x 50GbE SFP28
图 16. Front-Port Application Block Diagram
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Typical Applications (接下页)
AC coupling
capacitors needed
No AC coupling
capacitors needed
Egress Retimer
RX0P
RX0N
TX0P
TX0N
CDR
RX
TX
.
.
.
.
.
.
.
.
.
.
.
.
RX3P
RX3N
TX3P
TX3N
CDR
RX
TX
2.5V or
3.3V
VDD
SMBus
Slave mode
To other
open-drain
interrupt pins
1 kΩ
INT_N
EN_SMB
SDA
SDC
To system
SMBus(1)
Address straps
(pull-up, pull-
down, or float)
ADDR0
ADDR1
NC_TEST[5:0]
CAL_CLK_IN
To next device‘s
CAL_CLK_IN
25 MHz
CAL_CLK_OUT
SMBus Slave
mode
ALL_DONE_N
GND
READ_EN_N
VDD
2.5V
Minimum
recommended
decoupling
0.1ꢀF
(4x)
1ꢀF
(2x)
1 x QSFP28
Or
4 x SFP28
Host ASIC /
FPGA
AC coupling
capacitors needed
No AC coupling
capacitors needed
Ingress Retimer
TX0P
RX0P
CDR
TX
RX
TX0N
RX0N
.
.
.
.
.
.
.
.
.
.
.
.
TX7P
TX7N
RX7P
RX7N
CDR
TX
RX
VDD
SMBus
Slave mode
1 kΩ
INT_N
EN_SMB
SDA
SDC
Address straps
(pull-up, pull-
down, or float)
ADDR0
ADDR1
NC_TEST[5:0]
CAL_CLK_IN
CAL_CLK_OUT
SMBus Slave
mode
ALL_DONE_N
GND
READ_EN_N
VDD
2.5V
Minimum
recommended
decoupling
0.1ꢀF
(4x)
1ꢀF
(2x)
(1) SMBus signals need to be pulled up elsewhere in the system.
图 17. Front-Port Application Schematic
9.2.1.1 Design Requirements
For this design example, the following guidelines outlined in 表 12 apply.
78
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ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
Typical Applications (接下页)
表 12. Front-Port Application Design Guidelines
DESIGN PARAMETER
REQUIREMENT
Egress (ASIC-to-module) direction: AC coupling capacitors in the
range of 100 to 220 nF are required for the RX inputs and are NOT
required for the TX outputs.
Ingress (module-to-ASIC) direction: AC coupling capacitors in the
range of 100 to 220 nF are required for the TX outputs and are NOT
required for the RX inputs.
AC coupling capacitors
Input channel insertion loss
Output channel insertion loss
≤ 35 dB at 25.78125 Gbps Nyquist frequency (12.9 GHz)
Egress (ASIC-to-module) direction: Follow CAUI-4 / CEI-25G-VSR
host channel requirements (approximately 7dB at 12.9 GHz).
Ingress (module-to-ASIC) direction: Depends on downstream ASIC /
FPGA capabilities. The DS250DF410 has a low-jitter output driver
with 3-tap FIR filter for equalizing a portion of the output channel.
Host ASIC TX launch amplitude
Host ASIC TX FIR filter
800 mVppd to 1200 mVppd.
Depends on channel loss. Refer to Setting the Output VOD, Pre-
Cursor, and Post-Cursor Equalization.
9.2.1.2 Detailed Design Procedure
The design procedure for front-port applications is as follows:
1. Determine the total number of channels on the board which require a DS250DF410 for signal conditioning.
This will dictate the total number of DS250DF410 devices required for the board. It is generally
recommended that channels connected to the same front-port cage be grouped together in the same
DS250DF410 device. This will simplify the device settings, as similar loss channels generally utilize similar
settings.
2. Determine the maximum current draw required for all DS250DF410 retimers. This may impact the selection
of the regulator for the 2.5-V supply rail. To calculate the maximum current draw, multiply the maximum
transient power supply current by the total number of DS250DF410 devices.
3. Determine the maximum operational power consumption for the purpose of thermal analysis. There are two
ways to approach this calculation:
a. Maximum mission-mode operational power consumption is when all channels are locked and re-
transmitting the data which is received. PRBS pattern checkers/generators are not used in this mode
because normal traffic cannot be checked with a PRBS checker. For this calculation, multiply the worst-
case power consumption in mission mode by the total number of DS250DF410 devices.
b. Maximum debug-mode operational power consumption is when all channels are locked and re-
transmitting the data which is received. At the same time, some channels’ PRBS checkers or generators
may be enabled. For this calculation, multiply the worst-case power consumption in debug mode by the
total number of DS250DF410 devices.
4. Determine the SMBus address scheme needed to uniquely address each DS250DF410 device on the board,
depending on the total number of devices identified in step 2. Each DS250DF410 can be strapped with one
of 16 unique SMBus addresses. If there are more DS250DF410 devices on the board than the number of
unique SMBus addresses which can be assigned, then use an I2C expander like the TCA/PCA family of
I2C/SMBus switches and multiplexers to split up the SMBus into multiple busses.
5. Determine if the device will be configured from EEPROM (SMBus Master Mode) or from the system I2C bus
(SMBus Slave Mode).
a. If SMBus Master Mode will be used, provisions should be made for an EEPROM on the board with 8-bit
SMBus address 0xA0. Refer to SMBus Master Mode for more details on SMBus Master Mode including
EEPROM size requirements.
b. If SMBus Slave Mode will be used for all device configurations, an EEPROM is not needed.
6. Make provisions in the schematic and layout for standard decoupling capacitors between the device VDD
supply and GND. Refer to the pin function description in Pin Configuration and Functions for more details.
7. Make provisions in the schematic and layout for a 25 MHz (±100 ppm) single-ended CMOS clock. Each
DS250DF410 retimer buffers the clock on the CAL_CLK_IN pin and presents the buffered clock on the
CAL_CLK_OUT pin. This allows multiple (up to 20) retimers’ calibration clocks to be daisy chained to avoid
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the need for multiple oscillators on the board. If the oscillator used on the board has a 2.5-V CMOS output,
then no AC coupling capacitor or resistor ladder is required at the input to CAL_CLK_IN. No AC coupling or
resistor ladder is needed between one retimer’s CAL_CLK_OUT output and the next retimer’s CAL_CLK_IN
input. The final retimer’s CAL_CLK_OUT output can be left floating.
8. Connect the INT_N open-drain output to an FPGA or CPU if interrupt monitoring is desired. Note that
multiple retimers’ INT_N outputs can be connected together because this is an open-drain output. The
common INT_N net should be pulled high.
9. If the application requires initial CDR lock acquisition at the ambient temperature extremes defined in
Recommended Operating Conditions, care should be taken to ensure the operating junction temperature is
met as well as the CDR stay-in-lock ambient temperature range defined in Timing Requirements, Retimer
Jitter Specifications. For example, if initial CDR lock acquisition occurs at an ambient temperature of 85 ºC,
then maintaining CDR lock would require the ambient temperature surrounding the DS250DF410 to be kept
above (85 ºC - TEMPLOCK-).
9.2.1.3 Application Curves
图 18. DS250DF410 Operating at 25.78125 Gbps
图 19. DS250DF410 FIR Transmit Equalization While
Operating at 25.78125 Gbps
图 18 shows a typical output eye diagram for the DS250DF410 operating at 25.78125 Gbps with PRBS9 pattern
using FIR main-cursor of +18, pre-cursor of -1 and post-cursor of +2. All other device settings are left at default.
图 19 shows an example of DS250DF410 FIR transmit equalization while operating at 25.78125 Gbps. In this
example, the Tx FIR filter main-cursor is set to +15, post-cursor to -3 and pre-cursor to -3. An 8T pattern is used
to evaluate the FIR filter, which consists of 0xFF00. All other device settings are left at default.
80
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DS250DF410
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ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
9.2.2 Active Cable Applications
The DS250DF410 has strong equalization capabilities that allow it to recover data over long and/or thin-gauge
copper cables. A single DS250DF410 can be used on a QSFP28 paddle card to create a half-active cable
assembly which is longer and/or thinner than passive cables. Alternatively, two DS250DF410 devices can be
used on a QSFP28 paddle card to create a full-active cable assembly and achieve even longer reach and/or
thinner cables.
图 20 illustrates these configurations, 图 21 shows an example simplified schematic for a half-active cable
application, and 图 22 shows an example simplified schematic for a full-active cable application.
Line Card
Full-Active Cable
DS250DF410
DS250DF410
DS250DF410
DS250DF410
QSFP
x4 25G VSR
ASIC
FPGA
Half-Active Cable
DS250DF410
QSFP
x4 25G VSR
DS250DF410
图 20. Active Cable Application Block Diagram
版权 © 2016–2019, Texas Instruments Incorporated
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DS250DF410
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
www.ti.com.cn
No Retimer and no AC coupling capacitors needed
Paddle
card host
Paddle
card cable
side
AC coupling
capacitors needed
RX Retimer
AC coupling
capacitors needed
TX0P
RX0P
CDR
TX
RX
side
TX0N
RX0N
.
.
.
.
.
.
.
.
.
.
.
.
TX7P
TX7N
RX7P
RX7N
CDR
TX
RX
2.5V or
3.3V
VDD
To micro-
controller
interrupt pin
SMBus
Slave mode
1 kΩ
INT_N
EN_SMB
SDA
SDC
To paddle
card SMBus
Address straps
(pull-up, pull-
down, or float)
ADDR0
ADDR1
NC_TEST[5:0]
CAL_CLK_IN
25 MHz
CAL_CLK_OUT
SMBus Slave
mode
ALL_DONE_N
GND
READ_EN_N
VDD
2.5V
Minimum
recommended
decoupling
0.1ꢀF
(4x)
1ꢀF
(2x)
图 21. Half-Active Cable Application Schematic
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DS250DF410
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ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
TX Retimer
RX0P
RX0N
TX0P
TX0N
CDR
RX
TX
.
.
.
.
.
.
.
.
.
.
.
.
RX3P
RX3N
TX3P
TX3N
CDR
RX
TX
2.5V or
3.3V
VDD
To micro-
controller
interrupt pin
SMBus
Slave mode
1 kΩ
INT_N
EN_SMB
SDA
SDC
To paddle
card SMBus
Address straps
(pull-up, pull-
down, or float)
ADDR0
ADDR1
NC_TEST[5:0]
CAL_CLK_IN
To next device‘s
CAL_CLK_IN
25 MHz
CAL_CLK_OUT
SMBus Slave
mode
ALL_DONE_N
GND
READ_EN_N
VDD
2.5V
Minimum
recommended
decoupling
0.1ꢀF
(4x)
1ꢀF
(2x)
Paddle
card host
side
Paddle
AC coupling
capacitors needed
RX Retimer
AC coupling
card cable
capacitors needed
TX0P
RX0P
CDR
TX
RX
side
TX0N
RX0N
.
.
.
.
.
.
.
.
.
.
.
.
TX7P
TX7N
RX7P
RX7N
CDR
TX
RX
VDD
1 kΩ
SMBus
Slave mode
INT_N
EN_SMB
SDA
SDC
Address straps
(pull-up, pull-
down, or float)
ADDR0
ADDR1
NC_TEST[5:0]
CAL_CLK_IN
CAL_CLK_OUT
SMBus Slave
mode
ALL_DONE_N
GND
READ_EN_N
VDD
2.5V
Minimum
recommended
decoupling
0.1ꢀF
(4x)
1ꢀF
(2x)
图 22. Full-Active Cable Application Schematic
版权 © 2016–2019, Texas Instruments Incorporated
83
DS250DF410
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
www.ti.com.cn
9.2.2.1 Design Requirements
For this design example, the following guidelines outlined in 表 13 and 表 14 apply.
表 13. Half-Active Cable Application Design Guidelines
DESIGN PARAMETER
REQUIREMENT
Place the DS250DF410 on the receive side of the paddle card such
that it is receiving data from the cable, and transmitting towards the
host.
Device placement
100 nF AC coupling capacitors are required for the RX inputs and
the TX outputs.
AC coupling capacitors
The raw cable insertion loss including the insertion loss of the paddle
card should be ≤ 27 dB at 25.78125 Gbps Nyquist frequency (12.9
GHz). This is to ensure that the total loss at the input to the
DS250DF410 is ≤ 35 dB at 12.9 GHz. Assuming a worst-case host-
side PCB loss of 7 dB, plus a connector loss of 1 dB, the remaining
loss allocated for the raw cable and paddle cards is 27 dB.
Cable insertion loss
表 14. Full-Active Cable Application Design Guidelines
DESIGN PARAMETER
REQUIREMENT
A full-active QSFP cable will utilize two pieces of DS250DF410 per
paddle card. Typically, one device will be placed on each side of the
paddle card.
Device placement
Transmit-side Retimer: 100 nF AC coupling capacitors are required
for the RX inputs and are not required for the TX outputs. This link
segment will be AC coupled on the paddle card at the opposite end
of the cable.
Receive-side Retimer: 100 nF AC coupling capacitors are required
for the RX inputs and the TX outputs.
AC coupling capacitors
Cable insertion loss
The raw cable insertion loss including the insertion loss of the paddle
card should be ≤ 35 dB at 25.78125 Gbps Nyquist frequency (12.9
GHz).
9.2.2.2 Detailed Design Procedure
The design procedure for active cable applications is as follows:
1. Determine the maximum current draw required for the DS250DF410 retimer(s) on the paddle card. This may
impact the selection of the regulator for the 2.5-V supply rail. To calculate the maximum current draw,
multiply the maximum transient power supply current by the total number of DS250DF410 devices.
2. Determine the maximum operational power consumption for the purpose of thermal analysis. There are two
ways to approach this calculation:
a. Maximum mission-mode operational power consumption is when all channels are locked and re-
transmitting the data which is received. PRBS pattern checkers/generators are not used in this mode
because normal traffic cannot be checked with a PRBS checker. For this calculation, multiply the worst-
case power consumption in mission mode by the total number of DS250DF410 devices.
b. Maximum debug-mode operational power consumption is when all channels are locked and re-
transmitting the data which is received. At the same time, some channels’ PRBS checkers or generators
may be enabled. For this calculation, multiply the worst-case power consumption in debug mode by the
total number of DS250DF410 devices.
3. Determine the SMBus address for the DS250DF410 Retimer(s). If using just one Retimer for a half-active
cable, the ADDR[1:0] pins can be left floating for an 8-bit SMBus slave address of 0x44. If using a second
DS250DF410, as in the case of a full-active cable assembly, a single pull-up or pull-down resistor can be
used on one address pin. For example, with ADDR0 = Float and ADDR1 = 1 kΩ the 8-bit SMBus slave
address will be 0x34.
4. Determine if the device will be configured from EEPROM (SMBus Master Mode) or from the system I2C bus
(SMBus Slave Mode).
a. If SMBus Master Mode will be used, provisions should be made for an EEPROM on the board with 8-bit
SMBus address 0xA0. Refer to SMBus Master Mode for more details on SMBus Master Mode including
EEPROM size requirements.
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ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
b. If SMBus Slave Mode will be used for all device configurations, for example when the Retimer(s) is
configured with a microcontroller, an EEPROM is not needed.
5. Make provisions in the schematic and layout for standard decoupling capacitors between the device VDD
supply and GND. Refer to the pin function description in Pin Configuration and Functions for more details.
6. Make provisions in the schematic and layout for a 25 MHz (±100 ppm) single-ended CMOS clock. The
DS250DF410 retimer buffers the clock on the CAL_CLK_IN pin and presents the buffered clock on the
CAL_CLK_OUT pin. When using two Retimers on a paddle card, only one 25 MHz clock is required. The
CAL_CLK_OUT pin of one retimer can be connected to teh CAL_CLK_IN pin of the other retimer.
7. Connect the INT_N open-drain output to the paddle card MCU if interrupt monitoring is desired, otherwise
leave it floating. Note that multiple retimers’ INT_N outputs can be connected together because this is an
open-drain output. The common INT_N net should be pulled high.
8. If the application requires initial CDR lock acquisition at the ambient temperature extremes defined in
Recommended Operating Conditions, care should be taken to ensure the operating junction temperature is
met as well as the CDR stay-in-lock ambient temperature range defined in Timing Requirements, Retimer
Jitter Specifications. For example, if initial CDR lock acquisition occurs at an ambient temperature of 85 ºC,
then maintaining CDR lock would require the ambient temperature surrounding the DS250DF410 to be kept
above (85 ºC - TEMPLOCK-).
9.2.2.3 Application Curves
See Application Curves in section Front-Port Jitter Cleaning Applications.
版权 © 2016–2019, Texas Instruments Incorporated
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DS250DF410
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
www.ti.com.cn
9.2.3 Backplane and Mid-plane Applications
The DS250DF410 has strong equalization capabilities that allow it to recover data over channels up to 35 dB
insertion loss. As a result, the optimum placement for the DS250DF410 in a backplane/mid-plane application is
with the higher-loss channel segment at the input and the lower-loss channel segment at the output. This
reduces the equalization burden on the downstream ASIC/FPGA, as the DS250DF410 is equalizing a majority of
the overall channel. This type of asymmetric placement is not a requirement, but when an asymmetric placement
is required due to the presence of a passive backplane or mid-plane, then this becomes the recommended
placement.
Passive Backplane/
Midplane
Switch Fabric Card
Line Card
x4 25G
ASIC
FPGA
x4 25G
ASIC
FPGA
图 23. Backplane/Mid-Plane Application Block Diagram
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DS250DF410
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ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
RX0P
TX0P
CDR
CDR
RX
RX
TX
TX
RX0N
.
.
.
TX0N
.
.
.
.
.
.
.
.
.
RX3P
RX3N
TX3P
TX3N
CDR
CDR
RX
RX
TX
TX
VDD
2.5 V or 3.3 V
SMBus
Slave mode
1 kΩ
To other
open-drain
interrupt pins
EN_SMB
INT_N
NC_TEST[5:0]
SDA
SDC
To system
SMBus(1)
Address straps
(pull-up, pull-
down, or float)
ADDR0
ADDR1
25 MHz
CAL_CLK_IN
CAL_CLK_OUT
To next device‘s
CAL_CLK_IN
Output can float
in slave mode
SMBus Slave mode
2.5 V
READ_EN_N
VDD
ALL_DONE_N
GND
Minimum
recommended
decoupling
1 ꢀF
(2x)
0.1 ꢀF
(4x)
Backplane /
Mid-plane
Connector
ASIC / FPGA
TX0P
RX0P
CDR
CDR
TX
TX
RX
RX
TX0N
.
.
.
RX0N
.
.
.
TX3P
TX3N
RX3P
RX3N
CDR
CDR
TX
TX
RX
RX
VDD
SMBus
1 kΩ
Slave mode
EN_SMB
INT_N
SDA
SDC
NC_TEST[5:0]
Address straps
(pull-up, pull-
down, or float)
ADDR0
ADDR1
CAL_CLK_IN
CAL_CLK_OUT
ALL_DONE_N
GND
Output can float
in slave mode
SMBus Slave mode
2.5 V
READ_EN_N
VDD
1 ꢀF
(2x)
0.1 ꢀF
(4x)
Minimum
recommended
decoupling
图 24. Backplane/Mid-Plane Application Schematic
版权 © 2016–2019, Texas Instruments Incorporated
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DS250DF410
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
www.ti.com.cn
9.2.3.1 Design Requirements
For this design example, the following guidelines outlined in 表 15 apply.
表 15. Backplane/Mid-Plane Application Design Guidelines
DESIGN PARAMETER
REQUIREMENT
AC coupling capacitors in the range of 100 to 220 nF are required for
the RX inputs and TX outputs.
AC coupling capacitors
Input channel insertion loss
Output channel insertion loss
≤ 35 dB at 25.78125 Gbps Nyquist frequency (12.9 GHz)
Depends on downstream ASIC / FPGA capabilities. The
DS250DF410 has a low-jitter output driver with 3-tap FIR filter for
equalizing a portion of the output channel.
Link partner TX launch amplitude
Link partner TX FIR filter
800 mVppd to 1200 mVppd
Depends on channel loss. Refer to Setting the Output VOD, Pre-
Cursor, and Post-Cursor Equalization.
9.2.3.2 Detailed Design Procedure
The design procedure for backplane/mid-plane applications is as follows:
1. Determine the total number of channels on the board which require a DS250DF410 for signal conditioning.
This will dictate the total number of DS250DF410 devices required for the board. It is generally
recommended that channels with similar total insertion loss on the board be grouped together in the same
DS250DF410 device. This will simplify the device settings, as similar loss channels generally utilize similar
settings.
2. Determine the maximum current draw required for all DS250DF410 retimers. This may impact the selection
of the regulator for the 2.5-V supply rail. To calculate the maximum current draw, multiply the maximum
transient power supply current by the total number of DS250DF410 devices.
3. Determine the maximum operational power consumption for the purpose of thermal analysis. There are two
ways to approach this calculation:
a. Maximum mission-mode operational power consumption is when all channels are locked and re-
transmitting the data which is received. PRBS pattern checkers/generators are not used in this mode
because normal traffic cannot be checked with a PRBS checker. For this calculation, multiply the worst-
case power consumption in mission mode by the total number of DS250DF410 devices.
b. Maximum debug-mode operational power consumption is when all channels are locked and re-
transmitting the data which is received. At the same time, some channels’ PRBS checkers or generators
may be enabled. For this calculation, multiply the worst-case power consumption in debug mode by the
total number of DS250DF410 devices.
4. Determine the SMBus address scheme needed to uniquely address each DS250DF410 device on the board,
depending on the total number of devices identified in step 2. Each DS250DF410 can be strapped with one
of 16 unique SMBus addresses. If there are more DS250DF410 devices on the board than the number of
unique SMBus addresses which can be assigned, then use an I2C expander like the TCA/PCA family of
I2C/SMBus switches and multiplexers to split up the SMBus into multiple busses.
5. Determine if the device will be configured from EEPROM (SMBus Master Mode) or from the system I2C bus
(SMBus Slave Mode).
a. If SMBus Master Mode will be used, provisions should be made for an EEPROM on the board with 8-bit
SMBus address 0xA0. Refer to SMBus Master Mode for more details on SMBus Master Mode including
EEPROM size requirements.
b. If SMBus Slave Mode will be used for all device configurations, an EEPROM is not needed.
6. Make provisions in the schematic and layout for standard decoupling capacitors between the device VDD
supply and GND. Refer to the pin function description in Pin Configuration and Functions for more details.
7. Make provisions in the schematic and layout for a 25MHz (±100 ppm) single-ended CMOS clock. Each
DS250DF410 retimer buffers the clock on the CAL_CLK_IN pin and presents the buffered clock on the
CAL_CLK_OUT pin. This allows multiple (up to 20) retimers’ calibration clocks to be daisy chained to avoid
the need for multiple oscillators on the board. If the oscillator used on the board has a 2.5-V CMOS output,
then no AC coupling capacitor or resistor ladder is required at the input to CAL_CLK_IN. No AC coupling or
resistor ladder is needed between one retimer’s CAL_CLK_OUT output and the next retimer’s CAL_CLK_IN
input. The final retimer’s CAL_CLK_OUT output can be left floating.
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DS250DF410
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ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
8. Connect the INT_N open-drain output to an FPGA or CPU if interrupt monitoring is desired. Note that
multiple retimers’ INT_N outputs can be connected together because this is an open-drain output. The
common INT_N net should be pulled high.
9. If the application requires initial CDR lock acquisition at the ambient temperature extremes defined in
Recommended Operating Conditions, care should be taken to ensure the operating junction temperature is
met as well as the CDR stay-in-lock ambient temperature range defined in Timing Requirements, Retimer
Jitter Specifications. For example, if initial CDR lock acquisition occurs at an ambient temperature of 85 ºC,
then maintaining CDR lock would require the ambient temperature surrounding the DS250DF410 to be kept
above (85 ºC - TEMPLOCK-).
9.2.3.3 Application Curves
See Application Curves in section Front-Port Jitter Cleaning Applications.
版权 © 2016–2019, Texas Instruments Incorporated
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DS250DF410
ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
www.ti.com.cn
10 Power Supply Recommendations
Follow these general guidelines when designing the power supply:
1. The power supply should be designed to provide the recommended operating conditions outlined in
Specifications in terms of DC voltage, AC noise, and start-up ramp time.
2. The maximum current draw for the DS250DF410 is provided in Specifications . This figure can be used to
calculate the maximum current the power supply must provide. Typical mission-mode current draw can be
inferred from the typical power consumption in Specifications.
3. The DS250DF410 does not require any special power supply filtering (that is, ferrite bead), provided the
recommended operating conditions are met. Only standard supply decoupling is required. Refer to Pin
Configuration and Functions for details concerning the recommended supply decoupling.
11 Layout
11.1 Layout Guidelines
The following guidelines should be followed when designing the layout:
1. Decoupling capacitors should be placed as close to the VDD pins as possible. Placing them directly
underneath the device is one option if the board design permits.
2. High-speed differential signals TXnP/TXnN and RXnP/RXnN should be tightly coupled, skew matched, and
impedance controlled.
3. Vias should be avoided when possible on the high-speed differential signals. When vias must be used, care
should be taken to minimize the via stub, either by transitioning through most/all layers, or by back drilling.
4. GND relief can be used beneath the high-speed differential signal pads to improve signal integrity by
counteracting the pad capacitance.
5. GND relief can be used beneath the AC coupling capacitor pads to improve signal integrity by counteracting
the pad capacitance.
6. GND vias should be placed directly beneath the device connecting the GND plane attached to the device to
the GND planes on other layers. This has the added benefit of improving thermal conductivity from the
device to the board
7. BGA landing pads for a 0.5-mm pitch flip-chip BGA are typically 0.3 mm in diameter (exposed). The actual
size of the copper pad will depend on whether solder-mask-defined (SMD) or non-solder-mask-defined
solder land pads are used. For more information, refer to TI’s Surface Mount Technology (SMT) and
Packaging application notes on the TI website.
8. If vias are used for the high-speed signals, ground via should be implemented adjacent to the signal via to
provide return path and isolation. For differential pair, the typical via configuration is ground-signal-signal-
ground.
9. Note that some BGA balls in the DS250DF410 pinout have been de-populated to allow for GND and VDD
vias to be placed with ≥1.0 mm via-to-via spacing.
11.2 Layout Example
The following example layout demonstrates how all signals can be escaped from the BGA array using microstrip
routing on a generic multi-layer stackup. This example layout assumes the following:
•
•
•
Trace width: 0.159 mm (6.25 mil)
Trace edge-to-edge spacing: 0.197 mm (7.75 mil)
VIA-to-VIA spacing: 0.7 mm (27.9 mil) minimum; Note: 1.0 mm VIA-to-VIA spacing is also achievable if PCB
manufacturing rules stipulate
•
•
No VIA-in-pad used
Note: Some TI test pins (i.e. NC_TEST[5:0]) are routed in this example layout, but in most applications these
pins can be left floating.
Note that many other escape routing options exist using different trace width and spacing combinations. The
optimum trace width and spacing will depend on the PCB material, PCB routing density, and other factors.
90
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DS250DF410
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ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
Layout Example (接下页)
图 26. Layer 1 GND
图 25. Top Layer
图 27. Internal Low-Speed Signal Layers
图 28. VDD Layer
图 29. Bottom Layer
版权 © 2016–2019, Texas Instruments Incorporated
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ZHCSKE8D –MARCH 2016–REVISED OCTOBER 2019
www.ti.com.cn
12 器件和文档支持
12.1 文档支持
12.1.1 开发支持
更多相关信息,请参阅 TI 表面贴装技术 (SMT) 参考资料(位于
http://focus.ti.com/quality/docs 页面的“质量和无铅 (Pb) 数据”菜单下)。
12.2 文档支持
12.2.1 相关文档
请参阅如下相关文档:
•
《DS2x0DF810、DS250DFx10、DS250DF230 编程人员指南》 (SNLU182)
单击此处,请求访问 DS250DF410 MySecure 文件夹中的 DS2X0DFX10 IBIS-AMI 模型和编程人员指南。
12.3 接收文档更新通知
要接收文档更新通知,请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册,即可每周接收产品
信息更改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
12.4 支持资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 商标
E2E is a trademark of Texas Instruments.
12.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知,且
不会对此文档进行修订。如需获取此数据表的浏览器版本,请查阅左侧的导航栏。
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS250DF410ABMR
DS250DF410ABMT
ACTIVE
ACTIVE
FCCSP
FCCSP
ABM
ABM
101
101
1000 RoHS & Green
250 RoHS & Green
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
DS250DF4
DS250DF4
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS250DF410ABMR
DS250DF410ABMT
FCCSP
FCCSP
ABM
ABM
101
101
1000
250
330.0
178.0
16.4
16.4
6.3
6.3
6.3
6.3
1.5
1.5
12.0
12.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS250DF410ABMR
DS250DF410ABMT
FCCSP
FCCSP
ABM
ABM
101
101
1000
250
356.0
208.0
356.0
191.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
ABM0101A
FCBGA - 1.03 mm max height
SCALE 2.300
PLASTIC BALL GRID ARRAY
6.1
5.9
A
B
BALL A1 CORNER
6.1
5.9
1.03 MAX
C
SEATING PLANE
0.08 C
BALL TYP
0.26
TYP
0.15
5 TYP
SYMM
(0.5) TYP
L
K
J
(0.5) TYP
H
G
F
SYMM
5
TYP
E
D
C
0.35
101X
0.25
0.15
0.05
C A
C
B
B
A
0.5 TYP
1
2
3
4
5
6
7
8
9
10 11
0.5 TYP
BALL A1 CORNER
4222100/B 09/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
ABM0101A
FCBGA - 1.03 mm max height
PLASTIC BALL GRID ARRAY
(0.5) TYP
101X ( 0.28)
8
9
1
2
3
4
5
6
7
10
11
A
B
C
(0.5) TYP
D
E
F
G
H
J
SYMM
K
L
SYMM
LAND PATTERN EXAMPLE
SCALE:15X
0.05 MAX
0.05 MIN
METAL UNDER
SOLDER MASK
(
0.28)
METAL
(
0.28)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4222100/B 09/2015
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
www.ti.com
EXAMPLE STENCIL DESIGN
ABM0101A
FCBGA - 1.03 mm max height
PLASTIC BALL GRID ARRAY
(0.5) TYP
8
9
1
2
3
4
5
6
7
10
11
A
(0.5) TYP
B
C
D
E
F
G
H
J
SYMM
K
L
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:15X
101X ( 0.25)
PCB PAD
(R0.05) TYP
S
C
A
L
E
6
0
.
0
0
0
STENCIL DETAIL
NTS
4222100/B 09/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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